fn3662 rev.3.00 page 1 of 7 october 26, 2005 fn3662 rev.3.00 october 26, 2005 HI1171 8-bit, 40 msps, high speed d/a converter datasheet features ? throughput rate. . . . . . . . . . . . . . . . . . . . . . . . . . 40mhz ? resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-bit ? integral linearity error . . . . . . . . . . . . . . . . . . . 0.25 lsb ? low glitch noise ? single supply operation . . . . . . . . . . . . . . . . . . . . . +5v ? low power consumption (max) . . . . . . . . . . . . . 80mw ? evaluation board available (HI1171-ev) ? direct replacement for the sony cxd1171 applications ? wireless telecommunications ? signal reconstruction ? direct digital synthesis ?imaging ? presentation and broadcast video ? graphics displays ? signal generators description the HI1171 is an 8-bit, 40mhz, high speed d/a converter. the converter incorporates an 8-bit input data register with blanking capability, and current outputs. the HI1171 fea- tures low glitch outputs. the architecture is a current cell arrangement to provide low linearity errors. the HI1171 is available in an industrial temperature range and is offered in a 24 lead (200 mil) soic plastic package. for dual version, please refer to the hi1177 data sheet. for triple version, please refer to the hi1178 data sheet. ordering information part number temp. range ( o c) package pkg. no. HI1171jcb -40 to 85 24 ld soic m24.2-s HI1171-ev 25 evaluation board pinout HI1171 (soic) top view typical application circuit 1 2 3 4 5 6 7 8 9 10 11 12 (lsb) d0 d1 d2 d3 d4 d5 d6 d7 blnk dv ss v b clk 16 17 18 19 20 21 22 23 24 15 14 13 dv dd av dd i out2 i out1 av dd vg i ref av ss dv ss dv dd av dd v ref d7 (msb)(8) d6 (7) d5 (6) d4 (5) d3 (4) d2 (3) d1 (2) d0 (lsb) (1) d7 d6 d5 d4 d3 d2 d1 d0 +5v dv dd (23, 24) 0.1 ? f dv ss (10, 13) clk (12) blnk (9) +5v 0.1 ? f (18, 19, 22) av dd (14) av ss d/a (20) i out1 (21) i out2 (15) i ref v b (11) 0.1 ? f 3.3k ? 200 ? 0.1 ? f 1k ? (17) v g (16) v ref HI1171 out p b - f r e e a n d r o h s c o m p l i a n t
HI1171 fn3662 rev.3.00 page 2 of 7 october 26, 2005 functional block diagram decoder decoder 8-bit latch clock generator 6 msbs current cells current cells (for full scale) bias voltage generator 2 lsbs current cells + - i ref v ref vg i out1 i out2 (lsb) d0 d1 d2 d3 d4 d5 d6 (msb) d7 blnk vb clk
HI1171 fn3662 rev.3.00 page 3 of 7 october 26, 2005 absolute maximum ratings thermal information digital supply voltage dv dd to dv ss . . . . . . . . . . . . . . . . . . +7.0v analog supply voltage av dd to av ss . . . . . . . . . . . . . . . . . . +7.0v input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dd to v ss v output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0ma to 15ma operating conditions temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to 85 o c thermal resistance (typical, note 1) ? ja ( o c/w) soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 maximum junction temperature, plastic package . . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . 300 o c (soic - lead tips only) caution: stresses above those listed in ?abs olute maximum ratings? may cause permanent dam age to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. ? ja is measured with the component mount ed on an evaluation pc board in free air. electrical specifications av dd = +4.75v to +5.25v, dv dd = +4.75 to +5.25v, v ref = +2.0v, f s = 40mhz, clk pulse width = 12.5ns, t a = 25 o c (note 4) parameter test conditions min typ max units system performance resolution, n -8- bits integral linearity error, inl f s = 40mhz (end point) -0.5 - 1.3 lsb differential linearity error, dnl f s = 40mhz - - ? 0.25 lsb offset error, v os (note 2) - - 1 mv full scale error, fse (adjustable to zero) (note 2) - - ? 13 lsb full scale output current, i fs -1015 ma full scale output voltage, v fs 1.9 2.0 2.1 v output voltage range, v fsr 0.5 2.0 2.1 v dynamic characteristics throughput rate see figure 7 40.0 - - mhz glitch energy, ge r out = 75 ? -30- pv-s differential gain, ? a v (note 3) -1.2- % differential phase, ?? (note 3) -0.5-degree reference input voltage reference input range 0.5 - 2.0 v reference input resistance (note 3) 1.0 - - m ? digital inputs input logic high voltage, v ih (note 3) 3.0 - - v input logic low voltage, v il (note 3) - - 1.5 v input logic current, i il , i ih (note 3) - - ? 5.0 ? a digital input capacitance, c in (note 3) - 5.0 - pf timing characteristics data setup time, t su see figure 1 5 - - ns data hold time, t hld see figure 1 10 - - ns
HI1171 fn3662 rev.3.00 page 4 of 7 october 26, 2005 propagation delay time, t pd see figure 9 - 10 - ns settling time, t set (to 1 / 2 lsb) see figure 1 - 10 15 ns clk pulse width, t pw1 , t pw2 see figure 1 12.5 - - ns power supply characterisitics iav dd 14.3mhz, at color bar data input - 10.9 11.5 ma idv dd 14.3mhz, at color bar data input - 4.2 4.8 ma power dissipation 200 ? load at 2v p-p output - - 80 mw notes: 2. excludes error due to external reference drift. 3. parameter guaranteed by design or characterization and not production tested. 4. electrical specifications guaranteed only under the stated operating conditions. electrical specifications av dd = +4.75v to +5.25v, dv dd = +4.75 to +5.25v, v ref = +2.0v, f s = 40mhz, clk pulse width = 12.5ns, t a = 25 o c (note 4) (continued) parameter test conditions min typ max units timing diagram figure 1. clk data d/aout 100% 50% 0% t pw1 t pw2 t su t hld t su t su t pd t pd t pd t hld t hld
HI1171 fn3662 rev.3.00 page 5 of 7 october 26, 2005 typical performance curves figure 2. output full scale voltage vs reference voltage figure 3. output resistance vs glitch energy figure 4. output full scale voltage vs ambient temperature pin descriptions 24 pin soic pin name pin description 1-8 d0(lsb) thru d7(msb) digital data bit 0, the least significant bit thru digital data bit 7, the most significant bit. 9 blnk blanking line, used to clear the internal data register to the zero condition when high, normal operation when low. 10, 13 dv ss digital ground. 11 vb voltage bias, connect a 0.1 ? f capacitor to dv ss . 12 clk data clock pin 100khz to 40mhz. 14 av ss analog ground. 15 i ref current reference, used to set the current range. connect a resistor to av ss that is 16 times greater than the re- sistor on i out1 . (see typical applic ations circuit). 16 v ref input reference voltage used to set the output full scale range. 17 vg voltage ground, connect a 0.1 ? f capacitor to av dd . 18, 19, 22 av dd analog supply 4.75v to 7v. 20 i out1 current output pin. 2 1 12 v dd = 5.0v, r = 200 ? 16r = 3.3k ? , t a = 25 o c output full scale voltage (v) reference voltage (v) 100 200 100 200 output resistance ( ? ) glitch energy (pv/s) 2.0 1.9 0 -25 0 25 50 75 v dd = 5.0v, v ref = 2.0v r = 200 ??? 16r = 3.3k ? t a = 25 o c output full scale voltage (v) ambient temperature ( o c)
fn3662 rev.3.00 page 6 of 7 october 26, 2005 HI1171 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 1997-2005. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. detailed description the HI1171 is an 8-bit, current out d/a converter. the dac can convert at 40mhz and run on a single +5v supply. the architecture is an encoded, swit ched current cell arrangement. voltage output mode the output current of the HI1171 can be converted into a voltage by connecting an external resistor to i out1 . to calculate the output resistor use the following equation: r out = v fs /i fs , where v fs can range from +0.5v to +2.0v and i fs can range from 0ma to 15ma. in setting the out put current the i ref pin should have a resistor connected to it that is 16 times greater than the output resistor: r ref = 16 x r out as the values of both r out and r ref increase, power consumption is decreased, bu t glitch energy and output settling time is increased. clock phase relationship the internal latch is closed when the clock line is high. the latch can be cleared by the blnk line. when blnk is set (high) the contents of the internal data latch will be cleared. when blnk is low data is updated by the clk. noise reduction to reduce power supply noise separate analog and digital power supplies should be used with 0.1 ? f ceramic capacitors placed as close to the body of the HI1171 as possible. the analog (av ss ) and digital (dv ss ) ground returns should be connected together back at the po wer supply to ensure proper operation from power up. 21 i out2 current output pin used for a virtual ground connection. usually connected to av ss . 23, 24 dv dd digital supply 4.75v to 7v. pin descriptions (continued) 24 pin soic pin name pin description test circuits figure 5. maximum conve rsion speed test circuit oscilloscope 8-bit with latch clk 40mhz square wave counter 1 2 8 9 11 12 15 16 17 20 clk vb 0.1 ? f blk d7 (lsb) d0 io vg v ref 2v i ref av dd 1k ? av ss 3.3k ? 200 ? 0.1 ? f
HI1171 fn3662 rev.3.00 page 7 of 7 october 26, 2005 figure 6. dc characteristics test circuit figure 7. propagation delay time test circuit figure 8. set up hold time and glitch energy test circuit test circuits (continued) dvm clk 40mhz square wave controller 1 2 8 9 11 12 15 16 17 20 clk v b 0.1 ? f blk d7 (lsb) d0 io v g v ref 2v i ref av dd 1k ? av ss 3.3k ? 200 ? 0.1 ? f oscilloscope demultiplier clk 10mhz square wave frequency 1 2 8 9 11 12 15 16 17 20 clk v b 0.1 ? f blk d7 (lsb) d0 io v g v ref 2v i ref av dd 1k ? av ss 3.3k ? 200 ? 0.1 ? f oscilloscope 8-bit with latch clk 1mhz square wave counter 1 2 8 9 11 12 15 16 17 20 clk v b 0.1 ? f blk d7 (lsb) d0 io v g v ref 2v i ref av dd 1k ? av ss 1.2k ? 75 ? 0.1 ? f delay controller delay controller
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