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kinetis v series kv10 and kv11, 128/64 kb flash 75 mhz cortex-m0+ based microcontroller the kinetis v series kv11x mcu family is built on arm cortex- m0+ core and enabled by innovative 90nm thin film storage (tfs) flash process technology. the kv11x is an extension of the existing kv10x family providing increased memory, higher pin count, additional ftms and a flexcan serial interface. ? dual 16-bit adcs sampling at up to 1.2 ms/s in 12-bit mode ? highly accurate and flexible motor control timers ? ideal for industrial motor control applications, inverters, and low-end power conversion applications ? enabled to support kinetis motor suite (kms), a bundled hardware and software solution that enables rapid configuration of bldc and pmsm motor drive systems performance ? up to 75 mhz arm cortex-m0+ based core memories and memory interfaces ? up to 128 kb of program flash memory ? up to 16 kb of ram system peripherals ? nine low-power modes to provide power optimization based on application requirements ? 8-channel dma controller ? swd interface and micro trace buffer ? bit manipulation engine (bme) ? external watchdog timer ? advanced independent clocked watchdog ? memory mapped divide and square root (mmdvsq) module clocks ? 32-40 khz or 4-32 mhz external crystal oscillator ? multipurpose clock generator (mcg) with frequency- locked loop referencing either internal or external reference clock security and integrity modules ? 80-bit unique identification (id) number per chip ? hardware crc module communication interfaces ? one 16-bit spi module ? one i2c module ? two uart modules ? one flexcan module 1 timers ? programmable delay block ? two 6-channel flextimers (ftm) for motor control/ general purpose applications ? four 2-channel flextimers (ftm) with quadrature decoder functionality ? 16-bit low-power timer (lptmr) operating characteristics ? voltage range: 1.71 to 3.6 v ? flash write voltage range: 1.71 to 3.6 v ? temperature range (ambient): C40 to 105c analog modules ? two 16-bit sar adcs ? 12-bit dac ? two analog comparators (acmp) containing a 6-bit dac and programmable reference input human-machine interface ? general-purpose i/o mkv11z128vxx7 mkv11z64vxx7 mkv10z64vxx7 mkv10z128vxx7 mkv11z128vlx7p mkv10z64vlx7p 32 qfn 5 x 5 x 1.23 mm pitch 0.5 mm 64 lqfp 10 x 10 x 1.4 mm pitch 0.5 mm 32 lqfp 7 x 7 x 1.4 mm pitch 0.8 mm 48 lqfp 7 x 7 x 1.4 mm pitch 0.5 mm nxp semiconductors KV11P64M75 data sheet: technical data rev. 4, 05/2017 nxp reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.
kinetis motor suite ? supports velocity and position control of bldc & pmsm motors ? implements field orient control (foc) using back emf to improve motor efficiency ? utilizes spintac control theory that improves overall system performance and reliability 1. available only on kv11 parts ordering information part number 1 memory flexcan maximum number of i\o's flash (kb) sram (kb) mkv11z128vlh7 128 16 yes 46 mkv11z128vlf7 128 16 yes 35 mkv11z128vlc7 2 128 16 yes 26 mkv11z128vfm7 128 16 yes 26 mkv11z64vlh7 64 16 yes 46 mkv11z64vlf7 64 16 yes 35 mkv11z64vlc7 2 64 16 yes 26 mkv11z64vfm7 64 16 yes 26 mkv11z128vlh7p 120 16 yes 46 mkv11z128vlf7p 120 16 yes 35 mkv11z128vlc7p 2 120 16 yes 26 mkv11z128vfm7p 120 16 yes 26 mkv10z64vlh7p 56 16 yes 46 mkv10z64vlf7p 56 16 yes 35 mkv10z64vlc7p 2 56 16 yes 26 mkv10z64vfm7p 56 16 no 26 mkv10z64vlh7 64 16 no 46 mkv10z64vlf7 64 16 no 35 mkv10z64vlc7 2 64 16 no 26 mkv10z64vfm7 128 16 no 26 mkv10z128vlh7 128 16 no 46 mkv10z128vlf7 128 16 no 35 mkv10z128vlc7 2 128 16 no 26 mkv10z128vfm7 128 16 no 26 1. to confirm current availability of orderable part numbers, go to http://www.nxp.com and perform a part number search. 2. the 32-pin lqfp package supporting this part number is not yet available, however it is included in a package your way program for kinetis mcus. please visit http://www.nxp.com/kpyw for more details. 2 kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 nxp semiconductors
related resources type description resource selector guide the freescale solution advisor is a web-based tool that features interactive application wizards and a dynamic product selector. selector guide product brief the product brief contains concise overview/summary information to enable quick evaluation of a device for design suitability. kv10pb 1 reference manual the reference manual contains a comprehensive description of the structure and function (operation) of a device. kv10p48m75rm 1 data sheet the data sheet includes electrical characteristics and signal connections. this document kms user guide the kms user guide provides a comprehensive description of the features and functions of the kinetis motor suite solution. kinetis motor suite users guide (kms100ug) 1 kms api reference manual the kms api reference manual provides a comprehensive description of the api of the kinetis motor suite function blocks. kinetis motor suite api reference manual (kms100rm) 1 chip errata the chip mask set errata provides additional or corrective information for a particular device mask set. ? kv10z_1n81h 1 ? kinetis_v_0n63p 1 package drawing package dimensions are provided in package drawings. ? qfn 32-pin: 98asa00473d 1 ? lqfp 32-pin: 98ash70029a 1 ? lqfp 48-pin: 98ash00962a 1 ? lqfp 64-pin: 98ass23234w 1 1. to find the associated resource, go to http://www.nxp.com and perform a search using this term. kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 3 nxp semiconductors
legend not available on all parts. see ordering information table. figure 1. kv11 block diagram 4 kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 nxp semiconductors
table of contents 1 ratings................................................................................ 6 1.1 thermal handling ratings............................................. 6 1.2 moisture handling ratings............................................. 6 1.3 esd handling ratings................................................... 6 1.4 voltage and current operating ratings.......................... 6 2 general............................................................................... 7 2.1 ac electrical characteristics......................................... 7 2.2 nonswitching electrical specifications.......................... 8 2.2.1 voltage and current operating requirements.... 8 2.2.2 lvd and por operating requirements............ 9 2.2.3 voltage and current operating behaviors......... 10 2.2.4 power mode transition operating behaviors..... 10 2.2.5 kv11x power consumption operating behaviors......................................................... 11 2.2.6 emc radiated emissions operating behaviors.. 17 2.2.7 designing with radiated emissions in mind...... 18 2.2.8 capacitance attributes..................................... 18 2.3 switching specifications............................................... 18 2.3.1 device clock specifications.............................. 18 2.3.2 general switching specifications...................... 19 2.4 thermal specifications................................................. 20 2.4.1 thermal operating requirements...................... 20 2.4.2 thermal attributes............................................ 20 3 peripheral operating requirements and behaviors.............. 21 3.1 core modules............................................................... 21 3.1.1 swd electricals .............................................. 21 3.2 system modules.......................................................... 22 3.3 clock modules............................................................. 22 3.3.1 mcg specifications.......................................... 22 3.3.2 oscillator electrical specifications.................... 24 3.4 memories and memory interfaces................................ 26 3.4.1 flash electrical specifications........................... 26 3.5 security and integrity modules..................................... 28 3.6 analog.......................................................................... 28 3.6.1 adc electrical specifications............................ 28 3.6.2 cmp and 6-bit dac electrical specifications.... 32 3.6.3 12-bit dac electrical characteristics................ 34 3.7 timers.......................................................................... 37 3.8 communication interfaces........................................... 37 3.8.1 dspi switching specifications (limited voltage range)............................................................... 37 3.8.2 dspi switching specifications (full voltage range)............................................................... 40 3.8.3 i2c................................................................... 44 3.8.4 uart............................................................... 44 4 kinetis motor suite.............................................................. 44 5 dimensions.......................................................................... 44 5.1 obtaining package dimensions.................................... 44 6 pinout.................................................................................. 45 6.1 kv11 signal multiplexing and pin assignments.......... 45 6.2 kv11 pinouts............................................................... 48 7 ordering parts..................................................................... 52 7.1 determining valid orderable parts................................ 52 8 part identification................................................................. 52 8.1 description................................................................... 53 8.2 format.......................................................................... 53 8.3 fields........................................................................... 53 8.4 example....................................................................... 53 9 terminology and guidelines................................................ 54 9.1 definition: operating requirement................................ 54 9.2 definition: operating behavior..................................... 54 9.3 definition: attribute....................................................... 54 9.4 definition: rating.......................................................... 55 9.5 result of exceeding a rating........................................ 55 9.6 relationship between ratings and operating requirements................................................................ 56 9.7 guidelines for ratings and operating requirements...... 56 9.8 definition: typical value............................................... 57 9.9 typical value conditions............................................. 58 10 revision history................................................................... 58 kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 5 nxp semiconductors
1 ratings 1.1 thermal handling ratings symbol description min. max. unit notes t stg storage temperature C55 150 c 1 t sdr solder temperature, lead-free 260 c 2 1. determined according to jedec standard jesd22-a103, high temperature storage life . 2. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . 1.2 moisture handling ratings symbol description min. max. unit notes msl moisture sensitivity level 3 1 1. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . 1.3 esd handling ratings symbol description min. max. unit notes v hbm electrostatic discharge voltage, human-body model -2000 +2000 v 1 v cdm electrostatic discharge voltage, charged-device model -500 +500 v 2 i lat latch-up current at ambient temperature of 105 c -100 +100 ma 1. determined according to jedec standard jesd22-a114, electrostatic discharge (esd) sensitivity testing human body model (hbm) . 2. determined according to jedec standard jesd22-c101, field-induced charged-device model test method for electrostatic-discharge-withstand thresholds of microelectronic components . 1.4 voltage and current operating ratings ratings 6 kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 nxp semiconductors
symbol description min. max. unit v dd digital supply voltage C0.3 3.8 v i dd digital supply current 120 ma v io digital pin input voltage (except open drain pins) C0.3 vdd + 0.3 1 v open drain pins (ptc6 and ptc7) C0.3 5.5 v i d instantaneous maximum current single pin limit (applies to all port pins) C25 25 ma v dda analog supply voltage v dd C 0.3 v dd + 0.3 v 1. maximum value of v io (except open drain pins) must be 3.8 v. 2 general electromagnetic compatibility (emc) performance depends on the environment in which the mcu resides. board design and layout, circuit topology choices, location, characteristics of external components, and mcu software operation play a significant role in emc performance. see the following applications notes available on nxp.com for guidelines on optimizing emc performance. ? an2321: designing for board level electromagnetic compatibility ? an1050: designing for electromagnetic compatibility (emc) with hcmos microcontrollers ? an1263: designing for electromagnetic compatibility with single-chip microcontrollers ? an2764: improving the transient immunity performance of microcontroller- based applications ? an1259: system design and layout techniques for noise reduction in mcu- based systems 2.1 ac electrical characteristics unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. general kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 7 nxp semiconductors
80% 20% 50% v il input signal v ih fall time high low rise time midpoint1 the midpoint is v il + (v ih - v il ) / 2 figure 2. input signal measurement reference all digital i/o switching characteristics, unless otherwise specified, assume: 1. output pins ? have c l =30pf loads, ? are slew rate disabled, and ? are normal drive strength 2.2 nonswitching electrical specifications 2.2.1 voltage and current operating requirements table 1. voltage and current operating requirements symbol description min. max. unit notes v dd supply voltage 1.71 3.6 v v dda analog supply voltage 1.71 3.6 v v dd C v dda v dd -to-v dda differential voltage C0.1 0.1 v v ss C v ssa v ss -to-v ssa differential voltage C0.1 0.1 v v ih input high voltage ? 2.7 v v dd 3.6 v ? 1.71 v v dd 2.7 v 0.7 v dd 0.75 v dd v v v il input low voltage ? 2.7 v v dd 3.6 v ? 1.71 v v dd 2.7 v 0.35 v dd 0.3 v dd v v v hys input hysteresis 0.06 v dd v i icio pin negative dc injection currentsingle pin ? v in < v ss C0.3v -5 ma 1 table continues on the next page... general 8 kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 nxp semiconductors
table 1. voltage and current operating requirements (continued) symbol description min. max. unit notes i iccont contiguous pin dc injection currentregional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins ? negative current injection C25 ma v ram v dd voltage required to retain ram 1.2 v 1. all i/o pins are internally clamped to v ss through an esd protection diode. there is no diode connection to v dd . if v in greater than v io_min (= v ss -0.3 v) is observed, then there is no need to provide current limiting resistors at the pads. if this limit cannot be observed, then a current limiting resistor is required. the negative dc injection current limiting resistor is calculated as r = (v io_min - v in )/i icio . 2.2.2 lvd and por operating requirements table 2. v dd supply lvd and por operating requirements symbol description min. typ. max. unit notes v por falling v dd por detect voltage 0.8 1.1 1.5 v v lvdh falling low-voltage detect threshold high range (lvdv=01) 2.48 2.56 2.64 v v lvw1h v lvw2h v lvw3h v lvw4h low-voltage warning thresholds high range ? level 1 falling (lvwv=00) ? level 2 falling (lvwv=01) ? level 3 falling (lvwv=10) ? level 4 falling (lvwv=11) 2.62 2.72 2.82 2.92 2.70 2.80 2.90 3.00 2.78 2.88 2.98 3.08 v v v v 1 v hysh low-voltage inhibit reset/recover hysteresis high range 60 mv v lvdl falling low-voltage detect threshold low range (lvdv=00) 1.54 1.60 1.66 v v lvw1l v lvw2l v lvw3l v lvw4l low-voltage warning thresholds low range ? level 1 falling (lvwv=00) ? level 2 falling (lvwv=01) ? level 3 falling (lvwv=10) ? level 4 falling (lvwv=11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 v v v v 1 v hysl low-voltage inhibit reset/recover hysteresis low range 40 mv v bg bandgap voltage reference 0.97 1.00 1.03 v t lpo internal low power oscillator period factory trimmed 900 1000 1100 s 1. rising thresholds are falling threshold + hysteresis voltage general kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 9 nxp semiconductors
2.2.3 voltage and current operating behaviors table 3. voltage and current operating behaviors symbol description min. max. unit notes v oh output high voltage normal drive pad all port pins, except ptc6 and ptc7 ? 2.7 v v dd 3.6 v, i oh = C5 ma ? 1.71 v v dd 2.7 v, i oh = C1.5 ma v dd C 0.5 v dd C 0.5 v v v oh output high voltage high drive pad ptb0, ptb1, ptc3, ptc4, ptd4, ptd5, ptd6, ptd7 pins ? 2.7 v v dd 3.6 v, i oh = C18 ma ? 1.71 v v dd 2.7 v, i oh = C6 ma v dd C 0.5 v dd C 0.5 v v i oht output high current total for all ports 100 ma v ol output low voltage normal drive pad all port pins ? 2.7 v v dd 3.6 v, i ol = 5 ma ? 1.71 v v dd 2.7 v, i ol = 1.5 ma 0.5 0.5 v v v ol output low voltage high drive pad ptb0, ptb1, ptc3, ptc4, ptd4, ptd5, ptd6, ptd7 pins ? 2.7 v v dd 3.6 v, i ol = 18 ma ? 1.71 v v dd 2.7 v, i ol = 6 ma 0.5 0.5 v v i olt output low current total for all ports 100 ma i in input leakage current (per pin) for full temperature range 1 a i in input leakage current (per pin) at 25 c 0.025 a 1 i in input leakage current (total all pins) for full temperature range 41 a 1 i oz hi-z (off-state) leakage current (per pin) 1 a r pu internal pullup resistors 20 50 k 2 1. measured at v dd = 3.6 v 2. measured at v dd supply voltage = v dd min and vinput = v ss general 10 kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 nxp semiconductors
2.2.4 power mode transition operating behaviors all specifications except t por and vllsx run recovery times in the following table assume this clock configuration: ? cpu and system clocks = 75 mhz ? bus and flash clock = 25 mhz ? fei clock mode table 4. power mode transition operating behaviors symbol description min. typ. max. unit notes t por after a por event, amount of time from the point v dd reaches 1.8 v to execution of the first instruction across the operating temperature range of the chip. 300 s 1 ? vlls0 run 123 132 s ? vlls1 run 123 132 s ? vlls3 run 67 72 s ? vlps run 4 5 s ? stop run 4 5 s 1. normal boot ftfa_fopt[lpboot]=11 2.2.5 kv11x power consumption operating behaviors table 5. kv11x power consumption operating behaviors symbol description min. typ. max. unit notes i dda analog supply current 5 ma 1 i dd_run run mode current all peripheral clocks disabled, code executing from flash ? at 1.8 v 50 mhz (25 mhz bus) ? at 3.0 v 50 mhz (25 mhz bus) ? at 1.8 v 75 mhz (25 mhz bus) ? at 3.0 v 75 mhz (25 mhz bus) 5.3 5.4 7.2 7.3 6.2 6.3 8.3 8.3 ma ma ma ma target idd i dd_run run mode current all peripheral clocks enabled, code executing from flash target idd table continues on the next page... general kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 11 nxp semiconductors
table 5. kv11x power consumption operating behaviors (continued) symbol description min. typ. max. unit notes ? at 1.8 v 50 mhz ? at 3.0 v 50 mhz ? at 1.8 v 75 mhz ? at 3.0 v 75 mhz 8.5 8.5 11.6 11.7 9.7 9.8 13.0 13.2 ma ma ma ma i dd_wait wait mode high frequency 75 mhz current at 3.0 v all peripheral clocks disabled 4 ma i dd_wait wait mode reduced frequency 50 mhz current at 3.0 v all peripheral clocks disabled 3.4 ma i dd_vlpr very-low-power run mode current 4 mhz at 3.0 v all peripheral clocks disabled 268 a 4 mhz cpu speed, 1 mhz bus speed. i dd_vlpr very-low-power run mode current 4 mhz at 3.0 v all peripheral clocks enabled 437 a 4 mhz cpu speed, 1 mhz bus speed. i dd_vlpw very-low-power wait mode current at 3.0 v all peripheral clocks enabled 348.9 a 4 mhz cpu speed, 1 mhz bus speed. i dd_vlpw very-low-power wait mode current at 3.0 v all peripheral clocks disabled 173.4 a 4 mhz cpu speed, 1 mhz bus speed. i dd_stop stop mode current at 3.0 v ? -40 c to 25 c ? at 50 c ? at 70 c ? at 85 c ? at 105 c 247.2 260.7 286 324 422.7 286 300 312 353 494 a i dd_vlps very-low-power stop mode current at 3.0 v ? -40 c to 25 c ? at 50 c ? at 70 c ? at 85 c ? at 105 c 2.9 6.8 15.4 29.1 66.4 3 5.9 13 39 86 a i dd_vlls3 very-low-leakage stop mode 3 current at 3.0 v ? -40 c to 25 c ? at 50 c ? at 70 c 1.3 2 3.7 6.7 1.6 2.3 4.3 7.5 a table continues on the next page... general 12 kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 nxp semiconductors
table 5. kv11x power consumption operating behaviors (continued) symbol description min. typ. max. unit notes ? at 85 c ? at 105 c 15.1 16 i dd_vlls1 very-low-leakage stop mode 1 current at 3.0 v ? -40c to 25c ? at 50c ? at 70c ? at 85c ? at 105c 0.8 1.2 2.2 4.0 9.4 1.2 1.4 2.7 5.1 11.8 a i dd_vlls0 very-low-leakage stop mode 0 current (smc_stopctrl[porpo] = 0) at 3.0 v ? -40 c to 25 c ? at 50 c ? at 70 c ? at 85 c ? at 105 c 0.279 0.638 1.63 3.4 8.9 0.386 0.854 2.2 4.5 11.2 a i dd_vlls0 very-low-leakage stop mode 0 current (smc_stopctrl[porpo] = 1) at 3.0 v ? -40 c to 25 c ? at 50 c ? at 70 c ? at 85 c ? at 105 c 0.098 0.448 1.4 3.19 8.47 0.452 0.674 1.9 4.3 10.6 a 2 1. the analog supply current is the sum of the active or disabled current for each of the analog modules on the device. see each module's specification for its supply current. 2. no brownout table 6. low power mode peripheral adders typical value symbol description temperature (c) unit -40 25 50 70 85 105 i irefsten4mhz 4 mhz internal reference clock (irc) adder. measured by entering stop or vlps mode with 4 mhz irc enabled. 56 56 56 56 56 56 a i irefsten32khz 32 khz internal reference clock (irc) adder. measured by entering stop mode with the 32 khz irc enabled. 52 52 52 52 52 52 a table continues on the next page... general kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 13 nxp semiconductors
table 6. low power mode peripheral adders typical value (continued) symbol description temperature (c) unit -40 25 50 70 85 105 i erefsten4mhz external 4 mhz crystal clock adder. measured by entering stop or vlps mode with the crystal enabled. 206 228 237 245 251 258 ua i erefsten32khz external 32 khz crystal clock adder by means of the osc0_cr[erefsten and erefsten] bits. measured by entering all modes with the crystal enabled. vlls1 vlls3 vlps stop 440 440 510 510 490 490 560 560 540 540 560 560 560 560 560 560 570 570 610 610 580 580 680 680 na i cmp cmp peripheral adder measured by placing the device in vlls1 mode with cmp enabled using the 6-bit dac and a single external input for compare. includes 6-bit dac power consumption. 22 22 22 22 22 22 a i uart uart peripheral adder measured by placing the device in stop or vlps mode with selected clock source waiting for rx data at 115200 baud rate. includes selected clock source power consumption. mcgirclk (4 mhz internal reference clock) oscerclk (4 mhz external crystal) 66 214 66 237 66 246 66 254 66 260 66 268 a i spi spi peripheral adder measured by placing the device in stop or vlps mode with selected clock source waiting for rx data at 115200 baud rate. includes selected clock source power consumption. mcgirclk (4 mhz internal reference clock) oscerclk (4 mhz external crystal) 66 214 66 237 66 246 66 254 66 260 66 268 a i i2c i2c peripheral adder measured by placing the device in stop or vlps mode with selected clock source waiting for rx data at 115200 baud rate. includes selected clock source power consumption. mcgirclk (4 mhz internal reference clock) oscerclk (4 mhz external crystal) 66 214 66 237 66 246 66 254 66 260 66 268 a table continues on the next page... general 14 kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 nxp semiconductors
table 6. low power mode peripheral adders typical value (continued) symbol description temperature (c) unit -40 25 50 70 85 105 i ftm ftm peripheral adder measured by placing the device in stop or vlps mode with selected clock source configured for output compare generating 100hz clock signal. no load is placed on the i/o generating the clock signal. includes selected clock source and i/o switching currents. mcgirclk (4 mhz internal reference clock) oscerclk (4 mhz external crystal) 150 300 150 300 150 300 150 320 150 340 150 350 a i bg bandgap adder when bgen bit is set and device is placed in vlpx, lls, or vllsx mode. 45 45 45 45 45 45 a i adc adc peripheral adder combining the measured values at vdd and vdda by placing the device in stop or vlps mode. adc is configured for low power mode using the internal clock and continuous conversions. 366 366 366 366 366 366 a i wdog wdog peripheral adder measured by placing the device in stop or vlps mode with selected clock source waiting for rx data at 115200 baud rate. includes selected clock source power consumption. mcgirclk (4 mhz internal reference clock) oscerclk (4 mhz external crystal) 66 214 66 237 66 246 66 254 66 260 66 268 a 2.2.5.1 diagram: typical idd_run operating behavior the following data was measured under these conditions: ? mcg in fbe for run mode (except for 75 mhz which is in fee mode), and blpe for vlpr mode ? no gpios toggled ? code execution from flash with cache enabled ? for the alloff curve, all peripheral clocks are disabled except ftfa general kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 15 nxp semiconductors
figure 3. run mode supply current vs. core frequency general 16 kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 nxp semiconductors
figure 4. vlpr mode current vs. core frequency 2.2.6 emc radiated emissions operating behaviors table 7. emc radiated emissions operating behaviors symbol description frequency band (mhz) typ. unit notes v re1 radiated emissions voltage, band 1 0.15C50 15 dbv 1 , 2 v re2 radiated emissions voltage, band 2 50C150 17 dbv v re3 radiated emissions voltage, band 3 150C500 12 dbv v re4 radiated emissions voltage, band 4 500C1000 4 dbv v re_iec iec level 0.15C1000 m 2 , 3 1. determined according to iec standard 61967-1, integrated circuits - measurement of electromagnetic emissions, 150 khz to 1 ghz part 1: general conditions and definitions and iec standard 61967-2, integrated circuits - measurement of electromagnetic emissions, 150 khz to 1 ghz part 2: measurement of radiated emissionstem cell and wideband tem cell method . measurements were made while the microcontroller was running basic general kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 17 nxp semiconductors
application code. the reported emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each frequency range. 2. v dd = 3.3 v, t a = 25 c, f osc = 10 mhz (crystal), f sys = 75 mhz, f bus = 25 mhz 3. specified according to annex d of iec standard 61967-2, measurement of radiated emissionstem cell and wideband tem cell method 2.2.7 designing with radiated emissions in mind to find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. go to www.freescale.com . 2. perform a keyword search for emc design. 2.2.8 capacitance attributes table 8. capacitance attributes symbol description min. max. unit c in_a input capacitance: analog pins 7 pf c in_d input capacitance: digital pins 7 pf 2.3 switching specifications 2.3.1 device clock specifications table 9. device clock specifications symbol description min. max. unit notes normal run mode f sys system and core clock 48 mhz f bus bus clock 24 mhz f flash flash clock 24 mhz f lptmr lptmr clock 24 mhz high speed run mode f sys system and core clock 75 mhz f bus bus clock 25 mhz f flash flash clock 25 mhz f lptmr lptmr clock 25 mhz table continues on the next page... general 18 kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 nxp semiconductors
table 9. device clock specifications (continued) symbol description min. max. unit notes f ftm ftm clock 75 mhz vlpr mode f sys system and core clock 4 mhz f bus bus clock 1 mhz f flash flash clock 1 mhz f lptmr lptmr clock 25 mhz f erclk external reference clock 16 mhz f lptmr_pin lptmr clock 25 mhz f lptmr_ercl k lptmr external reference clock 16 mhz f osc_hi_2 oscillator crystal or resonator frequency high frequency mode (high range) (mcg_c2[range]=1x) 16 mhz 2.3.2 general switching specifications these general purpose specifications apply to all signals configured for gpio, uart, can, and i 2 c signals. table 10. general switching specifications symbol description min. max. unit notes gpio pin interrupt pulse width (digital glitch filter disabled) synchronous path 1.5 bus clock cycles 1 external reset and nmi pin interrupt pulse width asynchronous path 100 ns 2 gpio pin interrupt pulse width asynchronous path 16 ns 2 port rise and fall time fast slew rate 1.71 vdd 2.7 v 2.7 vdd 3.6 v 8 7 ns ns 3 port rise and fall time slow slew rate 1.71 vdd 2.7 v 2.7 vdd 3.6 v 15 25 ns ns 1. the greater synchronous and asynchronous timing must be met. 2. this is the shortest pulse that is guaranteed to be recognized. 3. for high drive pins with high drive enabled, load is 75pf; other pins load (low drive) is 25pf. general kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 19 nxp semiconductors
2.4 thermal specifications 2.4.1 thermal operating requirements table 11. thermal operating requirements symbol description min. max. unit t j die junction temperature C40 125 c t a ambient temperature 1 C40 105 c 1. maximum t a can be exceeded only if the user ensures that t j does not exceed maximum t j . the simplest method to determine t j is: t j = t a + r ja x chip power dissipation 2.4.2 thermal attributes table 12. thermal attributes board type symb ol description 64 lqfp 48 lqfp 32 lqfp 32 qfn unit notes single-layer (1s) r ja thermal resistance, junction to ambient (natural convection) 64 81 85 98 c/w 1 four-layer (2s2p) r ja thermal resistance, junction to ambient (natural convection) 46 57 57 34 c/w single-layer (1s) r jma thermal resistance, junction to ambient (200 ft./min. air speed) 52 68 72 82 c/w four-layer (2s2p) r jma thermal resistance, junction to ambient (200 ft./min. air speed) 39 51 50 28 c/w r jb thermal resistance, junction to board 28 35 33 14 c/w 2 r jc thermal resistance, junction to case 15 25 25 2.5 c/w 3 jt thermal characterization parameter, junction to package top outside center (natural convection) 2 7 7 8 c/w 4 1. determined according to jedec standard jesd51-2, integrated circuits thermal test method environmental conditionsnatural convection (still air) , or eia/jedec standard jesd51-6, integrated circuit thermal test method environmental conditionsforced convection (moving air) . general 20 kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 nxp semiconductors
2. determined according to jedec standard jesd51-8, integrated circuit thermal test method environmental conditionsjunction-to-board . 3. determined according to method 1012.1 of mil-std 883, test method standard, microcircuits , with the cold plate temperature used for the case temperature. the value includes the thermal resistance of the interface material between the top of the package and the cold plate. 4. determined according to jedec standard jesd51-2, integrated circuits thermal test method environmental conditionsnatural convection (still air) . 3 peripheral operating requirements and behaviors 3.1 core modules 3.1.1 swd electricals table 13. swd full voltage range electricals symbol description min. max. unit operating voltage 1.71 3.6 v j1 swd_clk frequency of operation ? serial wire debug 0 25 mhz j2 swd_clk cycle period 1/j1 ns j3 swd_clk clock pulse width ? serial wire debug 20 ns j4 swd_clk rise and fall times 3 ns j9 swd_dio input data setup time to swd_clk rise 10 ns j10 swd_dio input data hold time after swd_clk rise 0 ns j11 swd_clk high to swd_dio data valid 32 ns j12 swd_clk high to swd_dio high-z 5 ns j2 j3 j3 j4 j4 swd_clk (input) figure 5. serial wire clock input timing peripheral operating requirements and behaviors kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 21 nxp semiconductors
j11 j12 j11 j9 j10 input data valid output data valid output data valid swd_clk swd_dio swd_dio swd_dio swd_dio figure 6. serial wire data timing 3.2 system modules there are no specifications necessary for the device's system modules. 3.3 clock modules 3.3.1 mcg specifications table 14. mcg specifications symbol description min. typ. max. unit notes f ints_ft internal reference frequency (slow clock) factory trimmed at nominal v dd and 25 c 32.768 khz f ints_t internal reference frequency (slow clock) user trimmed 31.25 39.0625 khz fdco_res_t resolution of trimmed average dco output frequency at fixed voltage and temperature using sctrim and scftrim 0.3 0.6 %f dco 1 table continues on the next page... peripheral operating requirements and behaviors 22 kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 nxp semiconductors
table 14. mcg specifications (continued) symbol description min. typ. max. unit notes f dco_t total deviation of trimmed average dco output frequency over voltage and temperature +0.5/-0.7 2 %f dco 1 , 2 f dco_t total deviation of trimmed average dco output frequency over fixed voltage and temperature range of 0 - 70 c 0.4 1.5 %f dco 1 , 2 f intf_ft internal reference frequency (fast clock) factory trimmed at nominal v dd and 25 c 4 mhz f intf_ft frequency deviation of internal reference clock (fast clock) over temperature and voltage factory trimmed at nominal v dd and 25 c +1/-2 3 %f intf_ft 2 f intf_t internal reference frequency (fast clock) user trimmed at nominal v dd and 25 c 3 5 mhz f loc_low loss of external clock minimum frequency range = 00 (3/5) x f ints_t khz f loc_high loss of external clock minimum frequency range = 01, 10, or 11 (16/5) x f ints_t khz fll f fll_ref fll reference frequency range 31.25 39.0625 khz f dco dco output frequency range low range (drs = 00, dmx32 = 0) 640 f fll_ref 20 20.97 25 mhz 3 , 4 mid range (drs = 01, dmx32 = 0) 1280 f fll_ref 40 41.94 48 mhz mid range (drs = 10, dmx32 = 0) 1920 x f fll_ref 60 62.915 75 mhz f dco_t_dmx3 2 dco output frequency low range (drs = 00, dmx32 = 1) 732 f fll_ref 23.99 mhz 5 6 mid range (drs = 01, dmx32 = 1) 1464 f fll_ref 47.97 mhz mid range (drs = 10, dmx32 = 1) 2197 f fll_ref C 71.991 C mhz j cyc_fll fll period jitter ? f vco = 75 mhz 180 ps 7 t fll_acquire fll target frequency acquisition time 1 ms 8 1. this parameter is measured with the internal reference (slow clock) being used as a reference to the fll (fei clock mode). 2. the deviation is relative to the factory trimmed frequency at nominal v dd and 25 c, f ints_ft . 3. these typical values listed are with the slow internal reference clock (fei) using factory trim and dmx32 = 0. peripheral operating requirements and behaviors kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 23 nxp semiconductors
4. the resulting system clock frequencies must not exceed their maximum specified values. the dco frequency deviation ( f dco_t ) over voltage and temperature must be considered. 5. these typical values listed are with the slow internal reference clock (fei) using factory trim and dmx32 = 1. 6. the resulting clock frequency must not exceed the maximum specified clock frequency of the device. 7. this specification is based on standard deviation (rms) of period or frequency. 8. this specification applies to any time the fll reference source or reference divider is changed, trim value is changed, dmx32 bit is changed, drs bits are changed, or there is a change from fll disabled (blpe, blpi) to fll enabled (fei, fee, fbe, fbi). if a crystal/resonator is being used as the reference, this specification assumes it is already running. 3.3.2 oscillator electrical specifications 3.3.2.1 oscillator dc electrical specifications table 15. oscillator dc electrical specifications symbol description min. typ. max. unit notes v dd supply voltage 1.71 3.6 v i ddosc supply current low-power mode (hgo=0) ? 32 khz ? 4 mhz ? 8 mhz ? 16 mhz ? 24 mhz ? 32 mhz 500 200 300 950 1.2 1.5 na a a a ma ma 1 i ddosc supply current high gain mode (hgo=1) ? 4 mhz ? 8 mhz ? 16 mhz ? 24 mhz ? 32 mhz 500 600 2.5 3 4 a a ma ma ma 1 c x extal load capacitance 2 , 3 c y xtal load capacitance 2 , 3 r f feedback resistor low-frequency, low-power mode (hgo=0) m 2 , 4 feedback resistor low-frequency, high-gain mode (hgo=1) 10 m feedback resistor high-frequency, low-power mode (hgo=0) m feedback resistor high-frequency, high-gain mode (hgo=1) 1 m table continues on the next page... peripheral operating requirements and behaviors 24 kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 nxp semiconductors
table 15. oscillator dc electrical specifications (continued) symbol description min. typ. max. unit notes r s series resistor low-frequency, low-power mode (hgo=0) k series resistor low-frequency, high-gain mode (hgo=1) 200 k series resistor high-frequency, low-power mode (hgo=0) k series resistor high-frequency, high-gain mode (hgo=1) 0 k v pp 5 peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, low-power mode (hgo=0) 0.6 v peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, high-gain mode (hgo=1) v dd v peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, low-power mode (hgo=0) 0.6 v peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, high-gain mode (hgo=1) v dd v 1. v dd =3.3 v, temperature =25 c 2. see crystal or resonator manufacturer's recommendation 3. c x ,c y can be provided by using the integrated capacitors when the low frequency oscillator (range = 00) is used. for all other cases external capacitors must be used. 4. when low power mode is selected, r f is integrated and must not be attached externally. 5. the extal and xtal pins should only be connected to required oscillator components and must not be connected to any other devices. 3.3.2.2 oscillator frequency specifications table 16. oscillator frequency specifications symbol description min. typ. max. unit notes f osc_lo oscillator crystal or resonator frequency low- frequency mode (mcg_c2[range]=00) 32 40 khz f osc_hi_1 oscillator crystal or resonator frequency high-frequency mode (low range) (mcg_c2[range]=01) 3 8 mhz f osc_hi_2 oscillator crystal or resonator frequency high frequency mode (high range) (mcg_c2[range]=1x) 8 32 mhz f ec_extal input clock frequency (external clock mode) 50 mhz 1 , 2 t dc_extal input clock duty cycle (external clock mode) 40 50 60 % table continues on the next page... peripheral operating requirements and behaviors kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 25 nxp semiconductors
table 16. oscillator frequency specifications (continued) symbol description min. typ. max. unit notes t cst crystal startup time 32 khz low-frequency, low-power mode (hgo=0) 1000 ms 3 , 4 crystal startup time 32 khz low-frequency, high-gain mode (hgo=1) 250 ms crystal startup time 8 mhz high-frequency (mcg_c2[range]=01), low-power mode (hgo=0) 0.6 ms crystal startup time 8 mhz high-frequency (mcg_c2[range]=01), high-gain mode (hgo=1) 1 ms 1. other frequency limits may apply when external clock is being used as a reference for the fll. 2. when transitioning from fei or fbi to fbe mode, restrict the frequency of the input clock so that, when it is divided by frdiv, it remains within the limits of the dco input clock frequency. 3. proper pc board layout procedures must be followed to achieve specifications. 4. crystal startup time is defined as the time between the oscillator being enabled and the oscinit bit in the mcg_s register being set. note the 32 khz oscillator works in low power mode by default and cannot be moved into high power/gain mode. 3.4 memories and memory interfaces 3.4.1 flash electrical specifications this section describes the electrical characteristics of the flash memory module. 3.4.1.1 flash timing specifications program and erase the following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. table 17. nvm program/erase timing specifications symbol description min. typ. max. unit notes t hvpgm4 longword program high-voltage time 7.5 18 s t hversscr sector erase high-voltage time 13 113 ms 1 t hversall erase all high-voltage time 104 904 ms 1 1. maximum time based on expectations at cycling end-of-life. peripheral operating requirements and behaviors 26 kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 nxp semiconductors
3.4.1.2 flash timing specifications commands table 18. flash command timing specifications symbol description min. typ. max. unit notes t rd1sec2k read 1s section execution time (flash sector) 60 s 1 t pgmchk program check execution time 45 s 1 t rdrsrc read resource execution time 30 s 1 t pgm4 program longword execution time 65 145 s t ersscr erase flash sector execution time 14 114 ms 2 t rd1all read 1s all blocks execution time 0.9 ms 1 t rdonce read once execution time 30 s 1 t pgmonce program once execution time 100 s t ersall erase all blocks execution time 140 1150 ms 2 t vfykey verify backdoor access key execution time 30 s 1 1. assumes 25 mhz flash clock frequency. 2. maximum times for erase parameters based on expectations at cycling end-of-life. 3.4.1.3 flash high voltage current behaviors table 19. flash high voltage current behaviors symbol description min. typ. max. unit i dd_pgm average current adder during high voltage flash programming operation 2.5 12.0 ma i dd_ers average current adder during high voltage flash erase operation 1.5 8.0 ma 3.4.1.4 reliability specifications table 20. nvm reliability specifications symbol description min. typ. 1 max. unit notes program flash t nvmretp10k data retention after up to 10 k cycles 5 50 years t nvmretp1k data retention after up to 1 k cycles 20 100 years n nvmcycp cycling endurance 10 k 50 k cycles 2 1. typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25 c use profile. engineering bulletin eb618 does not apply to this technology. typical endurance defined in engineering bulletin eb619. 2. cycling endurance represents number of program/erase cycles at C40 c t j 125 c. peripheral operating requirements and behaviors kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 27 nxp semiconductors
3.5 security and integrity modules there are no specifications necessary for the device's security and integrity modules. 3.6 analog adc electrical specifications 3.6.1.1 16-bit adc operating conditions table 21. 16-bit adc operating conditions symbol description conditions min. typ. 1 max. unit notes v dda supply voltage absolute 1.71 3.6 v v dda supply voltage delta to v dd (v dd C v dda ) -100 0 +100 mv 2 v ssa ground voltage delta to v ss (v ss C v ssa ) -100 0 +100 mv 2 v refh adc reference voltage high 1.13 v dda v dda v v refl adc reference voltage low v ssa v ssa v ssa v v adin input voltage ? 16-bit differential mode ? all other modes vrefl vrefl 31/32 * vrefh vrefh v c adin input capacitance ? 16-bit mode ? 8-bit / 10-bit / 12-bit modes 8 4 10 5 pf r adin input resistance 2 5 k r as analog source resistance 13-bit / 12-bit modes f adck < 4 mhz 5 k 3 f adck adc conversion clock frequency 13-bit mode 1.0 24.0 mhz 4 f adck adc conversion clock frequency 16-bit mode 2.0 12.0 mhz 4 c rate adc conversion rate 13-bit modes no adc hardware averaging continuous conversions enabled, subsequent conversion time 20.000 1200 ksps 5 table continues on the next page... 3.6.1 adc electrical specifications 28 kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 nxp semiconductors
table 21. 16-bit adc operating conditions (continued) symbol description conditions min. typ. 1 max. unit notes c rate adc conversion rate 16-bit mode no adc hardware averaging continuous conversions enabled, subsequent conversion time 37.037 461.467 ksps 5 1. typical values assume v dda = 3.0 v, temp = 25 c, f adck = 1.0 mhz, unless otherwise stated. typical values are for reference only, and are not tested in production. 2. dc potential difference. 3. this resistance is external to mcu. to achieve the best results, the analog source resistance must be kept as low as possible. the results in this data sheet were derived from a system that had < 8 analog source resistance. the r as /c as time constant should be kept to < 1 ns. 4. to use the maximum adc conversion clock frequency, cfg2[adhsc] must be set and cfg1[adlpc] must be clear. 5. for guidelines and examples of conversion rate calculation, download the adc calculator tool . r as v as c as z as v adin z adin r adin r adin r adin r adin c adin pad leakage due to input protection input pin input pin input pin input pin simplified input pin equivalent circuit simplified channel select circuit adc sar engine figure 7. adc input impedance equivalency diagram 3.6.1.2 16-bit adc electrical characteristics table 22. 16-bit adc characteristics (v refh = v dda , v refl = v ssa ) symbol description conditions 1 . min. typ. 2 max. unit notes i dda_adc supply current 0.215 1.7 ma 3 table continues on the next page... adc electrical specifications kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 29 nxp semiconductors
table 22. 16-bit adc characteristics (v refh = v dda , v refl = v ssa ) (continued) symbol description conditions 1 . min. typ. 2 max. unit notes f adack adc asynchronous clock source ? adlpc = 1, adhsc = 0 ? adlpc = 1, adhsc = 1 ? adlpc = 0, adhsc = 0 ? adlpc = 0, adhsc = 1 1.2 2.4 3.0 4.4 2.4 4.0 5.2 6.2 3.9 6.1 7.3 9.5 mhz mhz mhz mhz t adack = 1/f adack sample time see reference manual chapter for sample times tue total unadjusted error ? 12-bit modes ? <12-bit modes 4 1.4 6.8 2.1 lsb 4 5 dnl differential non- linearity ? 12-bit modes ? <12-bit modes 0.7 0.2 C1.1 to +1.9 C0.3 to 0.5 lsb 4 5 inl integral non- linearity ? 12-bit modes ? <12-bit modes 1.0 0.5 C2.7 to +1.9 C0.7 to +0.5 lsb 4 5 e fs full-scale error ? 12-bit modes ? <12-bit modes C4 C1.4 C5.4 C1.8 lsb 4 v adin = v dda 5 e q quantization error ? 16-bit modes ? 13-bit modes C1 to 0 0.5 lsb 4 enob effective number of bits 16-bit differential mode ? avg = 32 ? avg = 4 16-bit single-ended mode ? avg = 32 ? avg = 4 12.8 11.9 12.2 11.4 14.5 13.8 13.7 13.1 bits bits bits bits 6 , 7 sinad signal-to-noise plus distortion see enob 6.02 enob + 1.76 db 7 thd total harmonic distortion 16-bit differential mode ? avg = 32 16-bit single-ended mode ? avg = 32 C97 C91 db db 7 , 8 sfdr spurious free dynamic range 16-bit differential mode 82 100 db 7 , 8 table continues on the next page... adc electrical specifications 30 kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 nxp semiconductors
table 22. 16-bit adc characteristics (v refh = v dda , v refl = v ssa ) (continued) symbol description conditions 1 . min. typ. 2 max. unit notes ? avg = 32 16-bit single-ended mode ? avg = 32 78 92 db e il input leakage error i in r as mv i in = leakage current (refer to the mcu's voltage and current operating ratings) temp sensor slope across the full temperature range of the device 1.55 1.62 1.69 mv/c 9 v temp25 temp sensor voltage 25 c 706 716 726 mv 9 1. all accuracy numbers assume the adc is calibrated with v refh = v dda 2. typical values assume v dda = 3.0 v, temp = 25 c, f adck = 2.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 3. the adc supply current depends on the adc conversion clock speed, conversion rate and adc_cfg1[adlpc] (low power). for lowest power operation, adc_cfg1[adlpc] must be set, the adc_cfg2[adhsc] bit must be clear with 1 mhz adc conversion clock speed. 4. 1 lsb = (v refh - v refl )/2 n 5. adc conversion clock < 16 mhz, max hardware averaging (avge = %1, avgs = %11) 6. input data is 100 hz sine wave. adc conversion clock < 12 mhz. 7. this data was collected with an external clock. 8. input data is 1 khz sine wave. adc conversion clock < 12 mhz. 9. adc conversion clock < 3 mhz adc electrical specifications kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 31 nxp semiconductors
typical adc 16-bit differential enob vs adc clock 100hz, 90% fs sine input enob adc clock frequency (mhz) 15.00 14.70 14.40 14.10 13.80 13.50 13.20 12.90 12.60 12.30 12.00 1 2 3 4 5 6 7 8 9 10 1211 hardware averaging disabled averaging of 4 samples averaging of 8 samples averaging of 32 samples figure 8. typical enob vs. adc_clk for 16-bit differential mode typical adc 16-bit single-ended enob vs adc clock 100hz, 90% fs sine input enob adc clock frequency (mhz) 14.00 13.75 13.25 13.00 12.75 12.50 12.00 11.75 11.50 11.25 11.00 1 2 3 4 5 6 7 8 9 10 1211 averaging of 4 samples averaging of 32 samples 13.50 12.25 figure 9. typical enob vs. adc_clk for 16-bit single-ended mode 3.6.2 cmp and 6-bit dac electrical specifications table 23. comparator and 6-bit dac electrical specifications symbol description min. typ. max. unit v dd supply voltage 1.71 3.6 v table continues on the next page... adc electrical specifications 32 kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 nxp semiconductors
table 23. comparator and 6-bit dac electrical specifications (continued) symbol description min. typ. max. unit i ddhs supply current, high-speed mode (en = 1, pmode = 1) 200 a i ddls supply current, low-speed mode (en = 1, pmode = 0) 20 a v ain analog input voltage v ss v dd v v aio analog input offset voltage 20 mv v h analog comparator hysteresis 1 ? cr0[hystctr] = 00 ? cr0[hystctr] = 01 ? cr0[hystctr] = 10 ? cr0[hystctr] = 11 5 10 20 30 mv mv mv mv v cmpoh output high v dd C 0.5 v v cmpol output low 0.5 v t dhs propagation delay, high-speed mode (en = 1, pmode = 1) 20 35 200 ns t dls propagation delay, low-speed mode (en = 1, pmode = 0) 80 100 600 ns analog comparator initialization delay 2 40 s i dac6b 6-bit dac current adder (enabled) 7 a inl 6-bit dac integral non-linearity C0.5 0.5 lsb 3 dnl 6-bit dac differential non-linearity C0.3 0.3 lsb 1. typical hysteresis is measured with input voltage range limited to 0.7 to v dd C 0.7 v. 2. comparator initialization delay is defined as the time between software writes to change control inputs (writes to dacen, vrsel, psel, msel, vosel) and the comparator output settling to a stable level. 3. 1 lsb = v reference /64 adc electrical specifications kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 33 nxp semiconductors
cmp hysteresis vs vinn 0 1 2 hystctr setting 000.00e+00 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 vinn (v) 3 30.00e-03 20.00e-03 10.00e-03 40.00e-03 50.00e-03 60.00e-03 70.00e-03 80.00e-03 90.00e-03 cmp hysteresis (v) figure 10. typical hysteresis vs. vin level (v dd = 3.3 v, pmode = 0) 180.00e-03 cmp hysteresis vs vinn 0 1 2 hystctr setting 60.00e-03 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 cmp hysteresis (v) vinn (v) 3 -20.00e-03 000.00e+00 20.00e-03 40.00e-03 80.00e-03 100.00e-03 120.00e-03 140.00e-03 160.00e-03 figure 11. typical hysteresis vs. vin level (v dd = 3.3 v, pmode = 1) 3.6.3 12-bit dac electrical characteristics adc electrical specifications 34 kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 nxp semiconductors
3.6.3.1 12-bit dac operating requirements table 24. 12-bit dac operating requirements symbol desciption min. max. unit notes v dda supply voltage 1.71 3.6 v v dacr reference voltage 1.13 3.6 v 1 c l output load capacitance 100 pf 2 i l output load current 1 ma 1. the dac reference can be selected to be v dda or v refh . 2. a small load capacitance (47 pf) can improve the bandwidth performance of the dac. 3.6.3.2 12-bit dac operating behaviors table 25. 12-bit dac operating behaviors symbol description min. typ. max. unit notes i dda_dacl p supply current low-power mode 150 a i dda_dach p supply current high-speed mode 700 a t daclp full-scale settling time (0x080 to 0xf7f) low-power mode 100 200 s 1 t dachp full-scale settling time (0x080 to 0xf7f) high-power mode 15 30 s 1 t ccdaclp code-to-code settling time (0xbf8 to 0xc08)high-speed mode 1 s 1 low-power mode 5 s 1 v dacoutl dac output voltage range low high- speed mode, no load, dac set to 0x000 100 mv v dacouth dac output voltage range high high- speed mode, no load, dac set to 0xfff v dacr ?100 v dacr mv inl integral non-linearity error high speed mode 8 lsb 2 dnl differential non-linearity error v dacr > 2 v 1 lsb 3 dnl differential non-linearity error v dacr = vref_out 1 lsb 4 v offset offset error 0.4 0.8 %fsr 5 e g gain error 0.1 0.6 %fsr 5 psrr power supply rejection ratio, v dda 2.4 v 60 90 db t co temperature coefficient offset voltage 3.7 v/c 6 t ge temperature coefficient gain error 0.000421 %fsr/c rop output resistance (load = 3 k) 250 sr slew rate -80h f7fh 80h v/s table continues on the next page... adc electrical specifications kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 35 nxp semiconductors
table 25. 12-bit dac operating behaviors (continued) symbol description min. typ. max. unit notes ? high power (sp hp ) ? low power (sp lp ) 1.2 0.05 1.7 0.12 bw 3db bandwidth ? high power (sp hp ) ? low power (sp lp ) 550 40 khz 1. settling within 1 lsb 2. the inl is measured for 0 + 100 mv to v dacr ?100 mv 3. the dnl is measured for 0 + 100 mv to v dacr ?100 mv 4. the dnl is measured for 0 + 100 mv to v dacr ?100 mv with v dda > 2.4 v 5. calculated by a best fit curve from v ss + 100 mv to v dacr ? 100 mv 6. v dda = 3.0 v, reference select set for v dda (dacx_co:dacrfs = 1), high power mode (dacx_c0:lpen = 0), dac set to 0x800, temperature range is across the full range of the device digital code dac12 inl (lsb) 0 500 1000 1500 2000 2500 3000 3500 4000 2 4 6 8 -2 -4 -6 -8 0 figure 12. typical inl error vs. digital code adc electrical specifications 36 kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 nxp semiconductors
temperature c dac12 mid level code voltage 25 55 85 105 125 1.499 -40 1.4985 1.498 1.4975 1.497 1.4965 1.496 figure 13. offset at half scale vs. temperature 3.7 timers see general switching specifications . 3.8 communication interfaces adc electrical specifications kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 37 nxp semiconductors
3.8.1 dspi switching specifications (limited voltage range) the dma serial peripheral interface (dspi) provides a synchronous serial bus with master and slave operations. many of the transfer attributes are programmable. the tables below provide dspi timing characteristics for classic spi timing modes. refer to the dspi chapter of the reference manual for information on the modified transfer formats used for communicating with slower peripheral devices. table 26. master mode dspi timing (limited voltage range) symbol description min. max. unit notes operating voltage 2.7 3.6 v frequency of operation 25 mhz 1 ds1 dspi_sck output cycle time 2 x t bus C ns 2 ds2 dspi_sck output high/low time (t sck /2) C 2 (t sck /2) + 2 ns ds3 dspi_pcs n valid to dspi_sck delay (t sck /2) C 2 C ns 3 ds4 dspi_sck to dspi_pcs n invalid delay (t sck /2) C 2 C ns 4 ds5 dspi_sck to dspi_sout valid C 8.7 ns ds6 dspi_sck to dspi_sout invalid C2 ? ns ds7 dspi_sin to dspi_sck input setup 17 C ns ds8 dspi_sck to dspi_sin input hold 0 C ns frequency of operation C 25 mhz 5 ds1 dspi_sck output cycle time 2 x t bus C ns 2 ds2 dspi_sck output high/low time (t sck /2) C 2 (t sck /2) + 2 ns ds3 dspi_pcs n valid to dspi_sck delay (t sck /2) C 2 C ns 3 ds4 dspi_sck to dspi_pcs n invalid delay (t sck /2) C 2 C ns 4 ds5 dspi_sck to dspi_sout valid C 14.7 ns ds6 dspi_sck to dspi_sout invalid C2 ? ns ds7 dspi_sin to dspi_sck input setup 17 C ns ds8 dspi_sck to dspi_sin input hold 0 C ns frequency of operation C 37.5 mhz 6 ds1 dspi_sck output cycle time 2 x t bus C ns 2 ds2 dspi_sck output high/low time (t sck /2) C 2 (t sck /2) + 2 ns ds3 dspi_pcs n valid to dspi_sck delay (t sck /2) C 2 C ns 3 ds4 dspi_sck to dspi_pcs n invalid delay (t sck /2) C 2 C ns 4 ds5 dspi_sck to dspi_sout valid C 8.7 ns ds6 dspi_sck to dspi_sout invalid C2 ? ns table continues on the next page... adc electrical specifications 38 kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 nxp semiconductors
table 26. master mode dspi timing (limited voltage range) (continued) symbol description min. max. unit notes ds7 dspi_sin to dspi_sck input setup 13 C ns ds8 dspi_sck to dspi_sin input hold 0 C ns 1. normal pads 2. the spi module is clocked by the system clock 3. the delay is programmable in spix_ctarn[pssck] and spix_ctarn[cssck]. 4. the delay is programmable in spix_ctarn[pasc] and spix_ctarn[asc]. 5. open drain pads: sin: ptc7, sout:ptc6 6. fast pads: sin: ptd7, sout:ptd6, sck: ptd5, pcs:ptd4 ds3 ds4 ds1 ds2 ds7 ds8 first data last data ds5 first data data last data ds6 data dspi_pcsn dspi_sck (cpol=0) dspi_sin dspi_sout figure 14. dspi classic spi timing master mode table 27. slave mode dspi timing (limited voltage range) symbol description min. max. unit notes operating voltage 2.7 3.6 v frequency of operation C 12.5 mhz 1 ds9 dspi_sck input cycle time 4 x t bus C ns 2 ds10 dspi_sck input high/low time (t sck /2) C 2 (t sck /2) + 2 ns ds11 dspi_sck to dspi_sout valid C 21 ns ds12 dspi_sck to dspi_sout invalid 0 C ns ds13 dspi_sin to dspi_sck input setup 2.2 C ns ds14 dspi_sck to dspi_sin input hold 7 C ns ds15 dspi_ss active to dspi_sout driven C 15 ns ds16 dspi_ss inactive to dspi_sout not driven C 15 ns frequency of operation C 12.5 mhz 3 ds9 dspi_sck input cycle time 4 x t bus ns 2 ds10 dspi_sck input high/low time (t sck /2) C 2 (t sck /2) + 2 ns ds11 dspi_sck to dspi_sout valid C 27 ns ds12 dspi_sck to dspi_sout invalid 0 C ns table continues on the next page... adc electrical specifications kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 39 nxp semiconductors
table 27. slave mode dspi timing (limited voltage range) (continued) symbol description min. max. unit notes ds13 dspi_sin to dspi_sck input setup 2.2 C ns ds14 dspi_sck to dspi_sin input hold 7 C ns ds15 dspi_ss active to dspi_sout driven C 15 ns ds16 dspi_ss inactive to dspi_sout not driven C 21 ns frequency of operation C 18.75 mhz 4 ds9 dspi_sck input cycle time 4 x t bus ns 2 ds10 dspi_sck input high/low time (t sck /2) C 2 (t sck /2) + 2 ns ds11 dspi_sck to dspi_sout valid C 17 ns ds12 dspi_sck to dspi_sout invalid 0 C ns ds13 dspi_sin to dspi_sck input setup 2.2 C ns ds14 dspi_sck to dspi_sin input hold 7 C ns ds15 dspi_ss active to dspi_sout driven C 15 ns ds16 dspi_ss inactive to dspi_sout not driven C 11 ns 1. normal pads 2. the spi module is clocked by the system clock 3. open drain pads: sin: ptc7, sout:ptc6 4. fast pads: sin: ptd7, sout:ptd6, sck: ptd5, pcs:ptd4 first data last data first data data last data data ds15 ds10 ds9 ds16 ds11 ds12 ds14 ds13 dspi_ss dspi_sck (cpol=0) dspi_sout dspi_sin figure 15. dspi classic spi timing slave mode adc electrical specifications 40 kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 nxp semiconductors
3.8.2 dspi switching specifications (full voltage range) the dma serial peripheral interface (dspi) provides a synchronous serial bus with master and slave operations. many of the transfer attributes are programmable. the tables below provides dspi timing characteristics for classic spi timing modes. refer to the dspi chapter of the reference manual for information on the modified transfer formats used for communicating with slower peripheral devices. table 28. master mode dspi timing (full voltage range) symbol description min. max. unit notes operating voltage 1.7 3.6 v 1 frequency of operation C 18.75 mhz 2 ds1 dspi_sck output cycle time 2 x t bus C ns 3 ds2 dspi_sck output high/low time (t sck /2) C 4 (t sck /2) + 4 ns ds3 dspi_pcs n valid to dspi_sck delay (t sck /2) C 4 C ns 4 ds4 dspi_sck to dspi_pcs n invalid delay (t sck /2) C 4 C ns 5 ds5 dspi_sck to dspi_sout valid C 10 ds6 dspi_sck to dspi_sout invalid C7.8 C ns ds7 dspi_sin to dspi_sck input setup 24 C ns ds8 dspi_sck to dspi_sin input hold 0 C ns frequency of operation C 18.75 mhz 6 ds1 dspi_sck output cycle time 2 x t bus C ns 3 ds2 dspi_sck output high/low time (t sck /2) C 4 (t sck /2) + 4 ns ds3 dspi_pcs n valid to dspi_sck delay (t sck /2) C 4 C ns 4 ds4 dspi_sck to dspi_pcs n invalid delay (t sck /2) C 4 C ns 5 ds5 dspi_sck to dspi_sout valid C 26 ds6 dspi_sck to dspi_sout invalid C7.8 C ns ds7 dspi_sin to dspi_sck input setup 24 C ns ds8 dspi_sck to dspi_sin input hold 0 C ns table continues on the next page... adc electrical specifications kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 41 nxp semiconductors
table 28. master mode dspi timing (full voltage range) (continued) symbol description min. max. unit notes frequency of operation C 25 mhz 7 ds1 dspi_sck output cycle time 2 x t bus C ns 3 ds2 dspi_sck output high/low time (t sck /2) C 4 (t sck /2) + 4 ns ds3 dspi_pcs n valid to dspi_sck delay (t sck /2) C 4 C ns 4 ds4 dspi_sck to dspi_pcs n invalid delay (t sck /2) C 4 C ns 5 ds5 dspi_sck to dspi_sout valid C 10 ds6 dspi_sck to dspi_sout invalid C7.8 C ns ds7 dspi_sin to dspi_sck input setup 17 C ns ds8 dspi_sck to dspi_sin input hold 0 C ns 1. the dspi module can operate across the entire operating voltage for the processor, but to run across the full voltage range the maximum frequency of operation is reduced. 2. normal pads 3. the spi module is clocked by the system clock 4. the delay is programmable in spix_ctarn[pssck] and spix_ctarn[cssck]. 5. the delay is programmable in spix_ctarn[pasc] and spix_ctarn[asc] 6. open drain pads: sin: ptc7, sout:ptc6 7. fast pads: sin: ptd7, sout:ptd6, sck: ptd5, pcs:ptd4 ds3 ds4 ds1 ds2 ds7 ds8 first data last data ds5 first data data last data ds6 data dspi_pcsn dspi_sck (cpol=0) dspi_sin dspi_sout figure 16. dspi classic spi timing master mode table 29. slave mode dspi timing (full voltage range) symbol description min. max. unit notes operating voltage 1.7 3.6 v frequency of operation C 9.375 mhz 1 table continues on the next page... adc electrical specifications 42 kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 nxp semiconductors
table 29. slave mode dspi timing (full voltage range) (continued) symbol description min. max. unit notes ds9 dspi_sck input cycle time 4 x t bus ns 2 ds10 dspi_sck input high/low time (t sck /2) C 4 (t sck /2) + 4 ns ds11 dspi_sck to dspi_sout valid C 27.8 ns ds12 dspi_sck to dspi_sout invalid 0 C ns ds13 dspi_sin to dspi_sck input setup 2.7 C ns ds14 dspi_sck to dspi_sin input hold 7 C ns ds15 dspi_ss active to dspi_sout driven C 22 ns ds16 dspi_ss inactive to dspi_sout not driven C 22 ns frequency of operation C 9.375 mhz 3 ds9 dspi_sck input cycle time 4 x t bus ns 2 ds10 dspi_sck input high/low time (t sck /2) C 4 (t sck /2) + 4 ns ds11 dspi_sck to dspi_sout valid C 43.8 ns ds12 dspi_sck to dspi_sout invalid 0 C ns ds13 dspi_sin to dspi_sck input setup 2.7 C ns ds14 dspi_sck to dspi_sin input hold 7 C ns ds15 dspi_ss active to dspi_sout driven C 22 ns ds16 dspi_ss inactive to dspi_sout not driven C 38 ns frequency of operation 12.5 mhz 4 ds9 dspi_sck input cycle time 4 x t bus ns 2 ds10 dspi_sck input high/low time (t sck /2) C 4 (t sck /2) + 4 ns ds11 dspi_sck to dspi_sout valid C 20.8 ns ds12 dspi_sck to dspi_sout invalid 0 C ns ds13 dspi_sin to dspi_sck input setup 2.7 C ns ds14 dspi_sck to dspi_sin input hold 7 C ns ds15 dspi_ss active to dspi_sout driven C 22 ns ds16 dspi_ss inactive to dspi_sout not driven C 15 ns 1. normal pads 2. the spi module is clocked by the system clock 3. open drain pads: sin: ptc7, sout:ptc6 4. fast pads: sin: ptd7, sout:ptd6, sck: ptd5, pcs:ptd4 adc electrical specifications kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 43 nxp semiconductors
first data last data first data data last data data ds15 ds10 ds9 ds16 ds11 ds12 ds14 ds13 dspi_ss dspi_sck (cpol=0) dspi_sout dspi_sin figure 17. dspi classic spi timing slave mode 3.8.3 i 2 c see general switching specifications . 3.8.4 uart see general switching specifications . 4 kinetis motor suite kinetis motor suite is a bundled software solution that enables the rapid configuration of motor drive systems, and accelerates development of the final motor drive application. several members of the kv1x family are enabled with kinetis motor suite. the enabled devices can be identified within the orderable part numbers in this table . for more information refer to kinetis motor suite user's guide (kms100ug ) and kinetis motor suite api reference manual (kms100rm , 1 ). 5 dimensions 1. to find the associated resource, go to http://www.nxp.com and perform a search using this term. kinetis motor suite 44 kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 nxp semiconductors
5.1 obtaining package dimensions package dimensions are provided in package drawings. to find a package drawing, go to www.nxp.com and perform a keyword search for the drawings document number: if you want the drawing for this package then use this document number 32-pin qfn 98asa00473d 32-pin lqfp 1 98ash70029a 48-pin lqfp 98ash00962a 64-pin lqfp 98ass23234w 1. the 32-pin lqfp package for this product is not yet available, however it is included in a package your way program for kinetis mcus. please visit http://www.nxp.com/kpyw for more details. 6 pinout 6.1 kv11 signal multiplexing and pin assignments the following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. the port control module is responsible for selecting which alt functionality is available on each pin. note ? ptb0, ptb1, ptc3, ptc4, ptd4, ptd5, ptd6, ptd7 are high current pins. ? ptc6 and ptc7 have open drain outputs 64 lqfp 48 qfp 32 qfn 32 lqfp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 7 7 vdda/ vrefh vdda/ vrefh vdda/ vrefh 8 8 vrefl/ vssa vrefl/ vssa vrefl/ vssa 1 pte0 adc1_se12 adc1_se12 pte0 uart1_tx 2 pte1/ llwu_p0 adc1_se13 adc1_se13 pte1/ llwu_p0 uart1_rx 3 1 1 1 vdd vdd vdd 4 2 2 2 vss vss vss 5 3 3 3 pte16 adc0_se1/ adc0_dp1/ adc1_se0 adc0_se1/ adc0_dp1/ adc1_se0 pte16 spi0_pcs0 uart1_tx ftm_ clkin0 ftm0_flt3 pinout kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 45 nxp semiconductors
64 lqfp 48 qfp 32 qfn 32 lqfp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 6 4 4 4 pte17/ llwu_p19 adc0_dm1/ adc0_se5/ adc1_se5 adc0_dm1/ adc0_se5/ adc1_se5 pte17/ llwu_p19 spi0_sck uart1_rx ftm_ clkin1 lptmr0_ alt3 7 5 5 5 pte18/ llwu_p20 adc0_se6/ adc1_se1/ adc1_dp1 adc0_se6/ adc1_se1/ adc1_dp1 pte18/ llwu_p20 spi0_sout uart1_ cts_b i2c0_sda spi0_sin 8 6 6 6 pte19 adc0_se7/ adc1_se7/ adc1_dm1 adc0_se7/ adc1_se7/ adc1_dm1 pte19 spi0_sin uart1_ rts_b i2c0_scl spi0_sout 9 7 pte20 adc0_se0/ adc0_dp0 adc0_se0/ adc0_dp0 pte20 ftm1_ch0 uart0_tx 10 8 pte21 adc0_se4/ adc0_dm0 adc0_se4/ adc0_dm0 pte21 ftm1_ch1 uart0_rx 11 pte22 adc0_se12 adc0_se12 pte22 12 pte23 adc0_se13 adc0_se13 pte23 13 9 vdda vdda vdda 14 10 vrefh vrefh vrefh 15 11 vrefl vrefl vrefl 16 12 vssa vssa vssa 17 13 pte29 cmp1_in5/ cmp0_in5 cmp1_in5/ cmp0_in5 pte29 ftm0_ch2 ftm_ clkin0 18 14 9 9 pte30 adc1_se4/ cmp1_in4/ dac0_out adc1_se4/ cmp1_in4/ dac0_out pte30 ftm0_ch3 ftm_ clkin1 19 pte31 adc0_se14/ cmp0_in4 adc0_se14/ cmp0_in4 pte31 20 15 10 10 pte24 disabled pte24 can0_tx ftm0_ch0 i2c0_scl ewm_out_ b 21 16 11 11 pte25/ llwu_p21 disabled pte25/ llwu_p21 can0_rx ftm0_ch1 i2c0_sda ewm_in 22 17 12 12 pta0 swd_clk swd_clk pta0 uart0_ cts_b ftm0_ch5 ewm_in swd_clk 23 18 13 13 pta1 disabled pta1 uart0_rx ftm2_ch0 cmp0_out ftm2_qd_ pha ftm1_ch1 ftm4_ch0 24 19 14 14 pta2 disabled pta2 uart0_tx ftm2_ch1 cmp1_out ftm2_qd_ phb ftm1_ch0 ftm4_ch1 25 20 15 15 pta3 swd_dio swd_dio pta3 uart0_ rts_b ftm0_ch0 ftm2_flt0 ewm_out_ b swd_dio 26 21 16 16 pta4/ llwu_p3 nmi_b nmi_b pta4/ llwu_p3 ftm0_ch1 ftm4_flt0 ftm0_flt3 nmi_b 27 pta5 disabled pta5 ftm0_ch2 ftm5_flt0 28 pta12 disabled pta12 can0_tx ftm1_ch0 ftm1_qd_ pha 29 pta13/ llwu_p4 disabled pta13/ llwu_p4 can0_rx ftm1_ch1 ftm1_qd_ phb 30 22 vdd vdd vdd pinout 46 kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 nxp semiconductors
64 lqfp 48 qfp 32 qfn 32 lqfp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 31 23 vss vss vss 32 24 17 17 pta18 extal0 extal0 pta18 ftm0_flt2 ftm_ clkin0 ftm3_ch2 33 25 18 18 pta19 xtal0 xtal0 pta19 ftm0_flt0 ftm1_flt0 ftm_ clkin1 lptmr0_ alt1 34 26 19 19 pta20 reset_b pta20 reset_b 35 27 20 20 ptb0/ llwu_p5 adc0_se8/ adc1_se8 adc0_se8/ adc1_se8 ptb0/ llwu_p5 i2c0_scl ftm1_ch0 ftm1_qd_ pha uart0_rx 36 28 21 21 ptb1 adc0_se9/ adc1_se9 adc0_se9/ adc1_se9 ptb1 i2c0_sda ftm1_ch1 ftm0_flt2 ewm_in ftm1_qd_ phb uart0_tx 37 29 ptb2 adc0_se10/ adc1_se10/ adc1_dm2 adc0_se10/ adc1_se10/ adc1_dm2 ptb2 i2c0_scl uart0_ rts_b ftm0_flt1 ftm0_flt3 38 30 ptb3 adc1_se2/ adc1_dp2 adc1_se2/ adc1_dp2 ptb3 i2c0_sda uart0_ cts_b ftm0_flt0 39 31 ptb16 disabled ptb16 uart0_rx ftm_ clkin2 can0_tx ewm_in 40 32 ptb17 disabled ptb17 uart0_tx ftm_ clkin1 can0_rx ewm_out_ b 41 ptb18 disabled ptb18 can0_tx ftm3_ch2 42 ptb19 disabled ptb19 can0_rx ftm3_ch3 43 33 ptc0 adc1_se11 adc1_se11 ptc0 spi0_pcs4 pdb_ extrg0 cmp0_out ftm0_flt0 spi0_pcs0 44 34 22 22 ptc1/ llwu_p6 adc1_se3 adc1_se3 ptc1/ llwu_p6 spi0_pcs3 uart1_ rts_b ftm0_ch0 ftm2_ch0 45 35 23 23 ptc2 adc0_se11/ cmp1_in0 adc0_se11/ cmp1_in0 ptc2 spi0_pcs2 uart1_ cts_b ftm0_ch1 ftm2_ch1 46 36 24 24 ptc3/ llwu_p7 cmp1_in1 cmp1_in1 ptc3/ llwu_p7 spi0_pcs1 uart1_rx ftm0_ch2 clkout ftm3_flt0 47 vss vss vss 48 vdd vdd vdd 49 37 25 25 ptc4/ llwu_p8 disabled ptc4/ llwu_p8 spi0_pcs0 uart1_tx ftm0_ch3 cmp1_out 50 38 26 26 ptc5/ llwu_p9 disabled ptc5/ llwu_p9 spi0_sck lptmr0_ alt2 cmp0_out ftm0_ch2 51 39 27 27 ptc6/ llwu_p10 cmp0_in0 cmp0_in0 ptc6/ llwu_p10 spi0_sout pdb_ extrg1 uart0_rx i2c0_scl 52 40 28 28 ptc7 cmp0_in1 cmp0_in1 ptc7 spi0_sin uart0_tx i2c0_sda 53 ptc8 adc1_se14/ cmp0_in2 adc1_se14/ cmp0_in2 ptc8 ftm3_ch4 54 ptc9 adc1_se15/ cmp0_in3 adc1_se15/ cmp0_in3 ptc9 ftm3_ch5 55 ptc10 adc1_se16 adc1_se16 ptc10 ftm5_ch0 ftm5_qd_ pha pinout kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 47 nxp semiconductors
64 lqfp 48 qfp 32 qfn 32 lqfp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 56 ptc11/ llwu_p11 adc1_se17 adc1_se17 ptc11/ llwu_p11 ftm5_ch1 ftm5_qd_ phb 57 41 ptd0/ llwu_p12 disabled ptd0/ llwu_p12 spi0_pcs0 uart0_ cts_b ftm0_ch0 uart1_rx ftm3_ch0 58 42 ptd1 adc0_se2 adc0_se2 ptd1 spi0_sck uart0_ rts_b ftm0_ch1 uart1_tx ftm3_ch1 59 43 ptd2/ llwu_p13 disabled ptd2/ llwu_p13 spi0_sout uart0_rx ftm0_ch2 ftm3_ch2 i2c0_scl 60 44 ptd3 disabled ptd3 spi0_sin uart0_tx ftm0_ch3 ftm3_ch3 i2c0_sda 61 45 29 29 ptd4/ llwu_p14 disabled ptd4/ llwu_p14 spi0_pcs1 uart0_ rts_b ftm0_ch4 ftm2_ch0 ewm_in spi0_pcs0 62 46 30 30 ptd5 adc0_se3 adc0_se3 ptd5 spi0_pcs2 uart0_ cts_b ftm0_ch5 ftm2_ch1 ewm_out_ b spi0_sck 63 47 31 31 ptd6/ llwu_p15 adc1_se6 adc1_se6 ptd6/ llwu_p15 ftm4_ch0 uart0_rx ftm0_ch0 ftm1_ch0 ftm0_flt0 spi0_sout 64 48 32 32 ptd7 disabled ptd7 ftm4_ch1 uart0_tx ftm0_ch1 ftm1_ch1 ftm0_flt1 spi0_sin 6.2 kv11 pinouts the following figure shows the pinout diagram for the devices supported by this document. many signals may be multiplexed onto a single pin. to determine what signals can be used on which pin, see the previous section. pinout 48 kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 nxp semiconductors
pte24 pte31 pte30 pte29 vssa vrefl vrefh vdda pte23 pte22 pte21 pte20 pte19 pte18/llwu_p20 pte17/llwu_p19 pte16 vss vdd pte1/llwu_p0 pte0 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 64 63 62 61 ptd7 ptd6/llwu_p15 ptd5 ptd4/llwu_p14 ptd3 ptd2/llwu_p13 ptd1 ptd0/llwu_p12 ptc11/llwu_p11 ptc10 ptc9 ptc8 ptc7 ptc6/llwu_p10 ptc5/llwu_p9 ptc4/llwu_p8 vdd vss ptc3/llwu_p7 ptc2 ptc1/llwu_p6 ptc0 ptb19 ptb18 ptb17 ptb16 ptb3 ptb2 ptb1 ptb0/llwu_p5 pta20 pta19 pta18 vss vdd pta13/llwu_p4 pta12 pta5 pta4/llwu_p3 pta3 pta2 pta1 pta0 pte25/llwu_p21 figure 18. 64 lqfp pinout diagram pinout kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 49 nxp semiconductors
vssa vrefl vrefh vdda pte21 pte20 pte19 pte18/llwu_p20 pte17/llwu_p19 pte16 vss vdd 12 11 10 9 8 7 6 5 4 3 2 1 48 47 46 45 44 43 42 41 40 39 38 37 ptd7 ptd6/llwu_p15 ptd5 ptd4/llwu_p14 ptd3 ptd2/llwu_p13 ptd1 ptd0/llwu_p12 ptc7 ptc6/llwu_p10 ptc5/llwu_p9 ptc4/llwu_p8 36 35 34 33 ptc3/llwu_p7 ptc2 ptc1/llwu_p6 ptc0 32 31 30 29 28 27 26 25 ptb17 ptb16 ptb3 ptb2 ptb1 ptb0/llwu_p5 pta20 pta19 pta3 pta2 pta1 pta0 24 23 22 21 20 19 18 17 pte25/llwu_p21 pte24 pte30 pte29 16 15 14 13 pta18 vss vdd pta4/llwu_p3 figure 19. 48 qfp pinout diagram pinout 50 kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 nxp semiconductors
32 31 30 29 28 27 26 25 ptd7 ptd6/llwu_p15 ptd5 ptd4/llwu_p14 ptc7 ptc6/llwu_p10 ptc5/llwu_p9 ptc4/llwu_p8 pta0 pte25/llwu_p21 pte24 pte30 12 11 10 9 pta4/llwu_p3 pta3 pta2 pta1 16 15 14 13 ptb0/llwu_p5 pta20 pta19 pta18 24 23 22 21 20 19 18 17 ptc3/llwu_p7 ptc2 ptc1/llwu_p6 ptb1 vrefl/vssa vdda/vrefh pte19 pte18/llwu_p20 pte17/llwu_p19 pte16 vss vdd 8 7 6 5 4 3 2 1 figure 20. 32 lqfp pinout diagram pinout kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 51 nxp semiconductors
32 31 30 29 28 27 26 25 ptd7 ptd6/llwu_p15 ptd5 ptd4/llwu_p14 ptc7 ptc6/llwu_p10 ptc5/llwu_p9 ptc4/llwu_p8 pta0 pte25/llwu_p21 pte24 pte30 12 11 10 9 pta4/llwu_p3 pta3 pta2 pta1 16 15 14 13 ptb0/llwu_p5 pta20 pta19 pta18 24 23 22 21 20 19 18 17 ptc3/llwu_p7 ptc2 ptc1/llwu_p6 ptb1 vrefl/vssa vdda/vrefh pte19 pte18/llwu_p20 pte17/llwu_p19 pte16 vss vdd 8 7 6 5 4 3 2 1 figure 21. 32 qfn pinout diagram 7 ordering parts 7.1 determining valid orderable parts valid orderable part numbers are provided on the web. to determine the orderable part numbers for this device, go to www.nxp.com and perform a part number search for the mkv11 device numbers. 8 part identification ordering parts 52 kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 nxp semiconductors
8.1 description part numbers for the chip have fields that identify the specific part. you can use the values of these fields to determine the specific part you have received. 8.2 format part numbers for this device have the following format: q kv## m fff r t pp cc s n 8.3 fields this table lists the possible values for each field in the part number (not all combinations are valid): field description values q qualification status ? m = fully qualified, general market flow ? p = prequalification kv## kinetis family ? kv10 and kv11 m key attribute ? z = m0+ core fff program flash memory size ? 128 = 128 kb t temperature range (c) ? v = C40 to 105 pp package identifier ? lc = 32 lqfp (7 mm x 7 mm) ? fm = 32 qfn (5 mm x 5 mm) ? lf = 48 lqfp (7 mm x 7 mm) ? lh = 64 lqfp (10 mm x 10 mm) ccc maximum cpu frequency (mhz) ? 7 = 75 mhz s software type ? p = kms-pmsm and bldc ? (blank) = not software enabled n packaging type ? r = tape and reel ? (blank) = trays 8.4 example this is an example part number: mkv11z128vfm7 part identification kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 53 nxp semiconductors
9 terminology and guidelines 9.1 definition: operating requirement an operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. 9.1.1 example this is an example of an operating requirement: symbol description min. max. unit v dd 1.0 v core supply voltage 0.9 1.1 v 9.2 definition: operating behavior unless otherwise specified, an operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions. 9.2.1 example this is an example of an operating behavior: symbol description min. max. unit i wp digital i/o weak pullup/ pulldown current 10 130 a terminology and guidelines 54 kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 nxp semiconductors
9.3 definition: attribute an attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements. 9.3.1 example this is an example of an attribute: symbol description min. max. unit cin_d input capacitance: digital pins 7 pf 9.4 definition: rating a rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: ? operating ratings apply during operation of the chip. ? handling ratings apply when the chip is not powered. 9.4.1 example this is an example of an operating rating: symbol description min. max. unit v dd 1.0 v core supply voltage C0.3 1.2 v terminology and guidelines kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 55 nxp semiconductors
9.5 result of exceeding a rating 40 30 20 10 0 measured characteristic operating rating failures in time (ppm) the likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. 9.6 relationship between ratings and operating requirements C - no permanent failure - correct operation normal operating range fatal range expected permanent failure fatal range expected permanent failure operating rating (max.) operating requirement (max.) operating requirement (min.) operating rating (min.) operating (power on) degraded operating range degraded operating range C no permanent failure handling range fatal range expected permanent failure fatal range expected permanent failure handling rating (max.) handling rating (min.) handling (power off) - no permanent failure - possible decreased life - possible incorrect operation - no permanent failure - possible decreased life - possible incorrect operation 9.7 guidelines for ratings and operating requirements follow these guidelines for ratings and operating requirements: ? never exceed any of the chips ratings. ? during normal operation, dont exceed any of the chips operating requirements. ? if you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. terminology and guidelines 56 kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 nxp semiconductors
9.8 definition: typical value a typical value is a specified value for a technical characteristic that: ? lies within the range of values specified by the operating behavior ? given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions typical values are provided as design guidelines and are neither tested nor guaranteed. 9.8.1 example 1 this is an example of an operating behavior that includes a typical value: symbol description min. typ. max. unit i wp digital i/o weak pullup/pulldown current 10 70 130 a 9.8.2 example 2 this is an example of a chart that shows typical values for various voltage and temperature conditions: terminology and guidelines kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 57 nxp semiconductors
0.90 0.95 1.00 1.05 1.10 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 150 c 105 c 25 c C40 c v dd (v) i (a) dd_stop t j 9.9 typical value conditions typical values assume you meet the following conditions (or other conditions as specified): symbol description value unit t a ambient temperature 25 c v dd 3.3 v supply voltage 3.3 v 10 revision history the following table provides a revision history for this document. table 30. revision history rev. no. date substantial changes 0 11/2014 initial prelim release. 1 02/2015 updated the following sections: ? dspi switching specifications (limited voltage range) ? dspi switching specifications (full voltage range) ? kv11 signal multiplexing and pin assignments table continues on the next page... revision history 58 kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 nxp semiconductors
table 30. revision history (continued) rev. no. date substantial changes 2 04/2015 updated the following sections: ? power mode transition operating behaviors ? power consumption operating behaviors ? 16-bit adc operating conditions ? fields ? updated the table "16-bit adc electrical characteristics" with a footnote ? added the figure "run mode supply current vs. core frequency" to the section "diagram: typical idd_run operating behavior" 3 06/2015 ? added a footnote to the ambient temperature entry in the table "thermal operating requirements" 4 05/2017 ? added kms related information in front matter ? added the section "kms motor suite" ? added "s" in the sections "format" and "fields" to specify software type in part number ? updated the section "example" to add an example for kms part number ? added the kms supported part numbers in the table "ordering information" ? updated the table "related resources," to include references to kms documents ? updated the figure "kv11 block diagram" ? added a note to the t por in the table "power mode transition operating behaviors." ? changed freescale.com to nxp.com throughout revision history kinetis v series kv10 and kv11, 128/64 kb flash, rev. 4, 05/2017 59 nxp semiconductors
how to reach us: home page: nxp.com web support: nxp.com/support information in this document is provided solely to enable system and software implementers to use nxp products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. nxp reserves the right to make changes without further notice to any products herein. nxp makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does nxp assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. typical parameters that may be provided in nxp data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. all operating parameters, including typicals, must be validated for each customer application by customer's technical experts. nxp does not convey any license under its patent rights nor the rights of others. nxp sells products pursuant to standard terms and conditions of sale, which can be found at the following address: nxp.com/salestermsandconditions . freescale, nxp, the nxp logo, and kinetis are trademarks of nxp b.v. all other product or service names are the property of their respective owners. arm and cortex are registered trademarks of arm limited (or its subsidiaries) in the eu and/or elsewhere. spintac is a trademark of linestream technologies, inc. all rights reserved. ?2014-2017 nxp b.v. document number KV11P64M75 revision 4, 05/2017

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