general description the DS1842A integrates the discrete high-voltagecomponents necessary for avalanche photodiode (apd) bias and monitor applications. a precision volt- age-divider network is used in conjunction with an external dc-dc controller and fet to create a boost dc-dc converter. a current clamp limits current through the apd and also features an external shut- down. the precision voltage-divider network is provid- ed for precise control of the apd bias voltage. the device also includes a dual current mirror to monitor the apd current. applications apd biasinggpon onu and olt features ? 76v maximum boost voltage ? current monitor with a wide 1? to 2ma range,fast 50ns time constant, and 10:1 and 5:1 ratio ? 2ma current clamp with external shutdown ? precision voltage feedback ? multiple external filtering options ? 3mm x 3mm, 14-pin tdfn package with exposed pad DS1842A 76v, apd, dual output current monitor ________________________________________________________________ maxim integrated products 1 ordering information 19-4994; rev 1; 9/11 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin-package DS1842An+ -40c to +85c 14 tdfn-ep* DS1842An+t&r -40c to +85c 14 tdfn-ep* + denotes a lead(pb)-free/rohs-compliant package. t&r = tape and reel. * ep = exposed pad. ds4830 DS1842A pwm adc gpio adc fbout r 1 r 2 mirin fbin mir1 clamp mirout gnd ep 3.3v current mirror current limit mir2 c bulk external monitor tia apd rosa typical application circuit downloaded from: http:///
DS1842A 76v, apd, dual output current monitor 2 _______________________________________________________________________________________ absolute maximum ratingselectrical characteristics (t a = -40? to +85?, unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2: rising mirout transition from 10? to 1ma; v mirin = 40v, 2.5k load. note 3: not production tested. guaranteed by design. voltage range on clamp relative to gnd...................................................-0.3v to +12v voltage range on mirin, mirout, fbin mir1, and mir2 relative to gnd........................-0.3v to +80v voltage range on fbout relative to gnd ..........-0.3v to +6.0v continuous power dissipation (ta = +70?) tdfn (derate 24.4mw/? above +70?).................1951.2mw operating junction temperature range ...........-40? to +150? storage temperature range .............................-55? to +135? lead temperature (soldering, 10s) .................................+300? soldering temperature (reflow) .......................................+260? package thermal characteristics (note 1)tdfn junction-to-ambient thermal resistance ( ja ) ............41?/w junction-to-case thermal resistance ( jc ) ...................8?/w parameter smbol conditions min tp max units clamp voltage v clamp 0 11 v clamp threshold v clt 1.25 1.8 2.35 v clamp = low 1.8 2.75 3.85 ma maximum mirout current i mirout clamp = high 10 a mir1 to mirout ratio k mir1 15v < v mirin < 76v, i mirout > 1a 0.096 0.100 0.104 a/a mir2 to mirout ratio k mir2 15v < v mirin < 76v, i mirout > 1a 0.192 0.200 0.208 a/a mir1, mir2 rise time (20%/80%) t rc (note 2) 30 ns shutdown temperature t shdn (note 3) +150 c hysteresis temperature t hys (note 3) 5 c leakage on clamp i il -1 +1 a resistor-divider ratio (r 1 /r 2 ) k r t a = +25c, v fbin = 76v 59.5 60.25 resistor-divider tempco 50 ppm/c resistor-divider end-to-end resistance r res t a = +25c, v fbin = 76v 308 385 481 k note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layerboard. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . downloaded from: http:///
DS1842A 76v, apd, dual output current monitor _______________________________________________________________________________________ 3 typical operating characteristics (t a = +25?, unless otherwise noted.) mirin current vs. mirout current (v mirin = 40v) DS1842A toc01 mirout current ( a) mirin current ( a) 1000 100 10 100 1000 10,000 10 1 10,000 mirin current vs. temperature (v mirin = 40v, i mirout = 250na) DS1842A toc02 temperature ( c) mirin current ( a) 80 60 20 40 0 -20 10 20 30 40 50 60 70 80 90 100 0 -40 100 mirin current vs. temperature (v mirin = 40v, i mirout = 2ma) DS1842A toc03 temperature ( c) mirin current (ma) 80 60 40 20 0 -20 1 2 3 4 50 -40 100 mir error vs. temperature (i mirout = 1 a) DS1842A toc04 temperature ( c) error (%) 80 60 40 20 0 -20 -1 0 1 2 -2 -40 100 v mirin = 40v mir2 mir1 mir error vs. temperature (i mirout = 1ma) DS1842A toc05 temperature ( c) error (%) 80 60 40 20 0 -20 -1 0 1 2 -2 -40 100 v mirin = 40v mir2 mir1 mir error vs. mirout current DS1842A toc06 mirout current ( a) error (%) 1000 100 10 -1 0 1 2 -2 1 10,000 v mirin = 40v mir2 mir1 downloaded from: http:///
DS1842A 76v, apd, dual output current monitor 4 _______________________________________________________________________________________ typical operating characteristics (continued) (t a = +25?, unless otherwise noted.) mir error vs. mirin voltage DS1842A toc07 mirin voltage (v) error (%) 70 60 50 40 30 20 -1 0 1 2 -2 10 80 i mir2 = 1 a i mir1 = 1 a i mir2 = 1ma i mir1 = 1ma mirout clamp current vs. mirin voltage DS1842A toc08 mirin voltage (v) i mirout (ma) 70 60 40 50 30 20 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.52.5 10 80 t a = -40 c t a = +25 c t a = +85 c resistor-divider ratio vs. fbin voltage DS1842A toc11 fbin voltage (v) ratio (k r ) 70 60 50 40 30 20 59.8 59.9 60.0 60.159.7 10 80 resistor-divider ratio vs. temperature DS1842A toc12 temperature ( c) ratio (k r ) 80 60 40 20 0 -20 59.85 59.90 59.95 60.0059.80 -40 100 v fbin = 40v downloaded from: http:///
DS1842A 76v, apd, dual output current monitor _______________________________________________________________________________________ 5 pin description pin name function 1 mir1 current mirror monitor output, 10:1 ratio 2 mir2 current mirror monitor output, 5:1 ratio 3, 6, 7 gnd ground connection for device. connect directly to ground plane. 4 fbout feedback output. resistor-divider output. 5 clamp clamp input. disables the current mirror output (mirout). 8C11 n.c. no connection 12 fbin feedback input. resistor-divider input. 13 mirin current mirror input 14 mirout current mirror output. connect to apd bias pin. ep exposed pad. connect directly to the same ground plane as gnd. block diagram tdfn top view 24 5 1311 10 mirinn.c. n.c. mir2 fbout clamp 1 14 mirout mir1 3 12 fbin gnd 6 9 n.c. gnd 7 8 n.c. gnd DS1842A *ep *exposed pad. + DS1842A mirinmir1 clamp mirout current mirror current limit fbin mir2 thermal shutdown fbout r 1 r 2 gnd ep pin configuration detailed description the DS1842A contains discrete high-voltage compo-nents required to create an apd bias voltage and to monitor the apd bias current. the device? mirror out- puts are a current that is a precise ratio of the output current across a large dynamic range. the mirror response time is fast enough to comply with gpon rx burst-mode monitoring requirements. the device has a built-in current-limiting feature to protect apds. the apd current can also be shut down by clamp or ther-mal shutdown. the resistor-divider is used in conjunc- tion with a dc-dc boost controller and fet to precisely create the apd bias voltage. current mirror the DS1842A has two current mirror outputs. one is a10:1 mirror connected at mir1, and the other is a 5:1 mirror connected to mir2. downloaded from: http:///
DS1842A 76v, apd, dual output current monitor 6 _______________________________________________________________________________________ the mirror output is typically connected to an adcusing a resistor to convert the mirrored current into a voltage. the resistor to ground should be selected such that the maximum full-scale voltage of the adc is reached when the maximum mirrored current is reached. for example, if the maximum monitored cur- rent through the apd is 2ma with a 1v adc full scale, and the 10:1 mirror is used, then the correct resistor is approximately 5k . if both mir1 and mir2 are con- nected together, the correct resistor is 1.6k . the mirror response time is dominated by the amount ofcapacitance placed on the output. for burst-mode rx systems where the fastest response times are required (approximately a 50ns time constant), a 3.3pf capacitor and external op amp should be used to buffer the signal sent to the adc. for continuous mode applications, a 10nf capacitor is all that is required on the output. current clamp the DS1842A has a current clamping circuit to protectthe apd by limiting the amount of current from mirout. there are three methods of current clamping available: 1) internally defined current limit the device? current clamp circuit automatically clamps the current when it exceeds the maximum mirout current. 2) external shutdown signal the clamp pin can completely shut down the current from mirout. the clamp pin is active high. 3) precise level set by external feedback circuit a feedback circuit is used to control the level applied to the clamp pin. figure 1 shows an example feedback circuit. thermal shutdown as a safety feature, the DS1842A has a thermal-shut-down circuit that turns off the mirout and mirin cur- rents when the internal die temperature exceeds t shdn . these currents resume after the device has cooled. precision voltage-divider the DS1842A includes a resistor-divider to use as thefeedback network for the boost converter. the DS1842A resistor-divider ratio, k r (r 1 /r 2 ), is tightly controlled, allowing the boost converter output to be setwith very high precision. k r can pair with the ds1875? internal dc-dc boost controller. k r can also be easily modified by adding external series/parallel resistors;however, the temperature coefficient of the external resistors must be considered. package information for the latest package outline information and land patterns(footprints), go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only.package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. clamp mir1 ref figure 1. current clamp from current feedback package type package code outline no. land pattern no. 14 tdfn-ep t1433+2 21-0137 90-0063 downloaded from: http:///
DS1842A 76v, apd, dual output current monitor maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 _____________________ 7 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 10/09 initial release 1 9/11 removed references to the internal switch fet and renamed pins ac cordingly; updated the soldering information in the absolute maximum ratings section; added the package thermal characteristics section; removed the fet tpical operating characteristics graphs 1, 2, 4, 5, 6 downloaded from: http:///
|
