fn8240 rev 3.00 page 1 of 10 august 31, 2006 fn8240 rev 3.00 august 31, 2006 ISL95710 digitally controlled potentiometer (xdcp?), terminal voltage 2 .7v to 5v, 128 taps, up/down interface datasheet the intersil ISL95710 is a digi tally controlled potentiometer (xdcp). the device consists of a resistor array, wiper switches, a control section, and nonvolatile memory. the wiper position is controlled by a up/down interface. the potentiometer is imple mented by a resistor array composed of 127 resistive e lements and a wiper switching network. between each elem ent and at either end are tap points accessible to the wiper terminal. the position of the wiper element is controlled by the cs , u/d , and inc inputs. the position of the wiper can be stored in nonvolatile memory and then be recalled upon a subsequent power-up operation. the device can be used as a three-terminal potentiometer or as a two-terminal va riable resistor in a wide variety of applications including: ? industrial and aut omotive control ? parameter and bias adjustments ? amplifier bias and control pinout ISL95710 (10 ld msop) top view features ? non-volatile solid-state potentiometer ? up/down interface with chip select enable ? dcp terminal voltage 2.7v to 5.5v ? 128 wiper tap points - wiper position stored i n nonvolatile memory and recalled on power-up ? 127 resistive elements -typical r total tempco = 50ppm/ c - end to end resistance range 20% ? low power cmos - standby current, 1a - active current, 3ma max -v cc = 2.7v to 5.5v - v- = -2.7v to -5.5v ? high reliability - endurance, 200,000 data changes per bit - register data retention, 50 years ?r total values = 10k ??? 50k ? ? package -10 ld msop - pb-free plus annea l (rohs compliant) gnd inc u/d v- 1 2 3 4 10 9 8 7 r h r w nc vcc 5 r l 6 cs ordering information part number (notes 1, 2) part marking resistance option ( ? ) temp. range (c) package (pb-free) pkg. dwg. # ISL95710wiu10z akr 10k -40 to +85 10 ld msop m10.118 ISL95710uiu10z akp 50k -40 to +85 10 ld msop m10.118 notes: 1. add -t suffix for tape and reel. 2. intersil pb-free plus anneal pr oducts employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible wit h both snpb and pb-free solderi ng operations. intersil pb-free products are msl classified at pb-free peak ref low temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. n o t re c o m m e n d e d f o r ne w d e s i g n s r e co m m e n d e d r e p l a c e m e n t : i s l 9 5 3 1 0
ISL95710 fn8240 rev 3.00 page 2 of 10 august 31, 2006 block diagram 7-bit up/down counter 7-bit nonvolatile memory store and recall control circuitry one of 128 decoder resistor array r h u/d inc cs transfer gates v- gnd r l r w control and memory up/down (u/d ) increment (inc ) device select (cs ) v- (analog voltage) gnd (ground) r h r w r l general detailed 0 1 2 124 125 126 127 v cc pin number symbol description 1u/d controls the direction of wiper movement and whether the counte r is incremented or decremented 2 v- negative bias voltage for t he potentiometer wiper control 3 gnd ground 4cs chip select. the device is selected when the cs input is low. also used to i nitiate a nonvolatile store 5 nc no connect. pin is to be left unconnected 6r h a fixed terminal for one end of the potentiometer resistor 7r w the wiper terminal which is equiva lent to the movable terminal of a potentiometer 8r l a fixed terminal for one end of the potentiometer resistor 9 vcc positive logic supply voltage 10 inc increment input; negative edge triggered
ISL95710 fn8240 rev 3.00 page 3 of 10 august 31, 2006 absolute maximum ratings thermal information temperature under bias . . . . . . . . . . . . . . . . . . . . . .-65 ? c to +135 ? c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c voltage on cs , inc , u/d and vcc with respect to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . -1v to +6v voltage on v- (referenced to gnd) . . . . . . . . . . . . . . . . . . . . . . . -6v ? v = |v (rh) -v (rl) | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12v lead temperature (soldering 10 seconds) . . . . . . . . . . . . . . . . 300c i w (10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6ma esd (mil-std 883, method 3015) . . . . . . . . . . . . . . . . . . . . . . . .>2kv esd machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>150v thermal resistance (typical, note 3) ? ja (c/w) msop package . . . . . . . . . . . . . . . . . . . . . . . . . . . . +170 recommended operating conditions temperature range (industrial) . . . . . . . . . . . . . . . . . -40c to +85c v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7v to 5.5v v- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.7v to -5.5v caution: stresses above those listed under ?absolute maximum rati ngs? may cause permanent damage to the device. this is a stres s rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. exposure to absolute maximum rating conditions for extend ed periods may affect device reliability. note: 3. ? ja is measured with the component mounted on a high effective the rmal conductivity test board in free air. see tech brief tb379 for details. analog specifications over recommended operating conditi ons unless otherwise stated. symbol parameter test conditions min typ (note 1) max unit r total r h to r l resistance w option 10 k ? u option 50 k ? r h to r l resistance tolerance -20 +20 % tc r (note 12, 13) resistance temperature coefficient i dcp = 1ma t = -40c to +85c 50 ppm/c v rh ,v rl r h ,r l terminal voltage v- v cc v r w wiper resistance v- = -5.5v; v cc = +5.5v, wiper current = (v cc -v-)/r total 70 200 ? c h /c l /c w (note 13) potentiometer capacitance 10/10/25 pf i lkgdcp leakage on dcp pins voltage at pins; v- to v cc -1 0.1 1 a voltage divider mode (v- @ r l ; v cc @ r h ; voltage at r w = v rw unloaded) inl (note 6) integral non-linearity -1 1 lsb (note 2) dnl (note 5) differential non-linearity w, u options -0.5 0.5 lsb (note 2) zserror (note 3) zero-scale error w option 0 1 4 lsb (note 2) u option 0 0.5 2 fserror (note 4) full-scale error w option -4 -1 0 lsb (note 2) u option -2 -0.5 0 tc v (notes 7, 13) ratiometric temperature coefficient dcp register set at 63d, t = -40c to +85c 4 ppm/c resistor mode (measurements between r w and r l with r h not connected, or between r w and r h with r l not connected) rinl (note 11) integral non-linearity dcp register set between 20 hex and 5f he x. monotonic over all tap positions -1 1 mi (note 8) rdnl (note 10) differential non-linearity w, u options -0.5 0.5 mi (note 8) roffset (note 9) offset dcp register set to 00 hex, w option 0 2 5 mi (note 8) dcp register set to 00 hex, u option 0 0.5 2
ISL95710 fn8240 rev 3.00 page 4 of 10 august 31, 2006 operating specifications over the recommended operating c onditions unless otherwise spec ified. symbol parameter test conditions min typ (note 1) max unit i cc1 v cc supply current, volatile write/read cs = v il , u/d = v il or v ih and inc = v il or v ih , r l , r h , r w not connected 500 a i v-1 v- supply current, volatile write/read cs = v il , u/d = v il or v ih and inc = v il or v ih , r l , r h , r w not connected -100 ? a i cc2 v cc supply current, nonvolatile write u/d = v il or v ih and inc = v ih , cs = transitions from v il to v ih . r l , r h , r w not connected 500 a i v-2 v- supply current, nonv olatile write u/d = v il or v ih and inc = v ih , cs = transitions from v il to v ih . r l , r h , r w not connected -3 ma i ccsb v cc current (standby) v cc = +5.5v, i 2 c interface in standby state 1 a v cc = +3.6v, i 2 c interface in standby state 1 a i v-sb v- current (standby) v- = -5.5v, cs = v ih -5 a v- = -3.6v, cs = v ih -2 a i lkgdig leakage current, at pins inc , cs , and u/d v il or v ih applied at pin -10 10 a i il_cs leakage at cs, input low v il = 0v -300 ? a vpor power-on recall for both v- and v cc v- -2.5 v v cc 2.5 v v- ramp v- ramp rate -0.2 v/ms eeprom specs eeprom endurance 200,000 cycles eeprom retention temperature ? +75c 50 years 3-wire interface specs v il inc , cs , and u/d input buffer low voltage -0.3 0.3*v cc v v ih inc , cs , and u/d input buffer high voltage 0.7*v cc v cc + 0.3 v hysteresis (note 13) inc , cs , and u/d input buffer hysteresis 0.15* v cc v cpin inc , cs , and u/d pin capacitance 10 pf ac electrical specifications v cc = 5v 10%, t a = full operating temperature range unless otherwise stated symbol parameter min typ (note 1) max unit t cl cs to inc setup 100 ns t ld inc high to u/d change 100 ns t di u/d to inc setup 1 s t ll inc low period 1 s t lh inc high period 1 s t lc inc inactive to cs inactive 1 s t cphs (note 14) cs deselect time (store) 20 ms t cphns cs deselect time (no store) 1 s
ISL95710 fn8240 rev 3.00 page 5 of 10 august 31, 2006 symbol table t iw inc to r w change 100 500 s t cyc inc cycle time 2 s t r , t f inc input rise and fall time 500 s notes: 1. typical values are for t a = +25c and 3.3v supply voltage. 2. lsb: [v(r w ) 127 C v(r w ) 0 ]/127. v(r w ) 127 and v(r w ) 0 are v(r w ) for the dcp register set to 7f hex and 00 hex respectively. l sb is the incremental voltage when changing from one tap to an adjacent t ap. 3. zs error = (v(r w ) 0 C v-)/lsb. 4. fs error = [v(r w ) 127 C v+]/lsb. 5. dnl = [v(r w ) i C v(r w ) i-1 ]/lsb-1, for i = 1 to 127. i is the dcp register setting. 6. inl = v(r w ) i C (i ? lsb C v(r w ) 0 )/lsb for i = 1 to 127. 7. for i = 16 to 120 decimal. max ( ) is the maximum value of the wiper voltage and min ( ) is the minimum value of the wiper vol tage over the temperature range. 8. mi = | r 127 C r 0 | /127. r 127 and r 0 are the measured resistances for the dcp register set to 7f he x and 00 hex respectively. 9. roffset = r 0 /mi, when measuring between rw and rl. roffset = r 127 /mi, when measuring between rw and rh. 10. rdnl = (r i C r i-1 )/mi -1, for i = 16 to 127. 11. rinl = [r i C (mi ? i) C r 0 ]/mi, for i = 16 to 127. 12. for i = 16 to 127, t = -40c to +85c. max ( ) is the maximum v alue of the resistance and min ( ) is the minimum value of the resistance over the temperature range. 13. this parameter is not 100% tested. 14. t cphs is the minimum cycle time to be allowed for any non-volatile w rite by the user. it is the time from a valid store condition t o the end of the self-timed internal non-volatile write cycle. no cs or inc changes should be allowed. ac electrical specifications v cc = 5v 10%, t a = full operating temperature range unless otherwise stated (continued) symbol parameter min typ (note 1) max unit tc v max v rw ?? i ?? min v rw ?? i ?? C max v rw ?? i ?? min v rw ?? i ?? + ?? 2 ? --------------------------------------------------------------- ------------------------------- x 10 6 125c ---------------- - = tc r max ri ?? min ri ?? C ?? max ri ?? min ri ?? + ?? 2 ? --------------------------------------------------------------- - 10 6 125c ---------------- - ? = waveform inputs outputs must be steady will be steady may change from low to high will change from low to high will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance may change from high to low
ISL95710 fn8240 rev 3.00 page 6 of 10 august 31, 2006 a.c. timing typical performance curves figure 1. wiper resistance vs tap position [i(rw) = v cc /r total ] for 10k ? (w) figure 2. standby i cc vs v cc figure 3. dnl vs tap position in voltage divider mode for 10k ? (w) figure 4. inl vs tap position in voltage divider mode for 10k ? (w) cs inc u/d r w t ci t il t ih t cyc t id t di t iw mi (1) t ic t cphs t f t r 10% 90% 90% t cphns note (1): mi in the ti ming diagram refers to the minimum increm ental change in the wiper position. 0 20 40 60 80 100 120 020406080100120 tap position (decimal) t=85o c t=25o c t=-40o c irw =0.6ma wiper resistance ( ? ) 0.3 0.4 0.5 0.6 2.7 3.2 3.7 4.2 4.7 5.2 vcc, v t = 25o c t = 85o c t = -40o c isb (a) -0.2 -0.1 0 0.1 0.2 0 20 40 60 80 100 120 tap position (decimal) vrh=5.5v, vrl=-5.5v vrh=2.7v, vrl=-2.7v dnl (lsb) -0.2 -0.1 0 0.1 0.2 0 20406080100120 tap position (decimal) vrh=2.7v, vrl=-2.7v vrh=5.5v, vrl=-5.5v inl (lsb)
ISL95710 fn8240 rev 3.00 page 7 of 10 august 31, 2006 figure 5. zserror vs temperature figure 6. fserror vs temperature figure 7. dnl vs tap position in rheostat mode for 10k ? (w) figure 8. inl vs tap position in rheostat mode for 10k ? (w) figure 9. end to end r total % change vs temperature figure 10. tc for voltage divider mode in ppm typical performance curves (continued) 0 0.4 0.8 1.2 1.6 -40-200 20406080 temperature (c) vrh=2.7v, vrl=-2.7v, 10k vrh=5.5v, vrl=-5.5v, 10k zserror (lsb) -2 -1.6 -1.2 -0.8 -0.4 0 -40 -20 0 20 40 60 80 temperature (c) vrh=5.5v, vrl=-5.5v, 10 k vrh=2.7v, vrl=-2.7v, 10k fserror (lsb) -0.1 -0.05 0 0.05 0.1 0 20406080100120 tap position (decimal) vcc=2.7v, v-=-2.7v vcc=5.5v, v-=-5.5v t=25 c rdnl (lsb) -0.2 0 0.2 0.4 0.6 0.8 1 0 50 100 ta p position (decim a l) t=25 c vcc=2.7v, v-=- 27v vcc=5.5v, v-=- 55v rinl (lsb) -1 -0.5 0 0.5 1 -40 -20 0 20 40 60 80 tem perature (c) idcp= 1.16ma idcp= 0.57ma end to end r total change (%) 0 20 40 60 80 100 16 36 56 76 96 116 tap position (decimal) 10k 50k tcv (ppm/c)
ISL95710 fn8240 rev 3.00 page 8 of 10 august 31, 2006 power up and down requirements in order to prevent unwanted tap position changes, or an inadvertent store, bring the cs and inc high before or concurrently with the v cc pin on power-up. the potentiometer voltages must be applied after this sequence is completed. during power-up, the data she et parameters for the dcp do not fully apply until 1ms after v cc reaches its final value. the v cc ramp spec is always in effect. pin descriptions r h and r l the high (r h ) and low (r l ) terminals of the ISL95710 are equivalent to the fixed t erminals of a mechanical potentiometer. the terminology of r l and r h references the relative position of the termina l in relation to wiper movement direction selected by the u/d input and not the voltage potential on the terminal. r w r w is the wiper terminal and is equivalent to the movable terminal of a mechanical poten tiometer. the position of the wiper within the array is det ermined by the wiper counter. up/down (u/d ) the u/d input controls the direction of the wiper movement and whether the wiper counter is i ncriminated or decremented. increment (inc ) the inc input is negative-edge triggered. toggling inc will move the wiper and either incre ment or decrem ent the wiper counter in the direction indica ted by the logic level on the u/ d input. chip select (cs ) the device is selected when the cs input is low. the current wiper counter value is stored in nonvol atile memory when cs is returned high while the inc input is also high. after the store operation is com plete the ISL95710 will be placed in the low power standby mode until the device is selected once again. figure 11. tc for rheostat mode in ppm figure 12. frequency response (1.8mhz) figure 13. wiper movement figure 14. large signal settling time typical performance curves (continued) 0 50 100 150 200 16 36 56 76 96 tap position (decimal) 10k 50k tcr (ppm/c)
fn8240 rev 3.00 page 9 of 10 august 31, 2006 ISL95710 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas ll c 2005-2006. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. principles of operation there are three sections of th e ISL95710: the input control, wiper counter and deco de section; the non volatile memory; and the resistor array. the input control section operates as a n up/down counter. the output of t his wiper counter is decoded to turn on a electronic switch connecting a point on the resist or array to the wiper output. the contents of the wiper counter can be stored in nonvol atile memory and re tained for future use. the resistor array is com prised of individual resistors connected in series. at either end of the array and between each resistor is an electronic switch that transfers the potent ial at that point t o the wiper. the wiper, when at either fix ed terminal, acts like its mechanical equivalent and does not move beyond the last position. the wiper counter does not wrap around when clocked to either extreme. the electronic switches on th e device operate in a make before break mode w hen the wiper changes tap positions. if the wiper is moved several pos itions, multiple taps are connected to the wiper for t iw (inc to r w change). the r total value for the device can te mporarily be reduced by a significant amount if the wiper is moved several positions. when the device is powered-do wn, the last wiper position stored will be maintained in the nonvolatile memory. when power is restored, the contents of the memory are recalled and the wiper is set to t he value last stored. instructions and programming the inc , u/d and cs inputs control the movement of the wiper along the resistor array. with cs set low the device is selected and enabled t o respond to the u/d and inc inputs. high to low transitions on inc will increment or decrement (depending on the state of the u/d input) a seven bit wiper counter. the output of this wiper counter is decoded to select one of 128 wiper positions along the resistive array. the value of the wiper counter i s stored in nonvolatile memory whenever cs transitions high while the inc input is also high. the system may select the is l95710, move the wiper and deselect the device without having to store the latest wiper position in nonvolatile memory . after the wiper movement is performed as described above and once the new position is reached, the system must keep inc low while taking cs high. the new wiper position will be maintained until changed by the system or until a pow er-up/down cycle recalls the previously stored data. this procedure allows the syst em to always po wer-up to a preset value stored in nonvola tile memory; then during system operation minor adjustments co uld be made. the adjustments might be based on user preference, system parameter changes due to temper ature drift, etc. the state of u/d may be changed while cs remains low. this allows the host system to enable the device and then move the wiper up and down until the proper trim is attained. during initial power-up cs must go high along with or before v cc to avoid an accidental store generation. table 1. mode selection cs inc u/d mode l h wiper up l l wiper down h x store wiper position h x x standby current l x no store, return to standby h h x standby l h wiper up one position (not recommended) l l wiper down one position (not recommended)
ISL95710 fn8240 rev 3.00 page 10 of 10 august 31, 2006 mini small outline pl astic packages (msop) notes: 1. these package dimensions are wi thin allowable dimensions of jedec mo-187ba. 2. dimensioning and tolerancing per ansi y14.5m - 1994. 3. dimension ?d? does not include mold flash, protrusions or gate burrs and are measured at datum plane. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e1? does not includ e interlead flash or protrusions and are measured at datum plane. interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. formed leads shall be planar wi th respect to one another within 0.10mm (.004) at seating plane. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of ?b? dimension at maximum ma terial condition. minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. datums and to be determined at datum plane . 11. controlling dimension: millimeter. converted inch dimen- sions are for reference only l 0.25 (0.010) l1 r1 r 4x ? 4x ? gauge plane seating plane e e1 n 12 top view index area -c- -b- 0.20 (0.008) a b c seating plane 0.20 (0.008) c 0.10 (0.004) c -a- -h- side view b e d a a1 a2 -b- end view 0.20 (0.008) c d e 1 c l c a m10.118 (jedec mo-187ba) 10 lead mini small outline plastic package symbol inches millimeters notes min max min max a 0.037 0.043 0.94 1.10 - a1 0.002 0.006 0.05 0.15 - a2 0.030 0.037 0.75 0.95 - b 0.007 0.011 0.18 0.27 9 c 0.004 0.008 0.09 0.20 - d 0.116 0.120 2.95 3.05 3 e1 0.116 0.120 2.95 3.05 4 e 0.020 bsc 0.50 bsc - e 0.187 0.199 4.75 5.05 - l 0.016 0.028 0.40 0.70 6 l1 0.037 ref 0.95 ref - n10 107 r 0.003 - 0.07 - - r1 0.003 - 0.07 - - 5 o 15 o 5 o 15 o - ? 0 o 6 o 0 o 6 o - rev. 0 12/02 ?
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