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mb91460c series fr60 32-bit microcontroller cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-04609 rev. *a revised april 12, 2016 mb91460c series is a line of general-purpose 32-bit risc micr ocontrollers designed for embedded control applications which requ ire high-speed real-time processing, such as consumer devices and on-board vehicle systems. this series uses the fr60 cpu, which is compatible with the fr family of cpus. this series contains the lin-usart and can controllers. features fr60 cpu core 32-bit risc, load/store architecture, five-stage pipeline 16-bit fixed-length instruct ions (basic instructions) instruction execution speed: 1 instruction per cycle instructions including memory -to-memory transfer, bit manipulation, and barrel shift instructions: instructions suitable for embedded applications function entry/exit instructions and register data multi-load store instructions : instructions supporting c language register interlock function: facilitating assembly-language coding built-in multiplier with in struction-level support ? signed 32-bit multip lication: 5 cycles ? signed 16-bit multip lication: 3 cycles interrupts (save pc/ps) : 6 cycles (16 priority levels) harvard architecture enabling program access and data access to be performed simultaneously instructions compatible with the fr family internal peripheral resources general-purpose ports : maximum 104 ports dmac (dma controller) ? maximum of 5 channels able to operate simultaneously. ? 2 transfer sources (internal peripheral/software) ? activation source can be selected using software ? addressing mode specifies full 32-bit addresses (increment/decrement/fixed) ? transfer mode (demand transf er/burst transfer/step transfer/block transfer) ? transfer data size selectable from 8/16/32-bit ? multi-byte transfer enabled (by software) ? dmac descriptor in i/o areas (200h to 240h, 1000h to 1024h) a/d converter (successive approximation type) ? 10-bit resolution: 30 channels ? conversion time: minimum 1 s external interrupt inputs : 15 channels ? 8 channels shared with can rx or i 2 c pins bit search module (for realos) ? function to search the first bit position of ?1?, ?0?, ?changed? from the msb (most signif icant bit) within one word lin-usart (full duplex double buffer): 5 channels ? clock synchronous/asynchronous selectable ? sync-break detection ? internal dedicated baud rate generator i 2 c bus interface (supports 400 kbps): 3 channels ? master/slave transmission and reception ? arbitration function, clock synchronization function can controller (c-can): 3 channels ? maximum transfer speed: 1 mbps ? 32 transmission/reception message buffers stepper motor controller : 6 channels ? 4 high current output to each channel ? 2 synchronized pwms per channel (8/10-bit) sound generator : 1 channel ? tone frequency : pwm frequency divide-by-two (reload value ? 1) alarm comparator : 1 channel ? monitor external voltage ? generate an interrupt in case of voltage lower/higher than the defined thresholds (reference voltage) 16-bit ppg timer : 12 channels 16-bit pfm timer : 1 channel 16-bit reload timer: 8 channels 16-bit free-run timer: 8 channels (1 channel each for icu and ocu) input capture: 8 channels (oper ates in conjunction with the free-run timer) output compare: 4 channels (operates in conjunction with the free-run timer) up/down counter: 3 channels (3*8-bit or 2*16-bit) watchdog timer real-time clock low-power consumption modes : sleep/stop mode function low voltage detection circuit clock supervisor ? monitors the sub-clock (32 khz) and the main clock (4 mhz) , and switches to a recovery clock (cr oscillator, etc.) when the oscillations stop. clock modulator clock monitor
document number: 002-04609 rev. *a page 2 of 106 mb91460c series sub-clock calibration ? corrects the real-time clock timer when operating with the 32 khz or cr oscillator main oscillator stabilization timer ? generates an interrupt in sub-clock mode after the stabiliza- tion wait time has elapsed on the 23-bit stabilization wait time counter ? sub-oscillator stabilization timer ? generates an interrupt in main clock mode after the stabilization wait time has elapsed on the 15-bit stabilization wait time counter package and technology package: qfp-144 cmos 180 nm technology power supply range 3 v to 5 v (1.8 v internal logic provided by a step-down voltage converter) operating temperature range: between ? 40c and ? 105c note: mb91f463ca is under development.
document number: 002-04609 rev. *a page 3 of 106 mb91460c series contents product lineup ................................................................. 4 pin assignment ................................................................ 6 mb91f463ca, mb91f465ca, mb91f467cx ............. 6 pin description ................................................................. 7 mb91f463ca, mb91f465ca, mb91f467cx ............. 7 i/o circuit types ............................................................. 14 handling devices ............................................................ 20 preventing latch-up .................................................. 20 handling of unused input pins .............. .............. ....... 20 power supply pins ..................................................... 20 crystal oscillator circuit ...... ........................................ 20 notes on using external clo ck ................................... 20 mode pins (md_x) ..................................................... 21 notes on operating in pll cl ock mode ....... ........... .... 21 pull-up control ........................................................... 21 notes on debugger ........................................................ 22 execution of the reti command .............................. 22 break function ........................................................... 22 operand break .......................................................... 22 notes on ps register ................................................. 22 block diagram ................................................................ 23 mb91f463ca, mb91f465ca, mb91f467cx ........... 23 cpu and control unit ..................................................... 24 features .................................................................... 24 internal architecture ................................................... 24 programming model .................................................. 25 registers ................................................................... 26 embedded program/data memo ry (flash) ................... 29 flash features ............................................................ 29 operation modes: ...................................................... 29 flash access in cpu mode ....................................... 30 parallel flash programming mode ............................ 35 power on sequence in parallel programming mode . 38 flash security ............................................................ 38 memory space ................................................................ 41 memory maps .................................................................. 42 mb91f467cx, mb91f465ca .................................... 42 mb91f463ca ............................................................ 43 i/o map ............................................................................. 44 mb91f463ca, mb91f465ca, mb91f467cx ........... 44 flash memory and external bus area ........................ 67 interrupt vector table .................................................... 69 recommended settings ................................................. 74 pll and clockgear settings .. .............. .............. ........ 74 clock modulator settings ........................................... 75 electrical characteristics ............................................... 80 absolute maximum ra tings ........................................ 80 recommended operating conditions ......................... 82 dc characteristics ..................................................... 83 a/d converter characteristics .................................... 88 alarm comparator characterist ics .............................. 92 flash memory program/erase characteristics ........ 93 ac characteristics ..................................................... 94 ordering information .................................................... 101 package dimension ...................................................... 102 revision history ........................................................... 103 main changes ............................................................... 104 document history ......................................................... 105
document number: 002-04609 rev. *a page 4 of 106 mb91460c series 1. product lineup feature mb91v460 mb91f463ca mb91f465ca mb91f467ca mb91f467cb max. core frequency (clkb) 80 mhz 100 mhz 100 mhz 100 mhz max. resource frequency (clkp) 40 mhz 50 mhz 50 mhz 50 mhz max. external bus frequency (clkt) 40 mhz - - - max. can frequency (clkcan) 20 mhz 50 mhz 50 mhz 50 mhz max. flexray frequency (sclk) - - - - technology 0.35 m0.18 m0.18 m0.18 m watchdog timer yes yes yes yes watchdog timer (rc osc. based) yes (disengageable) yes yes yes bit search yes yes yes yes reset input (initx) yes yes yes yes hardware standby input (hstx) yes no no no clock modulator yes yes yes yes clock monitor yes yes yes yes low power mode yes yes yes yes dma 5 ch 5 ch 5 ch 5 ch mmu/mpu mpu (16 ch) *1 mpu (4 ch) *1 mpu (8 ch) *1 mpu (8 ch) *1 flash memory emulation sram 32bit read data 288 kbyte 544 kbyte 1088 kbyte satellite flash memory - - - - flash protection - yes yes yes d-ram 64 kbyte 16 kbyte 16 kbyte 32 kbyte id-ram 64 kbyte 8 kbyte 16 kbyte 32 kbyte flash-cache (instruction cache) 16 kbyte 4 kbyte 8 kbyte 8 kbyte boot-rom / bi-rom 4 kbyte fixed 4 kbyte 4 kbyte 4 kbyte rtc 1 ch 1 ch 1 ch 1 ch free running timer 8 ch 8 ch 8 ch 8 ch icu 8 ch 8 ch 8 ch 8 ch ocu 8 ch 4 ch 4 ch 4 ch reload timer 8 ch 8 ch 8 ch 8 ch ppg 16-bit 16 ch 12 ch 12 ch 12 ch pfm 16-bit 1 ch 1 ch 1 ch 1 ch sound generator 1 ch 1 ch 1 ch 1 ch up/down counter (8/16 bit) 4 ch (8-bit) / 2 ch (16-bit) 3 ch (8-bit) / 2ch (16-bit) 3 ch (8-bit) / 2ch (16-bit) 3 ch (8-bit) / 2ch (16-bit) c_can 6 ch (128msg) 3 ch (32msg) 3 ch (32msg) 3 ch (32msg) lin-usart 4 ch + 4 ch fifo + 8 ch 1 ch + 4 ch fifo 1 ch + 4 ch fifo 1 ch + 4 ch fifo
document number: 002-04609 rev. *a page 5 of 106 mb91460c series *1: mpu channels use edsu breakpoint regist ers (shared operation between mpu and edsu) . feature mb91v460 mb91f463ca mb91f465ca mb91f467ca mb91f467cb i 2 c (400k) 4 ch 3 ch 3 ch 3 ch fr external bus yes (32bit addr, 32bit data) --- external interrupts 16 ch 15 ch 15 ch 15 ch nmi interrupts 1 ch 1 ch 1 ch 1 ch smc 6 ch 6 ch 6 ch 6 ch lcd controller (40x4) 1 ch - - - adc (10-bit) 32 ch 30 ch 30 ch 30 ch alarm comparator 2 ch 1 ch 1 ch 1 ch supply supervisor (low voltage detec- tion) yes yes yes yes clock supervisor yes yes yes yes main clock oscillator 4 mhz 4 mhz 4 mhz 4 mhz sub clock oscillator 32khz 32khz 32khz 32khz rc oscillator 100khz 100khz / 2mhz 100khz / 2mhz 100khz / 2mhz pll x 20 x 25 x 25 x 25 dsu4 yes no no no edsu yes (32 bp) *1 yes (8 bp) *1 yes (16 bp) *1 yes (16 bp) *1 supply voltage 3v/5v 3v/5v 3v/5v 3v/5v regulator yes yes yes yes power consumption n.a. < 1 w < 1 w < 1 w temperature range (ta) 0.70 c -40.105 c -40.105 c -40.105 c package bga660 qfp-144 qfp-144 qfp-144 power on to pll run < 20 ms < 20 ms < 20 ms < 20 ms flash download time n.a. < 5 sec. typica l < 5 sec. typical < 6 sec typical
document number: 002-04609 rev. *a page 6 of 106 mb91460c series 2. pin assignment 2.1 mb91f463ca, mb91f465ca, mb91f467cx (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 vdd5 avcc5 avrh5 avss alarm_0 p28_3/ an11 p28_2/ an10 p28_1/ an9 p28_0/ an8 p29_7/ an7 p29_6/ an6 p29_5/ an5 p29_4/ an4 p29_3/ an3 p29_2/ an2 p29_1/ an1 p29_0/ an0 vss5 vdd5 vdd5r vdd5r vcc18c vss5 nmix initx x1a x0a vss5 x0 x1 md_3 monclk md_2 md_1 md_0 vss5 vss5 p02_0 p02_1 p02_2 p02_3 p02_4 p02_5 p02_6 p02_7 p14_0/ icu0/ tin0/ ttg8/ 0 p14_1/ icu1/ tin1/ ttg9/ 1 p14_2/ icu2/ tin2/ ttg10/ 2 p14_3/ icu3/ tin3/ ttg11/ 3 p14_4/ icu4/ tin4/ ttg12/ 4 p14_5/ icu5/ tin5/ ttg13/ 5 p14_6/ icu6/ tin6/ ttg14/ 6 p14_7/ icu7/ tin7/ ttg15/ 7 vdd5 vss5 p15_0/ ocu0/ tot0 p15_1/ ocu1/ tot1 p15_2/ ocu2/ tot2 p15_3/ ocu3/ tot3 p17_4/ ppg4 p17_5/ ppg5 p17_6/ ppg6 p17_7/ ppg7 p16_0/ ppg8 p16_1/ ppg9 p16_2/ ppg10 p16_3/ ppg11 p16_4/ ppg12/ sga p16_5/ ppg13/ sgo p16_6/ ppg14/ pfm p16_7/ ppg15/ atgx vdd5 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 vdd5 p22_2/ int13 p22_0/ int12 p25_7/ smc2m5 p25_6/ smc2p5 p25_5/ smc1m5 p25_4/ smc1p5 hvss5 hvdd5 p25_3/ smc2m4 p25_2/ smc2p4 p25_1/ smc1m4 p25_0/ smc1p4 p26_7/ smc2m3/ an31 p26_6/ smc2p3/ an30 p26_5/ smc1m3/ an29 p26_4/ smc1p3/ an28 hvss5 hvdd5 p26_3/ smc2m2/ an27 p26_2/ smc2p2/ an26 p26_1/ smc1m2/ an25 p26_0/ smc1p2/ an24 p27_7/ smc2m1/ an23 p27_6/ smc2p1/ an22 p27_5/ smc1m1/ an21 p27_4/ smc1p1/ an20 hvss5 hvdd5 p27_3/ smc2m0/ an19 p27_2/ smc2p0/ an18 p27_1/ smc1m0/ an17 p27_0/ smc1p0/ an16 p28_5/ an13 p28_4/ an12 vss5 vss5 p20_0/ sin2/ ain0 p20_1/ sot2/ bin0 p20_2/ sck2/ zin0/ ck2 p19_0/ sin4 p19_1/ sot4 p19_2/ sck4/ ck4 p19_4/ sin5 p19_5/ sot5 p19_6/ sck5/ ck5 p18_0/ sin6/ ain2 p18_1/ sot6/ bin2 p18_2/ sck6/ zin2/ ck6 p18_4/ sin7/ ain3 p18_5/ sot7/ bin3 p18_6/ sck7/ zin3/ ck7 p23_6/ int11 vdd5 vss5 p24_0/ int0 p24_1/ int1 p24_2/ int2 p24_3/ int3 p24_4/ int4/ sda2 p24_5/ int5/ scl2 p24_6/ int6/ sda3 p24_7/ int7/ scl3 p23_0/ rx0/ int8 p23_1/ tx0 p23_2/ rx1/ int9 p23_3/ tx1 p23_4/ rx2/ int10 p23_5/ tx2 p22_4/ sda0/ int14 p22_5/ scl0 vdd5 qfp-144
document number: 002-04609 rev. *a page 7 of 106 mb91460c series 3. pin description 3.1 mb91f463ca, mb91f465ca, mb91f467cx pin no. pin name i/o i/o circuit type* function 2 to 9 p02_0 to p02_7 i/o a general-purpose input/output ports 10 to 17 p14_0 to p14_7 i/o a general-purpose input/output ports icu0 to icu7 input capture input pins tin0 to tin7 external trigger input pins of reload timer ttg8/0 to ttg15/7 external trigger input pins of ppg timer 20 to 23 p15_0 to p15_3 i/o a general-purpose input/output ports ocu0 to ocu3 output compare output pins tot0 to tot3 reload timer output pins 24 to 27 p17_4 to p17_7 i/o a general-purpose input/output ports ppg4 to ppg7 output pins of ppg timer 28 to 31 p16_0 to p16_3 i/o a general-purpose input/output ports ppg8 to ppg11 output pins of ppg timer 32 p16_4 i/o a general-purpose input/output ports ppg12 output pins of ppg timer sga sga output pin of sound generator 33 p16_5 i/o a general-purpose input/output ports ppg13 output pins of ppg timer sgo sgo output pin of sound generator 34 p16_6 i/o a general-purpose input/output ports ppg14 output pins of ppg timer pfm pulse frequency modulator output pin 35 p16_7 i/o a general-purpose input/output ports ppg15 output pins of ppg timer atgx a/d converter external trigger input pin 38 p20_0 i/o a general-purpose input/output ports sin2 data input pin of usart2 ain0 up/down counter input pin 39 p20_1 i/o a general-purpose input/output ports sot2 data output pin of usart2 bin0 up/down counter input pin 40 p20_2 i/o a general-purpose input/output ports sck2 clock input/output pin of usart2 zin0 up/down counter input pin ck2 external clock input pin of free-run timer 2
document number: 002-04609 rev. *a page 8 of 106 mb91460c series 41 p19_0 i/o a general-purpose input/output ports sin4 data input pin of usart4 42 p19_1 i/o a general-purpose input/output ports sot4 data output pin of usart4 43 p19_2 i/o a general-purpose input/output ports sck4 clock input/output pin of usart4 ck4 external clock input pin of free-run timer 4 44 p19_4 i/o a general-purpose input/output ports sin5 data input pin of usart5 45 p19_5 i/o a general-purpose input/output ports sot5 data output pin of usart5 46 p19_6 i/o a general-purpose input/output ports sck5 clock input/output pin of usart5 ck5 external clock input pin of free-run timer 5 47 p18_0 i/o a general-purpose input/output ports sin6 data input pin of usart6 ain2 up/down counter input pin 48 p18_1 i/o a general-purpose input/output ports sot6 data output pin of usart6 bin2 up/down counter input pin 49 p18_2 i/o a general-purpose input/output ports sck6 clock input/output pin of usart6 zin2 up/down counter input pin ck6 external clock input pin of free-run timer 6 50 p18_4 i/o a general-purpose input/output ports sin7 data input pin of usart7 ain3 up/down counter input pin 51 p18_5 i/o a general-purpose input/output ports sot7 data output pin of usart7 bin3 up/down counter input pin 52 p18_6 i/o a general-purpose input/output ports sck7 clock input/output pin of usart7 zin3 up/down counter input pin ck7 external clock input pin of free-run timer 7 53 p23_6 i/o a general-purpose input/output ports int11 external interrupt input (can wakeup) pin no. pin name i/o i/o circuit type* function
document number: 002-04609 rev. *a page 9 of 106 mb91460c series 56 to 59 p24_0 to p24_3 i/o a general-purpose input/output ports int0 to int3 external interrupt input 60 p24_4 i/o a general-purpose input/output ports int4 external interrupt input sda2 i 2 c bus data input/output pin (open drain) 61 p24_5 i/o a general-purpose input/output ports int5 external interrupt input scl2 i 2 c bus clock input/output pin (open drain) 62 p24_6 i/o a general-purpose input/output ports int6 external interrupt input sda3 i 2 c bus data input/output pin (open drain) 63 p24_7 i/o a general-purpose input/output ports int7 external interrupt input scl3 i 2 c bus clock input/output pin (open drain) 64 p23_0 i/o a general-purpose input/output ports rx0 rx input/output pin of can0 int8 external interrupt input (can wakeup) 65 p23_1 i/o a general-purpose input/output ports tx0 tx output pin of can0 66 p23_2 i/o a general-purpose input/output ports rx1 rx input/output pin of can1 int9 external interrupt input (can wakeup) 67 p23_3 i/o a general-purpose input/output ports tx1 tx output pin of can1 68 p23_4 i/o a general-purpose input/output ports rx2 rx input/output pin of can2 int10 external interrupt input (can wakeup) 69 p23_5 i/o a general-purpose input/output ports tx2 tx output pin of can2 70 p22_4 i/o a general-purpose input/output ports sda0 i 2 c bus data input/output pin (open drain) int14 external interrupt input (i 2 c wakeup) 71 p22_5 i/o a general-purpose input/output ports scl0 i 2 c bus clock input/output pin (open drain) 74 to 76 md_0 to md_2 i g mode setting pins 77 monclk o g clock monitor pin 78 md_3 i g to be connected to vss pin no. pin name i/o i/o circuit type* function
document number: 002-04609 rev. *a page 10 of 106 mb91460c series 79 x1 ? j1 clock (oscillation) output 80 x0 ? j1 clock (oscillation) output 82 x0a ? j2 sub clock (oscillation) output 83 x1a ? j2 sub clock (oscillation) output 84 initx i h external reset input pin 85 nmix i h non-maskable interrupt input 92 to 99 p29_0 to p29_7 i/o b general-purpose input/output ports an0 to an7 analog input pins of a/d converter 100 to 103 p28_0 to p28_3 i/o b general-purpose input/output ports an8 to an11 analog input pins of a/d converter 104 alarm_0 i i alarm comparator input pin 110, 111 p28_4, p28_5 i/o b general-purpose input/output ports an12 to an13 analog input pins of a/d converter 112 p27_0 i/o f general-purpose input/output ports smc1p0 controller output pin of stepper motor an16 analog input pins of a/d converter 113 p27_1 i/o f general-purpose input/output ports smc1m0 controller output pin of stepper motor an17 analog input pins of a/d converter 114 p27_2 i/o f general-purpose input/output ports smc2p0 controller output pin of stepper motor an18 analog input pins of a/d converter 115 p27_3 i/o f general-purpose input/output ports smc2m0 controller output pin of stepper motor an19 analog input pins of a/d converter 118 p27_4 i/o f general-purpose input/output ports smc1p1 controller output pin of stepper motor an20 analog input pins of a/d converter 119 p27_5 i/o f general-purpose input/output ports smc1m1 controller output pin of stepper motor an21 analog input pins of a/d converter 120 p27_6 i/o f general-purpose input/output ports smc2p1 controller output pin of stepper motor an22 analog input pins of a/d converter 121 p27_7 i/o f general-purpose input/output ports smc2m1 controller output pin of stepper motor an23 analog input pins of a/d converter pin no. pin name i/o i/o circuit type* function
document number: 002-04609 rev. *a page 11 of 106 mb91460c series 122 p26_0 i/o f general-purpose input/output ports smc1p2 controller output pin of stepper motor an24 analog input pins of a/d converter 123 p26_1 i/o f general-purpose input/output ports smc1m2 controller output pin of stepper motor an25 analog input pins of a/d converter 124 p26_2 i/o f general-purpose input/output ports smc2p2 controller output pin of stepper motor an26 analog input pins of a/d converter 125 p26_3 i/o f general-purpose input/output ports smc2m2 controller output pin of stepper motor an27 analog input pins of a/d converter 128 p26_4 i/o f general-purpose input/output ports smc1p3 controller output pin of stepper motor an28 analog input pins of a/d converter 129 p26_5 i/o f general-purpose input/output ports smc1m3 controller output pin of stepper motor an29 analog input pins of a/d converter 130 p26_6 i/o f general-purpose input/output ports smc2p3 controller output pin of stepper motor an30 analog input pins of a/d converter 131 p26_7 i/o f general-purpose input/output ports smc2m3 controller output pin of stepper motor an31 analog input pins of a/d converter 132 p25_0 i/o e general-purpose input/output ports smc1p4 controller output pin of stepper motor 133 p25_1 i/o e general-purpose input/output ports smc1m4 controller output pin of stepper motor 134 p25_2 i/o e general-purpose input/output ports smc2p4 controller output pin of stepper motor 135 p25_3 i/o e general-purpose input/output ports smc2m4 controller output pin of stepper motor 138 p25_4 i/o e general-purpose input/output ports smc1p5 controller output pin of stepper motor 139 p25_5 i/o e general-purpose input/output ports smc1m5 controller output pin of stepper motor pin no. pin name i/o i/o circuit type* function
document number: 002-04609 rev. *a page 12 of 106 mb91460c series * : for information about the i/o circui t type, refer to ?4. i/o circuit types?. 140 p25_6 i/o e general-purpose input/output ports smc2p5 controller output pin of stepper motor 141 p25_7 i/o e general-purpose input/output ports smc2m5 controller output pin of stepper motor 142 p22_0 i/o a general-purpose input/output ports int12 external interrupt input (i 2 c wakeup) 143 p22_2 i/o a general-purpose input/output ports int13 external interrupt input (i 2 c wakeup) pin no. pin name i/o i/o circuit type* function
document number: 002-04609 rev. *a page 13 of 106 mb91460c series [power supply/ground pins] pin no. pin name i/o function 1, 19, 37, 55, 73, 81, 86, 91, 109 vss5 supply ground pins 117, 127, 137 hvss5 ground pins for stepper motor controller 18, 36, 54, 72, 90, 108, 144 vdd5 power supply pins 116, 126, 136 hvdd5 power supply pins for stepper motor controller 88, 89 vdd5r power supply pins for internal regulator 105 avss5 analog ground pin for a/d converter 107 avcc5 power supply pin for a/d converter 106 avrh5 reference power supply pin for a/d converter 87 vcc18c capacitor connection pin for internal regulator
document number: 002-04609 rev. *a page 14 of 106 mb91460c series 4. i/o circuit types type circuit remarks a cmos level output (programmable i ol = 5ma, i oh = -5ma and i ol = 2ma, i oh = -2ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function ttl input with input shutdown function programmable pull-up resistor: 50k ? approx. b cmos level output (programmable i ol = 5ma, i oh = -5ma and i ol = 2ma, i oh = -2ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function ttl input with input shutdown function programmable pull-up resistor: 50k ? approx. analog input pull-up control r cmos hysteresis type1 automotive inputs ttl input cmos hysteresis type2 pull- down control driver strength control data line standby control for input shutdown r analog input pull-up control pull- down control driver strength control data line cmos hysteresis type1 automotive inputs ttl input cmos hysteresis type2 standby control for input shutdown
document number: 002-04609 rev. *a page 15 of 106 mb91460c series c cmos level output (i ol = 3ma, i oh = -3ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function ttl input with input shutdown function programmable pull-up resistor: 50k ? approx. d cmos level output (i ol = 3ma, i oh = -3ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function ttl input with input shutdown function programmable pull-up resistor: 50k ? approx. analog input type circuit remarks pull-up control r cmos hysteresis type1 automotive inputs ttl input cmos hysteresis type2 pull- down control data line standby control for input shutdown r analog input pull-up control pull- down control data line cmos hysteresis type1 automotive inputs ttl input cmos hysteresis type2 standby control for input shutdown
document number: 002-04609 rev. *a page 16 of 106 mb91460c series e cmos level output (programmable i ol = 5ma, i oh = -5ma and i ol = 2ma, i oh = -2ma, and i ol = 30ma, i oh = -30ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function ttl input with input shutdown function programmable pull-up resistor: 50k ? approx. f cmos level output (programmable i ol = 5ma, i oh = -5ma and i ol = 2ma, i oh = -2ma, and i ol = 30ma, i oh = -30ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function ttl input with input shutdown function programmable pull-up resistor: 50k ? approx. analog input type circuit remarks pull-up control r cmos hysteresis type1 automotive inputs ttl input cmos hysteresis type2 pull- down control driver strength control data line standby control for input shutdown r analog input pull-up c ontrol pull- down control driver strength control data line cmos hysteresis type1 automotive inputs ttl input cmos hysteresis type2 standby control for input shutdown
document number: 002-04609 rev. *a page 17 of 106 mb91460c series g mask rom and eva device: cmos hysteresis input pin flash device: cmos input pin 12 v withstand (for md [2:0]) h cmos hysteresis input pin pull-up resistor value: 50 k ? approx. j1 high-speed oscillation circuit: ? programmable between oscillation mode (external crystal or resonator connected to x0/x1 pins) and fast external clock input (fci) mode (external clock connected to x0 pin) ? feedback resistor = approx. 2 * 0.5 m ? . feedback resistor is grounded in the center when the oscillator is disabled or in fci mode. j2 low-speed oscillation circuit: ? feedback resistor = approx. 2 * 5 m ? . feedback resistor is grounded in the center when the oscillator is disabled. type circuit remarks r hysteresis inputs r pull-up resistor hysteresis inputs x1 x0 r r xout fci 0 1 fci or osc disable x1a x0a r r xout osc disable
document number: 002-04609 rev. *a page 18 of 106 mb91460c series k cmos level output (programmable i ol = 5ma, i oh = -5ma and i ol = 2ma, i oh = -2ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function ttl input with input shutdown function programmable pull-up resistor: 50k ? approx. lcd seg/com output l cmos level output (programmable i ol = 5ma, i oh = -5ma and i ol = 2ma, i oh = -2ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function) ttl input with input shutdown function programmable pull-up resistor: 50k ? approx. analog input lcd voltage input type circuit remarks pull-up control r cmos hysteresis type1 automotive inputs ttl input cmos hysteresis type2 pull- down control driver strength control data line standby control for input shutdown lcd seg/com r pull-up control pull- down control driver strength control data line cmos hysteresis type1 automotive inputs ttl input cmos hysteresis type2 standby control for input shutdown vlcd
document number: 002-04609 rev. *a page 19 of 106 mb91460c series m cmos level tri-state output (i ol = 5ma, i oh = -5ma) n analog input pin with protection type circuit remarks tri-state control data line analog input line
document number: 002-04609 rev. *a page 20 of 106 mb91460c series 5. handling devices 5.1 preventing latch-up latch-up may occur in a cmos ic if a voltage higher than (v dd 5, v dd 35 or hv dd 5 * 1 ) or less than (v ss 5 or hv ss 5 * 1 ) is applied to an input or output pin or if a voltage exceeding the rating is applied between the power supply pins and ground pins. if latch- up occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the device . therefore, be very careful not to apply voltages in excess of the absolute maximum ratings. note *1: hv dd 5, hv ss 5 are available only on devices having stepper motor controller. 5.2 handling of unused input pins if unused input pins are left open, abnormal operation may result . any unused input pins should be connected to pull-up or pull -down resistor (2k ? to 10k ? ) or enable internal pullup or pulldown resisters (pper/ ppcr) before the input enable (porten) is activated by software. the mode pins md_x can be connected to v ss 5 or v dd 5 directly. unused alarm input pins can be connected to av ss 5 directly. 5.3 power supply pins in mb91460 series, devices including multiple power supply pins and ground pins are designed as follows; pins necessary to be a t the same potential are interconnected internally to prevent malf unctions such as latch-up. all of the power supply pins and gro und pins must be externally connected to the power supply and ground re spectively in order to reduce unnecessary radiation, to prev ent strobe signal malfunctions due to the ground level rising and to follow the total output current ratings. furthermore, the powe r supply pins and ground pins of the mb91460 series must be con nected to the current supply source via a low impedance. it is also recommended to connect a ceramic capacitor of approximately 0.1 ? f as a bypass capacitor between power supply pin and ground pin near this device. this series has a built-in step-down regulator. connect a bypass capacitor of 4.7 ? f (use a x7r ceramic capacitor) to vcc18c pin for the regulator. 5.4 crystal oscillator circuit noise in proximity to the x0 (x0a) and x1 (x1a) pins can cause the device to operate abnormally. printed circuit boards should be designed so that the x0 (x0a) and x1 (x1a) pins, and crystal o scillator, as well as bypass capacitors connected to ground, are located near the device and ground. it is recommended that the printed circuit board layout be designed such that the x0 and x1 pins or x0a and x1a pins are surrou nded by ground plane for the stable operation. please request the oscillator manufacture r to evaluate the oscillational characte ristics of the crystal and this device. 5.5 notes on using external clock when using the external clock, it is necessary to simultaneous ly supply the x0 (x0a) and the x1 (x1a) pins. in the described combination, x1 (x1a) should be supplied with a clock signal whic h has the opposite phase to the x0 (x0a) pins. at x0 and x1, a frequency up to 16 mhz is possible. example of using opposite phase supply (continued) x0 (x0a) x1 (x1a)
document number: 002-04609 rev. *a page 21 of 106 mb91460c series (continued) 5.6 mode pins (md_x) these pins should be connected directly to the power supply or gr ound pins. to prevent the device from entering test mode accid entally due to noise, minimize the lengths of the patterns between each mode pin and power supply pin or ground pin on the printed circ uit board as possible and connect them with low impedance. 5.7 notes on operating in pll clock mode if the oscillator is disconnected or the clock input stops when th e pll clock is selected, the mi crocontroller may continue to operate at the free-running frequency of the self-oscillating circuit of the pll. however, this self-running operation cannot be guaran teed. 5.8 pull-up control the ac standard is not guaranteed in case a pull-up resistor is connected to the pin serving as an external bus pin.
document number: 002-04609 rev. *a page 22 of 106 mb91460c series 6. notes on debugger 6.1 execution of the reti command if single-step execution is used in an envir onment where an interrupt occurs frequently , the corresponding interrupt handling r outine will be executed repeatedly to the exclusion of other processing. this will prevent th e main routine and the handlers for low p riority level interrupts from being executed (for example, if the time-b ase timer interrupt is enabled, stepping over the reti instruct ion will always break on the first line of the time-base timer interrupt handler). disable the corresponding interrupts when the corresponding interrupt handling routine no longer needs debugging. 6.2 break function if the range of addresses that cause a hardware break (including event breaks) is set to the ad dress of the current system stac k pointer or to an area that contains the stack pointer, execution will break after each instruction regardless of whether the user progr am actually contains data access instructions. to prevent this, do not set (word) access to the area containing the address of the system stack pointer as the target of the h ardware break (including an event breaks). 6.3 operand break it may cause malfunctions if a stack pointer exists in the area which is set as the dsu operand break. do not set the access to the areas containing the address of system stack pointer as a target of data event break. 6.4 notes on ps register as the ps register is processed in adv ance by some instructions, when the debugger is being used, the exception handling may re sult in execution breaking in an interrupt handling routine or the displayed values of the flags in the ps register being updated. as the microcontroller is designed to carry out reprocessing corre ctly upon returning from such an eit event, the operation bef ore and after the eit always proce eds according to specification. the following behavior may occur if any of the follo wing occurs in the instruction immediately after a div0u/div0s instruction: a. a user interrupt or nmi is accepted; b. single-step execution is performed; c. execution breaks due to a data event or from the emulator menu. 1. d0 and d1 flags are updated in advance. 2. an eit handling routine (user inte rrupt/nmi or emulator) is executed. 3. upon returning from the eit, the div0u/div0s instruction is executed and the d0 and d1 flags are updated to the same values as those in 1. the following behavior occurs when an orccr, stilm, mov ri,ps instruction is executed to enable a user interrupt or nmi source while that interrupt is in the active state. 1 . the ps register is updated in advance. 2. an eit handling routine (user inte rrupt/nmi or emulator) is executed. 3. upon returning from the eit, the above in structions are executed and the ps register is updated to the same value as in 1.
document number: 002-04609 rev. *a page 23 of 106 mb91460c series 7. block diagram 7.1 mb91f463ca, mb91f465ca, mb91f467cx ain0,ain2,ain3 bin0,bin2,bin3 zin0,zin2,zin3 ttg4 to ttg15 ppg4 to ppg15 tin0 to tin7 tot0 to tot3 ck2,ck4 to ck7 icu0 to icu7 ocu0 to ocu3 alarm_0 pfm sda0,sda2,sda3 scl0,scl2,scl3 an0 to an13, an16 to an31 atgx sga sg0 sin2,sin4 to sin7 sot2,sot4 to sot7 sck2,sck4 to sck7 smc1p0 to smc1p5 smc1m0 to smc1m5 smc2m0 to smc2m5 smc2p0 to smc2p5 rx0 to rx2 tx0 to tx2 r-bus 16 i-bus 32 d-bus 32 fr60 cpu core flash-cache 8 kbytes (mb91f467cx) 8 kbytes (mb91f465ca) 4 kbytes (mb91f463ca) flash memory 1088 kbytes (mb91f467cx) 544 kbytes (mb91f465ca) 288 kbytes (mb91f463ca) bus converter bit search can 3 channels 32 <-> 16 bus adapter dmac 5 channels clock modulator clock monitor monclk interrupt controller int0 to int14 external interrupt 15 channels clock supervisor clock control ppg timer 12 channels reload timer 8 channels free-run timer 8 channels input capture 8 channels output compare 4 channels up/down counter 3 channels pfm timer 1 channel alarm comparator 1 channel lin-usart 5 channels 3 channels i c 2 real time clock a/d converter 30 channels stepper motor controller 6 channels sound generator 1 channel d-ram 32 kbytes (mb91f467cx) 16 kbytes (mb91f465ca) 16 kbytes (mb91f463ca) id-ram 32 kbytes (mb91f467cx) 16 kbytes (mb91f465ca) 8 kbytes (mb91f463ca)
document number: 002-04609 rev. *a page 24 of 106 mb91460c series 8. cpu and control unit the fr family cpu is a high performance core that is designed based on the risc architecture with advanced instructions for embedded applications. 8.1 features adoption of risc architecture basic instruction: 1 instruction per cycle general-purpose registers: 32-bit 16 registers 4 gbytes linear memory space multiplier installed 32-bit 32-bit mult iplication: 5 cycles 16-bit 16-bit mult iplication: 3 cycles enhanced interrupt processing function quick response speed (6 cycles) multiple-interrupt support level mask function (16 levels) enhanced instructions for i/o operation memory-to-memory transfer instruction bit processing instruction basic instruction word length: 16 bits low-power consumption sleep mode/stop mode 8.2 internal architecture the fr family cpu uses the harvard architecture in which the instruction bus and data bus are independent of each other. a 32-bit ? 16-bit buffer is connected to the 32-bit bus (d-bus) to pr ovide an interface between the cpu and peripheral resources. a harvard ? princeton bus converter is connected to both the i-bu s and d-bus to provide an interface between the cpu and the bus controller.
document number: 002-04609 rev. *a page 25 of 106 mb91460c series 8.3 programming model 8.3.1 basic programming model ilm scr ccr fp sp ac . . . . . . . . . . . . xxxx xxxx h 0000 0000 h xxxx xxxx h . . . . . . . . . r0 r1 r12 r13 r14 r15 pc rs rp tbr ssp usp mdl mdh . . . . . . 32 bits initial value general-purpose registers program counter program status table base register return pointer system stack pointer user stack pointer multiply & divide registers
document number: 002-04609 rev. *a page 26 of 106 mb91460c series 8.4 registers 8.4.1 general-purpose register registers r0 to r15 are general-purpose regi sters. these registers can be used as accumu lators for computation operations and a s pointers for memory access. of the 16 registers, enhanced commands are provided for the fo llowing registers to enable their use for particular applications . r13 : virtual accumulator r14 : frame pointer r15 : stack pointer initial values at reset are undefined for r0 to r14. the value for r15 is 00000000 h (ssp value). 8.4.2 ps (program status) this register holds the program status, and is divided into three parts, ilm, scr, and ccr. all undefined bits (-) in the diagram are reserved bits. the read values are always ?0?. write access to these bits is invalid. fp sp ac . . . . . . . . . . . . xxxx xxxx h 0000 0000 h xxxx xxxx h . . . . . . . . . r0 r1 r12 r13 r14 r15 . . . . . . 32 bits initial value bit position bit 20 bit 0 bit 7 bit 8 bit 10 bit 16 ilm scr ccr bit 31
document number: 002-04609 rev. *a page 27 of 106 mb91460c series 8.4.3 ccr (condition code register) sv : supervisor flag s : stack flag i : interrupt enable flag n : negative enable flag z : zero flag v : overflow flag c : carry flag 8.4.4 scr (system condition register) flag for step division (d1, d0) this flag stores interim data during execution of step division. step trace trap flag (t) this flag indicates whether the step trace trap is enabled or disabled. the step trace trap function is used by emul ators. when an emulator is in use, it ca nnot be used in execut ion of user programs. 8.4.5 ilm (interrupt level mask register) this register stores interrupt level mask values, and the values stored in ilm4 to ilm0 are used for level masking. the register is initialized to value ?01111 b ? at reset. 8.4.6 pc (program counter) the program counter indicates the address of the instruction that is being executed. the initial value at reset is undefined. - 000xxxx b bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 c v z n i s sv initial value bit 10 bit 8 bit 9 d1 d0 t xx0 b initial value bit 18 bit 16 bit 17 ilm2 ilm1 ilm0 01111 b ilm3 ilm4 bit 20 bit 19 initial value bit 0 bit 31 xxxxxxxx h initial value
document number: 002-04609 rev. *a page 28 of 106 mb91460c series 8.4.7 tbr (table base register) the table base register stores the starting add ress of the vector tabl e used in eit processing. the initial value at reset is 000ffc00 h . 8.4.8 rp (return pointer) the return pointer stores the address for return from subroutines. during execution of a call instruction, the pc value is transferred to this rp register. during execution of a ret instruction, the conten ts of the rp register are transferred to pc. the initial value at reset is undefined. 8.4.9 usp (user stack pointer) the user stack pointer, when the s flag is ?1?, this register functions as the r15 register. ? the usp register can also be explicitly specified. the initial value at reset is undefined. ? this register cannot be used with reti instructions. 8.4.10 multiply & divide registers these registers are for multiplication and division, and are each 32 bits in length. the initial value at reset is undefined. bit 0 bit 31 000ffc00 h initial value bit 0 bit 31 xxxxxxxx h initial value bit 0 bit 31 xxxxxxxx h initial value bit 0 mdl bit 31 mdh
document number: 002-04609 rev. *a page 29 of 106 mb91460c series 9. embedded program /data memory (flash) 9.1 flash features mb91f467cx: 1088 kbytes (16 64 kbytes ? 8 8 kbytes = 8.5 mbits) mb91f465ca:544 kbytes (8 64 kbytes ? 4 8 kbytes = 4.25 mbits) mb91f463ca:288 kbytes (4 64 kb ytes + 4 8 kbytes = 2.25 mbits) programmable wait states for read/write access flash and boot security with security vector at 0x0014:8000 - 0x0014:800f boot security basic specification: same as mbm29lv400tc (e xcept size and part of sector configuration) 9.2 operation modes: (1) 64-bit cpu mode (available on mb91f467cx only) : ? cpu reads and executes programs in word (32-bit) length units. ? flash writing is not possible. ? actual flash memory access is performed in d-word (64-bit) length units. (1) 32-bit cpu mode: ? cpu reads and executes programs in word (32-bit) length units. ? actual flash memory access is performed in word (32-bit) length units. (2) 16-bit cpu mode: ? cpu reads and writes in half-word (16-bit) length units. ? program execution from the flash is not possible. ? actual flash memory access is performed in word (16-bit) length units. note: the operation mode of the mcu can be selected using a boot -rom function. the function start address is 0xbf60. the parame ter description is given in the hardware manual in chapter 54.6 ?flash access mode switching?.
document number: 002-04609 rev. *a page 30 of 106 mb91460c series 9.3 flash access in cpu mode 9.3.1 flash configuration flash memory map mb91f467cx roms1 roms0 addr+6 roms5 roms4 roms6 roms7 roms3 roms2 dat[31:16] dat[15:0] dat[31:0] dat[31:0] dat[31:16] dat[15:0] 16bit read/write 32bit read/write dat[63:0] 64bit read addr+7 addr+2 sa0 (8kb) sa16 (64kb) sa10 (64kb) sa21 (64kb) sa19 (64kb) addre ss 0014:ffffh 0014:c000h 0014:bfffh 0014:8000h sa7 (8kb) sa5 (8kb) sa3 (8kb) sa1 (8kb) sa23 (64kb) sa6 (8kb) sa4 (8kb) sa2 (8kb) sa22 (64kb) sa20 (64kb) 0013:ffffh 0012:0000h 0011:ffffh 0010:0000h sa18 (64kb) 0014:7fffh 0014:4000h 0014:3fffh 0014:0000h 000f:ffffh 000e:0000h sa15 (64kb) 000d:ffffh 000c:0000h 000b:ffffh 000a:0000h addr+5 sa11 (64kb) sa8 (64kb) sa9 (64kb) addr+0 addr+1 addr+3 addr+4 0009:ffffh 0008:0000h 0007:ffffh 0006:0000h 0005:ffffh 0004:0000h sa17 (64kb) sa14 (64kb) sa12 (64kb) sa13 (64kb)
document number: 002-04609 rev. *a page 31 of 106 mb91460c series flash memory map mb91f465ca roms7 addr+3 addr+4 0009:ffffh 0008:0000h 0007:ffffh 0006:0000h 0005:ffffh 0004:0000h sa12 (64kb) sa13 (64kb) 0014:7fffh 0014:4000h 0014:3fffh 0014:0000h sa15 (64kb) 000d:ffffh 000c:0000h 000b:ffffh 000a:0000h sa17 (64kb) sa14 (64kb) sa22 (64kb) sa20 (64kb) 0013:ffffh 0012:0000h 0011:ffffh 0010:0000h sa18 (64kb) 000f:ffffh 000e:0000h sa7 (8kb) sa5 (8kb) sa3 (8kb) sa1 (8kb) sa23 (64kb) sa6 (8kb) sa4 (8kb) sa2 (8kb) addr 0014:ffffh 0014:c000h 0014:bfffh 0014:8000h addr+7 addr+2 sa0 (8kb) sa16 (64kb) sa10 (64kb) sa21 (64kb) sa19 (64kb) dat[15:0] 16bit read/write 32bit read legend memory not available in thi s area roms2 dat[31:16] dat[15:0] dat[31:0] dat[31:0] dat[31:16] roms1 roms0 addr+6 roms5 roms4 roms6 roms3 memory available in thi s area addr+5 sa11 (64kb) sa8 (64kb) sa9 (64kb) addr+0 addr+1
document number: 002-04609 rev. *a page 32 of 106 mb91460c series flash memory map mb91f463ca roms7 addr+3 addr+4 0009:ffffh 0008:0000h 0007:ffffh 0006:0000h 0005:ffffh 0004:0000h sa12 (64kb) sa13 (64kb) 0014:7fffh 0014:4000h 0014:3fffh 0014:0000h sa15 (64kb) 000d:ffffh 000c:0000h 000b:ffffh 000a:0000h sa17 (64kb) sa14 (64kb) sa22 (64kb) sa20 (64kb) 0013:ffffh 0012:0000h 0011:ffffh 0010:0000h sa18 (64kb) 000f:ffffh 000e:0000h sa7 (8kb) sa5 (8kb) sa3 (8kb) sa1 (8kb) sa23 (64kb) sa6 (8kb) sa4 (8kb) sa2 (8kb) addre ss 0014:ffffh 0014:c000h 0014:bfffh 0014:8000h addr+7 addr+2 sa0 (8kb) sa16 (64kb) sa10 (64kb) sa21 (64kb) sa19 (64kb) dat[15:0] 16bit read/write 32bit read legend memory not available in thi s area roms2 dat[31:16] dat[15:0] dat[31:0] dat[31:0] dat[31:16] roms1 roms0 addr+6 roms5 roms4 roms6 roms3 memory available in thi s area addr+5 sa11 (64kb) sa8 (64kb) sa9 (64kb) addr+0 addr+1
document number: 002-04609 rev. *a page 33 of 106 mb91460c series 9.3.2 flash access timing settings in cpu mode the following tables list all settings for a given maximum core frequency (through the setting of clkb or maximum clock modulat ion) for flash read and write access. flash read timing settings (synchronous read) flash write timing settings (synchronous write) core clock (clkb) atd aleh eq wexh wtc remark to 24 mhz 0 0 0 - 1 to 48 mhz 0 0 1 - 2 to 100 mhz 1 1 3 - 4 core clock (clkb) atd aleh eq wexh wtc remark to 16 mhz 0 - - 0 3 to 32 mhz 0 - - 0 4 to 48 mhz 0 - - 0 5 to 64 mhz 1 - - 0 6 to 96 mhz 1 - - 0 7 to 100 mhz 1 - - 1 8
document number: 002-04609 rev. *a page 34 of 106 mb91460c series 9.3.3 address mapping from cpu to parallel programming mode the following tables show the calculation from cpu addresses to flash macro addresses which are used in parallel programming. address mapping mb91f467cx note: fa result is without 20:0000h offs et for parallel flash programming. set offset by keeping fa[21] = 1 as described in section ?parallel flash programming mode?. address mapping mb91f463ca, mb91f465ca note: fa result is without 10:0000h offs et for parallel flash programming. set offset by keeping fa[20] = 1 as described in section ?parallel flash programming mode?. cpu address (addr) condition flash sectors fa (flash address) calculation 14:0000h to 14:ffffh addr[2]==0 sa0, sa2, sa4, sa6 (8 kbyte) fa := addr - addr%00:4000h + (addr%00:4000h)/2 - (addr/2)%4 + addr%4 - 05:0000h 14:0000h to 14:ffffh addr[2]==1 sa1, sa3, sa5, sa7 (8 kbyte) fa := addr - addr%00:4000h + (addr%00:4000h)/2 + 00:2000h - (addr/2)%4 + addr%4 - 05:0000h 04:0000h to 13:ffffh addr[2]==0 sa8, sa10, sa12, sa14, sa16, sa18, sa20, sa22 (64 kbyte) fa := addr - addr%02:0000 + (addr%02:0000h)/2 - (addr/2)%4 + addr%4 + 0c:0000h 04:0000h to 13:ffffh addr[2]==1 sa9, sa11, sa13, sa15, sa17, sa19, sa21, sa23 (64 kbyte) fa := addr - addr%02:0000h + (addr%02:0000h)/2 + 01:0000h - (addr/2)%4 + addr%4 + 0c:0000h cpu address (addr) condition flash sectors fa (flash address) calculation 14:8000h to 14:ffffh addr[2]==0 sa4, sa6 (8 kbyte) fa := addr - addr%00:4000h + (addr%00:4000h)/2 - (addr/2)%4 + addr%4 - 0d:0000h 14:8000h to 14:ffffh addr[2]==1 sa5, sa7 (8 kbyte) fa := addr - addr%00:4000h + (addr%00:4000h)/2 + 00:2000h - (addr/2)%4 + addr%4 - 0d:0000h 08:0000h to 13f:ffffh addr[2]==0 sa12, sa14 (mb91f465ca) sa16, sa18 (64 kbyte) fa := addr - addr%02:0000 + (addr%02:0000h)/2 - (addr/2)%4 + addr%4 08:0000h to 13f:ffffh addr[2]==1 sa13, sa15 (mb91f465ca) sa17, sa19 (64 kbyte) fa := addr - addr%02:0000h + (addr%02:0000h)/2 + 01:0000h - (addr/2)%4 + addr%4
document number: 002-04609 rev. *a page 35 of 106 mb91460c series 9.4 parallel flash programming mode 9.4.1 flash configuration in parallel flash programming mode parallel flash programming mode (md[2:0] = 111): mb91f467cx mb91f465ca 16bit write mode dq[15:0] dq[15:0] sa20 (64kb) sa19 (64kb) sa18 (64kb) fa[21:0] 003e:ffffh 003e:0000h 003d:ffffh 003d:0000h 003f:ffffh 003f:0000h sa23 (64kb) sa22 (64kb) sa21 (64kb) 003c:ffffh 003c:0000h 003b:ffffh 003b:0000h 003a:ffffh 003a:0000h 0039:ffffh 0039:0000h sa17 (64kb) 0038:ffffh 0038:0000h 0037:ffffh 0037:0000h sa16 (64kb) sa15 (64kb) 0036:ffffh 0036:0000h 0035:ffffh 0035:0000h sa14 (64kb) sa13 (64kb) 0034:ffffh 0034:0000h 0033:ffffh 0033:0000h sa12 (64kb) sa11 (64kb) 0032:ffffh 0032:0000h 0031:ffffh 0031:0000h sa10 (64kb) sa9 (64kb) 0030:ffffh 0030:0000h 002f:ffffh 002f:e000h sa8 (64kb) sa7 (8kb) 002f:7fffh 002f:6000h sa4 (8kb) sa3 (8kb) 002f:dfffh 002f:c000h 002f:bfffh 002f:a000h sa6 (8kb) sa5 (8kb) 002f:1fffh 002f:0000h sa0 (8kb) fa[1:0]=00 fa[1:0]=10 002f:5fffh 002f:4000h 002f:3fffh 002f:2000h sa2 (8kb) sa1 (8kb) 002f:9fffh 002f:8000h remark: always keep fa[0] = 0 and fa[21] = 1 sa0 (8kb) fa[1:0]=00 fa[1:0]=10 sa2 (8kb) sa1 (8kb) 0017:9fffh 0017:8000h sa4 (8kb) sa3 (8kb) 0017:dfffh 0017:c000h 0017:bfffh 0017:a000h sa6 (8kb) sa5 (8kb) 0017:ffffh 0017:e000h sa8 (64kb) sa7 (8kb) sa10 (64kb) sa9 (64kb) 0018:ffffh 0018:0000h sa12 (64kb) sa11 (64kb) 001a:ffffh 001a:0000h 0019:ffffh 0019:0000h sa14 (64kb) sa13 (64kb) 001c:ffffh 001c:0000h 001b:ffffh 001b:0000h sa16 (64kb) sa15 (64kb) 001e:ffffh 001e:0000h 001d:ffffh 001d:0000h sa17 (64kb) 001f:ffffh 001f:0000h sa19 (64kb) sa18 (64kb) dq[15:0] dq[15:0] remark: alway s keep fa[0] = 0 and fa[20] = 1 16bit write mode legend memory available in thi s area memory not available in thi s area fa[20:0]
document number: 002-04609 rev. *a page 36 of 106 mb91460c series mb91f463ca fa[20:0] sa0 (8kb) fa[1:0]=00 fa[1:0]=10 sa2 (8kb) sa1 (8kb) 0017:9fffh 0017:8000h sa4 (8kb) sa3 (8kb) 0017:dfffh 0017:c000h 0017:bfffh 0017:a000h sa6 (8kb) sa5 (8kb) 0017:ffffh 0017:e000h sa8 (64kb) sa7 (8kb) sa10 (64kb) sa9 (64kb) sa12 (64kb) sa11 (64kb) sa14 (64kb) sa13 (64kb) 001c:ffffh 001c:0000h sa16 (64kb) sa15 (64kb) 001e:ffffh 001e:0000h 001d:ffffh 001d:0000h sa17 (64kb) 001f:ffffh 001f:0000h sa19 (64kb) sa18 (64kb) dq[15:0] dq[15:0] remark: alway s keep fa[0] = 0 and fa[20] = 1 16bit write mode legend memory available in thi s area memory not available in thi s area
document number: 002-04609 rev. *a page 37 of 106 mb91460c series 9.4.2 pin connections in parallel programming mode resetting after setting the md[2:0] pins to [111] will halt cpu f unctioning. at this time, the flash memory's interface circuit enables direct control of the flash memory unit from external pins by directly linking some of the signals to gp-ports. please see tabl e below for signal mapping. in this mode, the flash memory appears to the external pins as a stand-alone unit. this mode is generally set when writing/eras ing using the parallel flash programmer. in this mode, all operations of the 8.5 mbits flash memory's auto algorithms are available . correspondence between mbm29lv400tc and flash memory control signals mbm29lv400tc external pins fr-cpu mode mb91f465ca, mb91f467cx external pins comment flash memory mode normal function pin number ? initx ? initx 84 reset ? frstx nmix 85 ? ? md_2 md_2 76 set to ?1? ? ? md_1 md_1 75 set to ?1? ? ? md_0 md_0 74 set to ?1? ry/by fmcs:rdy bit ry/byx gp28_0 100 byte internally fixed to ?h? bytex gp28_2 102 we internal control signal + control via interface circuit wex gp28_5 111 oe oex gp28_4 110 ce cex gp20_0 38 ? atdin gp17_7 27 set to ?0? ? eqin gp17_6 26 set to ?0? ? testx gp28_3 103 set to ?1? ? rdyi gp28_1 101 set to ?0? a-1 internal address bus fa0 gp17_5 25 set to ?0? a0 to a3 fa1 to fa4 gp29_0 to gp29_3 92 to 95 a4 to a7 fa5 to fa8 gp29_4 to gp29_7 96 to 99 a8 to a11 fa9 to fa12 gp16_0 to gp16_3 28 to 31 a12 to a15 fa13 to fa16 gp16_4 to gp16_7 32 to 35 a16 to a18 fa17 to fa19 gp15_0 to gp15_2 20 to 22 a19 fa20 gp15_3 23 set to ?1? on mb91f463ca, mb91f465ca ? fa21 gp17_4 24 set to ?1? dq0 to dq7 internal data bus dq0 to dq7 gp14_0 to gp14_7 10 to 17 dq8 to dq15 dq8 to dq15 gp02_0 to gp02_7 2 to 9
document number: 002-04609 rev. *a page 38 of 106 mb91460c series 9.5 power on sequence in parallel programming mode the flash memory can be accessed in programming mode after a ce rtain wait time, which is needed for security vector fetch: minimum wait time after vdd5/vdd5r power on: 2.76 ms minimum wait time afte r initx rising: 1.0 ms 9.6 flash security 9.6.1 vector addresses two flash security vectors (fsv1, fsv2) are located parallel to the boot security vectors (bsv1, bsv2) controlling the protecti on functions of the flash security module: fsv1: 0x14:8000 bsv1: 0x14:8004 fsv2: 0x14:8008 bsv2: 0x14:800c 9.6.2 security vector fsv1 the setting of the flash security vector fsv1 is responsible fo r the read and write protection modes and the individual write p rotection of the 8 kbytes sectors. fsv1 (bit31 to bit16) the setting of the flash security vector fsv1 bits [31: 16] is responsible for the read and write protection modes. explanation of the bits in the fl ash security vector fsv1[31:16] fsv1[31:19] fsv1[18] write protection level fsv1[17] write protection fsv1[16] read protection flash security mode set all to ?0? set to ?0? set to ?0? set to ?1? read protection (all device modes, except in- tvec mode md[2:0]=?000?) set all to ?0? set to ?0? set to ?1? set to ?0? write protection (all de vice modes, without ex- ception) set all to ?0? set to ?0? set to ?1? set to ?1? read protection (all device modes, except in- tvec mode md[2:0]=?000?) and write protec- tion (all device modes) set all to ?0? set to ?1? set to ?0? set to ?1? read protection (all device modes, except in- tvec mode md[2:0]=?000?) set all to ?0? set to ?1? set to ?1? set to ?0? write protection (all device modes, except in- tvec mode md[2:0]=?000?) set all to ?0? set to ?1? set to ?1? set to ?1? read protection (all device modes, except in- tvec mode md[2:0]=?000?) and write protec- tion (all device modes except intvec mode md[2:0]=?000?)
document number: 002-04609 rev. *a page 39 of 106 mb91460c series fsv1 (bit15 to bit0) the setting of the flash security vector fsv1 bits [15:0] is responsible for the individual wr ite protection of the 8 kbytes se ctors. it is only evaluated if write protection bit fsv1[17] is set. explanation of the bits in the fl ash security vector fsv1[15:0] note : it is mandatory to always set the sector where the flash secu rity vectors fsv1 and fsv2 are located to write protected (here sector sa4). otherwise it is possible to overwrite the security vector to a se tting where it is possible to either read out the flash content or manipulate data by writing. see section ?9.3. flash access in cpu mode? for an over view about the sector organ isation of the flash memory . fsv1 bit sector enable write protection disable write protection comment fsv1[0] sa0 set to ?0? set to ?1? sectors available on mb91f467cx only fsv1[1] sa1 set to ?0? set to ?1? fsv1[2] sa2 set to ?0? set to ?1? fsv1[3] sa3 set to ?0? set to ?1? fsv1[4] sa4 set to ?0? ? write protection is mandatory! fsv1[5] sa5 set to ?0? set to ?1? fsv1[6] sa6 set to ?0? set to ?1? fsv1[7] sa7 set to ?0? set to ?1? fsv1[15:8] ??? not available
document number: 002-04609 rev. *a page 40 of 106 mb91460c series 9.6.3 security vector fsv2 the setting of the flash security vector f sv2 bits [31:0] is responsible for the i ndividual write protecti on of the 64 kbyte se ctors. it is only evaluated if write protection bit fsv1[17] is set. explanation of the bits in the fl ash security vector fsv2[31:0] note : see section ?9.3. flash access in cpu mode? for an ov erview about the sector organisation of the flash memory. fsv2 bit sector enable write protection disable write protection comment fsv2[0] sa8 set to ?0? set to ?1? sectors available on mb91f467cx only fsv2[1] sa9 set to ?0? set to ?1? fsv2[2] sa10 set to ?0? set to ?1? fsv2[3] sa11 set to ?0? set to ?1? fsv2[4] sa12 set to ?0? set to ?1? sectors available on mb91f467cx and mb91f465ca fsv2[5] sa13 set to ?0? set to ?1? fsv2[6] sa14 set to ?0? set to ?1? fsv2[7] sa15 set to ?0? set to ?1? fsv2[8] sa16 set to ?0? set to ?1? sectors available on mb91f467cx, mb91f465ca, mb91f463ca fsv2[9] sa17 set to ?0? set to ?1? fsv2[10] sa18 set to ?0? set to ?1? fsv2[11] sa19 set to ?0? set to ?1? fsv2[12] sa20 set to ?0? set to ?1? sectors available on mb91f467cx only fsv2[13] sa21 set to ?0? set to ?1? fsv2[14] sa22 set to ?0? set to ?1? fsv2[15] sa23 set to ?0? set to ?1? fsv2[31:16] ? set to ?0? set to ?1? sectors not available
document number: 002-04609 rev. *a page 41 of 106 mb91460c series 10. memory space the fr family has 4 gbytes of logical address space (2 32 addresses) available to the cpu by linear access. direct addressing area the following address space area is used for i/o. this area is called direct addressing area, and the address of an operand can be specified directly in an instruction. the size of directly addressable area depends on the le ngth of the data being accessed as shown below. byte data access : 000 h to 0ff h half word access : 000 h to 1ff h word data access : 000 h to 3ff h
document number: 002-04609 rev. *a page 42 of 106 mb91460c series 11. memory maps 11.1 mb91f467cx, mb91f465ca mb91f467cx mb91f465ca 00000000 h 00000400 h i/o (direct addressing area) i/o 00002000 h 00004000 h flash-cache (8 kbytes) 00001000 h dma 00006000 h 00007000 h flash memory control 00008000 h 0000b000 h boot rom (4 kbytes) 0000c000 h can 0000d000 h 00028000 h d-ram (0 wait, 32 kbytes) 00030000 h id-ram (32 kbytes) 00038000 h 00040000 h flash memory (1088 kbytes) 00150000 h 00180000 h 00500000 h ffffffff h note: access prohibited areas 00000000 h 00000400 h i/o (direct addressing area) i/o 00002000 h 00004000 h flash-cache (8 kbytes) 00001000 h dma 00006000 h 00007000 h flash memory control 00008000 h 0000b000 h boot rom (4 kbytes) 0000c000 h can 0000d000 h 0002c000 h d-ram (0 wait, 16 kbytes) 00030000 h id-ram (16 kbytes) 00034000 h flash memory (512 kbytes) 00150000 h 00500000 h ffffffff h note: access prohibited areas 00148000 h flash memory (32 kbytes) 00100000 h 00080000 h
document number: 002-04609 rev. *a page 43 of 106 mb91460c series 11.2 mb91f463ca mb91f463ca 00000000 h 00000400 h i/o (direct addressing area) i/o 00002000 h 00005000 h flash-cache (4 kbytes) 00001000 h dma 00006000 h 00007000 h flash memory control 00008000 h 0000b000 h boot rom (4 kbytes) 0000c000 h can 0000d000 h 0002c000 h d-ram (0 wait, 16 kbytes) 00030000 h id-ram (8 kbytes) 00032000 h flash memory (256 kbytes) 00150000 h 00180000 h 00500000 h ffffffff h note: access prohibited areas 00148000 h flash memory (32 kbytes) 00100000 h 000c0000 h
document number: 002-04609 rev. *a page 44 of 106 mb91460c series 12. i/o map 12.1 mb91f463ca, mb91f465ca, mb91f467cx note : initial values of register bi ts are represented as follows: ? 1 ? : initial value ? 1 ? ? 0 ? : initial value ? 0 ? ? x ? : initial value ? undefined ? ? - ? : no physical register at this location access is barred with an undefined data access attribute . address register block ? 0 ? 1 ? 2 ? 3 000000 h pdr0 [r/w] xxxxxxxx pdr1 [r/w] xxxxxxxx pdr2 [r/w] xxxxxxxx pdr3 [r/w] xxxxxxxx t-unit port data register read/write attribute register initial value after reset register name (column 1 register at address 4n, column 2 register at address 4n + 1...) leftmost register address (for word access, the register in column 1 becomes the msb side of the data.)
document number: 002-04609 rev. *a page 45 of 106 mb91460c series address register block +0 +1 +2 +3 000000 h reserved reserved pdr02 [r/w] xxxxxxxx reserved r-bus port data register 000004 h reserved reserved reserved reserved 000008 h reserved reserved reserved reserved 00000c h reserved reserved pdr14 [r/w] xxxxxxxx pdr15 [r/w] - - - - xxxx 000010 h pdr16 [r/w] xxxxxxxx pdr17 [r/w] xxxx - - - - pdr18 [r/w] - xxx - xxx pdr19 [r/w] - xxx - xxx 000014 h pdr20 [r/w] - - - - - xxx reserved pdr22 [r/w] - - xx - x - x pdr23 [r/w] - xxxxxxx 000018 h pdr24 [r/w] xxxxxxxx pdr25 [r/w] xxxxxxxx pdr26 [r/w] xxxxxxxx pdr27 [r/w] xxxxxxxx 00001c h pdr28 [r/w] - -xxxxx pdr29 [r/w] xxxxxxxx reserved reserved 000020 h to 00002c h reserved reserved 000030 h eirr0 [r/w] xxxxxxxx enir0 [r/w] 00000000 elvr0 [r/w] 00000000 00000000 external interrupt (int 0 to int 7) 000034 h eirr1 [r/w] xxxxxxxx enir1 [r/w] 00000000 elvr1 [r/w] 00000000 00000000 external interrupt (int 8 to int 14) 000038 h dicr [r/w] - - - - - - - 0 hrcl [r/w] 0 - - 11111 reserved delayed interrupt 00003c h - 00004c h reserved reserved 000050 h scr02 [r/w,w] 00000000 smr02 [r/w,w] 00000000 ssr02 [r/w,r] 00001000 rdr02/tdr02 [r/w] 00000000 lin-usart 2 000054 h escr02 [r/w] 00000x00 eccr02 [r/w,r,w] -00000xx reserved 000058 h to 00005c h reserved reserved 000060 h scr04 [r/w,w] 00000000 smr04 [r/w,w] 00000000 ssr04 [r/w,r] 00001000 rdr04/tdr04 [r/w] 00000000 lin-usart 4 with fifo 000064 h escr04 [r/w] 00000x00 eccr04 [r/w,r,w] -00000xx fsr04 [r] - - - 00000 fcr04 [r/w] 0001 - 000
document number: 002-04609 rev. *a page 46 of 106 mb91460c series address register block +0 +1 +2 +3 000068 h scr05 [r/w,w] 00000000 smr05 [r/w,w] 00000000 ssr05 [r/w,r] 00001000 rdr05/tdr05 [r/w] 00000000 lin-usart 5 with fifo 00006c h escr05 [r/w] 00000x00 eccr05 [r/w,r,w] -00000xx fsr05 [r] - - - 00000 fcr05 [r/w] 0001 - 000 000070 h scr06 [r/w,w] 00000000 smr06 [r/w,w] 00000000 ssr06 [r/w,r] 00001000 rdr06/tdr06 [r/w] 00000000 lin-usart 6 with fifo 000074 h escr06 [r/w] 00000x00 eccr06 [r/w,r,w] -00000xx fsr06 [r] - - - 00000 fcr06 [r/w] 0001 - 000 000078 h scr07 [r/w,w] 00000000 smr07 [r/w,w] 00000000 ssr07 [r/w,r] 00001000 rdr07/tdr07 [r/w] 00000000 lin-usart 7 with fifo 00007c h escr07 [r/w] 00000x00 eccr07 [r/w,r,w] -00000xx fsr07 [r] - - - 00000 fcr07 [r/w] 0001 - 000 000080 h reserved reserved 000084 h bgr102 [r/w] 00000000 bgr002 [r/w] 00000000 reserved reserved baud rate generator lin-usart 0 to 7 000088 h bgr104 [r/w] 00000000 bgr004 [r/w] 00000000 bgr105 [r/w] 00000000 bgr005 [r/w] 00000000 00008c h bgr106 [r/w] 00000000 bgr006 [r/w] 00000000 bgr107 [r/w] 00000000 bgr007 [r/w] 00000000 000090 h pwc20 [r/w] - - - - - - xx xxxxxxxx pwc10 [r/w] - - - - - - xx xxxxxxxx stepper motor 0 000094 h reserved reserved pws20 [r/w] -0000000 pws10 [r/w] - -000000 000098 h pwc21 [r/w] - - - - - - xx xxxxxxxx pwc11 [r/w] - - - - - - xx xxxxxxxx stepper motor 1 00009c h reserved reserved pws21 [r/w] -0000000 pws11 [r/w] - -000000 0000a0 h pwc22 [r/w] - - - - - - xx xxxxxxxx pwc12 [r/w] - - - - - - xx xxxxxxxx stepper motor 2 0000a4 h reserved reserved pws22 [r/w] -0000000 pws12 [r/w] - -000000 0000a8 h pwc23 [r/w] - - - - - - xx xxxxxxxx pwc13 [r/w] - - - - - - xx xxxxxxxx stepper motor 3 0000ac h reserved reserved pws23 [r/w] -0000000 pws13 [r/w] - -000000 0000b0 h pwc24 [r/w] - - - - - - xx xxxxxxxx pwc14 [r/w] - - - - - - xx xxxxxxxx stepper motor 4 0000b4 h reserved reserved pws24 [r/w] -0000000 pws14 [r/w] - -000000
document number: 002-04609 rev. *a page 47 of 106 mb91460c series address register block +0 +1 +2 +3 0000b8 h pwc25 [r/w] - - - - - - xx xxxxxxxx pwc15 [r/w] - - - - - - xx xxxxxxxx stepper motor 5 0000bc h reserved reserved pws25 [r/w] -0000000 pws15 [r/w] - -000000 0000c0 h reserved pwc0 [r/w] -00000-- reserved pwc1 [r/w] -00000-- stepper motor control 0 to 5 0000c4 h reserved pwc2 [r/w] -00000-- reserved pwc3 [r/w] -00000-- 0000c8 h reserved pwc4 [r/w] -00000-- reserved pwc5 [r/w] -00000-- 0000cc h reserved reserved 0000d0h ibcr0 [r/w] 00000000 ibsr0 [r] 00000000 itbah0 [r/w] - - - - - - 00 itbal0 [r/w] 00000000 i 2 c 0 0000d4h itmkh0 [r/w] 00 - - - - 11 itmkl0 [r/w] 11111111 ismk0 [r/w] 01111111 isba0 [r/w] - 0000000 0000d8h reserved idar0 [r/w] 00000000 iccr0 [r/w] - 0011111 reserved 0000dc h to 000100 h reserved reserved 000104 h gcn11 [r/w] 00110010 00010000 reserved gcn21 [r/w] - - - - 0000 ppg control 4 to 7 000108 h gcn12 [r/w] 00110010 00010000 reserved gcn22 [r/w] - - - - 0000 ppg control 8 to 11 000110 h to 00012c h reserved reserved 000130 h ptmr04 [r] 11111111 11111111 pcsr04 [w] xxxxxxxx xxxxxxxx ppg 4 000134 h pdut04 [w] xxxxxxxx xxxxxxxx pcnh04 [r/w] 0000000 - pcnl04 [r/w] 000000 - 0 000138 h ptmr05 [r] 11111111 11111111 pcsr05 [w] xxxxxxxx xxxxxxxx ppg 5 00013c h pdut05 [w] xxxxxxxx xxxxxxxx pcnh05 [r/w] 0000000 - pcnl05 [r/w] 000000 - 0 000140 h ptmr06 [r] 11111111 11111111 pcsr06 [w] xxxxxxxx xxxxxxxx ppg 6 000144 h pdut06 [w] xxxxxxxx xxxxxxxx pcnh06 [r/w] 0000000 - pcnl06 [r/w] 000000 - 0 000148 h ptmr07 [r] 11111111 11111111 pcsr07 [w] xxxxxxxx xxxxxxxx ppg 7 00014c h pdut07 [w] xxxxxxxx xxxxxxxx pcnh07 [r/w] 0000000 - pcnl07 [r/w] 000000 - 0
document number: 002-04609 rev. *a page 48 of 106 mb91460c series address register block +0 +1 +2 +3 000150 h ptmr08 [r] 11111111 11111111 pcsr08 [w] xxxxxxxx xxxxxxxx ppg 8 000154 h pdut08 [w] xxxxxxxx xxxxxxxx pcnh08 [r/w] 0000000 - pcnl08 [r/w] 000000 - 0 000158 h ptmr09 [r] 11111111 11111111 pcsr09 [w] xxxxxxxx xxxxxxxx ppg 9 00015c h pdut09 [w] xxxxxxxx xxxxxxxx pcnh09 [r/w] 0000000 - pcnl09 [r/w] 000000 - 0 000160 h ptmr10 [r] 11111111 11111111 pcsr10 [w] xxxxxxxx xxxxxxxx ppg 10 000164 h pdut10 [w] xxxxxxxx xxxxxxxx pcnh10 [r/w] 0000000 - pcnl10 [r/w] 000000 - 0 000168 h ptmr11 [r] 11111111 11111111 pcsr11 [w] xxxxxxxx xxxxxxxx ppg 11 00016c h pdut11 [w] xxxxxxxx xxxxxxxx pcnh11 [r/w] 0000000 - pcnl11 [r/w] 000000 - 0 000170 h p0tmcsrh [r/w] - 0 - 000 - 0 p0tmcsrl [r/w] - - - 00000 p1tmcsrh [r/w] - 0000000 p1tmcsrl [r/w] 01000000 pulse frequency modulator 000174 h p0tmrlr [w] xxxxxxxx xxxxxxxx p0tmr [r] xxxxxxxx xxxxxxxx 000178 h p1tmrlr [w] xxxxxxxx xxxxxxxx p1tmr [r] xxxxxxxx xxxxxxxx 00017c h reserved reserved 000180 h reserved ics01 [r/w] 00000000 reserved ics23 [r/w] 00000000 input capture 0 to 3 000184 h ipcp0 [r] xxxxxxxx xxxxxxxx ipcp1 [r] xxxxxxxx xxxxxxxx 000188 h ipcp2 [r] xxxxxxxx xxxxxxxx ipcp3 [r] xxxxxxxx xxxxxxxx 00018c h ocs01 [r/w] - - - 0 - - 00 0000 - - 00 ocs23 [r/w] - - - 0 - - 00 0000 - - 00 output compare 0 to 3 000190 h occp0 [r/w] xxxxxxxx xxxxxxxx occp1 [r/w] xxxxxxxx xxxxxxxx 000194 h occp2 [r/w] xxxxxxxx xxxxxxxx occp3 [r/w] xxxxxxxx xxxxxxxx 000198 h sgcrh [r/w] 0000 - - 00 sgcrl [r/w] - - 0 - - 000 sgfr [r/w, r] xxxxxxxx xxxxxxxx sound generator 00019c h sgar [r/w] 00000000 reserved sgtr [r/w] xxxxxxxx sgdr [r/w] xxxxxxxx
document number: 002-04609 rev. *a page 49 of 106 mb91460c series address register block +0 +1 +2 +3 0001a0 h aderh [r/w] 00000000 00000000 aderl [r/w] 00000000 00000000 a/d converter 0001a4 adcs1 [r/w] 00000000 adcs0 [r/w] 00000000 adcr1 [r] 000000xx adcr0 [r] xxxxxxxx 0001a8 h adct1 [r/w] 00010000 adct0 [r/w] 00101100 adsch [r/w] - - - 00000 adech [r/w] - - - 00000 0001ac h reserved acsr0 [r/w] - 11xxx00 reserved reserved alarm comparator 0 0001b0 h tmrlr0 [w] xxxxxxxx xxxxxxx tmr0 [r] xxxxxxxx xxxxxxxx reload timer 0 0001b4 h reserved tmcsrh0 [r/w] - - - 00000 tmcsrl0 [r/w] 0 - 000000 0001b8 h tmrlr1 [w] xxxxxxxx xxxxxxxx tmr1 [r] xxxxxxxx xxxxxxxx reload timer 1 0001bc h reserved tmcsrh1 [r/w] - - - 00000 tmcsrl1 [r/w] 0 - 000000 0001c0 h tmrlr2 [w] xxxxxxxx xxxxxxxx tmr2 [r] xxxxxxxx xxxxxxxx reload timer 2 (ppg 4, ppg 5) 0001c4 h reserved tmcsrh2 [r/w] - - - 00000 tmcsrl2 [r/w] 0 - 000000 0001c8 h tmrlr3 [w] xxxxxxxx xxxxxxxx tmr3 [r] xxxxxxxx xxxxxxxx reload timer 3 (ppg 6, ppg 7) 0001cc h reserved tmcsrh3 [r/w] - - - 00000 tmcsrl3 [r/w] 0 - 000000 0001d0 h tmrlr4 [w] xxxxxxxx xxxxxxxx tmr4 [r] xxxxxxxx xxxxxxxx reload timer 4 (ppg 8, ppg 9) 0001d4 h reserved tmcsrh4 [r/w] - - - 00000 tmcsrl4 [r/w] 0 - 000000 0001d8 h tmrlr5 [w] xxxxxxxx xxxxxxxx tmr5 [r] xxxxxxxx xxxxxxxx reload timer 5 (ppg 10, ppg 11) 0001dc h reserved tmcsrh5 [r/w] - - - 00000 tmcsrl5 [r/w] 0 - 000000 0001e0 h tmrlr6 [w] xxxxxxxx xxxxxxxx tmr6 [r] xxxxxxxx xxxxxxxx reload timer 6 (ppg 12, ppg 13) 0001e4 h reserved tmcsrh6 [r/w] - - - 00000 tmcsrl6 [r/w] 0 - 000000
document number: 002-04609 rev. *a page 50 of 106 mb91460c series address register block +0 +1 +2 +3 0001e8 h tmrlr7 [w] xxxxxxxx xxxxxxxx tmr7 [r] xxxxxxxx xxxxxxxx reload timer 7 (ppg 14, ppg 15) (a/d converter) 0001ec h reserved tmcsrh7 [r/w] - - - 00000 tmcsrl7 [r/w] 0 - 000000 0001f0 h tcdt0 [r/w] xxxxxxxx xxxxxxxx reserved tccs0 [r/w] 00000000 free running timer 0 (icu 0, icu 1) 0001f4 h tcdt1 [r/w] xxxxxxxx xxxxxxxx reserved tccs1 [r/w] 00000000 free running timer 1 (icu 2, icu 3) 0001f8 h tcdt2 [r/w] xxxxxxxx xxxxxxxx reserved tccs2 [r/w] 00000000 free running timer 2 (ocu 0, ocu 1) 0001fc h tcdt3 [r/w] xxxxxxxx xxxxxxxx reserved tccs3 [r/w] 00000000 free running timer 3 (ocu 2, ocu 3) 000200 h dmaca0 [r/w] 00000000 0000xxxx xxxxxxxx xxxxxxxx dmac 000204 h dmacb0 [r/w] 00000000 00000000 xxxxxxxx xxxxxxxx 000208 h dmaca1 [r/w] 00000000 0000xxxx xxxxxxxx xxxxxxxx 00020c h dmacb1 [r/w] 00000000 00000000 xxxxxxxx xxxxxxxx 000210 h dmaca2 [r/w] 00000000 0000xxxx xxxxxxxx xxxxxxxx 000214 h dmacb2 [r/w] 00000000 00000000 xxxxxxxx xxxxxxxx 000218 h dmaca3 [r/w] 00000000 0000xxxx xxxxxxxx xxxxxxxx 00021c h dmacb3 [r/w] 00000000 00000000 xxxxxxxx xxxxxxxx 000220 h dmaca4 [r/w] 00000000 0000xxxx xxxxxxxx xxxxxxxx 000224 h dmacb4 [r/w] 00000000 00000000 xxxxxxxx xxxxxxxx 000228 h to 00023c h reserved reserved 000240 h dmacr [r/w] 0 - -0 0000 reserved
document number: 002-04609 rev. *a page 51 of 106 mb91460c series address register block +0 +1 +2 +3 000244 h to 0002cc h reserved reserved 0002d0 h reserved ics045 [r/w] 00000000 reserved ics67 [r/w] 00000000 input capture 4 to 7 0002d4 h ipcp4 [r] xxxxxxxx xxxxxxxx ipcp5 [r] xxxxxxxx xxxxxxxx 0002d8 h ipcp6 [r] xxxxxxxx xxxxxxxx ipcp7 [r] xxxxxxxx xxxxxxxx 0002dc h to 0002ec h reserved reserved 0002f0 h tcdt4 [r/w] xxxxxxxx xxxxxxxx reserved tccs4 [r/w] 00000000 free running timer 4 (icu 4, icu 5) 0002f4 h tcdt5 [r/w] xxxxxxxx xxxxxxxx reserved tccs5 [r/w] 00000000 free running timer 5 (icu 6, icu 7) 0002f8 h tcdt6 [r/w] xxxxxxxx xxxxxxxx reserved tccs6 [r/w] 00000000 free running timer 6 0002fc h tcdt7 [r/w] xxxxxxxx xxxxxxxx reserved tccs7 [r/w] 00000000 free running timer 7 000300 h udrc1 [w] 00000000 udrc0 [w] 00000000 udcr1 [r] 00000000 udcr0 [r] 00000000 up/down counter 0 000304 h udcch0 [r/w] 00000000 udccl0 [r/w] 00000000 reserved udcs0 [r/w] 00000000 000308 h to 00030c h reserved reserved 000310 h udrc3 [w] 00000000 udrc2 [w] 00000000 udcr3 [r] 00000000 udcr2 [r] 00000000 up/down counter 2 to 3 000314 h udcch2 [r/w] 00000000 udccl2 [r/w] 00000000 reserved udcs2 [r/w] 00000000 000318 h udcch3 [r/w] 00000000 udccl3 [r/w] 00000000 reserved udcs3 [r/w] 00000000 00031c h reserved reserved 000320 h gcn13 [r/w] 00110010 00010000 reserved gcn23 [r/w] - - - - 0000 ppg control 12 to 15 000324 h to 00032c h reserved reserved 000330 h ptmr12 [r] 11111111 11111111 pcsr12 [w] xxxxxxxx xxxxxxxx ppg 12 000334 h pdut12 [w] xxxxxxxx xxxxxxxx pcnh12 [r/w] 0000000 - pcnl12 [r/w] 000000 - 0
document number: 002-04609 rev. *a page 52 of 106 mb91460c series address register block +0 +1 +2 +3 000338 h ptmr13 [r] 11111111 11111111 pcsr13 [w] xxxxxxxx xxxxxxxx ppg 13 00033c h pdut13 [w] xxxxxxxx xxxxxxxx pcnh13 [r/w] 0000000 - pcnl13 [r/w] 000000 - 0 000340 h ptmr14 [r] 11111111 11111111 pcsr14 [w] xxxxxxxx xxxxxxxx ppg 14 000344 h pdut14 [w] xxxxxxxx xxxxxxxx pcnh14 [r/w] 0000000 - pcnl14 [r/w] 000000 - 0 000348 h ptmr15 [r] 11111111 11111111 pcsr15 [w] xxxxxxxx xxxxxxxx ppg 15 00034c h pdut15 [w] xxxxxxxx xxxxxxxx pcnh15 [r/w] 0000000 - pcnl15 [r/w] 000000 - 0 000350 h to 000364 h reserved reserved 000368 h ibcr2 [r/w] 00000000 ibsr2 [r] 00000000 itbah2 [r/w] - - - - - - 00 itbal2 [r/w] 00000000 i 2 c 2 00036c h itmkh2 [r/w] 00 - - - - 11 itmkl2 [r/w] 11111111 ismk2 [r/w] 01111111 isba2 [r/w] - 0000000 000370 h reserved idar2 [r/w] 00000000 iccr2 [r/w] - 0011111 reserved 00374h ibcr3 [r/w] 00000000 ibsr3 [r] 00000000 itbah3 [r/w] - - - - - - 00 itbal3 [r/w] 00000000 i 2 c 3 000378 h itmkh3 [r/w] 00 - - - - 11 itmkl3 [r/w] 11111111 ismk3 [r/w] 01111111 isba3 [r/w] - 0000000 00037c h reserved idar3 [r/w] 00000000 iccr3 [r/w] - 0011111 reserved 000380 h to 00038c h reserved reserved 000390 h roms [r] 11111111 00000000 reserved rom select register 000394 h to 0003ec h reserved reserved 0003f0 h bsd0 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx bit search module 0003f4 h bsd1 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003f8 h bsdc [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003fc h bsrr [r] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000400 h to 00043c h reserved reserved
document number: 002-04609 rev. *a page 53 of 106 mb91460c series address register block +0 +1 +2 +3 000440 h icr00 [r/w] ---11111 icr01 [r/w] ---11111 icr02 [r/w] ---11111 icr03 [r/w] ---11111 interrupt controller 000444 h icr04 [r/w] ---11111 icr05 [r/w] ---11111 icr06 [r/w] ---11111 icr07 [r/w] ---11111 000448 h icr08 [r/w] ---11111 icr09 [r/w] ---11111 icr10 [r/w] ---11111 icr11 [r/w] ---11111 00044c h icr12 [r/w] ---11111 icr13 [r/w] ---11111 icr14 [r/w] ---11111 icr15 [r/w] ---11111 000450 h icr16 [r/w] ---11111 icr17 [r/w] ---11111 icr18 [r/w] ---11111 icr19 [r/w] ---11111 000454 h icr20 [r/w] ---11111 icr21 [r/w] ---11111 icr22 [r/w] ---11111 icr23 [r/w] ---11111 000458 h icr24 [r/w] ---11111 icr25 [r/w] ---11111 icr26 [r/w] ---11111 icr27 [r/w] ---11111 00045c h icr28 [r/w] ---11111 icr29 [r/w] ---11111 icr30 [r/w] ---11111 icr31 [r/w] ---11111 000460 h icr32 [r/w] ---11111 icr33 [r/w] ---11111 icr34 [r/w] ---11111 icr35 [r/w] ---11111 000464 h icr36 [r/w] ---11111 icr37 [r/w] ---11111 icr38 [r/w] ---11111 icr39 [r/w] ---11111 000468 h icr40 [r/w] ---11111 icr41 [r/w] ---11111 icr42 [r/w] ---11111 icr43 [r/w] ---11111 00046c h icr44 [r/w] ---11111 icr45 [r/w] ---11111 icr46 [r/w] ---11111 icr47 [r/w] ---11111 000470 h icr48 [r/w] ---11111 icr49 [r/w] ---11111 icr50 [r/w] ---11111 icr51 [r/w] ---11111 000474 h icr52 [r/w] ---11111 icr53 [r/w] ---11111 icr54 [r/w] ---11111 icr55 [r/w] ---11111 000478 h icr56 [r/w] ---11111 icr57 [r/w] ---11111 icr58 [r/w] ---11111 icr59 [r/w] ---11111 00047c h icr60 [r/w] ---11111 icr61 [r/w] ---11111 icr62 [r/w] ---11111 icr63 [r/w] ---11111 000480 h rsrr [r/w] 10000000 stcr [r/w] 00110011 tbcr [r/w] 00xxx ? 00 ctbr [w] xxxxxxxx clock controller 000484 h clkr [r/w] ---- 0000 wpr [w] xxxxxxxx divr0 [r/w] 00000011 divr1 [r/w] 00000000 000488 h ctest [r/w] xxxx00xx reserved reserved reserved c-unit test (hidden) 00048c h plldivm [r/w] - - - - 0000 plldivn [r/w] - - 000000 plldivg [r/w] - - - - 0000 pllmulg [w] 00000000 pll interface 000490 h pllctrl [r/w] - - - - 0000 reserved reserved reserved
document number: 002-04609 rev. *a page 54 of 106 mb91460c series address register block +0 +1 +2 +3 000494 h oscc1 [r/w] - - - - - 010 oscs1 [r/w] 00001111 oscc2 [r/w] - - - - - 010 oscs2 [r/w] 00001111 main/sub oscillator control 000498 h porten [r/w] - - - - - - 00 reserved reserved reserved port input enable control 00049c h reserved reserved 0004a0 h reserved wtcer [r/w] - - - - - - 00 wtcr [r/w] 00000000 000 ? 00 ? 0 real time clock (watch timer) 0004a4 h reserved wtbr [r/w] - - - xxxxx xxxxxxxx xxxxxxxx 0004a8 h wthr [r/w] - - - 00000 wtmr [r/w] - - 000000 wtsr [r/w] - - 000000 reserved 0004ac h csvtr [r/w] - - - 00010 csvcr [r/w] 00011100 cscfg [r/w] 0x000000 cmcfg [r/w] 00000000 clock- supervisor / selector / monitor 0004b0 h cucr [r/w] - - - - - - - - - - - 0 - - 00 cutd [r/w] 10000000 00000000 calibration of sub clock 0004b4 h cutr1 [r] - - - - - - - - 00000000 cutr2 [r] 00000000 00000000 0004b8 h cmpr [r/w] - - 000010 11111101 reserved cmcr [r/w] - 001 - - 00 clock modulator 0004bc h cmt1 [r/w] 00000000 1 - - - 0000 cmt2 [r/w] - - 000000 - - 000000 0004c0 h canpre [r/w] 0 - - - 0000 canckd [r/w] - - - - - 000 *1 reserved reserved can clock control 0004c4 h lvsel [r/w] 00000111 lvdet [r/w] 0000 0 ? 00 hwwde [r/w] - - - - - - 00 hwwd [r/w,w] 00011000 low voltage detection/ hardware watchdog 0004c8 h oscrh [r/w] 000 - - 001 oscrl [r/w] - - - - - 000 wpcrh [r/w] 00 - - - 000 wpcrl [r/w] - - - - - - 00 main-/sub-oscillation stabilisation timer 0004cc h osccr [r/w] - - - - - - 00 reserved regsel [r/w] - - 000110 regctr [r/w] - - - 0 - - 00 main- oscillation standby control main/subregulator control 0004d0 h to 0007f8 h reserved reserved 0007fc h reserved modr [w] xxxxxxxx reserved reserved mode register 000800 h to 000bfc h reserved reserved 000c00 h tvctw [w] xxxxxxxx tvctr [r] - - xxxxxx reserved ios [r/w] 00000000 i-unit test (hidden) 000c04 h to 000cfc h reserved reserved
document number: 002-04609 rev. *a page 55 of 106 mb91460c series address register block +0 +1 +2 +3 000d00 h reserved reserved pdrd02 [r] xxxxxxxx reserved r-bus port data direct read register 000d04 h reserved reserved reserved reserved 000d08 h reserved reserved reserved reserved 000d0c h reserved reserved pdrd14 [r] xxxxxxxx pdrd15 [r] - - - - xxxx 000d10 h pdrd16 [r] xxxxxxxx pdrd17 [r] xxxx - - - - pdrd18 [r] - xxx - xxx pdrd19 [r] - xxx - xxx 000d14 h pdrd20 [r] - - - - - xxx reserved pdrd22 [r] - - xx - x - x pdrd23 [r] - xxxxxxx 000d18 h pdrd24 [r] xxxxxxxx pdrd25 [r] xxxxxxxx pdrd26 [r] xxxxxxxx pdrd27 [r] xxxxxxxx 000d1c h pdrd28 [r] - - xxxxx pdrd29 [r] xxxxxxxx reserved reserved 000d20 h to 000d3c h reserved reserved 000d40 h reserved reserved ddr02 [r/w] 00000000 reserved r-bus port direction register 000d44 h reserved reserved reserved reserved 000d48 h reserved reserved reserved reserved 000d4c h reserved reserved ddr14 [r/w] 00000000 ddr15 [r/w] - - - - 0000 000d50 h ddr16 [r/w] 00000000 ddr17 [r/w] 0000 - - - - ddr18 [r/w] - 000 - 000 ddr19 [r/w] - 000 - 000 000d54 h ddr20 [r/w] - - - - - 000 reserved ddr22 [r/w] - - 00 - 0 - 0 ddr23 [r/w] - 0000000 000d58 h ddr24 [r/w] 00000000 ddr25 [r/w] 00000000 ddr26 [r/w] 00000000 ddr27 [r/w] 00000000 000d5c h ddr28 [r/w] - - 00000 ddr29 [r/w] 00000000 reserved reserved 000d60 h to 000d7c h reserved reserved
document number: 002-04609 rev. *a page 56 of 106 mb91460c series address register block +0 +1 +2 +3 000d80 h reserved reserved reserved reserved r-bus port function register 000d84 h reserved reserved reserved reserved 000d88 h reserved reserved reserved reserved 000d8c h reserved reserved pfr14 [r/w] 00000000 pfr15 [r/w] - - - - 0000 000d90 h pfr16 [r/w] 00000000 pfr17 [r/w] 0000 - - - - pfr18 [r/w] - 000 - 000 pfr19 [r/w] - 000 - 000 000d94 h pfr20 [r/w] - - - - - 000 reserved pfr22 [r/w] - - 00 - 0 - 0 pfr23 [r/w] - 000000 000d98 h pfr24 [r/w] 00000000 pfr25 [r/w] 00000000 pfr26 [r/w] 00000000 pfr27 [r/w] 00000000 000d9c h pfr28 [r/w] - - 00000 pfr29 [r/w] 00000000 reserved reserved 000da0 h to 000dbc h reserved reserved 000dc0 h reserved reserved reserved reserved r-bus extra port function register 000dc4 h reserved reserved reserved reserved 000dc8 h reserved reserved reserved reserved 000dcc h reserved reserved epfr14 [r/w] 00000000 epfr15 [r/w] - - - - 0000 000dd0 h epfr16 [r/w] 0000 - - - - reserved epfr18 [r/w] - 000 - 000 epfr19 [r/w] - 0 - - - 0 - - 000dd4 h epfr20 [r/w] - - - - - 000 reserved reserved reserved 000dd8 h reserved reserved epfr26 [r/w] 00000000 epfr27 [r/w] 00000000 000ddc h reserved reserved reserved reserved 000de0 h to 000dfc h reserved reserved
document number: 002-04609 rev. *a page 57 of 106 mb91460c series address register block +0 +1 +2 +3 000e00 h reserved reserved podr02 [r/w] 00000000 reserved r-bus port output drive select register 000e04 h reserved reserved reserved reserved 000e08 h reserved reserved reserved reserved 000e0c h reserved reserved podr14 [r/w] 00000000 podr15 [r/w] - - - - 0000 000e10 h podr16 [r/w] 00000000 podr17 [r/w] 0000 - - - - podr18 [r/w] - 000 - 000 podr19 [r/w] - 000 - 000 000e14 h podr20 [r/w] - - - - - 000 reserved podr22 [r/w] - - 00 - 0 - 0 podr23 [r/w] - 0000000 000e18 h podr24 [r/w] 00000000 podr25 [r/w] 00000000 podr26 [r/w] 00000000 podr27 [r/w] 00000000 000e1c h podr28 [r/w] - - 00000 podr29 [r/w] 00000000 reserved reserved 000e20 h to 000e3c h reserved reserved 000e40 h reserved reserved pilr02 [r/w] 00000000 reserved r-bus port input level select register 000e44 h reserved reserved reserved reserved 000e48 h reserved reserved reserved reserved 000e4c h reserved reserved pilr14 [r/w] 00000000 pilr15 [r/w] - - - - 0000 000e50 h pilr16 [r/w] 00000000 pilr17 [r/w] 0000 - - - - pilr18 [r/w] - 000 - 000 pilr19 [r/w] - 000 - 000 000e54 h pilr20 [r/w] - - - - - 000 reserved pilr22 [r/w] - - 00 - 0 - 0 pilr23 [r/w] - 0000000 000e58 h pilr24 [r/w] 00000000 pilr25 [r/w] 00000000 pilr26 [r/w] 00000000 pilr27 [r/w] 00000000 000e5c h pilr28 [r/w] - - 000000 pilr29 [r/w] 00000000 reserved reserved 000e60 h to 000e7c h reserved reserved
document number: 002-04609 rev. *a page 58 of 106 mb91460c series address register block +0 +1 +2 +3 000e80 h reserved reserved epilr02 [r/w] 00000000 reserved r-bus extra port input level select register 000e84 h reserved reserved reserved reserved 000e88 h reserved reserved reserved reserved 000e8c h reserved reserved epilr14 [r/w] 00000000 epilr15 [r/w] - - - - 0000 000e90 h epilr16 [r/w] 00000000 epilr17 [r/w] 0000 - - - - epilr18 [r/w] - 000 - 000 epilr19 [r/w] - 000 - 000 000e94 h epilr20 [r/w] - - - - - 000 reserved epilr22 [r/w] - - 00 - 0 - 0 epilr23 [r/w] - 0000000 000e98 h epilr24 [r/w] 00000000 epilr25 [r/w] 00000000 epilr26 [r/w] 00000000 epilr27 [r/w] 00000000 000e9c h epilr28 [r/w] - - 00000 epilr29 [r/w] 00000000 reserved reserved 000ea0 h to 000ebc h reserved reserved 000ec0 h reserved reserved pper02 [r/w] 00000000 reserved r-bus port pull-up/down enable register 000ec4 h reserved reserved reserved reserved 000ec8 h reserved reserved reserved reserved 000ecc h reserved reserved pper14 [r/w] 00000000 pper15 [r/w] - - - - 0000 000ed0 h pper16 [r/w] 00000000 pper17 [r/w] 0000 - - - - pper18 [r/w] - 000 - 000 pper19 [r/w] - 000 - 000 000ed4 h pper20 [r/w] - - - - - 000 reserved pper22 [r/w] - - 00 - 0 - 0 pper23 [r/w] - 0000000 000ed8 h pper24 [r/w] 00000000 pper25 [r/w] 00000000 pper26 [r/w] 00000000 pper27 [r/w] 00000000 000edc h pper28 [r/w] - - 00000 pper29 [r/w] 00000000 reserved reserved 000ee0 h to 000efc h reserved reserved
document number: 002-04609 rev. *a page 59 of 106 mb91460c series address register block +0 +1 +2 +3 000f00 h reserved reserved ppcr02 [r/w] 11111111 reserved r-bus port pull-up/down control register 000f04 h reserved reserved reserved reserved 000f08 h reserved reserved reserved reserved 000f0c h reserved reserved ppcr14 [r/w] 11111111 ppcr15 [r/w] - - - - 1111 000f10 h ppcr16 [r/w] 11111111 ppcr17 [r/w] 1111 - - - - ppcr18 [r/w] - 111 - 111 ppcr19 [r/w] - 111 - 111 000f14 h ppcr20 [r/w] - - - - - 111 reserved ppcr22 [r/w] - - 11 - 1 - 1 ppcr23 [r/w] -1111111 000f18 h ppcr24 [r/w] 11111111 ppcr25 [r/w] 11111111 ppcr26 [r/w] 11111111 ppcr27 [r/w] 11111111 000f1c h ppcr28 [r/w] - - 11111 ppcr29 [r/w] 11111111 reserved reserved 000f20 h to 000f3c h reserved reserved 001000 h dmasa0 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx dmac 001004 h dmada0 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001008 h dmasa1 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00100c h dmada1 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001010 h dmasa2 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001014 h dmada2 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001018 h dmasa3 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00101c h dmada3 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001020 h dmasa4 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001024 h dmada4 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001028 h to 001ffc h reserved reserved 002000 h to 006ffc h mb91f467cx flash-cache size is 8 kbytes : 004000 h to 005ffc h mb91f465ca flash-cache size is 8 kbytes : 004000 h to 005ffc h mb91f463ca flash-cache size is 4 kbytes : 005000 h to 005ffc h flash-cache / i-ram area
document number: 002-04609 rev. *a page 60 of 106 mb91460c series address register block +0 +1 +2 +3 007000 h fmcs [r/w] 01101000 fmcr [r] - - - 00000 fchcr [r/w] - - - - - - 00 10000011 flash memory/ flash-cache/ i-ram control register 007004 h fmwt [r/w] 11111111 11111111 fmwt2 [r] - 001 - - - - fmps [r/w] - - - - - 000 007008 h fmac [r] 00000000 00000000 00000000 00000000 00700c h fcha0 [r/w] - - - - - - - - - - - 00000 00000000 00000000 flash-cache non- cacheable area setting reg- ister 007010 h fcha1 [r/w] - - - - - - - - - - - 00000 00000000 00000000 007014 h to 007ffch reserved reserved 008000h to 00bffc h mb91f467cx boot-rom size is 4 kbytes : 00b000 h to 00bffc h mb91f465ca boot-rom size is 4 kbytes : 00b000 h to 00bffc h mb91f463ca boot-rom size is 4 kbytes : 00b000 h to 00bffc h (instruction access is 1 wait cycl e, data access is 1 wait cycle) boot rom area 00c000 h ctrlr0 [r/w] 00000000 00000001 statr0 [r/w] 00000000 00000000 can 0 control register 00c004 h errcnt0 [r] 00000000 00000000 btr0 [r/w] 00100011 00000001 00c008 h intr0 [r] 00000000 00000000 testr0 [r/w] 00000000 x0000000 00c00c h brpe0 [r/w] 00000000 00000000 reserved 00c010 h if1creq0 [r/w] 00000000 00000001 if1cmsk0 [r/w] 00000000 00000000 can 0 if 1 register 00c014 h if1msk20 [r/w] 11111111 11111111 if1msk10 [r/w] 11111111 11111111 00c018 h if1arb20 [r/w] 00000000 00000000 if1arb10 [r/w] 00000000 00000000 00c01c h if1mctr0 [r/w] 00000000 00000000 reserved 00c020 h if1dta10 [r/w] 00000000 00000000 if1dta20 [r/w] 00000000 00000000 00c024 h if1dtb10 [r/w] 00000000 00000000 if1dtb20 [r/w] 00000000 00000000 00c028 h to 00c02c h reserved 00c030 h if1dta20 [r/w] 00000000 00000000 if1dta10 [r/w] 00000000 00000000 00c034 h if1dtb20 [r/w] 00000000 00000000 if1dtb10 [r/w] 00000000 00000000
document number: 002-04609 rev. *a page 61 of 106 mb91460c series address register block +0 +1 +2 +3 00c038 h to 00c03c h reserved 00c040 h if2creq0 [r/w] 00000000 00000001 if2cmsk0 [r/w] 00000000 00000000 can 0 if 2 register 00c044 h if2msk20 [r/w] 11111111 11111111 if2msk10 [r/w] 11111111 11111111 00c048 h if2arb20 [r/w] 00000000 00000000 if2arb10 [r/w] 00000000 00000000 00c04c h if2mctr0 [r/w] 00000000 00000000 reserved 00c050 h if2dta10 [r/w] 00000000 00000000 if2dta20 [r/w] 00000000 00000000 00c054 h if2dtb10 [r/w] 00000000 00000000 if2dtb20 [r/w] 00000000 00000000 00c058 h to 00c05c h reserved 00c060 h if2dta20 [r/w] 00000000 00000000 if2dta10 [r/w] 00000000 00000000 00c064 h if2dtb20 [r/w] 00000000 00000000 if2dtb10 [r/w] 00000000 00000000 00c068 h to 00c07c h reserved 00c080 h treqr20 [r] 00000000 00000000 treqr10 [r] 00000000 00000000 can 0 status flags 00c084 h to 00c08c h reserved 00c090 h newdt20 [r] 00000000 00000000 newdt10 [r] 00000000 00000000 00c094 h to 00c09c h reserved 00c0a0 h intpnd20 [r] 00000000 00000000 intpnd10 [r] 00000000 00000000 00c0a4 h to 00c0ac h reserved 00c0b0 h msgval20 [r] 00000000 00000000 msgval10 [r] 00000000 00000000 00c0b4 h to 00c0fc h reserved reserved
document number: 002-04609 rev. *a page 62 of 106 mb91460c series address register block +0 +1 +2 +3 00c100 h ctrlr1 [r/w] 00000000 00000001 statr1 [r/w] 00000000 00000000 can 1 control register 00c104 h errcnt1 [r] 00000000 00000000 btr1 [r/w] 00100011 00000001 00c108 h intr1 [r] 00000000 00000000 testr1 [r/w] 00000000 x0000000 00c10c h brpe1 [r/w] 00000000 00000000 reserved 00c110 h if1creq1 [r/w] 00000000 00000001 if1cmsk1 [r/w] 00000000 00000000 can 1 if 1 register 00c114 h if1msk21 [r/w] 11111111 11111111 if1msk11 [r/w] 11111111 11111111 00c118 h if1arb21 [r/w] 00000000 00000000 if1arb11 [r/w] 00000000 00000000 00c11c h if1mctr1 [r/w] 00000000 00000000 reserved 00c120 h if1dta11 [r/w] 00000000 00000000 if1dta21 [r/w] 00000000 00000000 00c124 h if1dtb11 [r/w] 00000000 00000000 if1dtb21 [r/w] 00000000 00000000 00c128 h to 00c12c h reserved 00c130 h if1dta21 [r/w] 00000000 00000000 if1dta11 [r/w] 00000000 00000000 00c134 h if1dtb21 [r/w] 00000000 00000000 if1dtb11 [r/w] 00000000 00000000 00c138 h to 00c13c h reserved reserved
document number: 002-04609 rev. *a page 63 of 106 mb91460c series address register block +0 +1 +2 +3 00c140 h if2creq1 [r/w] 00000000 00000001 if2cmsk1 [r/w] 00000000 00000000 can 1 if 2 register 00c144 h if2msk21 [r/w] 11111111 11111111 if2msk11 [r/w] 11111111 11111111 00c148 h if2arb21 [r/w] 00000000 00000000 if2arb11 [r/w] 00000000 00000000 00c14c h if2mctr1 [r/w] 00000000 00000000 reserved 00c150 h if2dta11 [r/w] 00000000 00000000 if2dta21 [r/w] 00000000 00000000 00c154 h if2dtb11 [r/w] 00000000 00000000 if2dtb21 [r/w] 00000000 00000000 00c158 h to 00c15c h reserved 00c160 h if2dta21 [r/w] 00000000 00000000 if2dta11 [r/w] 00000000 00000000 00c164 h if2dtb21 [r/w] 00000000 00000000 if2dtb11 [r/w] 00000000 00000000 00c168 h to 00c17c h reserved 00c180 h treqr21 [r] 00000000 00000000 treqr11 [r] 00000000 00000000 can 1 status flags 00c184 h to 00c18c h reserved 00c190 h newdt21 [r] 00000000 00000000 newdt11 [r] 00000000 00000000 00c194 h to 00c19c h reserved 00c1a0 h intpnd21 [r] 00000000 00000000 intpnd11 [r] 00000000 00000000 00c1a4 h to 00c1ac h reserved reserved 00c1b0 h msgval21 [r] 00000000 00000000 msgval11 [r] 00000000 00000000 can 1 status flags 00c1b4 h to 00c1fc h reserved reserved 00c200 h ctrlr2 [r/w] 00000000 00000001 statr2 [r/w] 00000000 00000000 can 2 control register 00c204 h errcnt2 [r] 00000000 00000000 btr2 [r/w] 00100011 00000001 00c208 h intr2 [r] 00000000 00000000 testr2 [r/w] 00000000 x0000000 00c20c h brpe2 [r/w] 00000000 00000000 reserved
document number: 002-04609 rev. *a page 64 of 106 mb91460c series address register block +0 +1 +2 +3 00c210 h if1creq2 [r/w] 00000000 00000001 if1cmsk2 [r/w] 00000000 00000000 can 2 if 1 register 00c214 h if1msk22 [r/w] 11111111 11111111 if1msk12 [r/w] 11111111 11111111 00c218 h if1arb22 [r/w] 00000000 00000000 if1arb12 [r/w] 00000000 00000000 00c21c h if1mctr2 [r/w] 00000000 00000000 reserved 00c220 h if1dta12 [r/w] 00000000 00000000 if1dta22 [r/w] 00000000 00000000 00c224 h if1dtb12 [r/w] 00000000 00000000 if1dtb22 [r/w] 00000000 00000000 00c228 h to 00c22c h reserved 00c230 h if1dta22 [r/w] 00000000 00000000 if1dta12 [r/w] 00000000 00000000 00c234 h if1dtb22 [r/w] 00000000 00000000 if1dtb12 [r/w] 00000000 00000000 00c238 h to 00c23c h reserved reserved 00c240 h if2creq2 [r/w] 00000000 00000001 if2cmsk2 [r/w] 00000000 00000000 can 2 if 2 register 00c244 h if2msk22 [r/w] 11111111 11111111 if2msk12 [r/w] 11111111 11111111 00c248 h if2arb22 [r/w] 00000000 00000000 if2arb12 [r/w] 00000000 00000000 00c24c h if2mctr2 [r/w] 00000000 00000000 reserved 00c250 h if2dta12 [r/w] 00000000 00000000 if2dta22 [r/w] 00000000 00000000 00c254 h if2dtb12 [r/w] 00000000 00000000 if2dtb22 [r/w] 00000000 00000000 00c258 h to 00c25c h reserved 00c260 h if2dta22 [r/w] 00000000 00000000 if2dta12 [r/w] 00000000 00000000 00c264 h if2dtb22 [r/w] 00000000 00000000 if2dtb12 [r/w] 00000000 00000000 00c268 h to 00c27c h reserved reserved
document number: 002-04609 rev. *a page 65 of 106 mb91460c series address register block +0 +1 +2 +3 00c280 h treqr22 [r] 00000000 00000000 treqr12 [r] 00000000 00000000 can 2 status flags 00c284 h to 00c28c h reserved 00c290 h newdt22 [r] 00000000 00000000 newdt12 [r] 00000000 00000000 00c294 h to 00c29c h reserved 00c2a0 h intpnd22 [r] 00000000 00000000 intpnd12 [r] 00000000 00000000 00c2a4 h to 00c2ac h reserved 00c2b0 h msgval22 [r] 00000000 00000000 msgval12 [r] 00000000 00000000 can 2 status flags 00c2b4 h to 00effc h reserved reserved 00f000 h bctrl [r/w] - - - - - - - - - - - - - - - - 11111100 00000000 edsu / mpu 00f004 h bstat [r/w] - - - - - - - - - - - - - 000 00000000 10 - - 0000 00f008 h biac [r] - - - - - - - - - - - - - - - - 00000000 00000000 00f00c h boac [r] - - - - - - - - - - - - - - - - 00000000 00000000 00f010 h birq [r/w] - - - - - - - - - - - - - - - - 00000000 00000000 00f014 h to 00f01c h reserved 00f020 h bcr0 [r/w] - - - - - - - - 00000000 00000000 00000000 00f024 h bcr1 [r/w] - - - - - - - - 00000000 00000000 00000000 00f028 h bcr2 [r/w] - - - - - - - - 00000000 00000000 00000000 00f02c h bcr3 [r/w] - - - - - - - - 00000000 00000000 00000000 00f030 h to 00f07c h reserved reserved
document number: 002-04609 rev. *a page 66 of 106 mb91460c series *1 : depends on the number of available can channels address register block +0 +1 +2 +3 00f080 h bad0 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx edsu / mpu 00f084 h bad1 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00f088 h bad2 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00f08c h bad3 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00f090 h bad4 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00f094 h bad5 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00f098 h bad6 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00f09c h bad7 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx edsu / mpu 00f0a0 h bad8 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00f0a4 h bad9 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00f0a8 h bad10 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00f0ac h bad11 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00f0b0 h bad12 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00f0b4 h bad13 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00f0b8 h bad14 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00f0bc h bad15 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00f0c0 h to 01fffc h reserved reserved 020000 h to 02fffc h mb91f467cx d-ram size is 32 kbytes : 028000 h to 02fffc h mb91f465ca d-ram size is 16 kbytes : 02c000 h to 02fffc h mb91f463ca d-ram size is 16 kbytes : 02c000 h to 02fffc h (data access is 0 wait cycles) d-ram area 030000 h to 03fffc h mb91f467cx id-ram size is 32 kbytes : 030000 h to 037ffc h mb91f465ca id-ram size is 16 kbytes : 030000 h to 033ffc h mb91f463ca id-ram size is 8 kbytes : 030000 h to 031ffc h (instruction access is 0 wait cycl es, data access is 1 wait cycle) id-ram area
document number: 002-04609 rev. *a page 67 of 106 mb91460c series 12.2 flash memory and external bus area 32bit read/write dat[31:0] dat[31:0] 16bit read/write dat[31:16] dat[15:0] dat[31:16] dat[15:0] address register block ? 0 ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 ? 7 040000 h to 05fff8 h sa8 (64kb, mb91f467cx); reserved (mb91f465ca, mb91f463ca) sa9 (64kb, mb91f467cx); reserved (mb91f465ca, mb91f463ca) roms0 060000 h to 07fff8 h sa10 (64kb, mb91f467cx); reserved (mb91f465ca, mb91f463ca) sa11 (64kb, mb91f467cx); reserved (mb91f465ca, mb91f463ca) roms1 080000 h to 09fff8 h sa12 (64kb, mb91f467cx, mb91f465ca); reserved (mb91f463ca) sa13 (64kb, mb91f467cx, mb91f465ca); reserved (mb91f463ca) roms2 0a0000 h to 0bfff8 h sa14 (64kb, mb91f467cx, mb91f465ca); reserved (mb91f463ca) sa15 (64kb, mb91f467cx, mb91f465ca); reserved (mb91f463ca) roms3 0c0000 h to 0dfff8 h sa16 (64kb) sa17 (64kb) roms4 0e0000 h to 0ffff0 h sa18 (64kb) fmv [r] 06 00 00 00h sa19 (64kb) frv [r] 00 00 bf f8h roms5 0ffff8 h 100000 h to 11fff8 h sa20 (64kb, mb91f467cx); reserved (mb91f465ca, mb91f463ca) sa21 (64kb, mb91f467cx); reserved (mb91f465ca, mb91f463ca) roms6 120000 h to 13fff8 h sa22 (64kb, mb91f467cx); reserved (mb91f465ca, mb91f463ca) sa23 (64kb, mb91f467cx); reserved (mb91f465ca, mb91f463ca) 140000 h to 143ff8 h sa0 (8kb, mb91f467cx); reserved (mb91f465ca, mb91f463ca) sa1 (8kb, mb91f467cx); reserved (mb91f465ca, mb91f463ca) roms7 144000 h to 17ff8 h sa2 (8kb, mb91f467cx); reserved (mb91f465ca, mb91f463ca) sa3 (8kb, mb91f467cx); reserved (mb91f465ca, mb91f463ca) 148000 h to 14bff8 h sa4 (8kb) sa5 (8kb) 14c000 h to 14fff8 h sa6 (8kb) sa7 (8kb) 150000 h to 17fff8 h reserved
document number: 002-04609 rev. *a page 68 of 106 mb91460c series notes: write operations to address 0ffff8 h and 0ffffc h are not possible. when reading these addresses, the values shown above will be read. on mb91f465ca and mb91f463ca, write access to the flash is only possible in 16-bit mode. 32bit read/write dat[31:0] dat[31:0] 16bit read/write dat[31:16] dat[15:0] dat[31:16] dat[15:0] address register block ? 0 ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 ? 7 180000 h to 1bfff8 h reserved roms8 1c0000 h to 1ffff8 h roms9 200000 h to 27fff8 h roms10 280000 h to 2ffff8 h roms11 300000 h to 37fff8 h roms12 380000 h to 3ffff8 h roms13 400000 h to 47fff8 h roms14 480000 h to 4ffff8 h roms15
document number: 002-04609 rev. *a page 69 of 106 mb91460c series 13. interrupt vector table interrupt interrupt number interrupt level *1 interrupt vector *2 dma resource number decimal hexa- decimal setting register register address offset default vector address reset 0 00 - - 0x3fc 0x000ffffc mode vector 1 01 - - 0x3f8 0x000ffff8 system reserved 2 02 - - 0x3f4 0x000ffff4 system reserved 3 03 - - 0x3f0 0x000ffff0 system reserved 4 04 - - 0x3ec 0x000fffec cpu supervisor mode (int #5 instruction) *6 5 05 - - 0x3e8 0x000fffe8 memory protection exception *6 6 06 - - 0x3e4 0x000fffe4 co-processor fault trap *5 7 07 - - 0x3e0 0x000fffe0 co-processor error trap *5 8 08 - - 0x3dc 0x000fffdc inte instruction *5 9 09 - - 0x3d8 0x000fffd8 instruction break exception *5 10 0a - - 0x3d4 0x000fffd4 operand break trap *5 11 0b - - 0x3d0 0x000fffd0 step trace trap *5 12 0c - - 0x3cc 0x000fffcc nmi interrupt (tool) *5 13 0d - - 0x3c8 0x000fffc8 undefined instruction exception 14 0e - - 0x3c4 0x000fffc4 nmi request 15 0f f h fixed 0x3c0 0x000fffc0 external interrupt 0 16 10 icr00 0x440 0x3bc 0x000fffbc 0, 16 external interrupt 1 17 11 0x3b8 0x000fffb8 1, 17 external interrupt 2 18 12 icr01 0x441 0x3b4 0x000fffb4 2, 18 external interrupt 3 19 13 0x3b0 0x000fffb0 3, 19 external interrupt 4 20 14 icr02 0x442 0x3ac 0x000fffac 20 external interrupt 5 21 15 0x3a8 0x000fffa8 21 external interrupt 6 22 16 icr03 0x443 0x3a4 0x000fffa4 22 external interrupt 7 23 17 0x3a0 0x000fffa0 23 external interrupt 8 24 18 icr04 0x444 0x39c 0x000fff9c external interrupt 9 25 19 0x398 0x000fff98 external interrupt 10 26 1a icr05 0x445 0x394 0x000fff94 external interrupt 11 27 1b 0x390 0x000fff90 external interrupt 12 28 1c icr06 0x446 0x38c 0x000fff8c external interrupt 13 29 1d 0x388 0x000fff88
document number: 002-04609 rev. *a page 70 of 106 mb91460c series external interrupt 14 30 1e icr07 0x447 0x384 0x000fff84 reserved 31 1f 0x380 0x000fff80 reload timer 0 32 20 icr08 0x448 0x37c 0x000fff7c 4, 32 reload timer 1 33 21 0x378 0x000fff78 5, 33 reload timer 2 34 22 icr09 0x449 0x374 0x000fff74 34 reload timer 3 35 23 0x370 0x000fff70 35 reload timer 4 36 24 icr10 0x44a 0x36c 0x000fff6c 36 reload timer 5 37 25 0x368 0x000fff68 37 reload timer 6 38 26 icr11 0x44b 0x364 0x000fff64 38 reload timer 7 39 27 0x360 0x000fff60 39 free run timer 0 40 28 icr12 0x44c 0x35c 0x000fff5c 40 free run timer 1 41 29 0x358 0x000fff58 41 free run timer 2 42 2a icr13 0x44d 0x354 0x000fff54 42 free run timer 3 43 2b 0x350 0x000fff50 43 free run timer 4 44 2c icr14 0x44e 0x34c 0x000fff4c 44 free run timer 5 45 2d 0x348 0x000fff48 45 free run timer 6 46 2e icr15 0x44f 0x344 0x000fff44 46 free run timer 7 47 2f 0x340 0x000fff40 47 can 0 48 30 icr16 0x450 0x33c 0x000fff3c can 1 49 31 0x338 0x000fff38 can 2 50 32 icr17 0x451 0x334 0x000fff34 reserved 51 33 0x330 0x000fff30 reserved 52 34 icr18 0x452 0x32c 0x000fff2c reserved 53 35 0x328 0x000fff28 reserved 54 36 icr19 0x453 0x324 0x000fff24 6, 48 reserved 55 37 0x320 0x000fff20 7, 49 reserved 56 38 icr20 0x454 0x31c 0x000fff1c 8, 50 reserved 57 39 0x318 0x000fff18 9, 51 usart (lin) 2 rx 58 3a icr21 0x455 0x314 0x000fff14 52 usart (lin) 2 tx 59 3b 0x310 0x000fff10 53 reserved 60 3c icr22 0x456 0x30c 0x000fff0c 54 reserved 61 3d 0x308 0x000fff08 55 system reserved 62 3e icr23 *4 0x457 0x304 0x000fff04 delayed interrupt 63 3f 0x300 0x000fff00 system reserved *3 64 40 (icr24) (0x458) 0x2fc 0x000ffefc system reserved *3 65 41 0x2f8 0x000ffef8 interrupt interrupt number interrupt level *1 interrupt vector *2 dma resource number decimal hexa- decimal setting register register address offset default vector address
document number: 002-04609 rev. *a page 71 of 106 mb91460c series usart (lin, fifo) 4 rx 66 42 icr25 0x459 0x2f4 0x000ffef4 10, 56 usart (lin, fifo) 4 tx 67 43 0x2f0 0x000ffef0 11, 57 usart (lin, fifo) 5 rx 68 44 icr26 0x45a 0x2ec 0x000ffeec 12, 58 usart (lin, fifo) 5 tx 69 45 0x2e8 0x000ffee8 13, 59 usart (lin, fifo) 6 rx 70 46 icr27 0x45b 0x2e4 0x000ffee4 60 usart (lin, fifo) 6 tx 71 47 0x2e0 0x000ffee0 61 usart (lin, fifo) 7 rx 72 48 icr28 0x45c 0x2dc 0x000ffedc 62 usart (lin, fifo) 7 tx 73 49 0x2d8 0x000ffed8 63 i 2 c 0 / i 2 c 2 74 4a icr29 0x45d 0x2d4 0x000ffed4 i 2 c 3 75 4b 0x2d0 0x000ffed0 reserved 76 4c icr30 0x45e 0x2cc 0x000ffecc 64 reserved 77 4d 0x2c8 0x000ffec8 65 reserved 78 4e icr31 0x45f 0x2c4 0x000ffec4 66 reserved 79 4f 0x2c0 0x000ffec0 67 reserved 80 50 icr32 0x460 0x2bc 0x000ffebc 68 reserved 81 51 0x2b8 0x000ffeb8 69 reserved 82 52 icr33 0x461 0x2b4 0x000ffeb4 70 reserved 83 53 0x2b0 0x000ffeb0 71 reserved 84 54 icr34 0x462 0x2ac 0x000ffeac 72 reserved 85 55 0x2a8 0x000ffea8 73 reserved 86 56 icr35 0x463 0x2a4 0x000ffea4 74 reserved 87 57 0x2a0 0x000ffea0 75 reserved 88 58 icr36 0x464 0x29c 0x000ffe9c 76 reserved 89 59 0x298 0x000ffe98 77 reserved 90 5a icr37 0x465 0x294 0x000ffe94 78 reserved 91 5b 0x290 0x000ffe90 79 input capture 0 92 5c icr38 0x466 0x28c 0x000ffe8c 80 input capture 1 93 5d 0x288 0x000ffe88 81 input capture 2 94 5e icr39 0x467 0x284 0x000ffe84 82 input capture 3 95 5f 0x280 0x000ffe80 83 input capture 4 96 60 icr40 0x468 0x27c 0x000ffe7c 84 input capture 5 97 61 0x278 0x000ffe78 85 input capture 6 98 62 icr41 0x469 0x274 0x000ffe74 86 input capture 7 99 63 0x270 0x000ffe70 87 output compare 0 100 64 icr42 0x46a 0x26c 0x000ffe6c 88 output compare 1 101 65 0x268 0x000ffe68 89 interrupt interrupt number interrupt level *1 interrupt vector *2 dma resource number decimal hexa- decimal setting register register address offset default vector address
document number: 002-04609 rev. *a page 72 of 106 mb91460c series output compare 2 102 66 icr43 0x46b 0x264 0x000ffe64 90 output compare 3 103 67 0x260 0x000ffe60 91 reserved 104 68 icr44 0x46c 0x25c 0x000ffe5c 92 reserved 105 69 0x258 0x000ffe58 93 reserved 106 6a icr45 0x46d 0x254 0x000ffe54 94 reserved 107 6b 0x250 0x000ffe50 95 sound generator 108 6c icr46 0x46e 0x24c 0x000ffe4c phase frequ. modulator 109 6d 0x248 0x000ffe48 system reserved 110 6e icr47 *4 0x46f 0x244 0x000ffe44 system reserved 111 6f 0x240 0x000ffe40 reserved 112 70 icr48 0x470 0x23c 0x000ffe3c 15, 96 reserved 113 71 0x238 0x000ffe38 97 reserved 114 72 icr49 0x471 0x234 0x000ffe34 98 reserved 115 73 0x230 0x000ffe30 99 prog. pulse gen. 4 116 74 icr50 0x472 0x22c 0x000ffe2c 100 prog. pulse gen. 5 117 75 0x228 0x000ffe28 101 prog. pulse gen. 6 118 76 icr51 0x473 0x224 0x000ffe24 102 prog. pulse gen. 7 119 77 0x220 0x000ffe20 103 prog. pulse gen. 8 120 78 icr52 0x474 0x21c 0x000ffe1c 104 prog. pulse gen. 9 121 79 0x218 0x000ffe18 105 prog. pulse gen. 10 122 7a icr53 0x475 0x214 0x000ffe14 106 prog. pulse gen. 11 123 7b 0x210 0x000ffe10 107 prog. pulse gen. 12 124 7c icr54 0x476 0x20c 0x000ffe0c 108 prog. pulse gen. 13 125 7d 0x208 0x000ffe08 109 prog. pulse gen. 14 126 7e icr55 0x477 0x204 0x000ffe04 110 prog. pulse gen. 15 127 7f 0x200 0x000ffe00 111 up/down counter 0 128 80 icr56 0x478 0x1fc 0x000ffdfc reserved 129 81 0x1f8 0x000ffdf8 up/down counter 2 130 82 icr57 0x479 0x1f4 0x000ffdf4 up/down counter 3 131 83 0x1f0 0x000ffdf0 real time clock 132 84 icr58 0x47a 0x1ec 0x000ffdec calibration unit 133 85 0x1e8 0x000ffde8 a/d converter 0 134 86 icr59 0x47b 0x1e4 0x000ffde4 14, 112 reserved 135 87 0x1e0 0x000ffde0 alarm comparator 0 136 88 icr60 0x47c 0x1dc 0x000ffddc reserved 137 89 0x1d8 0x000ffdd8 interrupt interrupt number interrupt level *1 interrupt vector *2 dma resource number decimal hexa- decimal setting register register address offset default vector address
document number: 002-04609 rev. *a page 73 of 106 mb91460c series notes: *1 : the interrupt control registers (icrs) are located in the inte rrupt controller and set the in terrupt level fo r each interrupt request. an icr is provided for each interrupt request. *2 :the vector address for each eit (exception, interrupt or trap) is calculated by adding the listed offset to the table base reg ister value (tbr). the tbr specifies the top of the eit vector table. the addresses listed in the table are for the default tbr value (0x000ffc00). the tbr is initialized to this value by a reset. af ter execution of the internal bo ot rom tbr is set to 0x000ffc0 0. *3 : used by realos *4 : icr23 and icr47 can be exchanged by setting the realos compatibility bi t (addr 0x0c03 : ios[0]) *5 : system reserved *6 : memory protection unit (mpu) support low voltage detection 138 8a icr61 0x47d 0x1d4 0x000ffdd4 reserved 139 8b 0x1d0 0x000ffdd0 timebase overflow 140 8c icr62 0x47e 0x1cc 0x000ffdcc pll clock gear 141 8d 0x1c8 0x000ffdc8 dma controller 142 8e icr63 0x47f 0x1c4 0x000ffdc4 main/sub osc stability wait 143 8f 0x1c0 0x000ffdc0 security vector 144 90 - - 0x1bc 0x000ffdbc used by the int instruction. 145 to 255 91 to ff -- 0x1b8 to 0x000 0x000ffdb8 to 0x000ffc00 interrupt interrupt number interrupt level *1 interrupt vector *2 dma resource number decimal hexa- decimal setting register register address offset default vector address
document number: 002-04609 rev. *a page 74 of 106 mb91460c series 14. recommended settings 14.1 pll and clockgear settings please note that for mb91f460c series the core base clock frequenci es are valid in the 1.8v operation mode of the main regulato r and flash. recommended pll divider and clockgear settings pll input (clk) [mhz] frequency parameter clockgear parameter pll output (x) [mhz] core base clock [mhz] remarks divm divn divg mulg mulg 4 2 25 16 24 200 100 4 2 24 16 24 192 96 4 2 23 16 24 184 92 4 2 22 16 24 176 88 4 2 21 16 20 168 84 4 2 20 16 20 160 80 4 2 19 16 20 152 76 4 2 18 16 20 144 72 4 2 17 16 16 136 68 4 2 16 16 16 128 64 4 2 15 16 16 120 60 4 2 14 16 16 112 56 4 2 13 16 12 104 52 4 2 12 16 12 96 48 4 2 11 16 12 88 44 4 4 10 16 24 160 40 449162414436 448162412832 447162411228 466162414424 485162816020 4 10 4 16 32 160 16 4 12 3 16 32 144 12
document number: 002-04609 rev. *a page 75 of 106 mb91460c series 14.2 clock modulator settings the following table shows all possible settings for the clock modulat or in a base clock frequency range from 32mhz up to 88mhz. the flash access time settings need to be adjusted according to fm ax while the pll and clockgear settings should be set accordi ng to base clock frequency. clock modulator settings, frequency range and supported supply voltage modulation degree (k) random no (n) cmpr [hex] baseclk [mhz] fmin [mhz] fmax [mhz] 1 3 026f 88 79.5 98.5 1 3 026f 84 76.1 93.8 1 3 026f 80 72.6 89.1 1 5 02ae 80 68.7 95.8 2 3 046e 80 68.7 95.8 1 3 026f 76 69.1 84.5 1 5 02ae 76 65.3 90.8 1 7 02ed 76 62 98.1 2 3 046e 76 65.3 90.8 3 3 066d 76 62 98.1 1 3 026f 72 65.5 79.9 1 5 02ae 72 62 85.8 1 7 02ed 72 58.8 92.7 2 3 046e 72 62 85.8 3 3 066d 72 58.8 92.7 1 3 026f 68 62 75.3 1 5 02ae 68 58.7 80.9 1 7 02ed 68 55.7 87.3 1 9032c685395 2 3 046e 68 58.7 80.9 2 504ac685395 3 3 066d 68 55.7 87.3 4 3086c685395 1 3 026f 64 58.5 70.7 1 5 02ae 64 55.3 75.9 1 7 02ed 64 52.5 82 1 9 032c 64 49.9 89.1 1 11 036b 64 47.6 97.6 2 3 046e 64 55.3 75.9 2 5 04ac 64 49.9 89.1 3 3 066d 64 52.5 82 4 3 086c 64 49.9 89.1 5 3 0a6b 64 47.6 97.6
document number: 002-04609 rev. *a page 76 of 106 mb91460c series 1 3 026f 60 54.9 66.1 1 5 02ae 60 51.9 71 1 7 02ed 60 49.3 76.7 1 9 032c 60 46.9 83.3 1 11 036b 60 44.7 91.3 2 3 046e 60 51.9 71 2 5 04ac 60 46.9 83.3 3 3 066d 60 49.3 76.7 4 3 086c 60 46.9 83.3 5 3 0a6b 60 44.7 91.3 1 3 026f 56 51.4 61.6 1 5 02ae 56 48.6 66.1 1 7 02ed 56 46.1 71.4 1 9 032c 56 43.8 77.6 1 11 036b 56 41.8 84.9 1 13 03aa 56 39.9 93.8 2 3 046e 56 48.6 66.1 2 5 04ac 56 43.8 77.6 2 7 04ea 56 39.9 93.8 3 3 066d 56 46.1 71.4 3 5 06aa 56 39.9 93.8 4 3 086c 56 43.8 77.6 5 3 0a6b 56 41.8 84.9 6 3 0c6a 56 39.9 93.8 1 3 026f 52 47.8 57 1 5 02ae 52 45.2 61.2 1 7 02ed 52 42.9 66.1 1 9 032c 52 40.8 71.8 1 11 036b 52 38.8 78.6 1 13 03aa 52 37.1 86.8 1 15 03e9 52 35.5 96.9 2 3 046e 52 45.2 61.2 2 5 04ac 52 40.8 71.8 2 7 04ea 52 37.1 86.8 3 3 066d 52 42.9 66.1 3 5 06aa 52 37.1 86.8 4 3 086c 52 40.8 71.8 modulation degree (k) random no (n) cmpr [hex] baseclk [mhz] fmin [mhz] fmax [mhz]
document number: 002-04609 rev. *a page 77 of 106 mb91460c series 5 3 0a6b 52 38.8 78.6 6 3 0c6a 52 37.1 86.8 7 3 0e69 52 35.5 96.9 1 3 026f 48 44.2 52.5 1 5 02ae 48 41.8 56.4 1 7 02ed 48 39.6 60.9 1 9 032c 48 37.7 66.1 1 11 036b 48 35.9 72.3 1 13 03aa 48 34.3 79.9 1 15 03e9 48 32.8 89.1 2 3 046e 48 41.8 56.4 2 5 04ac 48 37.7 66.1 2 7 04ea 48 34.3 79.9 3 3 066d 48 39.6 60.9 3 5 06aa 48 34.3 79.9 4 3 086c 48 37.7 66.1 5 3 0a6b 48 35.9 72.3 6 3 0c6a 48 34.3 79.9 7 3 0e69 48 32.8 89.1 1 3 026f 44 40.6 48.1 1 5 02ae 44 38.4 51.6 1 7 02ed 44 36.4 55.7 1 9 032c 44 34.6 60.4 1 11 036b 44 33 66.1 1 13 03aa 44 31.5 73 1 15 03e9 44 30.1 81.4 2 3 046e 44 38.4 51.6 2 5 04ac 44 34.6 60.4 2 7 04ea 44 31.5 73 2 9 0528 44 28.9 92.1 3 3 066d 44 36.4 55.7 3 5 06aa 44 31.5 73 4 3 086c 44 34.6 60.4 4 5 08a8 44 28.9 92.1 5 3 0a6b 44 33 66.1 6 3 0c6a 44 31.5 73 7 3 0e69 44 30.1 81.4 modulation degree (k) random no (n) cmpr [hex] baseclk [mhz] fmin [mhz] fmax [mhz]
document number: 002-04609 rev. *a page 78 of 106 mb91460c series 8 3 1068 44 28.9 92.1 1 3 026f 40 37 43.6 1 5 02ae 40 34.9 46.8 1 7 02ed 40 33.1 50.5 1 9 032c 40 31.5 54.8 1 11 036b 40 30 59.9 1 13 03aa 40 28.7 66.1 1 15 03e9 40 27.4 73.7 2 3 046e 40 34.9 46.8 2 5 04ac 40 31.5 54.8 2 7 04ea 40 28.7 66.1 2 9 0528 40 26.3 83.3 3 3 066d 40 33.1 50.5 3 5 06aa 40 28.7 66.1 3 7 06e7 40 25.3 95.8 4 3 086c 40 31.5 54.8 4 5 08a8 40 26.3 83.3 5 3 0a6b 40 30 59.9 6 3 0c6a 40 28.7 66.1 7 3 0e69 40 27.4 73.7 8 3 1068 40 26.3 83.3 9 3 1267 40 25.3 95.8 1 3 026f 36 33.3 39.2 1 5 02ae 36 31.5 42 1 7 02ed 36 29.9 45.3 1 9 032c 36 28.4 49.2 1 11 036b 36 27.1 53.8 1 13 03aa 36 25.8 59.3 1 15 03e9 36 24.7 66.1 2 3 046e 36 31.5 42 2 5 04ac 36 28.4 49.2 2 7 04ea 36 25.8 59.3 2 9 0528 36 23.7 74.7 3 3 066d 36 29.9 45.3 3 5 06aa 36 25.8 59.3 3 7 06e7 36 22.8 85.8 4 3 086c 36 28.4 49.2 modulation degree (k) random no (n) cmpr [hex] baseclk [mhz] fmin [mhz] fmax [mhz]
document number: 002-04609 rev. *a page 79 of 106 mb91460c series 4 5 08a8 36 23.7 74.7 5 3 0a6b 36 27.1 53.8 6 3 0c6a 36 25.8 59.3 7 3 0e69 36 24.7 66.1 8 3 1068 36 23.7 74.7 9 3 1267 36 22.8 85.8 1 3 026f 32 29.7 34.7 1 5 02ae 32 28 37.3 1 7 02ed 32 26.6 40.2 1 9 032c 32 25.3 43.6 1 11 036b 32 24.1 47.7 1 13 03aa 32 23 52.5 1 15 03e9 32 22 58.6 2 3 046e 32 28 37.3 2 5 04ac 32 25.3 43.6 2 7 04ea 32 23 52.5 2 9 0528 32 21.1 66.1 2 11 0566 32 19.5 89.1 3 3 066d 32 26.6 40.2 3 5 06aa 32 23 52.5 3 7 06e7 32 20.3 75.9 4 3 086c 32 25.3 43.6 4 5 08a8 32 21.1 66.1 5 3 0a6b 32 24.1 47.7 5 5 0aa6 32 19.5 89.1 6 3 0c6a 32 23 52.5 7 3 0e69 32 22 58.6 8 3 1068 32 21.1 66.1 9 3 1267 32 20.3 75.9 10 3 1466 32 19.5 89.1 modulation degree (k) random no (n) cmpr [hex] baseclk [mhz] fmin [mhz] fmax [mhz]
document number: 002-04609 rev. *a page 80 of 106 mb91460c series 15. electrical characteristics 15.1 absolute maximum ratings parameter symbol rating unit remarks min max power supply slew rate ?? 50 v/ms power supply voltage 1* 1 v dd 5r ? 0.3 ? 6.0 v power supply voltage 2* 1 v dd 5 ? 0.3 ? 6.0 v power supply voltage 3* 1 hv dd 5 ? 0.3 ? 6.0 v relationship of the supply voltages hv dd 5 v dd 5-0.3 v dd 5+0.3 v smc mode v ss 5-0.3 v dd 5+0.3 v general purpose port mode av cc 5 v dd 5-0.3 v dd 5+0.3 v at least one pin of the ports 25 to 29 (smc, ann) is used as digital input or output. v ss 5-0.3 v dd 5+0.3 v all pins of the ports 25 to 29 (smc, ann) follow the condition of v ia analog power supply voltage* 1 av cc 5 ? 0.3 ? 6.0 v *2 analog reference power supply voltage* 1 avrh ? 0.3 ? 6.0 v *2 input voltage 1* 1 v i1 vss5 ? 0.3 v dd 5 ? 0.3 v input voltage 3* 1 v i3 hvss5 ? 0.3 hv dd 5 ? 0.3 v stepper motor controller analog pin input voltage* 1 v ia avss5 ? 0.3 avcc5 ? 0.3 v output voltage 1* 1 v o1 vss5 ? 0.3 v dd 5 ? 0.3 v output voltage 3* 1 v o3 hvss5 ? 0.3 hv dd 5 ? 0.3 v stepper motor controller maximum clamp current i clamp ? 4.0 ? 4.0 ma *3 total maximum clamp current ? ?? i clamp ?? 20 ma *3 ?l? level maximum output current* 4 i ol ? 10 ma ? 40 ma stepper motor controller ?l? level average output current* 5 i olav ? 8ma ? 30 ma stepper motor controller ?l? level total maximum output current ? i ol ? 100 ma ? 360 ma stepper motor controller ?l? level total average output current* 6 ? i olav ? 50 ma ? 230 ma stepper motor controller ?h? level maximum output current* 4 i oh ? ? 10 ma ? ? 40 ma stepper motor controller ?h? level average output current* 5 i ohav ? ? 4ma ? ? 30 ma stepper motor controller ?h? level total maximum output current ? i oh ? ? 100 ma ? ? 360 ma stepper motor controller
document number: 002-04609 rev. *a page 81 of 106 mb91460c series *1 : the parameter is based on v ss 5 ? hv ss 5 ? av ss 5 ? 0.0 v. *2 : av cc 5 and avrh5 must not exceed v dd 5 ? 0.3 v. * 3 : ? use within recommended operating conditions. ? use with dc voltage (current). ? ? b signals are input signals that exceed the v dd 5 voltage. ? b signals should always be applied by connecting a limiting resistor between the ? b signal and the microcontroller. ? the value of the limiting resistor should be set so that the current input to the microcontroller pin does not exceed the rated value at any time , either instantaneously or for an extended period , when the ? b signal is input. ? note that when the microcontroller drive current is lo w, such as in the low power consumption modes, the ? b input potential can increase the potential at the power supply pin via a protective diode, possibly affecting other devices. ? note that if the ? b signal is input when the microcontroll er is off (not fixed at 0 v), power is supplied through the +b input pin; therefore, the microcontro ller may partially operate. ? note that if the ? b signal is input at power-on , since the power is supplied through the pi n, the power-on reset may not function in the power supply voltage. ? do not leave ? b input pins open. ? example of recommended circuit : *4 : maximum output current is defined as the value of the pe ak current flowing through any one of the corresponding pins. *5 : average output current is defined as the value of the average current flowing through any one of the corresponding pins fo r a 100 ms period. *6 : total average output current is defined as the value of the average current flowing through all of the corresponding pins for a 100 ms period. warning:semiconductor devices can be permanen tly damaged by application of stress (vol tage, current, temperature, etc.) in exce ss of absolute maximum ratings. do not exceed these ratings. ?h? level total average output current* 6 ? i ohav ? ? 25 ma ? ? 230 ma stepper motor controller power consumption p d ? 1000 mw operating temperature t a ? 40 ? 105 ? c storage temperature tstg ? 55 ? 150 ? c parameter symbol rating unit remarks min max p-ch n-ch v cc r input/output equivalent circuit ? b input (0 v to 16 v) limiting resistor protective diode
document number: 002-04609 rev. *a page 82 of 106 mb91460c series 15.2 recommended operating conditions ( v ss 5 ? av ss 5 ? 0.0 v ) warning: the recommended operating conditions ar e required in order to ensure the normal operation of the semiconductor device. all of the device?s electrical characteristics are warra nted when the device is oper ated within these ranges. always use semiconductor devices with in their recommended operating conditi on ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditio ns, or combinations not represented on the data sheet. users considering application outside the list ed conditions are advised to contact their cypress representatives beforehand. parameter symbol value unit remarks min typ max power supply voltage v dd 53.0 ? 5.5 v v dd 5r 3.0 ? 5.5 v internal regulator hv dd 5 4.5 ? 5.5 v stepper motor controller 3.0 ? 5.5 v stepper motor controller (when all pins are used as general-purpose ports) av cc 53.0 ? 5.5 v a/d converter smoothing capacitor at vcc18c pin c s ? 4.7 ? f use a x7r ceramic capacitor or a capacitor that has similar frequency characteristics. power supply slew rate ?? 50 v/ms operating temperature t a ? 40 ? ? 105 c stepper motor control slew rate 40 ns cload = 0 pf main oscillation stabilisation time 10 ms lock-up time pll (4 mhz ->16 ...100mhz) 0.6 ms esd protection (human body model) v surge 2kv r discharge = 1.5k ? c discharge = 100pf rc oscillator f rc100khz f rc2mhz 50 1 100 2 200 4 khz mhz vdd core 1.65v c s avss5 vss5 vcc18c
document number: 002-04609 rev. *a page 83 of 106 mb91460c series 15.3 dc characteristics note: in the following tables, ?v dd ? means hv dd 5 for smc pins or v dd 5 for other pins. in the following tables, ?v ss ? means hvss5 for ground pins of the stepper motor and v ss 5 for the other pins. ( v dd 5 ? av cc 5 ? 3.0 v to 5.5 v , v ss 5 ? av ss 5 ? 0 v , t a ? ? 40 c to ? 105 c ) parameter symbol pin name condition value unit remarks min typ max input ?h? voltage v ih ? port inputs if cmos hysteresis 0.8/0.2 input is selected 0.8 ?? v dd ? v dd ? 0.3 v cmos hysteresis input ? port inputs if cmos hysteresis 0.7/0.3 input is selected 0.7 ?? v dd ? v dd ? 0.3 v 4.5 v ? v dd ? 5.5 v 0.74 ?? v dd ? v dd ? 0.3 v 3 v ? v dd ? 4.5 v ? automotive hysteresis input is selected 0.8 ?? v dd ? v dd ? 0.3 v ? port inputs if ttl input is selected 2.0 ? v dd ? 0.3 v v ihr initx ? 0.8 ?? v dd ? v dd ? 0.3 v initx input pin (cmos hysteresis) v ihm md_3 to md_0 ? v dd ? 0.3 ? v dd ? 0.3 v mode input pins v ihx0s x0, x0a ? 2.5 ? v dd ? 0.3 v external clock in ?oscillation mode? v ihx0f x0 ? 0.8 ?? v dd ? v dd ? 0.3 v external clock in ?fast clock input mode? input ?l? voltage v il ? port inputs if cmos hysteresis 0.8/0.2 in- put is selected v ss ? 0.3 ? 0.2 ?? v dd v ? port inputs if cmos hysteresis 0.7/0.3 input is selected v ss ? 0.3 ? 0.3 ?? v dd v ? port inputs if automotive hysteresis input is selected v ss ? 0.3 ? 0.5 ?? v dd v 4.5 v ? v dd ? 5.5 v v ss ? 0.3 ? 0.46 ?? v dd v3 v ? v dd ? 4.5 v ? port inputs if ttl input is selected v ss ? 0.3 ? 0.8 v v ilr initx ? v ss ? 0.3 ? 0.2 ?? v dd v initx input pin (cmos hysteresis) v ilm md_3 to md_0 ? v ss ? 0.3 ? v ss ? 0.3 v mode input pins v ilxds x0, x0a ? v ss ? 0.3 ? 0.5 v external clock in ?oscillation mode?
document number: 002-04609 rev. *a page 84 of 106 mb91460c series (v dd 5 ? av cc 5 ? 3.0 v to 5.5 v, v ss 5 ? av ss 5 ? 0 v, t a ? ? 40 c to ? 105 c) parameter symbol pin name condition value unit remarks min typ max input ?l? voltage v ilxdf x0 ? v ss ? 0.3 ? 0.2 ? v dd v external clock in ?fast clock input mode? output ?h? voltage v oh2 normal outputs 4.5v ? v dd ? 5.5v, i oh ? ? 2ma v dd ? 0.5 ?? v driving strength set to 2 ma 3.0v ? v dd ? 4.5v, i oh ? ? 1.6ma v oh5 normal outputs 4.5v ? v dd ? 5.5v, i oh ? ? 5ma v dd ? 0.5 ?? v driving strength set to 5 ma 3.0v ? v dd ? 4.5v, i oh ? ? 3ma v oh3 i 2 c outputs 3.0v ? v dd ? 5.5v, i oh ? ? 3ma v dd ? 0.5 ?? v v oh30 high current outputs 4.5v ? v dd ? 5.5v, t a = -40c, i oh = -40ma v dd ? 0.5 v driving strength set to 30ma 4.5v ? v dd ? 5.5v, i oh = -30ma 3.0v ? v dd ? 4.5v, i oh = -20ma output ?l? voltage v ol2 normal outputs 4.5v ? v dd ? 5.5v, i oh ? ? 2ma ?? 0.4 v driving strength set to 2 ma 3.0v ? v dd ? 4.5v, i oh ? ? 1.6ma v ol5 normal outputs 4.5v ? v dd ? 5.5v, i oh ? ? 5ma ?? 0.4 v driving strength set to 5 ma 3.0v ? v dd ? 4.5v, i oh ? ? 3ma v ol3 i 2 c outputs 3.0v ? v dd ? 5.5v, i oh ? ? 3ma ?? 0.4 v v ol30 high current outputs 4.5v ? v dd ? 5.5v, t a = -40c, i oh = +40ma 0.5 v driving strength set to 30ma 4.5v ? v dd ? 5.5v, i oh = +30ma 3.0v ? v dd ? 4.5v, i oh = +20ma input leakage current i il pnn_m * 1 3.0v ? v dd ? 5.5v v ss 5 < v i < v dd t a =25 c ? 1 ? ? 1 a 3.0v ? v dd ? 5.5v v ss 5 < v i < v dd t a =105 c ? 3 ? ? 3
document number: 002-04609 rev. *a page 85 of 106 mb91460c series analog input leakage current i ain ann * 2 3.0v ? v dd ? 5.5v t a =25 c ? 1 ? ? 1 a 3.0v ? v dd ? 5.5v t a =105 c ? 3 ? ? 3 a pull-up resistance r up pnn_m* 3 , initx 3.0v ? v dd ? 3.6v 40 100 160 k ? 4.5v ? v dd ? 5.5v 25 50 100 pull-down resistance r down pnn_m* 4 3.0v ? v dd ? 3.6v 40 100 180 k ? 4.5v ? v dd ? 5.5v 25 50 100 input capacitance c in all except v dd 5, v dd 5r, v ss 5, av cc 5, av ss , avrh5 f ? 1 mhz ? 515pf power supply current mb91- f467cx i cc v dd 5r mb91f467cx: clkb: 100 mhz clkp: 50 mhz clkt: 50 mhz clkcan: 50 mhz ? 120 150 ma code fetch from flash i cch v dd 5r t a ? ? 25 c ? 30 150 a at stop mode *5 t a ? ? 105 c ? 400 2000 a t a ? ? 25 c ? 100 500 a rtc : 4 mhz mode *5 t a ? ? 105 c ? 500 2400 a t a ? ? 25 c ? 50 250 artc : 100 khz mode *5 32 khz mode *6 t a ? ? 105 c ? 450 2200 a i lve v dd 5 ?? 70 150 a external low voltage detection i lvi v dd 5r ?? 50 100 a internal low voltage detection i osc v dd 5 ?? 250 500 a main clock (4 mhz) ?? 20 40 a sub clock (32 khz) parameter symbol pin name condition value unit remarks min typ max
document number: 002-04609 rev. *a page 86 of 106 mb91460c series power supply current mb91- f465ca i cc v dd 5r mb91f465ca: clkb: 100 mhz clkp: 50 mhz clkt: 50 mhz clkcan: 50 mhz ? 110 140 ma code fetch from flash i cch v dd 5r t a ? ? 25 c ? 30 150 a at stop mode *5 t a ? ? 105 c ? 300 2000 a t a ? ? 25 c ? 100 500 a rtc : 4 mhz mode *5 t a ? ? 105 c ? 500 2400 a t a ? ? 25 c ? 50 250 artc : 100 khz mode *5 32 khz mode *6 t a ? ? 105 c ? 400 2200 a i lve v dd 5 ?? 70 150 a external low voltage detection i lvi v dd 5r ?? 50 100 a internal low voltage detection i osc v dd 5 ?? 250 500 a main clock (4 mhz) ?? 20 40 a sub clock (32 khz) power supply current mb91- f463ca (target data) i cc v dd 5r mb91f463ca: clkb: 100 mhz clkp: 50 mhz clkt: 50 mhz clkcan: 50 mhz ? 100 130 ma code fetch from flash i cch v dd 5r t a ? ? 25 c ? 30 150 a at stop mode *5 t a ? ? 105 c ? 300 2000 a t a ? ? 25 c ? 100 500 a rtc : 4 mhz mode *5 t a ? ? 105 c ? 500 2400 a t a ? ? 25 c ? 50 250 artc : 100 khz mode *5 32 khz mode *6 t a ? ? 105 c ? 400 2200 a i lve v dd 5 ?? 70 150 a external low voltage detection i lvi v dd 5r ?? 50 100 a internal low voltage detection i osc v dd 5 ?? 250 500 a main clock (4 mhz) ?? 20 40 a sub clock (32 khz) 1. pnn_m includes all gpio pins. analog (an) channels and pullup/pulldown are disabled. 2. ann includes all pins where an channels are enabled. 3. pnn_m includes all gpio pins. the pull up resistors must be en abled by pper/ppcr setting and the pins must be in input direction. parameter symbol pin name condition value unit remarks min typ max
document number: 002-04609 rev. *a page 87 of 106 mb91460c series 4. pnn_m includes all gpio pins. the pull do wn resistors must be enabled by pper/pp cr setting and the pi ns must be in input direction. 5. main regulator off, sub regulator set to 1.2 v, low voltage detection disabled. 6. main regulator off, sub regulator set 1.2 v, low voltage detection disabled, rc oscillator enabled. additional current consumption of sub oscillator i osc has to be taken into account.
document number: 002-04609 rev. *a page 88 of 106 mb91460c series 15.4 a/d converter characteristics (v dd 5 ? av cc 5 ? 3.0 v to 5.5 v , v ss 5 ? av ss 5 ? 0 v , t a ? ? 40 c to ? 105 c ) (continued) note : the accuracy gets worse as avrh - avrl becomes smaller parameter symbol pin name value unit remarks min typ max resolution ? ? ? ? 10 bit total error ? ? ? 3? ? 3lsb nonlinearity error ? ? ? 2.5 ? ? 2.5 lsb differential nonlinearity error ? ? ? 1.9 ? ? 1.9 lsb zero reading voltage v ot ann avrl ? 1.5 lsb avrl ? 0.5 lsb avrl ? 2.5 lsb v full scale reading voltage v fst ann avrh ? 3.5 lsb avrh ? 1.5 lsb avrh ? 0.5 lsb v compare time t comp ? 0.6 ? 16,500 s 4.5 v ? av cc 5 ? 5.5 v 2.0 ? ? s 3.0 v ? av cc 5 ? 4.5 v sampling time t samp ? 0.4 ? ? s 4.5 v ? av cc 5 ? 5.5 v, r ext < 2 k ? 1.0 ? ? s 3.0 v ? av cc 5 ? 4.5 v, r ext < 1 k ? conversion time t conv ? 1.0 ? ? s 4.5 v ? av cc 5 ? 5.5 v 3.0 ? ? s 3.0 v ? av cc 5 ? 4.5 v input capacitance c in ann ? ? 11 pf input resistance r in ann ??2.6k ? 4.5 v ? av cc 5 ? 5.5 v ??12.1k ? 3.0 v ? av cc 5 ? 4.5 v analog input leakage current i ain ann ? 1? ? 1 at a ? ? 25 c ? 3? ? 3 at a ? ? 105 c analog input voltage range v ain ann avrl ? avrh v offset between input channels ? ann ? ? 4 lsb
document number: 002-04609 rev. *a page 89 of 106 mb91460c series (continued) * 1 : supply current at av cc 5, if a/d converter and alarm comparator are not operating, (v dd 5 = av cc 5 = avrh = 5.0 v) * 2 : input current at avrh5, if a/ d converter is not operating, (v dd 5 = av cc 5 = avrh = 5.0 v) * 3 : the current consumption per adc macro is given here. on devi ces having more then one a/d converter, the current values have to be multiplied by the number of macros. sampling time calculation t samp = ( 2.6 kohm + r ext ) ??? 11pf ??? 7; for 4.5v ? av cc 5 ? 5.5v t samp = (12.1 kohm + r ext ) ??? 11pf ??? 7; for 3.0v ? av cc 5 ? 4.5v conversion time calculation t conv = t samp + t comp definition of a/d converter terms resolution analog variation that is recognizable by the a/d converter. nonlinearity error deviation between actual conversion characteristics and a straight line connecting the zero transition point (00 0000 0000 b ? 00 0000 0001 b ) and the full scale transition point (11 1111 1110 b ? 11 1111 1111 b ). differential nonlinearity error deviation of the input voltage from the ideal value th at is required to change the output code by 1 lsb. total error this error indicates the difference between actual and theoretical values, including the zero transition error, full scale tra nsition error, and nonlinearity error. parameter symbol pin name value unit remarks min typ max reference voltage range avrh avrh5 0.75 av cc 5 ?av cc 5v avrl av ss 5av ss 5?av cc 5 0.25 v power supply current per adc macro * 3 i a av cc 5? 2.5 5ma a/d converter active i ah av cc 5? ? 5 a a/d converter not operated * 1 reference voltage current per adc macro * 3 i r avrh5 ? 0.7 1 ma a/d converter active i rh avrh5 ? ? 5 a a/d converter not operated * 2
document number: 002-04609 rev. *a page 90 of 106 mb91460c series (continued) 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h av ss 5 avrh 0.5 lsb' {1 lsb? (n ? 1) + 0.5 lsb?} 1.5 lsb? analog input total error digital output actual conversion characteristics v nt ( measurement value) ideal characteristics actual conversion characteristics total error of digital output n ? 1 lsb' v nt ? {1 lsb' ??? (n ? 1) ? 0.5 lsb'} n : a/d converter digital output value v ot ' (ideal value) ? av ss 5 ? 0.5 lsb' [v] v fst ' (ideal value) ? avrh ? 1.5 lsb' [v] v nt : voltage at which the digital output changes from (n ? 1) h to n h 1lsb' (ideal value) ? 1024 avrh ? av ss 5 [v]
document number: 002-04609 rev. *a page 91 of 106 mb91460c series (continued) (n+1) h n h (n-1) h (n-2) h av ss 5 avrh 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h av ss 5 avrh {1 lsb (n - 1) + v ot } analog input analog input differential nonlinearity error nonlinearity error digital output digital output actual conversion characteristics v fst (measure- ment value) v nt (measure- ment value) actual conversion characteristics ideal characteristics v to (measurement val- actual conversion characteristics v nt (measure- ment value) v fst (measure- ment value) nonlinearity error of digital output n ? 1lsb v nt ? {1lsb ??? (n ? 1) ? v ot } [lsb] differential nonlinearity error of digital output n ? 1lsb v ( n ? 1 ) t ? v nt ? 1 [lsb] 1lsb ? 1022 v fst ? v ot [v] n : a/d converter digital output value v ot : voltage at which the di gital output changes from 000 h to 001 h . v fst : voltage at which the digi tal output changes from 3fe h to 3ff h . actual conversion characteristics ideal characteristics
document number: 002-04609 rev. *a page 92 of 106 mb91460c series 15.5 alarm comparator characteristics note: *1 : the fast alarm comparator mode is enabled by setting acsr.md=1 setting acsr.md=0 sets the normal mode . parameter symbol pin name value unit remarks min typ max power supply cur- rent i a5almf av cc 5 ?2540 a alarm compara- tor enabled in fast mode (per channel) *1 i a5alms ?710 a alarm compara- tor enabled in normal mode (per channel) *1 i a5almh ?? 5 a alarm comparator disabled alarm pin input current i alin alarm_n ? 1? ? 1 at a =25 c ? 3? ? 3 at a =105 c alarm pin input voltage range v alin 0?av cc 5v alarm upper limit voltage v iah av cc 5 0.78 ? 3 ? av cc 5 0.78 av cc 5 0.78 ? 3 ? v alarm lower limit voltage v ial av cc 5 0.36 ? 5 ? av cc 5 0.36 av cc 5 0.36 ? 5 ? v alarm hysteresis voltage v iahys 50 ? 250 mv alarm input resistance r in 5??m ? comparion time t compf ?0.10.2 a alarm compara- tor enabled in fast mode *1 t comps ?1 2 a alarm compara- tor enabled in normal mode *1
document number: 002-04609 rev. *a page 93 of 106 mb91460c series 15.6 flash memory program/erase characteristics 15.6.1 mb91f463ca, mb91f465ca (t a = 25 o c, vcc = 5.0v) *1: this value was converted from the results of evaluating the re liability of the technology (using arrhenius equation to conve rt high temperature measurements into normalized value at 85 o c) 15.6.2 mb91f467cx (t a = 25 o c, vcc = 5.0v) *1: this value was converted from the results of evaluating th e reliability of the technology (using arrhenius equation to conv ert high temperature measurements in to normalized value at 85 o c) parameter value unit remarks min typ max sector erase time - 0.9 3.6 s erasure programming time not included chip erase time - n*0.9 n*3.6 s n is the nu mber of flash sector of the device word (16-bit width) programming time -23370 s system overhead time not included programme/erase cycle 10 000 cycle flash data retention time 20 year *1 parameter value unit remarks min typ max sector erase time - 0.5 2.0 s erasure programming time not included chip erase time - n*0.5 n*2.0 s n is the nu mber of flash sector of the device word (16-bit or 32-bit width) pro- gramming time - 6 100 s system overhead time not included programme/erase cycle 10 000 cycle flash data retention time 20 year *1
document number: 002-04609 rev. *a page 94 of 106 mb91460c series 15.7 ac characteristics 15.7.1 clock timing ( v dd 5 ? 3.0 v to 5.5 v , vss5 ? avss5 ? 0 v , t a ? ? 40 c to ? 105 c ) clock timing condition parameter symbol pin name value unit condition min typ max clock frequency f c x0 x1 3.5 4 16 mhz opposite phase external supply or crystal x0a x1a 32 32.768 100 khz 0.8 v cc 0.2 v cc p wh p wl t c x0, x1, x0a, x1a
document number: 002-04609 rev. *a page 95 of 106 mb91460c series 15.7.2 reset input ratings (v dd 5 ? 3.0 v to 5.5 v, v ss 5 ? av ss 5 ? 0 v, t a ? ? 40 c to ? 105 c) parameter symbol pin name condition value unit min max initx input time (at power-on) t intl initx ? 10 ? ms initx input time (other than the above) 20 ? s 0.2 v cc t intl initx
document number: 002-04609 rev. *a page 96 of 106 mb91460c series 15.7.3 lin-usart timings at v dd 5 = 3.0 to 5.5 v ? conditions during ac measurements ? all ac tests were measured under the following conditions: ? - io drive = 5 ma ? - v dd 5 = 3.0 v to 5.5 v, i load = 3 ma ? - v ss 5 = 0 v ? - t a = -40c to +105c ? - c l = 50 pf (load capacity value of pins when testing) ? - vol = 0.2 x v dd 5 ? - voh = 0.8 x v dd 5 ? - epilr = 0, pilr = 1 (a utomotive level = worst case) (v dd 5 ? 3.0 v to 5.5 v, v ss 5 ? av ss 5 ? 0 v, t a ? ? 40 c to ? 105 c) * : parameter m depends on t scyci and can be calculated as : ? if t scyci ? 2*k*t clkp , then m ? k, where k is an integer > 2 ? if t scyci ? (2*k ? 1)*t clkp , then m ? k ? 1, where k is an integer > 1 notes : ? the above values are ac characteristics for clk synchronous mode. ? t clkp is the cycle time of the peripheral clock. parameter symbol pin name condition v dd 5 ? 3.0 v to 4.5 v v dd 5 ? 4.5 v to 5.5 v unit min max min max serial clock cycle time t scyci sckn internal clock operation (master mode) 4 t clkp ? 4 t clkp ? ns sck ? ? sot delay time t slovi sckn sotn ? 30 30 ? 20 20 ns sot ??? sck ? delay time t ovshi sckn sotn m ? t clkp ? 30* ? m ? t clkp ? 20* ? ns valid sin ? sck ??? setup time t ivshi sckn sinn t clkp ? 55 ? t clkp ? 45 ? ns sck ????? valid sin hold time t shixi sckn sinn 0 ? 0 ? ns serial clock ?h? pulse width t shsle sckn external clock operation (slave mode) t clkp ? 10 ? t clkp ? 10 ? ns serial clock ?l? pulse width t slshe sckn t clkp ? 10 ? t clkp ? 10 ? ns sck ? ? sot delay time t slove sckn sotn ? 2 t clkp ? 55 ? 2 t clkp ? 45 ns valid sin ? sck ??? setup time t ivshe sckn sinn 10 ? 10 ? ns sck ????? valid sin hold time t shixe sckn sinn t clkp ? 10 ? t clkp ? 10 ? ns sck rising time t fe sckn ? 20 ? 20 ns sck falling time t re sckn ? 20 ? 20 ns
document number: 002-04609 rev. *a page 97 of 106 mb91460c series internal clock mode (master mode) external clock mode (slave mode) t ivshi v ih t shixi t slovi t scyci v ol sotn sckn for escr:sces = 0 sckn for escr:sces = 1 t ovshi v ol v ol v il v ol v il v ih v oh v oh v oh v oh sinn t ivshe v ih t shixe t slove t slshe v ol sotn sckn for escr:sces = 0 sckn for escr:sces = 1 v ol v il v ol v il v ih v oh v oh v ol v oh v oh v oh sinn t shsle v ol t re v oh t fe v ol
document number: 002-04609 rev. *a page 98 of 106 mb91460c series 15.7.4 i 2 c ac timings at v dd 5 = 3.0 to 5.5 v ? conditions during ac measurements all ac tests were measured under the following conditions: -io drive ? 3 ma -v dd 5 ? 3.0 v to 5.5 v, i load ? 3 ma (v dd = 4.5 v to 5.5 v for mb91f467cx) -v ss 5 ? 0 v -ta ? ? 40 c to ? 105 c -c l ? 50 pf - vol ? 0.3 ??? v dd 5 - voh ? 0.7 ? v dd 5 - epilr ? 0, pilr ? 0 (cmos hysteresis 0.3 ? v dd 5/0.7 ? v dd 5) fast mode: ( v dd 5 ? 3.5 v to 5.5 v , v ss 5 ? av ss 5 ? 0 v , t a ? ? 40 c to ? 105 c ) * 1 : on mb91f467cx only guaranteed for 4.5 v < v dd 5 < 5.5 v. * 2 : the noise filter will suppress single spikes with a pulse width of 0ns and between (1 to 1.5) cycles of peripheral clock, dep ending on the phase relationship between i 2 c signals (sda, scl) and peripheral clock. note: t clkp is the cycle time of the peripheral clock. parameter symbol pin name value unit remark min max scl clock frequency f scl scln 0 400 khz hold time (repeated) start condition. after this period, the first clock pulse is generated t hd;sta scln, sdan 0.6 ? s low period of the scl clock t low scln 1.3 ? s high period of the scl clock t high scln 0.6 ? s setup time for a repeated start condi- tion t su;sta scln, sdan 0.6 ? s data hold time for i 2 c-bus devices t hd;dat scln, sdan 0 0.9 s data setup time t su;dat scln sdan 100 ? ns rise time of both sda and scl signals t r scln, sdan 20 + 0.1cb 300 ns *1 fall time of both sda and scl signals t f scln, sdan 20 + 0.1cb 300 ns *1 setup time for stop condition t su;sto scln, sdan 0.6 ? s bus free time between a stop and start condition t buf scln, sdan 1.3 ? s capacitive load for each bus line c b scln, sdan ? 400 pf pulse width of spike suppressed by input filter t sp scln, sdan 0 (1.1.5) ?? t clkp ns * 2
document number: 002-04609 rev. *a page 99 of 106 mb91460c series sda s sr p s scl t hd;sta tr tr t sp t su;st0 t su;sta t su;dat t hd;dat t hd;sta t low t high t buf tf tf
document number: 002-04609 rev. *a page 100 of 106 mb91460c series 15.7.5 free-run timer clock ( v dd 5 ? 3.0 v to 5.5 v , v ss 5 ? av ss 5 ? 0 v , t a ? ? 40 c to ? 105 c ) note : t clkp is the cycle time of the peripheral clock. 15.7.6 trigger input timing ( v dd 5 ? 3.0 v to 5.5 v , v ss 5 ? av ss 5 ? 0 v , t a ? ? 40 c to ? 105 c ) note : t clkp is the cycle time of the peripheral clock. parameter symbol pin name condition value unit min max input pulse width t tiwh t tiwl ckn ? 4t clkp ?ns parameter symbol pin name condition value unit min max input capture input trigger t inp icun ? 5t clkp ?ns a/d converter trigger t atgx atgx ? 5t clkp ?ns t tiwh t tiwl ckn v ih v ih v il v il icun, atgx t atgx, t inp
document number: 002-04609 rev. *a page 101 of 106 mb91460c series 16. ordering information part number package remarks mb91f467capmc-gse2 144-pin plastic lqfp (fpt-144p-m08) not recommended mb91f467cbpmc-gse2 lead-free package mb91f465capmc-gse2 lead-free package MB91F463CAPMC-GSE2 lead-free package
document number: 002-04609 rev. *a page 102 of 106 mb91460c series 17. package dimension 144-pin pla s tic lqfp lead pitch 0.50 mm package width package length 20.0 20.0 mm lead s hape g u llwing sealing method pla s tic mold mo u nting height 1.70 mm max weight 1.20g code (reference) p-lfqfp144-20 20-0.50 144-pin pla s tic lqfp (fpt-144p-m08) (fpt-144p-m08) c 2003 fujitsu limited f144019s-c-4-6 detail s of "a" part 0.25(.010) (stand off) (.004.004) 0.100.10 (.024.006) 0.600.15 (.020.008) 0.500.20 1.50 +0.20 ?0.10 +.008 ?.004 .059 0 ? ~8 ? 0.50(.020) "a" 0.08(.003) 0.1450.055 (.006.002) lead no. 1 36 index 37 72 73 108 109 144 0.220.05 (.009.002) m 0.08(.003) 20.000.10(.787.004)sq 22.000.20(.866.008)sq (mo u nting height) * dimen s ion s in mm (inche s ). note: the val u e s in parenthe s e s are reference val u e s . ?2003-2008 fujitsu microelectronics limited f144019s-c-4-7 note 1) * :val u e s do not incl u de re s in protr us ion. re s in protr us ion i s +0.25(.010)max(each s ide). note 2) pin s width and pin s thickne ss incl u de plating thickne ss . note 3) pin s width do not incl u de tie bar c u tting remainder.
document number: 002-04609 rev. *a page 103 of 106 mb91460c series 18. revision history version date remark 2.0 2008-04-16 initial version 2.1 2008-08-15 handling devices: section notes on ps register changed for better understanding; interrupt vector table: corrected the footnotes flash: added note about the flas h operation mode switching; added section "poweron sequence in parallel programming mode"; flash security: corrected sect or assignments fsv1,fsv2 absolute maximum ratings: removed the note that analog input/output pins cannot accept +b signal input. dc characteristics: updated pullup/d own resistors and the footnotes, splitted i lv into external and internal lv detection ad converter characteristics updated (complete section); ordering information updated; company name updated 2.2 2008-11-24 flash: added mb91f463ca to all sections memory maps: removed external bus areas (no ext. bus available) io-map: added/corrected mb91f463ca ordering information: added mb91f463ca
document number: 002-04609 rev. *a page 104 of 106 mb91460c series 19. main changes spansion publication number: ds07-16610-2e note: please see ?document history? about later revised information. page section change results 2 features 2. internal peripheral resources deleted following description: fly-by transfer support (between external i/o and memory) 29 embedded program / data memory (flash) corrected the note: the operation mode of the flash memory the operation mode of the mcu 49 i/o map added reload timer 0 and 1 on address 0001b0 h to 0001bc h 89, 90 electrical characteristics 3. dc characteristics corrected the remarks column of parameter: power supply current rtc: 100 khz mode* 5 rtc: 100 khz mode* 5 , 32 khz mode* 6 91 added footnote 6: 99 electrical characteristics 7.2. reset input ratings corrected the spec value of initx input time (at power-on) min: 8 ms 10 ms
document number: 002-04609 rev. *a page 105 of 106 mb91460c series document history document title: mb91460c series fr60 32-bit microcontroller document number: 002-04609 revision ecn orig. of change submission date description of change ** ? tors 04/28/2010 migrated to cypress and assigned document number 002-04609. no change to document contents or format. *a 5200971 tors 04/12/2016 updated to cypress format.
document number: 002-04609 rev. *a revised april 12, 2016 page 106 of 106 mb91460c series ? cypress semiconductor corporation, 2009-2016. this document is the property of cypress semiconductor corporation and its subs idiaries, including spansion llc ("cypress"). this document, including any software or firmware included or referenced in this document ("software"), is owned by cypress under the intellec tual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragr aph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a writte n agreement with cypress governing the use of the software, then cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the software (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hardware products, only internally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardware product units, and (2) u nder those claims of cypress's patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely for use with cypress hardware product s. any other use, reproduction, modification, translation, or compilation of the software is prohibited. to the extent permitted by applicable law, cypress makes no warranty of any kind, express or implied, with regard to this docum ent or any software or accompanying hardware, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. to the extent permitted by applicable law, cypress reserves the right to make changes to this document without further notice. cypress does n ot assume any liability arising out of the application or use of any product or circuit described in this document. any information provided in this document, including any sample design informat ion or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly desi gn, program, and test the functionality and safety of any appli cation made of this information and any resulting product. cypress products are not designed, intended, or authorized fo r use as critical components in systems de signed or intended for the operation of w eapons, weapons systems, nuclear inst allations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazar dous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("unintended uses"). a crit ical component is any compo nent of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affe ct its safety or effectiveness. cypress is not liable, in who le or in part, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or related to all unintended uses of cypress products. you shall indemnify and hold cy press harmless from and against all claims, costs, damages, and other liabilities, including claims for personal inju ry or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, psoc, capsense, ez-usb, f-ram, and traveo are trademarks or registered trad emarks of cypress in the united states and other countries. for a more complete list of cypre ss trademarks, visit cypress.com. other names and brands may be claimed as property of their respective owners. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/arm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface lighting & power control cypress.com/powerpsoc memory cypress.com/memory psoc cypress.com/psoc touch sensing cypress.com/touch usb controllers cypress.com/usb wireless/rf cypress.com/wireless psoc ? solutions cypress.com/psoc psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/support

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