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this is information on a product in full production. february 2013 docid022116 rev 2 1/44 44 L3GD20 mems motion sensor: three-axis digital output gyroscope datasheet - production data features ? three selectable full scales (250/500/2000 dps) ? i 2 c/spi digital output interface ? 16 bit-rate value data output ? 8-bit temperature data output ? two digital output lines (interrupt and data ready) ? integrated low- and high-pass filters with user- selectable bandwidth ? wide supply voltage: 2.4 v to 3.6 v ? low voltage-compatible ios (1.8 v) ? embedded power-down and sleep mode ? embedded temperature sensor ? embedded fifo ? high shock survivability ? extended operating temperature range (-40 c to +85 c) ? ecopack ? rohs and ?green? compliant applications ? gaming and virtual reality input devices ? motion control with mmi (man-machine interface) ? gps navigation systems ? appliances and robotics description the L3GD20 is a low-power three-axis angular rate sensor. it includes a sensing element and an ic interface capable of providing the measured angular rate to the external world through a digital interface (i 2 c/spi). the sensing element is manufactured using a dedicated micro-machining process developed by stmicroelectronics to produce inertial sensors and actuators on silicon wafers. the ic interface is manufactured using a cmos process that allows a high level of integration to design a dedicated circuit which is trimmed to better match the sensing element characteristics. the L3GD20 has a full scale of 250/500/ 2000 dps and is capable of measuring rates with a user-selectable bandwidth. the L3GD20 is available in a plastic land grid array (lga) package and can operate within a temperature range of -40 c to +85 c. lga-16 (4x4x1 mm) table 1. device summary order code temperature range (c) package packing L3GD20 -40 to +85 lga-16 (4x4x1 mm) tray L3GD20tr -40 to +85 lga-16 (4x4x1 mm) tape and reel www.st.com
contents L3GD20 2/44 docid022116 rev 2 contents 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4.1 spi - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4.2 i2c - inter ic control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.5 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.6 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.6.1 sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.6.2 zero-rate level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.7 soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 digital main blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2 fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2.1 bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2.2 fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2.3 stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2.4 bypass-to-stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.5 stream-to-fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.6 retrieve data from fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5 digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1 i2c serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1.1 i2c operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.2 spi bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2.1 spi read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
docid022116 rev 2 3/44 L3GD20 contents 5.2.2 spi write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.2.3 spi read in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6 output register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.1 who_am_i (0fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.2 ctrl_reg1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.3 ctrl_reg2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.4 ctrl_reg3 (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.5 ctrl_reg4 (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.6 ctrl_reg5 (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.7 reference/datacapture (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.8 out_temp (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.9 status_reg (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.10 out_x_l (28h), out_x_h (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.11 out_y_l (2ah), out_y_h (2bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.12 out_z_l (2ch), out_z_h (2dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.13 fifo_ctrl_reg (2eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.14 fifo_src_reg (2fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.15 int1_cfg (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.16 int1_src (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.17 int1_ths_xh (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.18 int1_ths_xl (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.19 int1_ths_yh (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.20 int1_ths_yl (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.21 int1_ths_zh (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.22 int1_ths_zl (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.23 int1_duration (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
list of tables L3GD20 4/44 docid022116 rev 2 list of tables table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 4. mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 5. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 table 6. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 table 7. spi slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 8. i2c slave timing values (tbc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 9. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 10. serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 11. i2c terminology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 12. sad+read/write patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 13. transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 14. transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 15. transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 22 table 16. transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 22 table 17. register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 18. who_am_i register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 19. ctrl_reg1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 20. ctrl_reg1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 21. dr and bw configuration setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 22. power mode selection configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 23. ctrl_reg2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 24. ctrl_reg2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 25. high-pass filter mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 26. high-pass filter cut off frequency configuration [hz] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 27. ctrl_reg1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 28. ctrl_reg3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 29. ctrl_reg4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 30. ctrl_reg4 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 31. ctrl_reg5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 32. ctrl_reg5 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 33. reference register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 34. reference register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 table 35. out_temp register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 36. out_temp register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 37. status_reg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 38. status_reg description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 39. reference register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 40. reference register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 table 41. fifo mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 42. fifo_src register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 43. fifo_src register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 44. int1_cfg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 45. int1_cfg description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 46. int1_src register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 47. int1_src description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 48. int1_ths_xh register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 49. int1_ths_xh description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 50. int1_ths_xl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
docid022116 rev 2 5/44 L3GD20 list of tables table 51. int1_ths_xl description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 52. int1_ths_yh register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 53. int1_ths_yh description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 54. int1_ths_yl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 55. int1_ths_yl description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 56. int1_ths_zh register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 57. int1_ths_zh description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 58. int1_ths_zl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 59. int1_ths_zl description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 60. int1_duration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 61. int1_duration description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 62. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
list of figures L3GD20 6/44 docid022116 rev 2 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3. spi slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4. i2c slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5. L3GD20 electrical connections and external component values . . . . . . . . . . . . . . . . . . . . 13 figure 6. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 7. bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 8. fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 9. stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 10. bypass-to-stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 11. trigger stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 12. read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 13. spi read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 14. multiple byte spi read protocol (2-byte example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 15. spi write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 16. multiple byte spi write protocol (2-byte example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 17. spi read protocol in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 18. int1_sel and out_sel configuration block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 19. wait disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 20. wait enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 21. lga-16: mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
docid022116 rev 2 7/44 L3GD20 block diagram and pin description 1 block diagram and pin description figure 1. block diagram note: the vibration of the structure is maintained by drive circuitry in a feedback loop. the sensing signal is filtered and appears as a digital signal at the output. 1.1 pin description figure 2. pin connection fifo trimming circuits reference mixer charge amp clock low-pass filter + x,y,z i2c spi cs scl/spc sda/sdo/sdi sdo y+ z+ y- z- x+ x- driving mass feedback loop m u x a d d c i g i t a l f i l t e r i n g control logic & interrupt gen. int1 drdy/int2 a d c t e m p e r a t u r e s e n s o r 1 2 & phase generator am10126v1 (top view) directions of the detectable angular rates x vdd_io scl/spc sda/sdi/sdo sdo/sa0 res res res res int1 drdy/int2 cs res res res vdd gnd 1 8 12 5 4 9 13 16 + z + x bottom view + y am10127v1
block diagram and pin description L3GD20 8/44 docid022116 rev 2 table 2. pin description table 3. pin# name function 1 vdd_io (1) 1. 100 nf filter capacitor recommended. power supply for i/o pins 2 scl spc i 2 c serial clock (scl) spi serial port clock (spc) 3 sda sdi sdo i 2 c serial data (sda) spi serial data input (sdi) 3-wire interface serial data output (sdo) 4 sdo sa0 spi serial data output (sdo) i 2 c less significant bit of the device address (sa0) 5cs i 2 c/spi mode selection (1: spi idle mode / i 2 c communication enabled; 0: spi communication mode / i 2 c disabled) 6 drdy/int2 data ready/fifo interrupt (watermark/overrun/empty) 7 int1 programmable interrupt 8 reserved connect to gnd 9 reserved connect to gnd 10 reserved connect to gnd 11 reserved connect to gnd 12 reserved connect to gnd 13 gnd 0 v supply 14 reserved connect to gnd with ceramic capacitor (2) 2. 1 nf min value must be guaranteed under 11 v bias condition. 15 reserved connect to vdd 16 vdd (3) 3. 100 nf plus 10 f capacitors recommended. power supply
docid022116 rev 2 9/44 L3GD20 mechanical and electrical specifications 2 mechanical and electrical specifications 2.1 mechanical characteristics @ vdd = 3.0 v, t = 25 c unless otherwise noted. table 4. mechanical characteristics (1) symbol parameter test condition min. typ. (2) max. unit fs measurement range user-selectable 250 dps 500 2000 so sensitivity fs = 250 dps 8.75 mdps/digit fs = 500 dps 17.50 fs = 2000 dps 70 sodr sensitivity change vs. temperature from -40 c to +85 c 2 % dvoff digital zero-rate level fs = 250 dps 10 dps fs = 500 dps 15 fs = 2000 dps 75 offdr zero-rate level change vs. temperature fs = 250 dps 0.03 dps/c fs = 2000 dps 0.04 dps/c nl non linearity best fit straight line 0.2 % fs rn rate noise density 0.03 odr digital output data rate 95/190/ 380/760 hz to p operating temperature range -40 +85 c 1. the product is factory calibrated at 3.0 v. t he operational power supply range is specified in table 5 . 2. typical specifications are not guaranteed. dps hz () ?
mechanical and electrical specifications L3GD20 10/44 docid022116 rev 2 2.2 electrical characteristics @ vdd =3.0 v, t=25 c unless otherwise noted. 2.3 temperature sensor characteristics @ vdd =3.0 v, t=25 c unless otherwise noted. table 5. electrical characteristics (1) symbol parameter test condition min. typ. (2) max. unit vdd supply voltage 2.4 3.0 3.6 v vdd_io i/o pins supply voltage (3) 1.71 vdd+0.1 v idd supply current 6.1 ma iddsl supply current in sleep mode (4) selectable by digital interface 2ma iddpdn supply current in power-down mode selectable by digital interface 5 a vih digital high level input voltage 0.8*vdd_i o v vil digital low level input voltage 0.2*vdd_i o v to p operating temperature range -40 +85 c 1. the product is factory calibrated at 3.0 v. 2. typical specifications are not guaranteed. 3. it is possible to remove vdd maintaining vdd_io without blocking the communication busses; in this condition the measurement chain is powered off. 4. sleep mode introduces a faster turn-on time relative to power-down mode. table 6. electrical characteristics (1) symbol parameter test condition min. typ. (2) max. unit tsdr temperature sensor output change vs. temperature - -1 c/digit todr temperature refresh rate 1 hz to p operating temperature range -40 +85 c 1. the product is factory calibrated at 3.0 v. 2. typical specifications are not guaranteed.
docid022116 rev 2 11/44 L3GD20 mechanical and electrical specifications 2.4 communication interface characteristics 2.4.1 spi - serial peripheral interface subject to general operating conditions for vdd and t op . figure 3. spi slave timing diagram (a) table 7. spi slave timing values symbol parameter value (1) unit min max tc(spc) spi clock cycle 100 ns fc(spc) spi clock frequency 10 mhz tsu(cs) cs setup time 5 ns th(cs) cs hold time 8 tsu(si) sdi input setup time 5 th(si) sdi input hold time 15 tv(so) sdo valid output time 50 th(so) sdo output hold time 6 tdis(so) sdo output disable time 50 1. values are guaranteed at a 10 mhz clock frequency for spi with both 4 and 3 wires, based on characterization results; not tested in production. a. measurement points are at 0.2vdd_io and 0.8vdd_io, for both input and output port. 63& &6 6', 6'2 w vx&6 w y62 w k62 w k6, w vx6, w k&6 w glv62 w f63& 06%,1 06%287 /6%287 /6%,1 $0y
mechanical and electrical specifications L3GD20 12/44 docid022116 rev 2 2.4.2 i 2 c - inter ic control interface subject to general operating conditions for vdd and t op . figure 4. i 2 c slave timing diagram (b) table 8. i 2 c slave timing values (tbc) symbol parameter i 2 c standard mode (1) i 2 c fast mode (1) unit min max min max f (scl) scl clock frequency 0 100 0 400 khz t w(scll) scl clock low time 4.7 1.3 s t w(sclh) scl clock high time 4.0 0.6 t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time 0 3.45 0 0.9 s t r(sda) t r(scl) sda and scl rise time 1000 20 + 0.1c b (2) 300 ns t f(sda) t f(scl) sda and scl fall time 300 20 + 0.1c b (2) 300 t h(st) start condition hold time 4 0.6 s t su(sr) repeated start condition setup time 4.7 0.6 t su(sp) stop condition setup time 4 0.6 t w(sp:sr) bus free time between stop and start condition 4.7 1.3 1. data based on standard i 2 c protocol requirement; not tested in production. 2. cb = total capacitance of one bus line, in pf. b. measurement points are at 0.2vdd_io and 0.8vdd_io, for both ports. 6'$ 6&/ w i6'$ w vx63 w z6&// w vx6'$ w u6'$ w vx65 w k67 w z6&/+ w k6'$ w u6&/ w i6&/ w z6365 67$57 5(3($7(' 67$57 6723 67$57 $0y
docid022116 rev 2 13/44 L3GD20 mechanical and electrical specifications 2.5 absolute maximum ratings stresses above those listed as ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. note: supply voltage on any pin should never exceed 4.8 v table 9. absolute maximum ratings symbol ratings maximum value unit vdd supply voltage -0.3 to 4.8 v t stg storage temperature range -40 to +125 c sg acceleration g for 0.1 ms 10,000 g esd electrostatic discharge protection 2 (hbm) kv 1.5 (cdm) kv 200 (mm) v vin input voltage on any control pin (cs, scl/spc, sda/sdi/sdo, sdo/sa0) -0.3 to vdd_io +0.3 v this is a mechanical shock sensitive device, improper handling can cause permanent damage to the part this is an esd sensitive device, improper handling can cause permanent damage to the part
mechanical and electrical specifications L3GD20 14/44 docid022116 rev 2 2.6 terminology 2.6.1 sensitivity an angular rate gyroscope is a device that produces a positive-going digital output for counter-clockwise rotation around the sensitive axis considered. sensitivity describes the gain of the sensor and can be determined by applying a defined angular velocity to it. this value changes very little over temperature and time. 2.6.2 zero-rate level zero-rate level describes the actual output signal if there is no angular rate present. zero- rate level of precise mems sensors is, to some extent, a result of stress to the sensor and therefore zero-rate level can slightly change after mounting the sensor onto a printed circuit board or after exposing it to extensive mechanical stress. this value changes very little over temperature and time. 2.7 soldering information the lga package is compliant with the ecopack ? , rohs and ?green? standard. it is qualified for soldering heat resistance according to jedec j-std-020. leave ?pin 1 indicator? unconnected during soldering. land pattern and soldering recommendations are available at www.st.com/mems .
docid022116 rev 2 15/44 L3GD20 application hints 3 application hints figure 5. L3GD20 electrical connections and external component values power supply decoupling capacitors (100 nf + 10 f) should be placed as near as possible to the device (common design practice). if vdd and vdd_io are not connected together, 100 nf and 10 f decoupling capacitors must be placed between vdd and common ground, and 100 nf between vdd_io and common ground. capacitors should be placed as near as possible to the device (common design practice). 9nf 100 nf vdd gnd c1 gnd 10 f scl/spc cs dr sdo/sa0 sda_sdi_sdo 10nf(25v)* vdd_io vdd 1 8 12 5 49 13 16 top view int gnd (top view) directions of the detectable angular rates x + z + x + y vdd i2c bus rpu = 10kohm rpu scl/spc sda_sdi_sdo pull-up to be added when i2c interface is used 14 gnd * c1 must guarantee 1 nf value under 11 v bias condition am10128v1
digital main blocks L3GD20 16/44 docid022116 rev 2 4 digital main blocks 4.1 block diagram figure 6. block diagram 4.2 fifo the L3GD20 embeds 32 slots of 16-bit data fifo for each of the three output channels: yaw, pitch and roll. this allows consistent power saving for the system, since the host processor does not need to continuously poll data from the sensor, but can wake up only when needed and burst the significant data out from the fifo. this buffer can work accordingly in five different modes: bypass mode, fifo mode, stream mode, bypass-to- stream mode and stream-to-fifo mode. each mode is selected by the fifo_mode bits in the fifo_ctrl_reg (2eh). programmable watermark level, fifo_empty or fifo_full events can be enabled to generate dedicated interrupts on the drdy/int2 pin (configured through ctrl_reg3 (22h) and event detection information is available in fifo_src_reg (2fh). watermark level can be configured to wtm4:0 in fifo_ctrl_reg (2eh). adc lpf1 hpf 0 1 hpen lpf2 10 11 01 00 out_sel datareg 00 11 10 01 interrupt generator int_sel i 2 c spi int1 scr reg conf reg fifo 32x16x3 am07230v1
docid022116 rev 2 17/44 L3GD20 digital main blocks 4.2.1 bypass mode in bypass mode, the fifo is not operational and for this reason it remains empty. as described in figure 7 below, for each channel only the first address is used. the remaining fifo slots are empty. when new data is available, the old data is overwritten. figure 7. bypass mode 4.2.2 fifo mode in fifo mode, data from the yaw, pitch and roll channels is stored in the fifo. a watermark interrupt can be enabled (i2_wmk bit into ctrl_reg3 (22h)) in order to be raised when the fifo is filled to the level specified in the wtm 4:0 bits of fifo_ctrl_reg (2eh). the fifo continues filling until it is full (32 slots of 16-bit data for yaw, pitch and roll). when full, the fifo stops collecting data from the input channels. to restart data collection, the fifo_ctrl_reg (2eh) must be written back to bypass mode. fifo mode is represented in figure 8: fifo mode . l x 0 y i z 0 y 0 x 1 y 1 z 1 x 2 y 2 z 2 x 31 y 31 z 31 x i ,y i ,z i empty am07231v1
digital main blocks L3GD20 18/44 docid022116 rev 2 figure 8. fifo mode 4.2.3 stream mode in stream mode, data from yaw, pitch and roll measurement are stored in the fifo. a watermark interrupt can be enabled and set as in the fifo mode.the fifo continues filling until it is full (32 slots of 16-bit data for yaw, pitch and roll). when full, the fifo discards the older data as the new data arrives. programmable watermark level events can be enabled to generate dedicated interrupts on the drdy /int2 pin (configured through ctrl_reg3 (22h). stream mode is represented in figure 9: stream mode . x 0 y i z 0 y 0 x 1 y 1 z 1 x 2 y 2 z 2 x 31 y 31 z 31 x i ,y i ,z i am07232v1
docid022116 rev 2 19/44 L3GD20 digital main blocks figure 9. stream mode x 0 y 0 z 0 x 1 y 1 z 1 x 2 y 2 z 2 x 31 y 31 z 31 x i ,y i ,z i x 30 y 30 z 30 am07234v1
digital main blocks L3GD20 20/44 docid022116 rev 2 4.2.4 bypass-to-stream mode in bypass-to-stream mode, the fifo begins operating in bypass mode and once a trigger event occurs (related to int1_cfg (30h) register events), the fifo starts operating in stream mode. refer to figure 10 below. figure 10. bypass-to-stream mode 4.2.5 stream-to-fifo mode in stream-to-fifo mode, data from yaw, pitch and roll measurement is stored in the fifo. a watermark interrupt can be enabled on pin drdy/int2 by setting the i2_wtm bit in ctrl_reg3 (22h) in order to be raised when the fifo is filled to the level specified in the wtm4:0 bits of fifo_ctrl_reg (2eh). the fifo continues filling until it is full (32 slots of 16-bit data for yaw, pitch and roll). when full, the fifo discards the older data as the new data arrives. once a trigger event occurs (related to int1_cfg (30h) register events), the fifo starts operating in fifo mode. refer to figure 11 below. figure 11. trigger stream mode x 0 y i z 0 y 0 x 1 y 1 z 1 x 2 y 2 z 2 x 31 y 31 z 31 x i ,y i ,z i empty bypass mode stream mode trigger event x 0 y 0 z 0 x 1 y 1 z 1 x 2 y 2 z 2 x 31 y 31 z 31 x i ,y i ,z i x 30 y 30 z 30 am07235v1 x 0 y i z 0 y 0 x 1 y 1 z 1 x 2 y 2 z 2 x 31 y 31 z 31 x i ,y i ,z i stream mode fifo mode trigger event x 0 y 0 z 0 x 1 y 1 z 1 x 2 y 2 z 2 x 31 y 31 z 31 x i ,y i ,z i x 30 y 30 z 30 am07236v1
docid022116 rev 2 21/44 L3GD20 digital main blocks 4.2.6 retrieve data from fifo fifo data is read through out_x (addr reg 28h,29h), out_y (addr reg 2ah,2bh) and out_z (addr reg 2ch,2dh). when the fifo is in stream, trigger or fifo mode, a read operation of the out_x, out_y or out_z registers provides the data stored in the fifo. each time data is read from the fifo, the oldest pitch, roll and yaw data is placed in the out_x, out_y and out_z registers and both single read and read_burst (x,y & z with auto-incrementing address) operations can be used. when data included in out_z_h (2dh) is read, the system restarts to read information from addr out_x_l (28h).
digital interfaces L3GD20 22/44 docid022116 rev 2 5 digital interfaces the registers embedded in the L3GD20 may be accessed through both the i 2 c and spi serial interfaces. the latter may be sw-configured to operate either in 3-wire or 4-wire interface mode. the serial interfaces are mapped onto the same pins. to select/exploit the i 2 c interface, the cs line must be tied high (i.e connected to vdd_io). 5.1 i 2 c serial interface the L3GD20 i 2 c is a bus slave. the i 2 c is employed to write data into registers whose content can also be read back. the relevant i 2 c terminology is given in the table below. there are two signals associated with the i 2 c bus: the serial clock line (scl) and the serial data line (sda). the latter is a bidirectional line used for sending and receiving the data to/from the interface. both lines must be connected to vdd_io through external pull-up resistors. when the bus is free, both lines are high. the i 2 c interface is compliant with fast mode (400 khz) i 2 c standards as well as with normal mode. table 10. serial interface pin description pin name pin description cs i 2 c/spi mode selection (1: spi idle mode / i 2 c communication enabled; 0: spi communication mode / i 2 c disabled) scl/spc i 2 c serial clock (scl) spi serial port clock (spc) sda/sdi/sdo i 2 c serial data (sda) spi serial data input (sdi) 3-wire interface serial data output (sdo) sdo spi serial data output (sdo) i 2 c less significant bit of the device address table 11. i 2 c terminology term description transmitter the device which sends data to the bus receiver the device which receives data from the bus master the device which initiates a transfer, generates clock signals and terminates a transfer slave the device addressed by the master
docid022116 rev 2 23/44 L3GD20 digital interfaces 5.1.1 i 2 c operation the transaction on the bus is started through a start (st) signal. a start condition is defined as a high to low transition on the data line while the scl line is held high. after this has been transmitted by the master, the bus is considered busy. the next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. when an address is sent, each device in the system compares the first seven bits after a start condition with its address. if they match, the device considers itself addressed by the master. the slave address (sad) associated with the L3GD20 is 110101xb. the sdo pin can be used to modify the less significant bit of the device address. if the sdo pin is connected to voltage supply, lsb is ?1? (address 1101011b). otherwise, if the sdo pin is connected to ground, the lsb value is ?0? (address 1101010b). this solution allows to connect and address two different gyroscopes to the same i 2 c bus. data transfer with acknowledge is mandatory. the transmitter must release the sda line during the acknowledge pulse. the receiver must then pull the data line low so that it remains stable low during the high period of the acknowledge clock pulse. a receiver which has been addressed is obligated to generate an acknowledge after each byte of data received. the i 2 c embedded in the L3GD20 behaves like a slave device and the following protocol must be adhered to. after the start condition (st) a slave address is sent, once a slave acknowledge (sak) has been returned, an 8-bit sub-address is transmitted: the 7 lsb represent the actual register address while the msb enables address auto-increment. if the msb of the sub field is 1, the sub (register address) will be automatically incremented to allow multiple data read/write. the slave address is completed with a read/write bit. if the bit was ?1? (read), a repeated start (sr) condition must be issued after the two sub-address bytes; if the bit is ?0? (write) the master will transmit to the slave with direction unchanged. tab le 1 2 explains how the sad+read/write bit pattern is composed, listing all the possible configurations. table 12. sad+read/write patterns command sad[6:1] sad[0] = sdo r/w sad+r/w read 110101 0 1 11010101 (d5) write 110101 0 0 11010100 (d4) read 110101 1 1 11010111 (d7) write 110101 1 0 11010110 (d6) table 13. transfer when master is writing one byte to slave master st sad + w sub data sp slave sak sak sak
digital interfaces L3GD20 24/44 docid022116 rev 2 data is transmitted in byte format (data). each data transfer contains 8 bits. the number of bytes sent per transfer is unlimited. data is transferred with the most significant bit (msb) first. if a receiver cannot receive another complete byte of data until it has performed some other function, it can hold the clock line, scl, low to force the transmitter into a wait state. data transfer only continues when the receiver is ready for another byte and releases the data line. if a slave receiver does not acknowledge the slave address (i.e. it is not able to receive because it is performing some real-time function) the data line must be left high by the slave. the master can then abort the transfer. a low to high transition on the sda line while the scl line is high is defined as a stop condition. each data transfer must be terminated by the generation of a stop (sp) condition. in order to read multiple bytes, it is necessary to assert the most significant bit of the sub- address field. in other words, sub(7) must be equal to ?1? while sub(6-0) represents the address of the first register to be read. in the communication format presented, mak is master acknowledge and nmak is no master acknowledge. 5.2 spi bus interface the spi is a bus slave. the spi allows writing and reading the registers of the device. the serial interface interacts with the outside world through 4 wires: cs , spc , sdi and sdo . table 14. transfer when master is writing multiple bytes to slave master st sad + w sub data data sp slave sak sak sak sak table 15. transfer when master is receiving (reading) one byte of data from slave master st sad + w sub sr sad + r nmak sp slave sak sak sak data table 16. transfer when master is receiving (reading) multiple bytes of data from slave master st sad+w sub sr sad+r mak mak nmak sp slave sak sak sak data data data
docid022116 rev 2 25/44 L3GD20 digital interfaces figure 12. read and write protocol cs is the serial port enable and is controlled by the spi master. it goes low at the start of the transmission and goes back high at the end. spc is the serial port clock and it is controlled by the spi master. it is stopped high when cs is high (no transmission). sdi and sdo are respectively the serial port data input and output. those lines are driven at the falling edge of spc and should be captured at the rising edge of spc . both the read register and write register commands are completed in 16 clock pulses or in multiples of 8 in case of multiple bytes read/write. bit duration is the time between two falling edges of spc . the first bit (bit 0) starts at the first falling edge of spc after the falling edge of cs while the last bit (bit 15, bit 23, ...) starts at the last falling edge of spc just before the rising edge of cs . bit 0 : rw bit. when 0, the data di(7:0) is written to the device. when 1, the data do(7:0) from the device is read. in the latter case, the chip will drive sdo at the start of bit 8. bit 1 : ms bit. when 0, the address remains unchanged in multiple read/write commands. when 1, the address will be auto-incremented in multiple read/write commands. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data di(7:0) (write mode). this is the data that will be written to the device (msb first). bit 8-15 : data do(7:0) (read mode). this is the data that will be read from the device (msb first). in multiple read/write commands, further blocks of 8 clock periods will be added. when the ms bit is 0, the address used to read/write data remains the same for every block. when the ms bit is 1, the address used to read/write data is incremented at every block. the function and the behavior of sdi and sdo remain unchanged. cs spc sdi sdo rw ad5 ad4 ad3 ad2 ad1 ad0 di7 di6 di5 di4 di3 di2 di1 di0 do7do6do5do4do3do2do1do0 ms am10129v1
digital interfaces L3GD20 26/44 docid022116 rev 2 5.2.1 spi read figure 13. spi read protocol the spi read command is performed with 16 clock pulses. the multiple byte read command is performed by adding blocks of 8 clock pulses to the previous one. bit 0 : read bit. the value is 1. bit 1 : ms bit. when 0 do not increment address; when 1 increment address in multiple reading. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data do(7:0) (read mode). this is the data that will be read from the device (msb first). bit 16-... : data do(...-8). further data in multiple byte reading. figure 14. multiple byte spi r ead protocol (2-byte example) cs spc sdi sdo rw do7 do6 do5 do4 do3 do2 do1 do0 ad5 ad4 ad3 ad2 ad1 ad0 ms am10130v1 cs sp c sdi sd o rw do7do6do5do4do3do2 do1do0 ad5 ad4 ad 3 ad2 ad1 ad0 do 15 do 14 do 13 do 12 do 11 do 10 d o9 d o8 ms am10131v1
docid022116 rev 2 27/44 L3GD20 digital interfaces 5.2.2 spi write figure 15. spi write protocol the spi write command is performed with 16 clock pulses. the multiple byte write command is performed by adding blocks of 8 clock pulses to the previous one. bit 0 : write bit. the value is 0. bit 1 : ms bit. when 0, do not increment address; when 1, increment address in multiple writing. bit 2 -7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data di(7:0) (write mode). this is the data that will be written to the device (msb first). bit 16-... : data di(...-8). further data in multiple byte writing. figure 16. multiple byte spi write protocol (2-byte example) 5.2.3 spi read in 3-wire mode 3-wire mode is entered by setting the bit sim (spi serial interface mode selection) to ?1? in ctrl_reg2. cs spc sdi rw di7di6di5di4di3di2di1di0 ad5 ad 4 ad 3 ad2 ad 1 ad0 ms am10132v1 cs spc sdi rw ad5 ad4 ad3 ad2 ad1 ad 0 di 7 d i6 di 5 d i4 di 3 di 2 di 1 di 0 di 15 d i1 4 di 13 d i1 2 di 11 di 10 di 9 di 8 ms am10133v1
digital interfaces L3GD20 28/44 docid022116 rev 2 figure 17. spi read protocol in 3-wire mode the spi read command is performed with 16 clock pulses: bit 0 : read bit. the value is 1. bit 1 : ms bit. when 0, do not increment address; when 1, increment address in multiple reading. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data do(7:0) (read mode). this is the data that will be read from the device (msb first). multiple read command is also available in 3-wire mode. cs spc sdi/o rw do7do6do5do4do3do2do1do0 ad5 ad 4 ad 3 ad2 ad1 ad 0 ms am10134v1
docid022116 rev 2 29/44 L3GD20 output register mapping 6 output register mapping the table below provides a listing of the 8-bit registers embedded in the device, and the related addresses: table 17. register address map name type register address default hex binary reserved - 00-0e - - who_am_i r 0f 000 1111 11010100 reserved - 10-1f - - ctrl_reg1 rw 20 010 0000 00000111 ctrl_reg2 rw 21 010 0001 00000000 ctrl_reg3 rw 22 010 0010 00000000 ctrl_reg4 rw 23 010 0011 00000000 ctrl_reg5 rw 24 010 0100 00000000 reference rw 25 010 0101 00000000 out_temp r 26 010 0110 output status_reg r 27 010 0111 output out_x_l r 28 010 1000 output out_x_h r 29 010 1001 output out_y_l r 2a 010 1010 output out_y_h r 2b 010 1011 output out_z_l r 2c 010 1100 output out_z_h r 2d 010 1101 output fifo_ctrl_reg rw 2e 010 1110 00000000 fifo_src_reg r 2f 010 1111 output int1_cfg rw 30 011 0000 00000000 int1_src r 31 011 0001 output int1_tsh_xh rw 32 011 0010 00000000 int1_tsh_xl rw 33 011 0011 00000000 int1_tsh_yh rw 34 011 0100 00000000 int1_tsh_yl rw 35 011 0101 00000000 int1_tsh_zh rw 36 011 0110 00000000 int1_tsh_zl rw 37 011 0111 00000000 int1_duration rw 38 011 1000 00000000
output register mapping L3GD20 30/44 docid022116 rev 2 registers marked as reserved must not be changed. writing to these registers may cause permanent damage to the device. the content of the registers that are loaded at boot should not be changed. they contain the factory calibration values. their content is automatically restored when the device is powered up.
docid022116 rev 2 31/44 L3GD20 register description 7 register description the device contains a set of registers which are used to control its behavior and to retrieve angular rate data. the register address, consisting of 7 bits, is used to identify them and to write the data through the serial interface. 7.1 who_am_i (0fh) device identification register. 7.2 ctrl_reg1 (20h) dr<1:0> is used for odr selection. bw <1:0> is used for bandwidth selection. in the tab le 21 all frequencies resulting in combinations of dr / bw bits are reported. table 18. who_am_i register 11010100 table 19. ctrl_reg1 register dr1 dr0 bw1 bw0 pd zen xen yen table 20. ctrl_reg1 description dr1-dr0 output data rate selection. refer to table 21 bw1-bw0 bandwidth selection. refer to table 21 pd power-down mode enable. default value: 0 (0: power-down mode, 1: normal mode or sleep mode) zen z axis enable. default value: 1 (0: z axis disabled; 1: z axis enabled) yen y axis enable. default value: 1 (0: y axis disabled; 1: y axis enabled) xen x axis enable. default value: 1 (0: x axis disabled; 1: x axis enabled) table 21. dr and bw configuration setting dr <1:0> bw <1:0> odr [hz] cut-off 00 00 95 12.5 00 01 95 25 00 10 95 25
register description L3GD20 32/44 docid022116 rev 2 a combination of pd, zen, yen, xen is used to set device to different modes (power-down / normal / sleep mode) in accordance with table 22 below. 7.3 ctrl_reg2 (21h) 00 11 95 25 01 00 190 12.5 01 01 190 25 01 10 190 50 01 11 190 70 10 00 380 20 10 01 380 25 10 10 380 50 10 11 380 100 11 00 760 30 11 01 760 35 11 10 760 50 11 11 760 100 table 22. power mode selection configuration mode pd zen yen xen power-down 0 - - - sleep 1 0 0 0 normal 1 - - - table 21. dr and bw configuration setting (continued) dr <1:0> bw <1:0> odr [hz] cut-off table 23. ctrl_reg2 register 0 (1) 1. these bits must be set to ?0? to ensure proper operat ion of the device 0 (1) hpm1 hpm0 hpcf3 hpcf2 hpcf1 hpcf0 table 24. ctrl_reg2 description hpm1- hpm0 high-pass filter mode selection. default value: 00 refer to table 25 hpcf3- hpcf0 high-pass filter cutoff frequency selection refer to table 26
docid022116 rev 2 33/44 L3GD20 register description 7.4 ctrl_reg3 (22h) table 25. high-pass filter mode configuration hpm1 hpm0 high-pass filter mode 0 0 normal mode (reset reading hp_reset_filter) 0 1 reference signal for filtering 10normal mode 1 1 autoreset on interrupt event table 26. high-pass filter cut off frequency configuration [hz] hpcf3-0 odr=95 hz odr=190 hz odr=380 hz odr=760 hz 0000 7.2 13.5 27 51.4 0001 3.5 7.2 13.5 27 0010 1.8 3.5 7.2 13.5 0011 0.9 1.8 3.5 7.2 0100 0.45 0.9 1.8 3.5 0101 0.18 0.45 0.9 1.8 0110 0.09 0.18 0.45 0.9 0111 0.045 0.09 0.18 0.45 1000 0.018 0.045 0.09 0.18 1001 0.009 0.018 0.045 0.09 table 27. ctrl_reg1 register i1_int1 i1_boot h_lactive pp_od i2_drdy i2_wtm i2_orun i2_empty table 28. ctrl_reg3 description i1_int1 interrupt enable on int1 pin. default value 0. (0: disable; 1: enable) i1_boot boot status available on int1. default value 0. (0: disable; 1: enable) h_lactive interrupt active configuration on int1. default value 0. (0: high; 1:low) pp_od push-pull / open drain. default value: 0. (0: push- pull; 1: open drain) i2_drdy date-ready on drdy/int2. default value 0. (0: disable; 1: enable) i2_wtm fifo watermark interrupt on drdy/int2. default value: 0. (0: disable; 1: enable) i2_orun fifo overrun interrupt on drdy/int2 default value: 0. (0: disable; 1: enable) i2_empty fifo empty interrupt on drdy/int2. default value: 0. (0: disable; 1: enable)
register description L3GD20 34/44 docid022116 rev 2 7.5 ctrl_reg4 (23h) 7.6 ctrl_reg5 (24h) table 29. ctrl_reg4 register bdu ble fs1 fs0 - 0 (1) 1. this value must not be changed. 0 (1) sim table 30. ctrl_reg4 description bdu block data update. default value: 0 (0: continuos update; 1: output registers not updated until msb and lsb read- ing) ble big/little endian data selection. default value 0. (0: data lsb @ lower address; 1: data msb @ lower address) fs1-fs0 full scale selection. default value: 00 (00: 250 dps; 01: 500 dps; 10: 2000 dps; 11: 2000 dps) sim spi serial interface mode selection. default value: 0 (0: 4-wire interface; 1: 3-wire interface). table 31. ctrl_reg5 register boot fifo_en -- hpen int1_sel1 int1_sel0 out_sel1 out_sel0 table 32. ctrl_reg5 description boot reboot memory content. default value: 0 (0: normal mode; 1: reboot memory content) fifo_en fifo enable. default value: 0 (0: fifo disable; 1: fifo enable) hpen high-pass filter enable. default value: 0 (0: hpf disabled; 1: hpf enabled see figure 20) int1_sel1-int1_- sel0 int1 selection configuration. default value: 0 (see figure 20 ) out_sel1-out_- sel1 out selection configuration. default value: 0 (see figure 20 )
docid022116 rev 2 35/44 L3GD20 register description figure 18. int1_sel and out_sel configuration block diagram 7.7 reference/datacapture (25h) 7.8 out_temp (26h) temperature data (1lsb/deg - 8-bit resolution). the value is expressed as two's complement. adc lpf1 hpf 0 1 hpen lpf2 10 11 01 00 out_sel <1:0> datareg fifo 32x16x3 00 11 10 01 interrupt generator int1_sel <1:0> am07949v2 table 33. reference register ref7 ref6 ref5 ref4 ref3 ref2 ref1 ref0 table 34. reference register description ref 7-ref0 reference value for interrupt generation. default value: 0 table 35. out_temp register temp7 temp6 temp5 temp4 temp3 temp2 temp1 temp0 table 36. out_temp register description temp7-temp0 temperature data
register description L3GD20 36/44 docid022116 rev 2 7.9 status_reg (27h) 7.10 out_x_l (28h), out_x_h (29h) x-axis angular rate data. the value is expressed as two?s complement. 7.11 out_y_l (2ah), out_y_h (2bh) y-axis angular rate data. the value is expressed as two?s complement. 7.12 out_z_l (2ch), out_z_h (2dh) z-axis angular rate data. the value is expressed as two?s complement. 7.13 fifo_ctrl_reg (2eh) table 37. status_reg register zyxor zor yor xor zyxda zda yda xda table 38. status_reg description zyxor x, y, z -axis data overrun. default value: 0 (0: no overrun has occurred; 1: new data has overwritten the previous data before it was read) zor z axis data overrun. default value: 0 (0: no overrun has occurred; 1: new data for the z-axis has overwritten the previous data) yor y axis data overrun. default value: 0 (0: no overrun has occurred; 1: new data for the y-axis has overwritten the previous data) xor x axis data overrun. default value: 0 (0: no overrun has occurred; 1: new data for the x-axis has overwritten the previous data) zyxda x, y, z -axis new data available. default value: 0 (0: a new set of data is not yet available; 1: a new set of data is available) zda z axis new data available. default value: 0 (0: new data for the z-axis is not yet available; 1: new data for the z-axis is available) yda y axis new data available. default value: 0 (0: new data for the y-axis is not yet available;1: new data for the y-axis is available) xda x axis new data available. default value: 0 (0: new data for the x-axis is not yet available; 1: new data for the x-axis is available) table 39. reference register fm2 fm1 fm0 wtm4 wtm3 wtm2 wtm1 wtm0
docid022116 rev 2 37/44 L3GD20 register description 7.14 fifo_src_reg (2fh) 7.15 int1_cfg (30h) table 40. reference register description fm2-fm0 fifo mode selection. default value: 00 (see table 41 ) wtm4-wtm0 fifo threshold. watermark level setting table 41. fifo mode configuration fm2 fm1 fm0 fifo mode 000bypass mode 001fifo mode 010stream mode 011stream-to-fifo mode 100bypass-to-stream mode table 42. fifo_src register wtm ovrn empty fss4 fss3 fss2 fss1 fss0 table 43. fifo_src register description wtm watermark status. (0: fifo filling is lower than wtm level; 1: fifo filling is equal or higher than wtm level) ovrn overrun bit status. (0: fifo is not completely filled; 1:fifo is completely filled) empty fifo empty bit. (0: fifo not empty; 1: fifo empty) fss4-fss1 fifo stored data level table 44. int1_cfg register and/or lir zhie zlie yhie ylie xhie xlie
register description L3GD20 38/44 docid022116 rev 2 7.16 int1_src (31h) interrupt source register. read only register. table 45. int1_cfg description and/or and/or combination of interrupt events. default value: 0 (0: or combination of interrupt events 1: and combination of interrupt events lir latch interrupt request. default value: 0 (0: interrupt request not latched; 1: interrupt request latched) cleared by reading int1_src reg. zhie enable interrupt generation on z high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured value higher than preset threshold) zlie enable interrupt generation on z low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured value lower than preset threshold) yhie enable interrupt generation on y high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured value higher than preset threshold) ylie enable interrupt generation on y low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured value lower than preset threshold) xhie enable interrupt generation on x high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured value higher than preset threshold) xlie enable interrupt generation on x low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured value lower than preset threshold) table 46. int1_src register 0 ia zhzlyhylxhxl table 47. int1_src description ia interrupt active. default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) zh z high. default value: 0 (0: no interrupt, 1: z high event has occurred) zl z low. default value: 0 (0: no interrupt; 1: z low event has occurred) yh y high. default value: 0 (0: no interrupt, 1: y high event has occurred) yl y low. default value: 0 (0: no interrupt, 1: y low event has occurred) xh x high. default value: 0 (0: no interrupt, 1: x high event has occurred) xl x low. default value: 0 (0: no interrupt, 1: x low event has occurred)
docid022116 rev 2 39/44 L3GD20 register description reading at this address clears int1_src ia bit (and eventually the interrupt signal on the int1 pin) and allows the refresh of data in the int1_src register if the latched option was chosen. 7.17 int1_ths_xh (32h) 7.18 int1_ths_xl (33h) 7.19 int1_ths_yh (34h) 7.20 int1_ths_yl (35h) table 48. int1_ths_xh register - thsx14 thsx13 thsx12 thsx11 thsx10 thsx9 thsx8 table 49. int1_ths_xh description thsx14 - thsx9 interrupt threshold. default value: 0000 0000 table 50. int1_ths_xl register thsx7 thsx6 thsx5 thsx4 thsx3 thsx2 thsx1 thsx0 table 51. int1_ths_xl description thsx7 - thsx0 interrupt threshold. default value: 0000 0000 table 52. int1_ths_yh register - thsy14 thsy13 thsy12 thsy11 thsy10 thsy9 thsy8 table 53. int1_ths_yh description thsy14 - thsy9 interrupt threshold. default value: 0000 0000 table 54. int1_ths_yl register thsy7 thsy6 thsy5 thsy4 thsy3 thsy2 thsy1 thsy0 table 55. int1_ths_yl description thsy7 - thsy0 interrupt threshold. default value: 0000 0000
register description L3GD20 40/44 docid022116 rev 2 7.21 int1_ths_zh (36h) 7.22 int1_ths_zl (37h) 7.23 int1_duration (38h) the d6 - d0 bits set the minimum duration of the interrupt event to be recognized. duration steps and maximum values depend on the odr chosen. the wait bit has the following definitions: wait = ?0?: the interrupt falls immediately if the signal crosses the selected threshold wait = ?1?: if the signal crosses the selected threshold, the interrupt falls only after the duration has counted the number of samples at the selected data rate, written into the duration counter register. table 56. int1_ths_zh register - thsz14 thsz13 thsz12 thsz11 thsz10 thsz9 thsz8 table 57. int1_ths_zh description thsz14 - thsz9 interrupt threshold. default value: 0000 0000 table 58. int1_ths_zl register thsz7 thsz6 thsz5 thsz4 thsz3 thsz2 thsz1 thsz0 table 59. int1_ths_zl description thsz7 - thsz0 interrupt threshold. default value: 0000 0000 table 60. int1_duration register wait d6 d5 d4 d3 d2 d1 d0 table 61. int1_duration description wait wait enable. default value: 0 (0: disable; 1: enable) d6 - d0 duration value. default value: 000 0000
docid022116 rev 2 41/44 L3GD20 register description figure 19. wait disabled figure 20. wait enabled
package information L3GD20 42/44 docid022116 rev 2 8 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack is an st trademark. figure 21. lga-16: mechanical data and package dimensions dimensions ref. mm inch min. typ. max. min. typ. max. a1 1.000 0.03 9 4 a2 0.785 0.030 9 a3 0.200 0.007 9 d 0.300 0.0118 d1 3.850 4.000 4.150 0.1516 0.1575 0.1634 e1 3.850 4.000 4.150 0.1516 0.1575 0.1634 l2 1. 9 50 0.0768 m 0.100 0.003 9 n1 0.650 0.0256 n2 0. 9 75 0.0384 p1 1.750 0.068 9 p2 1.525 0.0600 t1 0.400 0.0157 t2 0.300 0.0118 k 0.050 0.0020 lga-16 (4x4x1mm) land grid array package outline and 81250 9 7_a mechanical data
docid022116 rev 2 43/44 L3GD20 revision history 9 revision history table 62. document revision history date revision changes 18-aug-2011 1 initial release. 27-feb-2013 2 updated table 12: sad+read/write patterns and table 23: ctrl_reg2 register .
L3GD20 44/44 docid022116 rev 2 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not authorized for use in weapons. nor are st products designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statem ents and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - swed en - switzerland - united kingdom - united states of america www.st.com

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