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fedl630q464 - 01 issue date: oct . 26 , 201 6 ml6 3 0 q464/q466 ultra low power 32 - bit microcontroller 1/ 37 general description this lsi is a high - performance low power 32 - bit microcontroller. equipped with a 32 - bit cpu core cortex tm - m0 + , it implements a 128 kb flash memory, 16 kb ram, rich peripheral circuits, such as usb full speed device, synchronous serial p ort, uart, i 2 c bus interface, supply voltage level detect circuit, rc oscillation type a/d converter, successive approximation type a/d converter, and lcd driver . the flash rom that is installed as program memory achieves low - voltage low - power consumption operation (read operation) is most suitable for battery - driven applications. features ? cp u ? 32- bit risc cpu (cpu name: arm cortex tm - m0+ ) ? thumb ? /thumb ? - 2 instruction supported ? serial wire debug port ? minimum instruction execution time 30.5 s (@32 .768 khz system clock) 41.7 ns (@ 24 mhz system clock) ? internal memory ? re- writing the program memory area by software ? number of segments product name flash memory s ram program area d ata area ml6 3 0q 4 64 64 k b ( 16 k ? i nterrupt controller (nvic) ? 1 non - maskable interrupt source (internal sourc e: 1) ? 31 maskable interrupt sources (internal sources: 30 , external sources: 1) ? priority level (4 - level) can be set for each interrupt ? dma controller (dmac) ? 2 channels ? enable to allocate multiple dma transfer request sources for each channel. ? channel priority: fixed mode/round robin mode ? dma transfer mode: cycle steal mode/burst mode ? dma request type: software requests/hardware requests ? maximum transfer count: 65,536 ? data transfer size: 8 bits/16 bits/32 bits ? transfer request source : ssiof, uart, uartf, i2cf, rc- adc, sa - adc ? time base counter (tbc) ? low - speed time base counter 1 channel ? 1 khz timer ? 10 hz / 1 hz interrupt function
fed l6 3 0q 464 - 01 ml6 3 0 q464/q466 2/ 37 ? timer s (tmr) ? 8 bits 8 channels (timer0 -7 : 16 - bit x 4 configuration available by us ing timer0 - 1 or timer2 - 3, timer4 -5 , timer6 -7) ? selection of one shot timer mode is possible ? e xternal clock can be selected as timer clock . ? function timer s (ftm) ? 16- bit 4 channels ? equipped with the timer/capture/pwm functions using a 16 - bit cou nte r ? an event trigger (external pin input interrupt or timer interrupt request) can control start/stop/clear of the timer (however , th e minimum pulse width of pin input is timer clock 3 ) ? 1 to 64 dividing of lscl k/osclk/h s clk/external input selectable as timer clock ? two types of pwm with the same period and different duties and complementary pwm with the dead time set can b e o utput . ? real time clock (rtc) ? 1 channels (99 years calend a r, al a rm, revision of the clock) ? watchdog timer (wdt) ? non - maskable interrupt and reset ? free running ? overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s when lsclk = 32.768 khz) ? synchronous serial port (ssiof/ssio) ? without fifos (ssio) : 1 channel ? with 16- byte transmits and receives fifos (s siof) : 1 channel ? master/slave selectable ? lsb first/msb first selectable ? clock polarity (data out at rising edge and data in at falling edge/data out at falling edge and data in at rising edge) selectable ? 8- bit length/16 - bit length selectable ? in itial clock level (high start/low start) selectable ? supports slave - select signal (only ssiof) ? uart (uartf/uart) ? without fifos (uart) : 1channel ? with 16- byte transmits and receives fifos (uartf) :1 channels ? full duplex buffer system ? communicati on speed: settable within the range of 2400bps to 115200bps . ? programmable interface ( data length , parity , stop bits selectable ) ? i 2 c bus interface (i 2 c f/ i 2 c) ? without fifos(i 2 c) :1 channel ? with 16- byte transmits and receives fifos ( i 2 cf ) : 1 ch anne ls ? master/slave function (only i2cf) ? fast mode (400 k hz ), standard mode (100 k hz ) ? usb full - speed device ? compliant with universal serial bus (usb) ? full speed (12 mbps) 1 port. ? end points: 5 or 6 ? supports all data transfer types (control trans fer, bulk transfer, interrupt transfer, isochronous transfer). ? built - in sof generation and crc5/16 generation functions ? access size to data transfer fifos: 8 bits/16 bits/32 bits ? general - purpose ports (port) ? input/output port 38 channels (includ ing secondary or tertiary or q uaternary or q uinary functions) . ( ml6 3 0q4 64 and ml630q466 : including lcd com /seg ports ( each 20 ports ))
fed l6 3 0q 464 - 01 ml6 3 0 q464/q466 3/ 37 ? rc oscillation type a/d converter (rc - adc) ? time division 2 channels ? starting by trigger of timer/ftm function . ? 24- bit counter ? successive approximation type a/d converter (sa - adc) ? input 12 channels ? 12- bit a/d converter ? starting by trigger of timer/ftm function. ? capacitive touch sense function ? analog comparator (cmp) ? input 2ch ? common mode i nput voltage: 0.2v to v dd 0.2 v ? input offset voltage: 30mv(max) ? interrupt allow edge selection and sampling selection ? voltage level supervisor (vls) ? threshold voltages: one of 64 levels ? acuraccy: 3% ? interrupt or reset generation are slectable ? voltage measurement wit h voltage input pin or v dd pin ? low level detector(lld) ? judgment voltage: 1.8v 0.2v ? can be used as low level detection reset. ? lcd driver ? maximun 400 dots (50 segment x 8 common) ? 1/ 1 to 1/ 8 duty ? 1/2, 1/3 bias (built - in bias generation circu it) ? frame frequency selecable ? bias voltage multiplying clock selectable ( 5 types) ? contrast adjustment (32 steps) ? 4 operating mode: lcd drive stop, lcd display, all lcds on, all lcds off ? programmable display allocation function ? random number ge nerator (random) ? generates 8 - bit random numbers ? aes ? 128- bit common key ? supports key sizes of 128, 192, and 256 bits ? supports ecb, cbc, and ctr modes ? reset ? reset by the reset_n pin input ? reset by power - on detection ? reset by overflow of w atchdog timer (wdt) ? reset by threshold detection in voltage leve l supervisor(vls) ? reset by low level detection in low level detector(lld) ? reset by the low - speed crystal oscillation stop detection ? reset by sysresetreq of cortex tm - m0 + (software rese t)
fed l6 3 0q 464 - 01 ml6 3 0 q464/q466 4/ 37 ? clock ? l ow-s peed clock: ? crystal oscillation ( 32.768 khz) ? built - in rc oscillation (32.768khz) ? high - speed clock: ? pll ( 24 mhz) generated from crystal oscillation ( 32.768 khz) ? built - in rc oscillation (16mhz) ? power management ? halt mode: instruction execution by cpu is suspended . all peripheral circuits can keep in operating states. ? halt -h mode: instruction execution by cpu is suspended . stop of high - speed oscillation auto matically. all peripheral circuits can keep in operating states. ? deep - halt mode: instruction execution by cpu is suspended . some peripheral circuits(timer, ltbc etc.) can keep in operating states. ? ultra - deep - halt mode: instruction execution by cpu is s uspended . some peripheral circuits(timer, ltbc etc.) can keep in operating states, at v dd >2.5v . ? stop mode: stop of low - speed oscillation and high - speed oscillation (operations of cpu and peripheral circuits are stopped.) ? clock gear: the frequency of hi gh - speed system clock can be changed by software (1/1, 1/2, 1/4, 1/8 ,1/16,1/32 of the oscillation clock) ? block control function: power down (reset registers and stop clock supply) the circuits of unused peripherals. ? guaranteed operating range ? operat ing temperature (ambient) : ? 40 c to +85 c ? operating voltage: v dd = 1. 8 v to 3.6 v ? supply current (typ) ? high - speed operation ( 24 mhz) : 250ua/mhz ? ultra - deep - halt : 0. 80 ua package ? 100- pin plastic tqfp ? tray ml630q464- xxxtbzwa x ml6 30q466 - xxxtbzwa x
fed l6 3 0q 464 - 01 ml6 3 0 q464/q466 5/ 37 block diagram ml6 3 0q 4 64/q 4 66 block diagram figure 1 . ml6 3 0q 4 64/q 4 66 block diagram program memory (flash) 64k/128kb ssio 1 ssiof 1 sck0 sin0 sout0 rxd0 txd 0 i 2 c 1 i 2 cf 1 sda 1 scl 1 int 2 ram 8k/16 k b cpu ( cortex - m0+ ) l tbc int 1 wdt int 8 t 8 t t p o p p3 p3 p3 p p p tot rt o t t p r r r t rt r r rt rt p t t pp ot tot t pp p r p p p p t r t 3o rt p p 3 o o 3 o rt rt t t p t t p t t t t pt t t t t t r
fed l6 3 0q 464 - 01 ml6 3 0 q464/q466 6/ 37 pin configuration f igure 2 . pin layout of ml6 30 q4 64 /q4 66
fed l6 3 0q 464 - 01 ml6 3 0 q464/q466 7/ 37 pin list pin no. . reset state primary function secondary function tertiary function quaternary function quinary function pin name i/o pin name i/o pin name i/o pin name i/o pin name i/o 14 68 79 C v ss C C C C C C C C C 65 81 C v dd C C C C C C C C C 80 C v ddl C C C C C C C C C 70 C v hf C C C C C C C C C 90 C v ref C C C C C C C C C 74 C xt0 C C C C C C C C C 73 C xt1 C C C C C C C C C 78 pull - up input reset_n i C C C C C C C C 77 pull - up input swc i C C C C C C C C 76 pull - up input swd i/o C C C C C C C C 75 pull - down input brmp i C C C C C C C C 95 hi -z output p00/ exi00/ ain8 i/o in0 i sout0 o rxd f0 i C C 96 hi -z output p01/ exi01/ ain9 i/o cs0 o sin0 i txd f0 o C C 97 hi -z output p02/ exi02/ ain10 i/o rct0 o sck0 i/o tmout0 o C C 98 hi -z output p03/ exi03/ a in11 i/o rs0 o C C tmout1 o C C 99 hi - z output p04/ exi04 i/o rt0 o C C C C C C 100 hi - z output p05/ exi05 i/o rcm o C C C C C C 91 hi -z output p20/ exi20/ ain4 i/o in1 i soutf0 o C C C C 92 hi -z output p21/ exi21/ ain5 i/o cs1 o sinf0 i C C C C 93 hi -z output p22/ exi22/ ain6 i/o rs1 o sckf0 i/o tmout2 o C C 94 hi -z output p23/ exi23/ ain7 i/o rt1 o ssf0 i/o tmout3 o C C 82 hi -z output p30/ exi30/ cmp0p v vlsp i/o sda f0 i/o sout0 o C C C C 83 hi -z output p31/ exi31/ cmp0m i/o scl f0 i/o sin0 i C C C C 84 hi -z output p32/ exi32/ cmp1p / ain2 i/o rxdf 0 i sck0 i/o tmout4 o C C 85 hi -z output p33/ exi33/ cmp1m / ain3 i/o txdf 0 o 32kclko o tmout5 o C C 86 hi -z output p34/ exi34/ ain0 led i/o sda1 i/o soutf0 o C C C C 87 hi -z output p35/ exi35/ ain1 led i /o scl1 o sinf0 i C C C C 88 hi -z output p36/ exi36/ tmcki4 i/o rxd 0 i sckf0 i/o tmout6 o C C 89 hi -z output p37/ exi37/ tmcki 5 i/o txd 0 o ssf0 i/o tmout7 o C C 13 to 10 low level o utput com0 to com3 o C C C C C C C C 9 hi - z output p 6 0/ exi 6 0 i/o c om4 o C C C C C C 8 hi - z output p 6 1/ exi 6 1 i/o c om5 o C C C C C C 7 hi - z output p 6 2/ exi 6 2 i/o c om6 o C C C C C C 6 hi - z output p 6 3/ exi 6 3 i/o c om7 o C C C C C C 15 to 48 low level o utput seg0 to seg 33 o C C C C C C C C 49 hi -z output p40/ exi40/ led i/o sda f0 i/o sout0 o C C seg34 o
fed l6 3 0q 464 - 01 ml6 3 0 q464/q466 8/ 37 pin no. . reset state primary function secondary function tertiary function quaternary function quinary function pin name i/o pin name i/o pin name i/o pin name i/o pin name i/o 50 hi -z output p41/ exi41/ led i/o scl f0 i/o sin0 i C C seg35 o 51 hi -z output p42/ exi42/ tmcki0 i/o rxd f0 i sck0 i/o tmout8 o seg36 o 52 hi -z output p43/ exi43/ tmcki1 i/o txd f0 o 32kclko o tmout9 o seg37 o 53 hi - z outpu t p44/ exi44 i/o sda1 i/o soutf0 o C C seg38 o 54 hi - z output p45/ exi45 i/o scl1 o sinf0 i C C seg39 o 55 hi -z output p46/ exi46/ tmcki2 i/o rxd0 i sckf0 i/o tmouta o seg40 o 56 hi -z output p47/ exi47/ tmcki3 i/o txd0 o ssf0 i/o tmoutb o seg41 o 57 hi - z output p50/ exi50 i/o sda f0 i/o sout0 o C C seg42 o 58 hi - z output p51/ exi51 i/o scl f0 i/o sin0 i C C seg43 o 59 hi - z output p52/ exi52 i/o rxd f0 i sck0 i/o tmoutc o seg44 o 60 hi -z output p53/ exi53 i/o txd f0 o 32kclko o tmoutd o seg45 o 61 hi -z output p54/ exi54 i/o sda1 i/o soutf0 o C C seg46 o 62 hi - z output p55/ exi55 i/o scl1 o sinf0 i C C seg47 o 63 hi -z output p56/ exi56/ tmcki6 i/o rxd0 i sckf0 i/o tmoute o seg48 o 64 hi -z output p57/ exi57/ tmcki7 i/o txd0 o ssf0 i/o tmoutf o seg49 o 66 hi - z out put dp i/o C C C C C C C C 67 hi - z output dm i/o C C C C C C C C 69 low output puctl o C C C C C C C C 3 C v l1 C C C C C C C C C 4 C v l2 C C C C C C C C C 5 C v l3 C C C C C C C C C 1 C c 1 C C C C C C C C C 2 C c 2 C C C C C C C C C 71 C c h1 C C C C C C C C C 72 C c h2 C C C C C C C C C
fed l6 3 0q 464 - 01 ml6 3 0 q464/q466 9/ 37 pin description in the table below indicates the functional pin description. the pin name represents the function pin name of the primary function of each terminal, the pin mode represents the set of mode register of port control. (1 st :primary function, 2 nd :secondary function, 3 rd : tertiary function, 4 th : quaternary function, 5 th :quinary function) pin name i/o description lsi pin name p in mode logic system reset_n i reset input pin. when this pin is se t to a l level, system reset mode is set and the internal section is initialized. when this pin is set to a h level subsequently, program execution starts. a pull - up resistor is internally connected. reset_n C l brmp i remapping control input (for fir mware update) based on the brmp pin setting at the time of the reset release, bank0 is remapped. brmp C h xt0 i crystal connection pin for low - speed clock. capacitors c dl and c gl are connected across this pin and v ss as required. xt0 C C xt1 o xt1 C C 32kclko o low - speed clock output pin p33,p43,p53 2 nd general - purpose input/output port p00 - p05 i/o general - purpose input/output port. p00 - p05 1 st C p20 - p23 i/o general - purpose input/output port. p20 - p23 1 st C p30 - p37 i/o general - purpose input/outpu t port. p30 - p37 1 st C p40 - p47 i/o general - purpose input/output port. p40 - p47 1 st C p50 - p57 i/o general - purpose input/output port. p50 - p57 1 st C p 6 0 - p 63 i/o general - purpose input/output port. p 6 0 - p 63 1 st C external interrupt exi00 -05 exi20 -23 exi30 -37 exi40 -47 exi50 -57 exi60 - 63 i external maskable interrupt input pins. it is possible, for each bit, to specify whether the interrupt is enabled and select the interrupt edge by software. p00-p05 p20-p23 p30-p37 p40-p47 p50-p57 p 6 0 - p 63 1 st h/l led led o n - channel open drain output pins to drive led. p 34 ,p 35 ,p40,p41 1 st C uart txd 0 o uart data output pin. p37 , p47, p5 7 2 nd C rxd 0 i uart data input pin. p3 6 , p46, p5 6 2 nd C txd f0 o uart f with fifo data output pin. p 0 1,p3 3,p43 ,p5 3 2 nd C rxd f0 i uart f with fi fo data input pin. p00,p32,p42 ,p5 2 2 nd C i 2 c bus interface sda 1 i/o i2c 1 data input/output pin. this pin has an nmos open drain output. when using this pin as a function of the i 2 c, externally connect a pull - up resistor. p34,p44,p54 2 nd C scl 1 o i2c 1 cl ock output pin. this pin has an nmos open drain output. when using this pin as a function of the i 2 c, externally connect a pull - up resistor. p35,p45,p55 2 nd C sda f0 i/o i2c f0 data input/output pin. this pin has an nmos open drain output. when using this pin as a function of the i 2 c, externally connect a pull - up resistor. p3 0,p40 ,p5 0 2 nd C scl f0 i/o i2c f0 clock input/ output pin. this pin has an nmos open drain output. when using this pin as a function of the i 2 c, externally connect a pull - up resistor. p31, p41 ,p5 1 2 nd C
fed l6 3 0q 464 - 01 ml6 3 0 q464/q466 10 / 37 pin name i/o description lsi pin name p in mode logic synchronous serial sck0 i/o synchronous serial (ssio) clock input/output pin. p02,p32,p42,p52 3 rd C sin0 i synchronous serial (ssio) data input pin. p01,p31,p41,p51 3 rd C sout0 o s ynchronous serial (ssio) data output pin. p00,p30,p40,p50 3 rd C sck f0 i/o synchronous serial with fifo (ssiof) clock input/output pin. p22,p36,p46,p56 3 rd C sin f0 i synchronous serial with fifo (ssiof) data input pin. p21,p35,p45,p55 3 rd C sout f0 o s ynchronous serial with fifo (ssiof) data output pin. p20,p34,p44,p54 3 rd C ssf0 i/ o synchronous serial with fifo (ssiof) select input/ output pin. p23,p37,p47,p57 3 rd l ftm tmout0 - 9 tmouta -f o ftm output pin. p02,p03,p22,p23 p32,p33,p36,p37 p42,p43 ,p 46,p 47 p52,p53,p56,p57 4 th C tmcki 0 - 7 i external clock input pin for ftm. p42,p43,p46,p47 p 36 ,p 37 ,p56,p57 1 st C rc oscillation type a/d converter in0 i os cillation input pin of channel 0 . p00 2 nd C cs0 o reference capacitor connection pin of channel 0 . p01 2 nd C rs0 o reference resistor connection pin of channel 0 . p03 2 nd C rt0 o resistor sensor connection pin for measurement of channel 0 . p04 2 nd C rc t0 o resistor/capacitor sensor connection pin of channel 0 for measurement. p02 2 nd C rcm o rc o scillation monitor pin. p05 2 nd C in1 i oscillation input pin of channel 1. p20 2 nd C cs1 o reference capacitor connection pin of channel 1. p21 2 nd C rs1 o reference resistor connection pin of channel 1. p22 2 nd C rt1 o resistor sensor connection p in for measurement of channel 1. p23 2 nd C successive approximation type a/d converter v ref i reference power supply pin for successive approximation type a/d converter. v ref C C ain0 -11 i a nalog input for successive approximation type a/d converter. (ain0 - 3) p3 2 - 3 5 , (ain4- 7) p20 - 23, (ain8 - 11) p00 - 03 1 st C analog comparator cmp0p i comparator0 non - inverted input pin. p30 1 st C cmp0m i comparator0 inverted input pin. p31 1 st C cmp1p i comparator1 non - inverted input pin. p32 1 st C cmp1m i comparat or1 inverted input pin. p33 1 st C usb fs device dp i/o usb dev d + pin . dp C C dm i/o usb dev d - pin . dm C C puctl o usb dev pull - up control puctl C C debug interface swc i serial clock of serial wire debug port swc C C swd i/o serial i/o data of s erial wire debug port swd C C
fed l6 3 0q 464 - 01 ml6 3 0 q464/q466 11 / 37 pin name i/o description lsi pin name p in mode logic power supply v ss C negative power supply pin. v ss C C v dd C positive power supply pin. v dd C C v ddl C positive power supply pin (internally generated) for internal logic. capacitors c l is connected between this pin and v ss . v ddl C C v hf C positive power supply pin (internally generated) for built - in halver circuit . capacitor c vh is connected between this pin and v ss . v hf C C c h1 C c h2 C capacitor pins of built - in ha lver circuit c h1 C c h2 C C lcd driver com0 C com3 C common pins of lcd driver com0 C com3 C C com4 C com7 C common pins of lcd driver p60-p63 2 nd C seg0 C seg33 C segment pins of lcd driver seg0 C seg33 C C seg34 C seg49 C segment pins of lcd driver p 40 - p47 p50 - p57 5 th C c 1 C c 2 C capacitor pins of built - in generation bias circuit c 1 C c 2 C C v l1 C v l3 C reference voltage input pins of built - in bias generation circuit v l1 C v l3 C C
fed l6 3 0q 464 - 01 ml6 3 0 q464/q466 12 / 37 termination of unused pins table 1 shows methods of terminating the unused pins. table 1 termination of unused pins pin recommended pin termination reset_n open brmp connect a pull - down resistor. swc connect a pull - up resistor. swd connect a pull - up resistor. v ref connect to v dd p00 to p0 5 open p20 to p2 3 open p 3 0 to p 37 open p40 to p4 7 open p50 to p57 o pen p 6 0 to p 63 o pen com0 to com3 o pen seg0 to seg33 o pen dp, dm, puctl open v l1 , v l2 , v l3 o pen c 1 , c 2 o pen [ n ote ] for unused input ports or unused input/output ports, if the corresponding pins are configured as high - impedance inputs and left open, the supply current may become excessively large. therefore, it is recommended to configure those pins as either inputs with a pull - down resistor/pull - up resistor or outputs.
fed l6 3 0q 464 - 01 ml6 3 0 q464/q466 13 / 37 electrical characteristics absol ute maximum ratings v ss = 0v parameter symbol condition rating unit power supply voltage 1 v dd ta=25 c - 0.3 to + 4.6 v power supply voltage 2 v ddl ta=25 c - 0.3 to + 2.0 v power supply voltage 3 v l1 -3 ta=25 c - 0.3 to +6.0 v input voltage (p00 - p05, p20 - p23 , p30 - p3 5, swc, swd, brmp, reset_n, dp, dm ) v in ta=25 c - 0.3 to v dd +0.3 v input voltage (5 v tolerant) (p36, p37, p40 - p47, p50 - p57, p60 - p63) v in t ta=25 c - 0.3 to +6.0 v output voltage 1 v out 1 ta=25 c - 0.3 to v dd +0.3 v output voltage 2 (com0 to com7 seg 0 to seg49) v out2 ta=25 c - 0.3 to v l1 -3 +0.3 v output current 1 i out1 ta=25 c -12 to +11 ma output current 2 i out 2 ta=25 c -12 to + 20 ma power dissipation pd ta=25 c 0.9 w storage temperature t stg C -55 to + 150 c
fed l6 3 0q 464 - 01 ml6 3 0 q464/q466 14 / 37 recommended operating conditions v ss = 0v parameter symbol condition range unit operating temperature (ambience) t op C -40 to +85 c operating voltage v dd C 1. 8 to 3.6 v reference voltage v ref C 1.8 to v dd v operating frequency (cpu) f op C lsclk:32.768k hsclk:500k to 24m hz low spee d crystal oscillation frequency f xtl C 32.768k hz low speed crystal oscillation external capacitor 1 c dl using vt - 200- fl(from sii 6.8 to 12 pf c gl 6.8 to 12 low speed crystal oscillation external capacitor 2 c dl using dt - 26(from daishinku) 12 to 16 pf c gl 12 to 16 low speed crystal *1 oscillation external capacitor 3 c dl using vt - 200- f(from sii 12 to 22 pf c gl 12 to 22 v ddl external capacitor *2 c l esr Q 500m 2.2 30% f v l1,2,3 pin external capacitor c a,b,c C 1.0 30% f c 1 - c 2 externa l capacitor c 12 C 1.0 30% f c h1 , c h2 external capacitor c h12 C 1 .0 30% f v hf external capacitor c hf C 1 .0 30% f *1 : please use this crystal except deephalt mode because this lsi may not be functioning at deephalt mode with the crystal. pleas e evaluate the matching when other crystal oscillator/ceramic oscillator is used. *2 please evaluate on users conditions, put on c l0 ( = 0.1uf) if necessary.
fed l6 3 0q 464 - 01 ml6 3 0 q464/q466 15 / 37 operating conditions of flash memory v ss = 0v parameter symbol c o ndition range unit operatin g temperature (ambience) t op data area : write/erase -40 to + 85 c program area : write/erase 0 to + 40 c operating voltage write time v dd w rite/erase 1.8 to 3.6 v c epd d ata area (1,024b x 2) 10,000 times c epp program area 100 times e rase unit C block erase p rogram area 8 kb data area 2 sector erase 1 kb erase time(maximum) C block erase/sector erase 100 ms write unit C C 1 word ( 4 byte ) C
fed l6 3 0q 464 - 01 ml6 3 0 q464/q466 16 / 37 ac characteristics (oscillation, reset) *1 : mean value of 1024 cycle. *2 : guarantee value at the time of the shipment. *3 : except deephalt mode and ultra - deephalt mode. (v dd =1.8 to 3.6v, v ss =0v, ta= - 40 to +85 c , unless other wise specified) parameter symbol condition rating unit m easuring circuit min. typ. max. low speed crystal oscillation start time t xt l C C C 2 s 1 low speed built - in rc oscillation frequency *1*2*3 f lcr ta=25 c t yp - 1.5% 32.768 t yp +1.5% k hz ta= -40 to 85 c typ -5% 32.768 typ+5% h igh speed build - in rc oscillation frequency *1*2 f hcr ta=25 c typ -1% 16 typ +1% mhz ta= -40 to 85 c typ -5% 16 typ +5% pll frequency f pll f xtl = 32.768khz typ - 0.2 5% 24 typ + 0.2 5% mhz low speed crystal oscillation stop detection time t stop C C 600 C s r eset pulse width p rst C 200 C C s reset noise elimination pulse width p nrst C C C 0. 3 s power - on reset activation power rise time t por C C C 10 ms p rst reset_n external reset sequence v dd 0.9* v dd 0.3* v dd v dd 0.9* v dd 0.1* v dd t por power on reset sequence p rst 0.3* v dd 0.3* v dd
fed l6 3 0q 464 - 01 ml6 3 0 q464/q466 17 / 37 dc characteristics (idd) (v dd =1.8 to 3.6v, v ss =0v, ta= - 40 to +85 c , unless otherwise specified) parameter symbol c ondition rating *1 unit m easuri ng c ircuit min. typ. max. power consumption 1 idd1 cpu is stopped low/high - speed oscillation is stopped ta=25 c C 0.70 2.5 a 1 ta= - 40 to 85 c C C 28 power consumption 2 idd2 -1 ultra - deep - halt mode * 3 * 4 (lbtc function) low - speed crystal oscillating (32.768khz) high - speed oscillation is stopped. 2.5v Qv dd ta=25 c C 0.80 2. 5 a ta= - 40 to 85 c C C 20 idd2 -2 deep - ha lt mode * 3 * 4 (lbtc function) low - speed crystal oscillating (32.768khz) high - speed oscillation is stopped. ta=25 c C 1.30 . 3.0 a ta= - 40 to 85 c C C 28 power consumption 3 idd3 halt mode * 3 * 4 ( ltbc function ) low - speed crystal oscillating (32.768khz) high speed oscillation is stopped. ta=25 c C 2.2 5 .0 a ta= - 40 to 85 c C C 32 power consumption 4 idd4 cpu low - speed * 2 * 4 low - speed crystal oscillating high speed oscillation is stopped. ta=25 c C 9.0 14 a ta= - 40 to 85 c C C 45 power con sumption 5 idd5 cpu high - speed(16mhz) * 2 * 4 high - speed buil t- in rc oscillating ta=25 c C 3.8 5.0 ma ta= - 40 to 85 c C C 5.5 power consumption 5 idd5 cpu high - speed(24 mhz) * 2 * 4 high - speed pll oscillating ta=25 c C 6.0 7.0 ma ta= - 40 to 85 c C C 7. 5 * 1 typ.rating is v dd =3.0v * 2 at cpu activity rate =100% no halt state * 3 : using 32.768khz crystal oscillator vt -200- fl (from sii)(c gl /c dl 12pf) using 32.768khz crystal oscillator dt - 26(from daishinku)(c gl /c dl 12pf * 4 : clkcon valid bits are 0 , rstco n valid bits are 1
fed l6 3 0q 464 - 01 ml6 3 0 q464/q466 18 / 37 dc characteristics (vls) (v dd =1.8 to 3.6v, v ss =0v, ta= - 40 to +85 c , unless otherwise specified) parameter symbol condition rating unit measuring circuit min. typ. max. vls judge voltage (v dd =fall) v vls vlslv[5:0] = 00h *1 t yp. -3% 1.200 typ. +3% v 1 vlslv[5:0] = 01h *1 1.225 vlslv[5:0] = 02h *1 1.250 vlslv[5:0] = 03h *1 1.275 vlslv[5:0] = 04h *1 1.300 vlslv[5:0] = 05h *1 1.325 vlslv[5:0] = 06h *1 1.350 vlslv[5:0] = 07h *1 1.375 vlslv[5:0] = 08h *1 1.400 vlslv[5:0] = 09h *1 1.425 vlslv[5:0] = 0ah *1 1.450 vlslv[5:0] = 0bh *1 1.475 vlslv[5:0] = 0ch *1 1.500 vlslv[5:0] = 0dh *1 1.525 vlslv[5:0] = 0eh *1 1.550 vlslv[5:0] = 0fh *1 1.575 vlslv[5:0] = 10h *1 1.600 vlslv[5:0] = 11h *1 1.625 vlslv[5:0] = 12h *1 1.650 vlslv[5:0] = 13h *1 1.675 vlslv[5:0] = 14h *1 1.700 vlslv[5:0] = 15h *1 1.725 vlslv[5:0] = 16h *1 1.750 vlslv[5:0] = 17h *1 1.775 vlslv[5:0] = 18h 1.800 vlslv[5:0] = 19h 1.825 vlslv[5:0] = 1ah 1.850 vlslv[5:0] = 1bh 1.875 vlslv[5:0] = 1ch 1.900 vlslv[5:0] = 1dh 1.925 vlslv[5:0] = 1eh 1.950 vlslv[5:0] = 1fh 1.975 vlslv[5:0] = 20h 2.000 vlslv[5:0] = 21h 2.050 vlslv[5:0] = 22h 2.100 vlslv[5:0] = 23h 2.150 vlslv[5:0] = 24h 2.200 vlslv[5:0] = 25h 2.250 vlslv[5:0] = 26h 2.300 vlslv[5:0] = 27h 2.350 vlslv[5:0] = 28h 2.400 vl slv[5:0] = 29h 2.450 vlslv[5:0] = 2ah 2.500 vlslv[5:0] = 2bh 2.550 vlslv[5:0] = 2ch 2.600
fed l6 3 0q 464 - 01 ml6 3 0 q464/q466 19 / 37 vlslv[5:0] = 2dh typ. -3% 2.650 typ. +3% v 1 vlslv[5:0] = 2eh 2.700 vlslv[5:0] = 2fh 2.750 vlslv[5:0] =30h 2.800 v lslv[5:0] = 31h 2.850 vlslv[5:0] = 32h 2.900 vlslv[5:0] = 33h 2.950 vlslv[5:0] = 34h 3.000 vlslv[5:0] = 35h 3.050 vlslv[5:0] = 36h 3.100 vlslv[5:0] = 37h 3.150 vlslv[5:0] = 38h 3.200 vlslv[5:0] = 39h 3.250 vlslv[5:0] = 3ah 3.300 vlslv[5:0] = 3bh 3.350 vlslv[5:0] = 3ch 3.400 vlslv[5:0] = 3dh 3.450 vlslv[5:0] = 3eh 3.500 vlslv[5:0] = 3fh 3.550 v vls hysteresis width (v dd =rise) h vls C v vls x 1.0% v vls x 2.7% v vls x 4.5% v vlslv [3:0] are bits of the vlscon register to change detection voltage level. *1 : setable only at the time of se lect to v v lsp pin . d c characteristics (lld) (v dd =1.8 to 3.6v, v ss =0v, ta= - 40 to +85 c , unless otherwise specified) parameter s ymbol condition rating unit measuring circuit min. typ. max. lld judge voltage vllr C 1. 6 0 1. 8 0 2.0 0 v 1 d c/ac characteristics (analog comp a rator) ( v dd =1.8 to 3.6v, v ss =0v, ta= - 40 to +85 c , unless otherwise specified) p arameter symbol c ondi tion r ating u nit measuring circuit min. typ. max. common input voltage range v cmp in C 0.2 C v dd - 0.2 v 1 i nput offset voltage v cmpof C -30 C 30 mv comparator judge time t cmp cmpp - cmp m =4 0mv C C 2 s
fed l6 3 0q 464 - 01 ml6 3 0 q464/q466 20 / 37 dc characteristics (lcd drive r) ( v dd =1.8 to 3.6v, v ss =0v, ta= - 40 to +85 c , unless otherwise specified) parameter symbol condition rating unit measuring circuit min. typ. max. v l1 voltage v l1 v dd = 3.0v , tj = 25 c lcn [4:0] = 00h * 2 0.89 0.94 0.99 v 1 lcn [4:0] = 01h * 2 0.91 0.96 1.01 lcn [4:0] = 02h * 2 0.93 0.98 1.03 lcn [4:0] = 03h * 2 0.95 1.00 1.05 lcn [4:0] = 04h * 2 0.97 1.02 1.07 lcn [4:0] = 05h * 2 0.99 1.04 1.09 lcn [4:0] = 06h * 2 1.01 1.06 1.11 lcn [4:0] = 07h * 2 1.03 1.08 1.13 lcn [4:0] = 08h * 2 1.05 1.10 1.15 lcn [4:0] = 09h * 2 1.07 1.12 1.17 lcn [4:0] = 0ah * 2 1.09 1.14 1.19 lcn [4:0] = 0bh * 2 1.11 1.16 1.21 lcn [4:0] = 0ch * 2 1.13 1.18 1.23 lcn [4:0] = 0dh * 2 1.15 1.20 1.25 lcn [4 :0] = 0eh * 2 1.17 1.22 1.27 lcn [4:0] = 0fh * 2 1.19 1.24 1.29 lcn [4:0] = 10h 1.21 1.26 1.31 lcn [4:0] = 11h 1.23 1.28 1.33 lcn [4:0] = 12h 1.25 1.30 1.35 lcn [4:0] = 13h 1.27 1.32 1.37 lcn [4:0] = 14h 1.29 1.34 1.39 lcn [4 :0] = 15h 1.31 1.36 1.41 lcn [4:0] = 16h 1.33 1.38 1.43 lcn [4:0] = 17h 1.35 1.40 1.45 lcn [4:0] = 18h 1.37 1.42 1.47 lcn [4:0] = 19h 1.39 1.44 1.49 lcn [4:0] = 1ah 1.41 1.46 1.51 lcn [4:0] = 1bh 1.43 1.48 1.53 lcn [4:0] = 1ch 1.45 1.50 1.55 lcn [4:0] = 1dh 1.47 1.52 1.57 lcn [4:0] = 1eh 1.49 1.54 1.59 lcn [4:0] = 1fh 1.51 1.56 1.61 v l1 temperature deviation* 1 ? v l1 v dd = 3.0v C ? 0.06 C %/c v l1 voltage dependency* 1 ? v l1 v dd = 1.8 to 3. 6v C 5 20 mv/v v l2 voltage v l2 v dd = 3.0v , tj = 25 c 1m ? load ( v l3 ? v ss ) typ. ? 2 typ. +4% v v l3 voltage v l3 typ. ? 10% v l1 3 typ. +4% lcd bias voltage generation time t bias C C C 600 ms * 1 : v l1 can not exceed v dd level. the maximum v l1 becomes v dd level when the v l1 calculated by the temperature deviation and voltage dependency is going to exceed the v dd level. * 2 : 1/3 bias only.
fed l6 3 0q 464 - 01 ml6 3 0 q464/q466 21 / 37 dc characteristics (vohl, iohl) (v dd =1.8 to 3.6v, v ss =0v, ta= - 40 to +85 c , unless otherwise specified) parameter symbol conditio n rating unit measuring circuit min. typ. max. output voltage 1 ( p00 - p05, p20- p23, p30- p37, p40 - p47, p50- p57,, p60 - p63, swd,puctl) voh1 ioh= -1 .0 ma v dd - 0.5 C C v 2 vol1 iol=+0.5ma C C 0.4 output voltage 2 ( p34, p35, p40, p41 ) (led mode is s elected) vol2 2.7v v dd 3.6v iol=+5.0ma C C 0.6 iol=+2.0ma C C 0.4 output voltage 3 (p30, p31, p34, p35, p40, p41, p44, p45, p50, p51, p54, p55 ) (i 2 c mode is selected) vol3 iol3= +3ma (i 2 cspec) (v dd 2v) C C 0.4 output voltage 4 ( p30, p31, p34, p35, p40, p41, p44, p45, p50, p51, p54, p55 ) (i 2 c mode is selected) vol4 iol 4 = +2ma(i 2 cspec) (v dd < 2v) C C v dd 0.2 output voltage 5 (com0 7) (seg00 49) (lcd mode is selected) voh5 1/3bias, ioh 5=- 0. 02ma, vl1=1.2v v l3 - 0.2 C C vom5 1/3bias, i om 5 =+0. 02ma, vl1=1.2v C C v l2 +0.2 vom5s 1/3bias, iom 5s=- 0. 02ma, vl1=1.2v v l2 - 0.2 C C voml5 1/3bias, ioml 5 =+0. 0 2ma, vl1=1.2v C C v l1 +0.2 voml5s 1/3bias, ioml 5s=- 0. 02ma, vl1=1.2v v l1 - 0.2 C C vol5 1/3bias, iol 5 =+0. 0 2ma, vl1=1.2v C C 0.2 output voltage 5 (com0 7) (seg00 49) (lcd mode is selected) voh 5 1/2bias, ioh 5=- 0. 01 ma, vl1=1. 4v v l3 -0. 3 D vom5 1/2bias, iom 5 =+0. 01 ma, vl1=1. 4v v l2 +0. 3 vom5s 1/2bias, iom 5s=- 0.01 ma, vl1=1. 4v v l2 -0. 3 D voml 5 1/2bias, ioml 5 =+0. 01 ma, vl1=1. 4v v l1 +0 . 3 voml 5s 1/2bias, ioml 5s=- 0.01 ma, vl1=1. 4v v l1 -0. 3 D vol 5 1/2bias, iol 5 =+0. 01 ma, vl1=1. 4v 0. 3
fed l6 3 0q 464 - 01 ml6 3 0 q464/q466 22 / 37 output leak 1 ( p00 - p05, p20- p23, p30- p37, p40- p47, p50- p57, p60- p63, swd,puctl ) iooh1 voh=v dd (at high impedance) C C +1 a 3 iool1 vol=v ss (at high impedance) -1 C C
fed l6 3 0q 464 - 01 ml6 3 0 q464/q466 23 / 37 dc characteristics (iihl) (v dd =1.8 to 3.6v, v ss =0v, ta= - 40 to +85 c , unless otherwise specified) parameter symbol condition rating unit measuring circuit min. typ. max. input current 1 (reset_n) iih1 vih1=v dd C C 1 a 4 iil1 vil1=v ss -900 -3 00 - 20 input current 3 (p00 - p05, p20 - p23 , p30 - p37 , p40 - p47, p50 - p57 , p60 - p63, swc, swd , brmp ) iih3 vih3=v dd ( at pull down ) 1 15 200 iil3 vil3=v ss (at pull up ) - 200 -15 -1 iih3z vih3=v dd (at high impedance) C C 1 iil3z vil3=v ss (at high impedance) -1 C C input current 4 (p3 6, p37, p40 - p47, p50 - p57 , p60 - p63 ) iih4z vih4= 5.0v (at high impedance) C C 1 * 1 typ.rating is v dd =3.0v , ta=25 c dc characteristics (vihl) (v dd =1.8 to 3 . 6v, v ss =0v, ta= - 40 to +85 c , u nless otherwise specified) p arameter s ymbol c ondition r ating unit measuring circuit min. typ. max. i nput voltage 1 (reset_n, swd, swc, brmp, p00 - p05, p20 - p23, p30 - p37 , p40 - p47, p50 - p57 , p60 - p63 ) vih1 C 0. 7 v dd C v dd v 5 vil1 C 0 C 0. 3 v dd i nput terminal capacitance (reset_n, swd, swc, brmp, p00 - p05, p20 - p23, p30 - p37 , p40 - p47, p50 - p57 , p60 - p63 ) cin f=10khz v rms =50mv ta=25 c C C 10 pf C
fed l6 3 0q 464 - 01 ml6 3 0 q464/q466 24 / 37 dc characteristics ( usb ) (v dd = 3.0 to 3 . 6v, v ss =0v, ta= - 40 to +85 c , unless otherwise specified) param eter symbol condition rating *1 unit measu ring circuit min. typ. max. differential input sensitivity v di absolute value of the difference between the dp and dm pins 0.2 - - v differential common mode range v cm includes vdi range 0.8 - 2.5 v singl e end input threshold voltage v se - 0.8 - 2.0 v high level output voltage v oh 15 k w rl is connected to gnd 2.8 - - v low level output voltage v ol 1.5 k w rl to 3.6 v - - 0.3 v hi - z state input/output leakage current i lo 0 v < vin < 3.3 v - 10 10 ua driver output resistance z drv steady state 28 44
fed l6 3 0q 464 - 01 ml6 3 0 q464/q466 25 / 37 measuring circuits measuring circuit1 m easuring circuit 2 input pins v v dd v ddl v l1 v l2 v l3 v ss vil output pins ( * 1) input logic circuit to determine the specified measuring conditions. ( *2) measured at the specified output pins. ( * 2) (* 1) vih xt0 xt1 32.768khz crystal a v dd v ddl v c l v l1 c a v l2 c b v l3 c c v ss c2 c1 c 12 c v c dl c gl c v : 1 f c a ,c b ,c c : 1 f c 12 : 1 f c gl : 12pf c dl : 12pf 32.768khz crystal oscilation : ( dt - 26 from daishinku )
fed l6 3 0q 464 - 01 ml6 3 0 q464/q466 26 / 37 m easuring circuit 3 measuring circuit 4 measuring circuit 5 v dd v ddl v l1 v l2 v l3 v ss vih vil input pins outut ins 1 1 inut logi iruit to determine te seified measuring onditions. aeform monitoring l l1 l2 l3 3 measured at te seified outut ins. inut ins out ut ins 3 inut ins l l1 l2 l3 i il outut ins 1 inut logi iruit to determine te seified measuring onditions. 2 measured at te seified outut ins. 2 1
fed l6 3 0q 464 - 01 ml6 3 0 q464/q466 27 / 37 a c characteristics ( usb ) (v dd = 3.0 to 3 . 6v, v ss =0v, ta= - 40 to +85 c , unless otherwise specified) parameter symbol condition rating unit applied pin min. typ. max. rise time (*1) t r cl = 50 pf 4 C 20 ns dp, dm fall time (*1) t f cl = 50 pf 4 C 20 ns output signal crossover voltage v crs cl = 50 pf 0.8 C 2 .5 v data rate t drate average bit rate (12mbps % %
fed l6 3 0q 464 - 01 ml6 3 0 q464/q466 28 / 37 ac charctoristics (synchronous serial port) (v dd =1.8 to 3.6v, v ss =0v, ta= - 40 to +85 c , unless otherwise specified) p arameter s ymbol c onditon r ating unit min. typ. max. sck input cycle (slave mode) t scyc h igh - speed oscillation is not active 10 C C s h igh - speed oscillation is active 500 C C ns sck output cycle (master mode) t scyc C C sck* 1 C s sck input pulse width (slave mode) t sw h igh - speed oscillation is n ot active 4 C C s h igh - speed oscillation is active 200 C C ns sck output pulse width (master mode) t sw C t scyc 0.4 t scyc 0.5 t scyc 0.6 s sout output delay time (slave mode) t sd C C C 180 ns sout output delay time (master mode) t sd C C C 80 ns sin input s etup time (slave mode) t ss C 50 C C ns sin input s etup time ( master mode) t ss C 130 C C ns sin input ho ld time t sh C 50 C C ns * 1 : the clock period which is selected by the below registers(min:250ns@ regu lar ly , min:500ns@p02,p22 is used) in c ase of ssio : s0ck2 - 0 of serial port 0 mode register(sio0mod). in case of ssiof : sf0br9 - 0 of siof0 port register(sf0brr) t sd sck 0/sckf0 ( "0" during transmission/reception ) sin 0/sinf0 sout 0/soutf0 t sd t ss t sh t sw t s cyc t sw sck 0/sckf0 ("1 " during transmission/reception )
fed l6 3 0q 464 - 01 ml6 3 0 q464/q466 29 / 37 ac characteristics i 2 c bus interface : standard mode 100khz (v dd =1.8 to 3.6v, v ss =0v, ta= - 40 to +85 c , unless otherwise specified) p arameter s ymbol c ondition r ating unit min. typ. max. scl clock frequency f scl C 0 C 100 khz scl hold time (star t/restart condition) t hd:sta C 4.0 C C s scl l level time t low C 4.7 C C s scl h level time t high C 4.0 C C s scl setup time (restart condition) t su:sta C 4.7 C C s sda setup time t su:dat C 0.25 C C s sda setup time (stop condition) t su:sto C 4 .0 C C s bus - free time t buf C 4.7 C C s a c characteristics i 2 c bus interface : fast mode 400khz (v dd =1.8 to 3.6v, v ss =0v, ta= - 40 to +85 c , u nless otherwise specified) p arameter s ymbol c ondition r ateing unit min. typ. max. scl clock frequen cy f scl C 0 C 400 khz sclhold time (start/restart condition) t hd:sta C 0.6 C C s scl l level time t low C 1.3 C C s scl h level time t high C 0.6 C C s scl setup time (restart condition) t su:sta C 0.6 C C s sda setup time t su:dat C 0.1 C C s sda setup time (stop condition) t su:sto C 0.6 C C s bus - free time t buf C 1.3 C C s *1 : only at the time of sysclk=16mhz or 24mhz scl sda start condition restart condition s top condition t buf t hd:sta t low t high t su:sta t hd:sta t su:dat t su:sto
fed l6 3 0q 464 - 01 ml6 3 0 q464/q466 30 / 37 ac characteristics (rc - adc) ( v dd =1. 8 to 3.6 v , v ss = 0v , ta = - 4 0 ~ + 85 c , unless otherwise specified ) p arameter s ymbol c ondition r ating unit min. typ. max. r esister for oscillation rs0,rs1,rt0, rt0 - 1,rt1 C 1 C 400 k o scillation freqency v dd = 3.0v cvr=820pf cs=560pf f osc1_0 r esister for oscillation =1k C 528 C khz f osc2_0 r esister for oscillation =10k C 59 C khz f osc3_0 r esister for oscillation =100k C 5.9 C khz rs to rt oscillation frequency ratio * 1 v dd = 3.0v cvr=820pf cs=560pf kf1_0 rt0, rt0 - 1, rt1=1k 8.225 8.94 9.655 C kf2_0 rt0, rt0 - 1, rt1=10k 0.99 1 1.01 C kf3_0 rt0, rt0 - 1, rt1=100k 0.093 0.101 0.109 C * 1 h kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor o n the same conditions. kfx = f oscx (rt0 - cs0 oscillation) f oscx (rt0 - 1 - cs0 oscillation) f oscx (rt1 - cs1 osci llation) f oscx (rs0 - cs0 oscillation) , f oscx (rs0 - cs0 oscillation) , f oscx (rs1 - cs1 oscillation) ( x = 1, 2, 3 ) m easuring circuit note ? please have the shortest layout for the common node (wiring patterns which are connected to the external capacitors, resistor s and in0/in1 pin), including cvr0/cvr1. especially, do not have long wire between in0/in1 and rs0/rs1. the coupling capacitance on the wires may occur incorrect a/d conversion. also, please do not have signals which may be a source of noise around the node. ? when rt0/rt1 (thermistor and etc.) requires long wiring due to the restricted placement, please shield the signal by v ss (gnd) . ? please make wiring to components (capacitor, resisteor and etc.) necessory for objective measurement. wiring to reserved comp onents may affect to the a/d conversion operation by noise the components itself may have . v dd v ddl c l1 c l0 v ss c v rt0, rt0 - 1, rt1: 1k cs0, ct0, cs1: 560pf cvr0, cvr1: 820pf rcm m easure frequency (f oscx ) input pins vih vil (*1) input logi c circuit to determine the specified measuring conditions. rt r rt r r r t r t t rt r rt r r
fed l6 3 0q 464 - 01 ml6 3 0 q464/q466 31 / 37 ac characteristics (low speed clock o utput ) (v dd =1.8 to 3.6v, v ss =0v, ta= - 40~+85 c , unless otherwise specified) parameter s ymbol c ondition r ating u nit min. typ. max. clock output frequency tclk C C 32.768 C khz
fed l6 3 0q 464 - 01 ml6 3 0 q464/q466 32 / 37 e lectrical characteristics of sa - adc (v dd =1.8 to 3.6v, v ss =0v, ta= - 40~+8 5 c , unless otherwise specified) parameter s ymbol c ondition r ating u nit min. typ. max. r esolution n C C 12 C bit integral non - linearity error inl 2.7v ? + ? + ? 10 C + 10 differential non - linearity error dnl 2.7v ? + ? + v ref < 2.2v (using low - speed clock) ? 9 C + 9 zero- scale error v off 2.2v v ref 3.6v ? 6 C + 6 1.8v ? 10 C + 10 full - scale error fse 2.2v v ref d 3.6v 6 C 6 1.8v v ref < 2.2v (using low - speed clock) ? 10 C + 10 i nput impidance ri C C C 5k reference voltage v ref C 1.8 C v dd v c onversion time t conv u sing high - speed clock(max. 4mhz) C 170 C clk using low - speed clock C 16 C measuring circuit a v dd v ss - ri
fed l6 3 0q 464 - 01 ml6 3 0 q464/q466 33 / 37 power - on and shutdown procedures in case of power - on or shutdown of v dd , the procedures and constraints are shown as following. note: if v ddl level is 100mv or more over, reset the ic by reset_n pin after power - on. 0.9* v dd 0.1* v dd t por power down/on and power on reset sequence ( v ss = 0) v dd v ddl ( v ss = 0) 30mv or less 10 0mv or less
fed l6 3 0q 464 - 01 ml6 3 0 q464/q466 34/ 37 application circuit example * : ma k e a decision the parameters after evaluating on u ser s conditions when d esign in g circuits for mass pro duction. c v : 1uf* c l : 2.2uf c l0 : open * c gl , c dl : 12 to 16pf* c a ~c c : 1uf* c 12 : 1uf* c h12 : 1uf* c vh : 1uf* c av : 1uf * rs0, rs1 : 10 k ? cs0, cs1 : 560 pf cvr0, cvr1 : 820 pf rt0, rt1 : thermistor (103at/se mitec) x l : dt - 26, daishinku p30/sdaf0 p35 /led p31 /sclf0 p34 /led p32 (output) led sda vcc scl i 2 c eeprom 0 1 2 c ref t0 t1 l c l c l 32.6 tal ml630q464/ q466 c l c l0 l ss p00/i0 p01/c0 p03/r0 p04/rt0 p02/rct0 c0 r0 rt0 p0/rcm p20/i1 p21/c1 p22/r1 p23/rt1 c1 r1 rt1 p ss l1 l3 l2 c1 c2 reet c f c 1 c 2 c 12 c a c b c c 12 c c 3.3 reet cr0 cr1
fed l6 3 0q 464 - 01 ml6 3 0 q464/q466 35 / 37 package dimensions ml630q464/q466 pack ag e dimensions figure b -1 tqfp 100 n otes for mounting the surface mount type package the surface mount type packages are very susceptible to heat in reflow and humidity absorbed in storage. therefore, before you perform reflow mounting, contact a rohm sales office for the product name, package name, pin number, package code and desired mounting conditions(reflow method, temperature and times).
fed l6 3 0q 464 - 01 ml6 3 0 q464/q466 36 / 37 re vision history document no. date page description previous edition current edition fedl 630 q464-01 oct. 26. 2016 - - final edition
fed l6 3 0q 464 - 01 ml6 3 0 q464/q466 37 / 37 notes 1) the information contained herein is sub ject to change without notice. 2) although lapis semiconductor is continuously working to improve product reliability and quality, semiconductors ca n b reak down and malfunction due to various factors. therefore, in order to prevent personal injury or fire a rising from failure, please take safety measures such as complying with the derating characteristics, implementing redundant and fire prevention designs, and utilizing backups and fail - safe procedures. lapis semiconductor shall have no responsibility for any damages arising out of the use of our products beyond the rating specified by lapis semiconductor. 3) examples of application circuits, circuit constants and any other information contained herein are provided only to illustrat e t he standard usage and op erations of the products.the peripheral conditions must be taken into account when designin g c ircuits for mass production. 4) the technical information specified herein is intended only to show the typical functions of the products and examples of applicatio n circuits for the products. no license, expressly or implied, is granted hereby under any intellectual property rights or other rights of lapis semiconductor or any third party with respect to the information contained in this document; therefore lapis s emiconductor shall have no responsibility whatsoever for any dispute, concerning such rights owned by third parties, arising out of the use of such technical information. 5) the products are intended for use in general electronic equipment (i.e. av/oa device s, communication, consumer systems, gaming/entertainment sets) as well as the applications indicated in this document. 6) the products specified in this document are not designed to be radiation tolerant. 7) for use of our products in applications requiring a high degree of reliability (as exemplified below), please contact and consult with a lapis semiconductor representative: transportation equipment (i.e. cars, ships, trains), primary communication equipment, traffic lights, fire/crime prevention, safety equipment, medical systems, servers, solar cells, and power transmission systems. 8) do not use our products in applications requiring extremely high reliability, such as aerospace equipment, nuclear power control systems, and submarine repeaters. 9) lapis semico nductor shall have no responsibility for any damages or injury arising from non - compliance with the recommended usage conditions and specifications contained herein. 10) lapis semiconductor has used reasonable care to ensure the accuracy of the information co ntained in this document. however, lapis semiconductor does not warrant that such information is error - free and lapis semiconductor shall hav e n o responsibility for any damages arising from any inaccuracy or misprint of such information. 11) please use the products in accordance with any applicable environmental laws and regulations, such as the rohs directive. for more details, including rohs compatibility, please contact a rohm sales office. lapis semiconductor shall have no responsibility for any damages or losses resulting non - compliance with any applicable laws or regulations. 12) when providing our products and technologies contained in this document to other countries, you must abide by the procedures and provisions stipulated in all applicable export laws and regulations, including without limitation the us export administration regulations and the foreign exchange and foreign trade act. 13) this document, in part or in whole, may not be reprinted or reproduced without prior consent of lapis semiconductor. co p yright 2016 lapis semiconductor co., ltd. 2-4- 8 shinyokohama, kouhoku - ku, yokohama 222 - 8575, japan http://www.lapis - semi.com/en/

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