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fn6656 rev 3.00 page 1 of 13 february 28, 2013 fn6656 rev 3.00 february 28, 2013 ISL8009A 1.5a low quiescent current 1.6mhz high efficiency synchronous b uck regulator datasheet the ISL8009A is a high effici ency, monolithic, synchronous step-down dc/dc regulator that can deliver up to 1.5a continuous output current. it is optimized for generating low output voltages down to 0.8v. the supply voltage range of 2.7v to 5.5v allows for the use of single li+cell, three nimh cells or a regulated 5v input. the ISL8009A uses current mode control architecture to deliver very low duty cycle operation at high frequency with fast transient response and excellent loop stability. it has flexible oper ation mode selection of forced pwm mode and automatic pfm/pwm with as low as 17a quiescent current, achieving high power conversion efficiency under light load condition, hence maximizing battery life. high 1.6mhz pulse-width modulation (pwm) switching frequency allows the use of small external components. the ISL8009A integrates a pair of low on-resistance p-channel and n-channel inte rnal mosfets to maximize efficiency and minimize external component count. the 100% duty-cycle operation allows less than 400mv dropout voltage at 1.5a output current. the ISL8009A offers a 2ms power-on-reset (por) timer at power-up. the timer output ca n be reset by rsi. when shutdown, ISL8009A discharges the output capacitor through a 100 ?? resistor. other features include internal digital soft- start, enable for power sequence, overcurrent protection, and thermal shutdown. the ISL8009A is offered in a 2mmx3mm 8 ld dfn package with 1mm maximum height. the complete converter occupies less than 1cm 2 area. features ? high efficiency synchronous buck regulator with up to 95% efficiency ? 2ms reset timer ? 2.7v to 5.5v supply voltage ? 3% output accuracy over-temperature/load/line ? 1.5a guaranteed output current ? 17a quiescent supply current in pfm mode ? selectable forced pwm mode and pfm mode ? less than 1a logic controlled shutdown current ? 90% maximum duty cycle for lowest dropout at 1.5a ? internal current mode compensation ? internal digital soft-start ? peak current limiting, short circuit protection ? over-temperature protection ?enable ? soft discharge disable ? small 8 ld 2mmx3mm dfn ? pb-free (rohs compliant) applications ? dc/dc pol modules ?c/p, fpga and dsp power ? plug-in dc/dc modules for routers and switchers ?portable instruments ? test and measurement systems pin configuration ISL8009A (8 ld dfn) top view 2 3 4 1 7 6 5 8 vin en por skip lx gnd vfb rsi *exposed pad must be connected to the gnd pin*
ISL8009A fn6656 rev 3.00 page 2 of 13 february 28, 2013 ordering information part number (notes 1, 2, 3) part marking temp. range (c) package (pb-free) pkg. dwg. # ISL8009Airz-t 09a -40 to +85 8 ld 2x3 dfn l8.2x3 ISL8009Airz-tk 09a -40 to +85 8 ld 2x3 dfn l8.2x3 ISL8009Airz-t7a 09a -40 to +85 8 ld 2x3 dfn l8.2x3 notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for ISL8009A . for more information on msl please see techbrief tb363 .
ISL8009A fn6656 rev 3.00 page 3 of 13 february 28, 2013 absolute maximum ratings (reference to gnd) thermal information supply voltage (v in ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.5v en, rsi, skip, vfb, por. . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to vin + 0.3v lx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.5v to 6.5v vfb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 2.7v recommended operating conditions vin supply voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7v to 5.5v load current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0a to 1.5a ambient temperature range . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c thermal resistance (typical) ? ja (c/w) ? jc (c/w) 8 ld 2x3 dfn (notes 4, 5) . . . . . . . . . . . 55 5.5 junction temperature range . . . . . . . . . . . . . . . . . . . . . . .-55c to +125c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ? ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 5. for ? jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications typical specifications are measured at the following conditions: t a = +25c, en = vin, rsi = skip = 0v, v in = 5v, l = 2.2h, c 1 = c 2 = 20f, i out = 0a to 1.5a. see ?typical applications? on page 9. parameter symbol test conditions min (note 7) typ max (note 7) units input supply vin undervoltage lockout threshold v uvlo rising - 2.5 2.7 v falling 2.2 2.4 - v quiescent supply current i vin skip = v in , no load at the output - 17 30 a skip = v in , no load at the output and no switches switching, design info only -15- a skip = gnd, no load at the output - 3.7 6 ma shutdown supply current i sd v in = 5.5v, en = low - 0.1 2 a output regulation vfb regulation voltage v vfb 0.784 0.8 0.816 v vfb bias current i vfb vfb = 0.75v - 0.1 - a output voltage accuracy v in = v o + 0.5v to 5.5v, i o = 0a to 1a (note 6) -3 - 3 % line regulation v in = v o + 0.5v to 5.5v (minimal 2.7v) - 0.2 - %/v compensation error amplifier trans-conductance adjusta ble version, design info only - 20 - a/v lx p-channel mosfet on-resistance v in = 5.5v, i o = 200ma - 0.12 0.22 ? v in = 2.7v, i o = 200ma - 0.16 0.27 ? n-channel mosfet on-resistance v in = 5.5v, i o = 200ma - 0.11 0.22 ? v in = 2.7v, i o = 200ma - 0.15 0.27 ? p-channel mosfet peak current limit i pk 1.8 2.1 2.6 a lx maximum duty cycle i o = 1.5a 90 - - ? pwm switching frequency f s 1.35 1.6 1.75 mhz lx minimum on-time skip = low (forced pwm mode) - 70 100 ns soft-start-up time -1.1- ms soft-discharge resistor enable = 0 80 100 120 ?
ISL8009A fn6656 rev 3.00 page 4 of 13 february 28, 2013 pin descriptions vin input supply voltage. connect a 10f ceramic capacitor to power ground. en regulator enable pin. enable the output when driven to high. shutdown the chip and discharge output capacitor when driven to low. do not leave this pin floating. por 2ms timer output. at power-up or en hi, this output is a 2ms delayed power-good signal for the ou tput voltage. this output can be reset by a low rsi signal. 2ms starts when rsi goes to high. skip mode selection pin. connect to lo gic high or input voltage vin for pfm mode; connect to logic low or ground for forced pwm mode. do not leave this pin floating. lx switching node connection. connect to one terminal of inductor. gnd system ground. vfb buck regulator output feedback. connect to the output through a resistor divider for adjustable output voltage (ISL8009A-adj). for preset output voltage, connect this pin to the output. rsi this input resets the 2ms timer. wh en the output voltage is within the pgood window, an internal ti mer is started and generates a por signal 2ms later when rsi is low. a high rsi resets por and rsi high to low transition restarts the internal counter if the output voltage is within the wind ow, otherwise the counter is reset by the output voltage condition. exposed pad the exposed pad must be connected to the gnd pin for proper electrical performance. the exposed pad must also be connected to as much as possible for optimal thermal performance. por output low voltage sinking 1ma, vfb = 0.7v - - 0.3 v delay time -2-ms por pin leakage current por = vin = 3.6v - 0.01 0.1 a minimum supply voltage for valid por signal 1.2 - - v internal pgood low rising threshold percentag e of nominal regulation voltage 89.5 92 94.5 % internal pgood low falling threshold percentage of nominal regulation voltage 85 88 91 % internal pgood high rising threshold percent age of nominal regulation voltage 108 112 114 % internal pgood high falling threshold percent age of nominal regulation voltage 104 107 110 % internal pgood delay time -6.5- s en, skip, rsi logic input low --0.4v logic input high 1.4 - - v logic input leakage current pulled up to 5.5v - 0.1 1 a thermal shutdown - 140 - c thermal shutdown hysteresis -25- c notes: 6. limits established by characteriza tion and are not production tested. 7. parameters with min and/or max limits are 100% tested at +25c , unless otherwise specified. te mperature limits established by characterization and are not production tested. electrical specifications typical specifications are measured at the following conditions: t a = +25c, en = vin, rsi = skip = 0v, v in = 5v, l = 2.2h, c 1 = c 2 = 20f, i out = 0a to 1.5a. see ?typical applications? on page 9. parameter symbol test conditions min (note 7) typ max (note 7) units
ISL8009A fn6656 rev 3.00 page 5 of 13 february 28, 2013 typical operating performance (unless otherwise noted, operating conditions are: t a = +25c, v vin = 5v, en = vin, rsi = skip = 0v, l = 2.2 h, c 1 = 20 f, c 2 = 20 f, i out = 0a ) figure 1. efficiency vs load, v in = 3.3v pwm figure 2. efficiency vs load, v in = 3.3v pfm figure 3. efficiency vs load, v in = 5v pwm figure 4. efficiency vs load, v in = 5v pfm figure 5. v out regulation vs load, v out = 1.2v figure 6. v out regulation vs load, v out = 1.5v 0 10 20 30 40 50 60 70 80 90 100 0.00 0.25 0.50 0.75 1.00 1.25 1.50 output load (a) efficiency (%) 1.5v out - pwm 1.2v out - pwm 1.8v out - pwm 2.5v out - pwm 40 50 60 70 80 90 100 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 output load (a) efficiency (%) 1.5v out - pfm 1.2v out - pfm 1.8v out - pfm 2.5v out - pfm 0 10 20 30 40 50 60 70 80 90 100 0.00 0.25 0.50 0.75 1.00 1.25 1.50 output load (a) efficiency (%) 1.5v out - pwm 1.2v out - pwm 1.8v out - pwm 2.5v out - pwm 3.3v out - pwm 40 50 60 70 80 90 100 0.05 0.15 0.25 0.35 0.45 0.55 0.65 0.75 output load (a) efficiency (%) 1.5v out - pfm 1.2v out - pfm 1.8v out - pfm 2.5v out - pfm 3.3v out - pfm 1.16 1.17 1.18 1.19 1.20 1.21 1.22 1.23 1.24 0.00 0.25 0.50 0.75 1.00 1.25 1.50 output load (a) output voltage (v) 5v in - pwm 3.3v in -pfm 3.3v in - pwm 2.8v in - pfm 5v in - pfm 2.8v in - pwm 1.46 1.47 1.48 1.49 1.50 1.51 1.52 1.53 1.54 0.00 0.25 0.50 0.75 1.00 1.25 1.50 output load (a) output voltage (v) 5v in - pwm 3.3v in -pfm 3.3v in - pwm 2.8v in - pfm 5v in - pfm 2.8v in - pwm
ISL8009A fn6656 rev 3.00 page 6 of 13 february 28, 2013 figure 7. v out regulation vs load, v out = 1.8v figure 8. v out regulation vs load, v out = 2.5v figure 9. v out regulation vs load, v out = 3.3v figure 10. power dissipation vs load, 1.6 mhz, v out =1.8v figure 11. power dissipation vs v in at no load, v out = 1.8v figure 12. output voltage regulation vs v in pwm mode typical operating performance (unless otherwise noted, operating conditions are: t a = +25c, v vin = 5v, en = vin, rsi = skip = 0v, l = 2.2 h, c 1 = 20 f, c 2 = 20 f, i out = 0a ) (continued) 1.76 1.77 1.78 1.79 1.80 1.81 1.82 1.83 1.84 0.00 0.25 0.50 0.75 1.00 1.25 1.50 output load (a) output voltage (v) 5.5v in - pwm 4v in -pfm 4v in - pwm 2.7v in - pfm 5.5v in - pfm 2.7v in - pwm 2.46 2.47 2.48 2.49 2.50 2.51 2.52 2.53 2.54 0.00 0.25 0.50 0.75 1.00 1.25 1.50 output load (a) output voltage (v) 3.3v in - pfm 3.3v in - pwm 5v in - pfm 5v in - pwm 3.26 3.28 3.30 3.32 3.34 3.36 3.38 3.40 3.42 0.00 0.25 0.50 0.75 1.00 1.25 1.50 output load (a) output voltage (v) 5v in -pfm 3.3v in - pwm 4v in - pfm 5.5v in - pfm 4v in - pwm 5.5v in - pwm 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.00 0.25 0.50 0.75 1.00 1.25 1.50 output load (a) power dissipation (w) 3.3v in -pfm 3.3v in - pwm 2.8v in - pfm 5v in - pfm 2.8v in - pwm 5v in - pwm 0 5 10 15 20 25 30 35 40 45 2.75 3.25 3.75 4.25 4.75 5.25 v in (v) power dissipation (mw) no load- pwm no load - pfm 0.0 0.5 1.0 1.5 2.0 2.5 2.02.53.03.54.04.55.05.5 input voltage (v) output voltage (v) 0.75a load 1.5a load no load
ISL8009A fn6656 rev 3.00 page 7 of 13 february 28, 2013 figure 13. output voltage regulation vs v in skip mode figure 14. steady state operation at no load (pwm), 1s/div figure 15. steady state operation at no load (pfm), 1s/div figure 16. steady state operation with full load, 1s/div figure 17. load transient (pwm), 200s/div figure 18. load transient (pfm), 200s/div typical operating performance (unless otherwise noted, operating conditions are: t a = +25c, v vin = 5v, en = vin, rsi = skip = 0v, l = 2.2 h, c 1 = 20 f, c 2 = 20 f, i out = 0a ) (continued) -0.5 0.0 0.5 1.0 1.5 2.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 input voltage (v) output voltage (v) 0.75a load 1.5a load no load i l 0.2a/div v out ripple 20mv/div lx 2v/div i l 0.2a/div v out ripple 20mv/div lx 2v/div i l 0.5a/div v out ripple 20mv/div lx 2v/div i l 1a/div v out ripple 50mv/div lx 2v/div i l 1a/div v out ripple 50mv/div lx 2v/div
ISL8009A fn6656 rev 3.00 page 8 of 13 february 28, 2013 figure 19. soft-start at no load, 500s/div figure 20. soft-start with pre-biased 1v, 500s/div figure 21. soft-start at full load, 500s/div figure 22. output short circuit, 10.0s/div figure 23. output short circuit recovery, 500s/div typical operating performance (unless otherwise noted, operating conditions are: t a = +25c, v vin = 5v, en = vin, rsi = skip = 0v, l = 2.2 h, c 1 = 20 f, c 2 = 20 f, i out = 0a ) (continued) i l 1a/div v out 1v/div en 2v/div por 2v/div i l 1a/div en 2v/div v out 0.5v/div por 1v/div i l 0.5a/div en 2v/div v out 0.5v/div por 2v/div i l 1a/div lx 2v/div v out 1v/div por 5v/div i l 1a/div v out 1v/div por 5v/div
ISL8009A fn6656 rev 3.00 page 9 of 13 february 28, 2013 typical applications block diagram figure 24. typical application diagram l lx gnd vfb rsi vin en por skip input 2.7v to 5.5v output 1.8v to 1.5a c 1 20f r 1 100k ISL8009A c 2 r 2 124k r 3 100k 2.2h 20f *c 3 220pf *c3 is optional to improve transient response. check loop bandwidth before use. figure 25. functional block diagram lx + + csa1 + + ocp 0.85v 0.17v skip + + + slop e comp slope comp 0.8v eamp comp pwm/pfm logic controller protection driver vfb + 0.736v 0.864v por skip shutdown vin gnd oscillator zero - cross sensing + bandgap scp + 0.2v en shutdown 2ms delay rsi 27pf 390k soft- start
ISL8009A fn6656 rev 3.00 page 10 of 13 february 28, 2013 theory of operation the ISL8009A is a step-down switching regulator optimized for battery-powered handheld applications. the regulator operates at 1.6mhz fixed switching frequency under heavy load condition to allow small external inductor and capacitors to be used for minimal printed-circuit board (pcb) area. at light load, the regulator reduces the switching fr equency, unless forced to the fixed frequency to minimize the switching loss and to maximize the battery life. the quiescent current when the output is not loaded is typically only 17a. the supply current is typically only 0.1a when the regulator is shutdown. pwm control scheme the ISL8009A employes the current-mode pulse-width modulation (pwm) control scheme for fast transient response and pulse-by-pulse current limiti ng. figure 25 shows the block diagram. the current loop consists of the oscillator, the pwm comparator comp, the current sensing circuit, and the slope compensation for the current loop stability. the current sensing circuit consists of the resistance of the p-channel mosfet when it is turned on and the current sense amplifier csa. the gain for the current sensing circuit is typically 0.4v/a. the control reference for the current loops comes from the error amplifier eamp of the voltage loop. the pwm operation is initialized by the clock from the oscillator. the p-channel mosfet is turned on at the beginning of a pwm cycle and the current in the mosfet starts to ramp up. when the sum of the current amplifier cs a and the compensation slope (0.675v/s) reach the control reference of the current loop, the pwm comparator comp sends a signal to the pwm logic to turn off the p-mosfet and to turn on the n-channe l mosfet. the n-mosfet stays on until the end of the pwm cycle. figure 26 shows the typical operating wavefo rms during the pwm operation. the dotted lines illustrate the su m of the compensation ramp and the current-sense amplifier csa output. the output voltage is regulated by controlling the reference voltage to the current loop. the bandgap circuit outputs a 0.8v reference voltage to the voltage control loop. the feedback signal comes from the vfb pin. the soft-start block only affects the operation during the start-up and will be discussed separately. the error amplifier is a transcondu ctance amplifier that converts the voltage error signal to a current output. the voltage loop is internally compensated with the 30pf and 300k ? rc network. the maximum eamp voltage output is precisely clamped to the bandgap voltage (1.172v). skip mode the ISL8009A enters a pulse-skipping mode at light load to minimize the switching loss by re ducing the switching frequency. figure 27 illustrates the skip -mode operation. a zero-cross sensing circuit shown in figure 25 monitors the n-mosfet current for zero crossing. when 8 consecutive cycles of the n- mosfet crossing zero are detected , the regulator enters the skip mode. during the 8 detecting cycles , the current in the inductor is allowed to become negative. the counter is reset to zero when the current in any cycle does not cross zero. figure 26. pwm operation waveforms v eamp v csa1 duty cycle i l v out duty cycle figure 27. skip mode operation waveforms clock i l v out nominal + 1.5% nominal current limit load current 0 8 cycles current limit load current nominal +1.5% 8 cycles nominal clock
ISL8009A fn6656 rev 3.00 page 11 of 13 february 28, 2013 once the skip mode is entered, the pulse modulation starts being controlled by the skip comparat or shown in figure 25. each pulse cycle is still synchronized by the pwm clock. the p-mosfet is turned on at the clock and turned off when its current reaches 20% of the current limit value (0 .2v at the csa output). as the average inductor current in each cycle is higher than the average current of the load, the output voltage rises cycle over cycle. when the output voltage reaches 1.5% above the nominal voltage, the p-mosfet is turned off immediately and the inductor current is fully discharged to zero and stays at zero. the output voltage reduces gradually due to the load current discharging the output capacitor. when the output voltage drops to the nominal voltage, the p-mosfet will be tu rned on again at the clock, repeating the previous operations. the regulator resumes normal pwm mode operation when the output voltage drops 1.5% below the nominal voltage. mode control the ISL8009A has a skip pin that controls the operation mode. when the skip pin is driven to low or shorted to ground, the regulator operates in a forced pwm mode. the forced pwm mode remains the fixed pwm frequency at light load instead of entering the skip mode. overcurrent protection the overcurrent protection is realized by monitoring the csa output with the ocp comparator , as shown in figure 25. the current sensing circuit has a gain of 0.4v/a, from the n-mosfet current to the csa output. when the csa output reaches 0.8v, (which is equivalent to 2a for the switch current) the ocp comparator is tripped to turn off the p-mosfet immediately. short-circuit protection a short-circuit protection scp co mparator monitors the vfb pin voltage for output short-circuit protection. when the vfb is lower than 0.2v, the scp comparator forces the pwm oscillator frequency to drop to 1/3 of the normal operation value. this comparator is effective during start-up or an output short-circuit event. rsi/por function when powering up, the open-collector power-on-reset output holds low for about 1ms after vo reaches the preset voltage. when the active-hi reset signal rsi is issued, por goes to low immediately and holds for the sa me period of time after rsi comes back to low. the output voltage is unaffected (figure 28). when the function is not used, connect rsi to ground and leave the pull-up resistor, r 1 , open at the por pin. the por output also serves as a 1ms delayed power-good signal when the pull-up resistor, r 1, is installed. the rsi pin needs to be directly or indirectly through another resistor connected to ground for this to function properly. . uvlo when the input voltage is below the undervoltage lock out (uvlo) threshold, the regulator is disabled. soft-start-up the soft start-up eliminates the in-rush current during the start-up. the soft-start block outputs a ramp reference to both the voltage loop and the current loop. the two ramps limit the inductor current rising speed as well as the output voltage speed so that the output voltage rises in a controlled fashion. at the very beginning of the start-up, the output voltage is less than 0.2v; hence the pwm operating frequency is 1/3 of the normal frequency. power mosfets the power mosfets are optimized for best efficiency. the on-resistance for the p-mosfet is typically 120m ? and the on-resistance for the n-mosfet is typically 110m ? . duty cycle the ISL8009A features duty cycle operation to maximize the battery life. when the battery voltage drops to a level that the ISL8009A can no longer maintain the regulation at the output, the regulator completely turns on the p-mosfet. the maximum drop out voltage under the duty-cyc le operation is the product of the load current and the on-resistance of the p-mosfet. enable the enable (en) input allows the user to control the turning on or off of the regulator for purposes such as power-up sequencing. when the regulator is enabled, there is typically a 600s delay for waking up the bandgap reference, then the soft-start-up begins. when the regulator is disabled, the p-mosfet and the n-mosfet are turned off immediately. the 100 ? soft discharge resistor from lx to gdn is activated and pulls the output to 0v. thermal shutdown the ISL8009A has built-in thermal protection. when the internal temperature reaches +140c, th e regulator is completely shutdown. as the temperature drops to +120c, the ISL8009A resumes operation by stepping through a soft-start-up. 2ms min 25ns 2ms por rsi v o figure 28. rsi and por timing diagram
fn6656 rev 3.00 page 12 of 13 february 28, 2013 ISL8009A intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2008-2013. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. applications information output inductor and capacitor selection to consider steady state and transient operation, ISL8009A typically uses a 3.3h output inductor. higher or lower inductor values can be used to optimize the total converter system performance. for example, for higher output voltage 3.3v application, in order to decrease the inductor current ripple and output voltage ripple, the output inductor value can be increased. the inductor ripple current can be expressed in equation 1: the inductor?s saturation current rating needs be at least larger than the peak current. the isl800 9a protects the typical peak current 2.1a. the saturation current needs to be over 2.4a for maximum output current application. ISL8009A uses internal compensation network and the output capacitor value is dependant on the output voltage. the ceramic capacitor is recommended to be x5r or x7r. the recommended minimum output capacitor values are shown in table 1. in table 1, the minimum output capacitor value is given for different output voltages to make sure the whole converter system is stable. maximum output capacitance should be limited to 50f or less. input capacitor selection the main functions for the input capacitor are to provide decoupling of the parasitic inductance and to provide filtering function to prevent the switching current from flowing back to the battery rail. a 10f, x5r or x7r ceramic capacitor is a good starting point for the input capacitor selection. output voltage setting resistor selection the resistors r 2 and r 3 shown in figure 24 set the output voltage for the adjustable version. the output voltage can be calculated by equation 2: where the 0.8v is the reference voltage. the voltage divider consists of r 2 and r 3 and increases the quiescent current by vo/(r 2 + r 3 ), so larger resistance is desirable. on the other hand, the vfb pin has leakage current that will cause error in the outp ut voltage setting. the leakage current has a typical value of 0.1a. to minimize the accuracy impact on the output voltage, select the r 3 no larger than 200k ? . for v o = 0.8v, it is recommended to short r 2 and open r 3 . layout recommendation the layout is a very important converter design step to make sure the designed converter works well. for the ISL8009A buck converter, the power loop is composed of the output inductor l, the output capacitor c out , the lx pin and the gnd pin. it is necessary to make the power loop as small as possible. the heat of the ic is mainly dissipated through the thermal pad. maximizing the copper area connected to the thermal pad is preferable. in addition, a solid ground plane is helpful for emi performance. it is recommended to add 5 vias under the thermal pad connection to the solid ground plane. table 1. output capacitor value vs v out v out (v) c out (f) l (h) 0.8 10 1.0~2.2 1.2 10 1.2~2.2 1.6 10 1.8~2.2 1.8 10 1.8~3.3 2.5 10 1.8~3.3 3.3 10 1.8~4.7 3.6 10 1.8~4.7 ? i v o 1 v o v in -------- C ?? ?? ?? ? lf s ? ------------------------------------ = (eq. 1) v o 0.8 1 r 2 r 3 ------ - + ?? ?? ?? ? = (eq. 2)
ISL8009A fn6656 rev 3.00 page 13 of 13 february 28, 2013 package outline drawing l8.2x3 8 lead dual flat no-lead plastic package rev 1, 3/10 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but mus t be between 0.25mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to asme y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view compies to jedec mo-229 vced-2. 7. (4x) 0.15 index area pin 1 pin #1 c seating plane base plane 0.08 see detail "x" c c 4 6 a b 0.90 0.10 0.05 max 0.05 max 0.20 ref 2.00 3.00 2x 1.50 8x 0.40 0.10 8x 0.25 +0.07/-0.05 index area 6x 0.50 (1.65) (1.50) (8x 0.60) (8x 0.25) (1.80) (2.80) (6x 0.50) 1 8 0.10 a mc b 0.10 c 1.80 +0.10/-0.15 1.65 +0.10/-0.15

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