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1 1 www.pericom.com 06/30/15 pi6cdbl402b block diagram pin configuration description pericom semiconductor's pi6cdbl402b is a pcie 3.0 compliant high-speed, low-noise diferential clock bufer designed to be companion to pcie 3.0 clock generator. it is backward compat- ible with pcie 1.0 and 2.0 specifcation. te device distributes the diferential src clock from pcie 3.0 clock generator to four diferential pairs of clock outputs either with or without pll. te clock outputs are controlled by input selection of pwrdwn# and smbus, sclk and sda. features ?? phase jitter flter for pcie 3.0/ 2.0/ 1.0 application ?? low power consumption with independent output power supply 1.8v~3.3v ?? low skew < 60ps ?? low cycle-to-cycle jitter - 45ps (typ.) @100mhz ?? < 1 ps additive rms phase jitter ?? output enable for all outputs ?? programmable pll bandwidth ?? 100 mhz pll mode operation ?? 1 - 400 mhz bypass mode operation ?? 3.3v operation ?? packaging (pb-free and green): -28-pin tssop (l28) 4 -output low power pcie gen 1-2-3 buffer out0 out0# out1 out1# out2 out2# out3 out3# output control smbus controller pll pll_bw# src src# pll/bypass# sclk sda oe_inv oe_0 & oe_3 pwrdwn# v dd_ a gnda oe_inv out3 out3# oe_3 out2 out2# pll_bw# v dd pwrdwn# 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 v dd src src# gnd v ddo out0 out0# oe_0 out1 out1# pll/bypass# sclk sda nc v ddo v ddo v ddo pll/bypass# all trademarks are property of their respective owners. 15-0083
2 2 www.pericom.com 06/30/15 pin description pin # pin name ty pe description 2, 3 src & src# input 0.7v diferential src input from pi6c410 clock synthesizer 8, 21 oe_0 & oe_3 input 3.3v lvttl input for enabling outputs, active high. oe_0 for out0 / out0# oe_3 for out3 / out3# 25 oe_inv input 3.3v lvttl input for inverting the oe and pwrdwn# pins. when 0 = same stage when 1 = oe_0, oe_3, pwrdwn# inverted. 6, 7, 9, 10, 19, 20, 22, 23 out[0:3] & out[0:3]# output 0.7v diferential outputs, refer power management table for detail output status 12 pll/bypass# input 3.3v lvttl input for selecting fan-out of pll operation. 13 sclk input smbus compatible sclock input 14 sda i/o smbus compatible sdata 26 nc no connect 17 pll _bw# input 3.3v lvttl input for selecting the pll bandwidth 15 pwrdwn# input 3.3v lvttl input for power down operation, active low 5, 11, 18, 24 v ddo power power supply for outputs, range from 1.8v~3.3v 4 gnd ground ground for outputs 27 gnda ground ground for pll 28 v dd_a power 3.3v power supply for pll 1, 16 v dd power 3.3v power supply for pll all trademarks are property of their respective owners. pi6cdbl402b 4 -output low power pcie gen 1-2-3 buffer 15-0083
3 3 www.pericom.com 06/30/15 serial data interface (smbus) tis part is a slave only device that supports blocks read and block write protocol using a single 7-bit address and read/write bit as shown below. read and write block transfers can be stopped afer any complete byte transfer by issuing stop. address assignment a6 a5 a4 a3 a2 a1 a0 w/r 1 1 0 1 1 1 0 0/1 data protocol 1 bit 7 bits 1 1 8 bits 1 8 bits 1 8 bits 1 8 bits 1 1 bit start bit slave addr r/w ack register ofset ack byte count = n ack data byte 0 ack data byte n - 1 ack stop bit notes: 1. register ofset for indicating the starting register for indexed block write and indexed block read. byte count in write mode cannot be 0. output[1]/ output[2] state choose oe_inv pwrdwn# byte0/bit7 oe(pin) oe(smbus bit) out1/ out2 out1#/ out2# 0 x x na 0 low low 0 0 0 na 1 high low 0 0 1 na x low low 0 1 x na 1 clock output clock output 1 x x na 0 low low 1 1 0 na 1 high low 1 1 1 na x low low 1 0 x na 1 clock output clock output notes: 1. all registers cant be written/read during pwrdwn# active power management table output[0]/ output[3] state choose oe_inv pwrdwn# byte0/bit7 oe_0/oe_3(pin) oe(smbus bit) out0/ out3 out0#/ out3# 0 x x 0 x low low 0 x x x 0 low low 0 0 0 1 1 high low 0 0 1 x x low low 0 1 x 1 1 clock output clock output 1 x x 1 x low low 1 x x x 0 low low 1 1 0 0 1 high low 1 1 1 x x low low 1 0 x 0 1 clock output clock output all trademarks are property of their respective owners. pi6cdbl402b 4 -output low power pcie gen 1-2-3 buffer 15-0083
4 4 www.pericom.com 06/30/15 data byte 0: control register bit descriptions ty pe power up condition output(s) afected source pin 0 reserved na 1 pll/bypass# 0 = fanout 1 = pll rw 1 = pll out[0:3], out[0:3]# na 2 pll bandwidth 0 = high bandwidth, 1 = low bandwidth rw 1 = low out[0:3], out[0:3]# na 3 reserved na 4 reserved na 5 reserved na 6 reserved na 7 pd_mode refer power management table rw 0 out[0:3], out[0:3]# na data byte 1: control register bit descriptions ty pe power up condition output(s) afected source pin 0 reserved na 1 outputs enable 1 = enabled 0 = disabled rw 1 = enabled out0, out0# na 2 rw 1 = enabled out1, out1# na 3 reserved na 4 reserved na 5 outputs enable 1 = enabled 0 = disabled rw 1 = enabled out2, out2# na 6 rw 1 = enabled out3, out3# na 7 reserved na all trademarks are property of their respective owners. pi6cdbl402b 4 -output low power pcie gen 1-2-3 buffer 15-0083
5 5 www.pericom.com 06/30/15 data byte 2: control register bit descriptions ty pe power up condition output(s) afected source pin 0 reserved na 1 reserved na 2 reserved na 3 reserved na 4 reserved na 5 reserved na 6 reserved na 7 reserved na data byte 3: control register bit descriptions ty pe power up condition output(s) afected source pin 0 reserved rw 1 rw 2 rw 3 rw 4 rw 5 rw 6 rw 7 rw data byte 4: control register bit descriptions ty pe power up condition output(s) afected source pin 0 pericom id r 0 na na 1 r 0 na na 2 r 0 na na 3 r 0 na na 4 r 0 na na 5 r 1 na na 6 r 0 na na 7 r 0 na na all trademarks are property of their respective owners. pi6cdbl402b 4 -output low power pcie gen 1-2-3 buffer 15-0083
6 6 www.pericom.com 06/30/15 power down (pwrdwn# assertion) power down (pwrdwn# de-assertion) pwrdwn# out# out pwrdwn# out out# tdrive_pwrdwn# <300us, >200mv tstable <1ms figure 1. power down sequence figure 2. power down de-assert sequence all trademarks are property of their respective owners. pi6cdbl402b 4 -output low power pcie gen 1-2-3 buffer 15-0083
7 7 www.pericom.com 06/30/15 driving lvds inputs with the pi6cdbl402b component va lue note receiver has termination receiver does not have termination r7a, r7b 10k f 140 f r8a, r8b 5.6k f 75 f cc 0.1 uf 0.1 uf vcm 1.2 volts 1.2 volts test loads rs r o 5 inches rs zo=100 2pf 2pf low-power hcsl differential output test load device driving lvds r zo device driving lvds cc cc r7a r7b r8a r8b 3.3v lvds clock input rs rs all trademarks are property of their respective owners. pi6cdbl402b 4 -output low power pcie gen 1-2-3 buffer 15-0083
8 8 www.pericom.com 06/30/15 electrical characteristicsCclock input parameters (t a = -40~85 o c; vdd = 3.3v+/-10%; vddo = 3.3v+/-10%, vddo = 2.5v+/-10%, vddo = 1.8v+/-10%, see test loads for loading conditions) symbol parameters condition min. ty pe max. units v ihdif input high voltage - dif_in 1 diferential inputs (single-ended measurement) 600 800 1150 mv v ildof input low voltage - dif_in 1,3 diferential inputs (single-ended measurement) v ss - 300 0 300 mv v com input common mode voltage - dif_in 1 common mode input voltage 300 725 mv v swing input amplitude - dif_in 1 peak to peak value (v ihdif - v ildif ) 300 1450 mv dv/dt input slew rate - dif_in 1,2 measured differentially 0.4 v/ns i in input leakage current 1 v in = v dd , v in = gnd -5 5 ua d tin input duty cycle 1 measurement from diferential wave- from 45 55 % j difin input jitter - cycle to cycle 1 diferential measurement 0 150 ps note: 1. guaranteed by design and characterization, not 100% tested in production. 2. slew rate measured through +/-75mv window centered around differential zero 3. the device can be driven from a single ended clock by driving the true clock and biasing the complement clock input to the vbias, where vbias is (vih- high - vihlow)/2 supply voltage to ground potential ...................................................... 4 .6v all inputs and output ..................................................... -0.5v tov dd +0.5v ambient operating temperature ........................................... -40 to +85c storage temperature .......................................................... C65c to +150c junction temperature .......................................................................... 125c soldering temperature ......................................................................... 2 60c esd protection (input) ........................................................... 2000v(hbm) note: stresses greater than those listed under maximum rat- ings may cause permanent damage to the device. tis is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may afect reliability. maximum ratings (above which useful life may be impaired. for user guidelines, not tested.) all trademarks are property of their respective owners. pi6cdbl402b 4 -output low power pcie gen 1-2-3 buffer 15-0083
9 9 www.pericom.com 06/30/15 electrical characteristicsCinput/supply/common parametersCnormal operating conditions (t a = -40~85 o c; svdd = 3.3v+/-10%; vddo = 3.3v+/-10%, vddo = 2.5v+/-10%, vddo = 1.8v+/- 10%, see test loads for loading conditions) symbol parameters condition min. ty pe max. units v dd_a , v dd supply voltage 1 supply voltage for core, analog 3.0 3.3 3.6 v v ddo supply voltage 1 3.3v operation 2.97 3.3 3.63 v 2.5v operation 2.25 2.5 2.75 1.8v operation 1.62 1.8 1.98 v ih input high voltage 1 single-ended inputs, except smbus 0.65 v dd v dd + 0.3 v v il input low voltage 1 single-ended inputs, except smbus -0.3 0.35 v dd v v ih output high voltage 1 single-ended outputs, except smbus. i oh = -2ma v dd - 0.45 v v il outputt low voltage 1 single-ended outputs, except smbus. i ol = -2ma 0.45 v i in input current 1 single-ended inputs, v in = gnd, v in = vdd -5 5 ua i inp single-ended inputs v in = 0 v; inputs with internal pull-up resistors v in = vdd; inputs with internal pull-down resis- tors -200 200 ua f ibyp input frequency 2 bypass mode 1 400 mhz f ipll100 100mhz pll mode 95 100.00 105 mhz lpin pin inductance 1 7 nh c in capacitance 1,4 logic inputs, except dif_in 1.5 5 pf c indif_in dif_in diferential clock inputs 1.5 2.7 pf c out output pin capacitance 6 pf t stab clk stabilization 1,2 from v dd power-up and afer input clock stabilization or de-assertion of pd# to 1st clock 0.6 1 ms f modin input ss modulation frequency 1 allowable frequency (triangular modulation) 30 31.500 33 khz t latoe# oe# latency 1,3 dif start afer oe# assertion dif stop afer oe# deassertion 1 3 clocks t drvpd tdrive_pd# 1,3 dif output enable afer pd# de-assertion 300 us t f tfall 1,2 fall time of single-ended control inputs 5 ns t r trise 1,2 rise time of single-ended control inputs 5 ns v ilsmb smbus input low voltage 1 0.8 v v ihsmb smbus input high voltage 1 2.1 3.6 v all trademarks are property of their respective owners. pi6cdbl402b 4 -output low power pcie gen 1-2-3 buffer 15-0083
10 10 www.pericom.com 06/30/15 electrical characteristicsCinput/supply/common parametersCnormal operating conditions cont... symbol parameters condition min. ty pe max. units v olsmb smbus output low voltage 1 @ i pullup 0.4 v i pullup smbus sink current 1 @ v ol 4 ma v ddsmb nominal bus voltage 1 3.3v bus voltage 2.7 3.6 v t rsmb sclk/sdata rise time 1 (max vil - 0.15) to (min vih + 0.15) 1000 ns t fsmb sclk/sdata fall time 1 (min vih + 0.15) to (max vil - 0.15) 300 ns f maxsmb smbus operating frequency 1,5 maximum smbus operating frequency 400 khz note: 1. guaranteed by design and characterization, not 100% tested in production. 2. control input must be monotonic from 20% to 80% of input swing. input frequency capacitance 3. time from deassertion until outputs are >200 mv 4. dif_in input 5. the differential input clock must be running for the smbus to be active electrical characteristicsCdif 0.7v low power hcsl outputs (t a = -40~85 o c; vdd = 3.3v+/-10%; vddo = 3.3v+/-10%, vddo = 2.5v+/-10%, vddo = 1.8v+/-10%, see test loads for loading conditions) symbol parameters condition min. ty pe max. units trf slew rate 1,2,3 1.1 2 4.5 v/ns v high voltage hig h 1,7 statistical measurement on single-ended signal using oscilloscope math function. (scope averaging on) 660 950 mv v low voltage l ow 1,7 -150 200 mv vmax ma x voltage 1 measurement on single ended signal using absolute value. (scope averaging of) 1150 mv vmin mi n voltage 1 -300 mv vsw ing vsw ing 1,2,7 scope averaging of 300 mv crossing voltage (abs) vcross_abs scope averaging of 250 550 mv crossing voltage (var) -vcross scope averaging of 140 mv note: 1. guaranteed by design and characterization, not 100% tested in production. 2. measured from differential waveform 3. slew rate is measured through the vswing voltage range centered around differential 0v. this results in a +/-150mv window around differential 0v. 4. matching applies to rising edge rate for clock and falling edge rate for clock#. it is measured using a +/-75mv window centered on the average cross point where clock rising meets clock# falling. the median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calcula- tions. 5. vcross is defned as voltage where clock = clock# measured on a component test board and only applies to the differential rising edge (i.e. clock rising and clock# falling). 6. the total variation of all vcross measurements in any particular system. note that this is a subset of vcross_min/max (vcross absolute) allowed. the intent is to limit vcross induced modulation by setting -vcross to be smaller than vcross absolute. 7. at default smbus settings. all trademarks are property of their respective owners. pi6cdbl402b 4 -output low power pcie gen 1-2-3 buffer 15-0083
11 11 www.pericom.com 06/30/15 electrical characteristicsCcurrent consumption (t a = -40~85 o c; vdd = 3.3v+/-10%; vddo = 3.3v+/- 10%, vddo = 2.5v+/-10%, vddo = 1.8v+/-10%, see test loads for loading conditions) symbol parameters condition min. ty pe max. units i ddop operating supply current 1 total power consumption, all outputs active @100mhz, typical value under vddo = 1.8v 50 60 ma total power consumption, all outputs active @100mhz pll bypass mode, typical value under vddo = 1.8v 24 28 ma i ddpd powerdown current 1,2 total power consumption, outputs low 1.3 ma note: 1. guaranteed by design and characterization, not 100% tested in production. 2. input clock stopped. electrical characteristicsCoutput duty cycle, jitter, skew and pll characterisitics (t a = -40~85 o c; vdd = 3.3v+/-10%; vddo = 3.3v+/-10%, vddo = 2.5v+/-10%, vddo = 1.8v+/-10%, see test loads for loading conditions) symbol parameters condition min. ty pe max. units t dc duty cycle 1 measured diferentially, pll mode 45 55 % t dcd duty cycle distortion 1,3 measured diferentially, bypass mode @100mhz -1.3 0 1.3 % t pdbyp skew, input to output 1,4 bypass mode, vt = 50% 2500 5000 ps t pdpll pll mode vt = 50% -260 260 ps t skew skew, output to output 1,2 pll mode vt = 50% 60 ps t jcyc-cyc jitter, cycle to cycle 1,2 pll mode 60 ps additive jitter in bypass mode 25 ps note: 1. guaranteed by design and characterization, not 100% tested in production. 2. measured from differential waveform 3. duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode. 4. all outputs at default slew rate 5. the min/typ/max values of each bw setting track each other, i.e., low bw max will never occur with hi bw min. all trademarks are property of their respective owners. pi6cdbl402b 4 -output low power pcie gen 1-2-3 buffer 15-0083
12 12 www.pericom.com 06/30/15 electrical characteristicsCphase jitter parameters (t a = -40~85 o c; vdd = 3.3v+/-10%; vddo = 3.3v+/-10%, vddo = 2.5v+/-10%, vddo = 1.8v+/-10%, see test loads for loading conditions) symbol parameters condition min. ty pe industry limit units t jphpcieg1 phase jitter, pll mode pcie gen 1 1,2,3 34 86 ps (p-p) t jphpcieg2 pcie gen 2 lo band 10khz < f < 1.5mhz 1,2 0.9 3 ps (rms) pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 1,2 2.2 3.1 ps (rms) t jphpcieg3 pcie gen 3 (pll bw of 2-4mhz, cdr = 10mhz) 1,2,3,4 0.5 1 ps (rms) t jphsgmii 125mhz, 1.5mhz to 20mhz, -20db/decade rollover < 1.5mhz, -40db/decade rollof > 10mhz 1,6 1.9 na ps (rms) t jphpcieg1 additive phase jitter, bypass mode pcie gen 1 1,2,3 0.6 n/a ps (p-p) t jphpcieg2 pcie gen 2 lo band 10khz < f < 1.5mhz 1,2,5 0.1 n/a ps (rms) pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 1,2,5 0.05 n/a ps (rms) t jphpcieg3 pcie gen 3 (pll bw of 2-4mhz, cdr = 10mhz) 1,2,4,5 0.05 n/a ps (rms) t jphsgmii 125mhz, 1.5mhz to 10mhz, -20db/decade rollover < 1.5mhz, -40db/decade rollof > 10mhz 1,6 0.15 n/a ps (rms) note: 1. applies to all outputs, with device driven by 9fg432aklf or equivalent. 2. see http://www.pcisig.com for complete specs 3. sample size of at least 100k cycles. this fgures extrapolates to 108ps pk-pk @ 1m cycles for a ber of 1-12. 4. subject to fnal ratifcation by pci sig. 5. for rms fgures, additive jitter is calculated by solving the following equation: additive jitter = sqrt[(total jitter)^2 - (input jitter)^2] 6. applies to all differential outputs all trademarks are property of their respective owners. pi6cdbl402b 4 -output low power pcie gen 1-2-3 buffer 15-0083
13 13 www.pericom.com 06/30/15 pericom semiconductor corporation ? 1-800-435-2336 packaging mechanical: 28-pin tssop (l) 1 description: 28-pin, 173-mil wide, tssop package code: l document control no. pd - 1313 revision: d date: 03/09/05 pericom semiconductor corporation 3545 n. 1st street, san jose, ca 95134 1-800-435-2335 ? www.pericom.com .378 .386 .047 1.20 .002 .006 seating plane .0256 bsc .018 .030 .252 bsc 1 28 .169 .177 0.05 0.15 6.4 0.45 0.75 0.09 0.20 4.3 4.5 9.6 9.8 0.65 0.19 0.30 .007 .012 .004 .008 max note: 1. package outline exclusive of mold flash and metal burr 2. controlling dimentions in millimeters 3. ref: jedec mo-153f/ae ordering information (1-3) ordering code package code package description pi6cdbl402blie le 28-pin, 173-mil wide (tssop) PI6CDBL402BLIEX le 28-pin, 173-mil wide (tssop), tape & reel notes: 1. t ermal characteristics can be found on the company web site at www.pericom.com/packaging/ 2. e = p b-free and green 3. a dding an x sufx = tape/reel all trademarks are property of their respective owners. pi6cdbl402b 4 -output low power pcie gen 1-2-3 buffer 15-0083

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