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rev. 1.1 september 2008 www.aosmd.com page 1 of 15 AOZ1073 ezbuck 3a synchronous buck regulator general description the AOZ1073 is a synchronous high ef?iency, simple to use, 3a buck regulator. the AOZ1073 works from a 4.5v to 16v input voltage range, and provides up to 3a of continuous output current with an output voltage adjustable down to 0.8v. the AOZ1073 comes in an so-8 packages and is rated ov er a -40? to +85? ambient temperature range. features 4.5v to 16v operating input voltage range synchronous recti?ation: 85m ? internal high-side s witch and 30m ? internal low-side switch high ef?iency: up to 95% internal soft start output voltage adjustable to 0.8v 3a continuous output current fixed 500khz pwm operation cycle-by-cycle current limit pre-bias start-up short-circuit protection thermal shutdown output over voltage protection small size so-8 package applications p oint of load dc/dc conversion pcie graphics cards set top boxes d vd drives and hdd lcd panels cable modems t elecom/networking/datacom equipment t ypical application figure 1. 3.3v/3a buck regulator lx vin vin vout fb pgnd en comp agnd c2, c3 22f ceramic r1 r2 c c r c c1 22f ceramic l1 4.7h AOZ1073
a oz1073 rev. 1.1 september 2008 www.aosmd.com page 2 of 15 ordering information all aos products are offered in packages with pb-free plating and compliant to rohs standards. parts marked as green products (with ? suf?) use reduced levels of halogens, and are also rohs compliant. please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information. pin con?uration pin description pa rt number ambient temperature range package environmental a oz1073ail -40? to +85? so-8 green (halogen free) lx lx en comp 1 2 3 4 pgnd vin agnd fb so-8 (top view) 8 7 6 5 pin number pin name pin function 1 pgnd power ground. electrically needs to be connected to agnd. 2v in supply voltage input. when v in rises above the uvlo threshold the device starts up. 3a gnd reference connection for controller section. also used as thermal connection for controller section. electrically needs to be connected to pgnd. 4f b the fb pin is used to determine the output voltage via a resistor divider between the output and gnd. 5 comp external loop compensation pin. 6e n the enable pin is active high. connect it to v in if not used and do not leave it open. 7, 8 lx pwm outputs connection to inductor.
rev. 1.1 september 2008 www.aosmd.com page 3 of 15 a oz1073 block diagram absolute maximum ratings exceeding the absolute maximum ratings may damage the device. note: 1. devices are inherently esd sensitive, handling precautions are required. human body model rating: 1.5k ? in series with 100pf. recommend operating ratings the device is not guaranteed to operate beyond the maximum operating ratings. note: 2. the value of ja is measured with the device mounted on 1-in 2 fr-4 board with 2oz. copper, in a still air environment with t a = 25?. the value in any given application depends on the user's speci? board design. 500khz/68khz oscillator agnd pgnd vin en fb comp lx otp internal +5v ilimit pwm control logic 5v ldo regulator uvlo & por softstart reference & bias 0.8v q1 q2 pwm comp level shifter + fet driver isen eamp 0.2v + ? + ? + ? + ? + frequency foldback comparator 0.96v + ? ovp comparator p arameter rating supply voltage (v in ) 18v lx to agnd -0.7v to v in +0.3v en to agnd -0.3v to v in +0.3v fb to agnd -0.3v to 6v comp to agnd -0.3v to 6v pgnd to agnd -0.3v to 0.3v j unction temperature (t j ) +150? storage temperature (t s ) -65? to +150? esd rating (1) 2.0kv p arameter rating supply voltage (v in ) 4.5v to 16v output voltage range 0.8v to v in ambient temperature (t a ) -40? to +85? pa c kage thermal resistance ( ja ) (2) so-8 87?/w pa c kage thermal resistance ( jc ) so-8 30?/w pa c kage power dissipation (p d ) @ 25? ambient so-8 1.15w
a oz1073 rev. 1.1 september 2008 www.aosmd.com page 4 of 15 electrical characteristics t a = 25?, v in = v en = 12v, v out = 3.3v unless otherwise speci?d. (3) note: 3. speci?ations in bold indicate an ambient temperature range of -40? to +85?. these speci?ations are guaranteed by design. symbol p arameter conditions min. t yp. max. units v in supply voltage 4.5 16 v v uvlo input under-voltage lockout threshold v in rising v in falling 4.1 3.7 v i in supply current (quiescent) i out = 0, v fb = 1.2v, v en > 1.2v 1.6 2.5 ma i off shutdown supply current v en = 0v 320 ? v fb f eedback voltage t a = 25? 0.788 0.8 0.812 v load regulation 0.5 % line regulation 1% i fb f eedback voltage input current 200 na enable v en en input threshold off threshold on threshold 2 0.6 v v hys en input hysteresis 100 mv modulator f o f requency 350 500 600 khz d max maximum duty cycle 100 % d min minimum duty cycle 6% g vea error ampli?r voltage gain 500 v / v g ea error ampli?r transconductance 200 ? / v protection i lim current limit 3.5 5.0 a v pr output over-voltage protection threshold off threshold on threshold 960 940 mv over-temperature shutdown limit t j rising t j falling 150 100 ? t ss soft start interval 3 5 6.5 ms pwm output stage high-side switch on-resistance v in = 12v v in = 5v 85 120 115 170 m ? low-side switch on-resistance v in = 12v v in = 5v 30 50 36 60 m ?
a oz1073 rev. 1.1 september 2008 www.aosmd.com page 5 of 15 t ypical performance characteristics circuit of figure 1. t a = 25?, v in = v en = 12v, v out = 3.3v unless otherwise speci?d. light load operation full load (ccm) operation startup to full load short circuit protection 50% to 100% load transient short circuit recovery 1 s/div 1 s/div 1ms/div 100 s/div 100 s/div 2ms/div vin ripple 0.1v/div vo ripple 20mv/div vo 2v/div vin 10v/div lx 10v/div lin 1a/div vo ripple 100mv/div lo 1a/div vo 2v/div il 2a/div lx 10v/div vo 2v/div il 2a/div il 1a/div vlx 10v/div vin ripple 0.1v/div vo ripple 20mv/div il 1a/div vlx 10v/div
a oz1073 rev. 1.1 september 2008 www.aosmd.com page 6 of 15 ef?iency thermal derating curves AOZ1073 efficiency efficiency (v in = 12v) vs. load current 75 80 70 65 85 90 95 5.0v output 3.3v output 1.8v output 1.2v output 1.8v 3.3v output 100 0 0.5 1.0 1.5 2.0 2.5 3.0 load current (a) efficieny (%) AOZ1073 efficiency efficiency (v in = 5v) vs. load current 75 80 70 65 85 90 95 100 0 0.5 1.0 1.5 2.0 2.5 3.0 load current (a) efficieny (%) derating curve at 5v/6v input 1.2v output 3.3v output 1.8v output 1.8v output ambient temperature (t a ) output current (i o ) 5 4 3 2 1 0 25 35 45 55 65 75 85 derating curve at 12 input 1.2v, 1.8v, 3.3v, 5.0v output ambient temperature (t a ) output current (i o ) 3.3 3.2 3.1 3.0 2.9 2.8 25 35 45 55 65 75 85
a oz1073 rev. 1.1 september 2008 www.aosmd.com page 7 of 15 detailed description the AOZ1073 is a current-mode, step down regulator with integrated high-side pmos switch and a low-side nmos s witch. it operates from a 4.5v to 16v input voltage range and supplies up to 3a of load current. the duty cycle can be adjusted from 6% to 100% allowing a wide output v oltage range. features include enable control, power-on reset, input under voltage lockout, output over voltage protection, active high power good state, ?ed internal soft-start and thermal shut down. the AOZ1073 is available in an so-8 package. enable and soft start the AOZ1073 has an internal soft start feature to limit in-rush current and ensure the output voltage ramps up smoothly to regulation voltage. a soft start process begins when the input voltage rises to 4.1v and voltage on en pin is high. in the soft start process, the output v oltage is typically ramped to regulation voltage in 4ms. the 4ms soft start time is set internally. the en pin of the AOZ1073 is active high. connect the en pin to v in if the enable function is not used. pulling en to ground will disable the AOZ1073. do not leave it open. the voltage on the en pin must be above 2v to enable the AOZ1073. when voltage on the en pin falls below 0.6v, the AOZ1073 is disabled. if an application circuit requires the AOZ1073 to be disabled, an open drain or open collector circuit should be used to interface to the en pin. steady-state operation under steady-state conditions, the converter operates in ?ed frequency and continuous-conduction mode (ccm). the AOZ1073 integrates an internal p-mosfet as the high-side switch. inductor current is sensed by amplifying the voltage drop across the drain to source of the high side power mosfet. output voltage is divided down by the external voltage divider at the fb pin. the difference of the fb pin voltage and reference is ampli?d by the internal transconductance error ampli?r. the error v oltage, which shows on the comp pin, is compared against the current signal, which is sum of inductor current signal and ramp compensation signal, at the pwm comparator input. if the current signal is less than the error voltage, the internal high-side switch is on. the inductor current ?ws from the input through the inductor to the output. when the current signal exceeds the error v oltage, the high-side switch is off. the inductor current is freewheeling through the internal low-side n-mosfet s witch to output. the internal adaptive fet driver guarantees no turn on overlap of both high-side and low-side switch. comparing with regulators using freewheeling schottky diodes, the AOZ1073 uses freewheeling nmosfet to realize synchronous recti?ation. it greatly improves the converter ef?iency and reduces power loss in the low-side switch. the AOZ1073 uses a p-channel mosfet as the high- side switch. it saves the bootstrap capacitor normally seen in a circuit which is using an nmos switch. it allows 100% turn-on of the high-side switch to achieve linear regulation mode of operation. the minimum voltage drop from v in to v o is the load current x dc resistance of mosfet + dc resistance of buck inductor. it can be calculated by the equation below: where; v o_max is the maximum output voltage, v in is the input voltage from 4.5v to 16v, i o is the output current from 0a to 3a, and r ds(on) is the on resistance of internal mosfet, the value is between 97m ? and 200m ? depending on input voltage and junction temperature. switching frequency the AOZ1073 switching frequency is ?ed and set by an internal oscillator. the practical switching frequency could range from 350khz to 600khz due to device va r iation. output voltage programming output voltage can be set by feeding back the output to the fb pin by using a resistor divider network. see the application circuit shown in figure 1. the resistor divider network includes r 1 and r 2 . usually, a design is started by picking a ?ed r 2 value and calculating the required r 1 with equation below: some standard value of r 1 , r 2 and most used output v oltage values are listed in table 1. v o (v) r 1 (k ? ) r 2 (k ? ) 0.8 1.0 open 1.2 4.99 10 1.5 10 11.5 1.8 12.7 10.2 2.5 21.5 10 3.3 31.1 10 5.0 52.3 10 v o _max v in i o r ds on () = v o 0.8 1 r 1 r 2 ------- + ?? ?? ?? =
a oz1073 rev. 1.1 september 2008 www.aosmd.com page 8 of 15 the combination of r 1 and r 2 should be large enough to av oid drawing excessive current from the output, which will cause power loss. since the switch duty cycle can be as high as 100%, the maximum output voltage can be set as high as the input v oltage minus the voltage drop on upper pmos and inductor. protection features the AOZ1073 has multiple protection features to prevent system circuit damage under abnormal conditions. over current protection (ocp) the sensed inductor current signal is also used for ov er current protection. since the AOZ1073 employs peak current mode control, the comp pin voltage is proportional to the peak inductor current. the comp pin v oltage is limited to be between 0.4v and 2.5v internally. the peak inductor current is automatically limited cycle by cycle. when the output is shorted to ground under fault conditions, the inductor current decays very slow during a switching cycle because of v o = 0v. to prevent cata- strophic failure, a secondary current limit is designed inside the AOZ1073. the measured inductor current is compared against a preset voltage which represents the current limit, between 3.5a and 5.0a. when the output current is more than current limit, the high side switch will be turned off. the converter will initiate a soft start once the over-current condition is resolved. output over voltage protection (ovp) the AOZ1073 monitors the feedback voltage: when the f eedback voltage is higher than 960mv, it immediately turns-off the pmos to protect the output voltage ov ershoot at fault condition. when feedback voltage is lower than 940mv, the pmos is allowed to turn on in the next cycle. po wer-on reset (por) a power-on reset circuit monitors the input voltage. when the input voltage exceeds 4.1v, the converter starts operation. when input voltage falls below 3.7v, the converter shuts down. thermal protection an internal temperature sensor monitors the junction temperature. it shuts down the internal control circuit and high side pmos if the junction temperature exceeds 150?. the regulator will restart automatically under the control of soft-start circuit when the junction temperature decreases to 100?. application information the basic AOZ1073 application circuit is show in figure 1. component selection is explained below. input capacitor the input capacitor must be connected to the v in pin and pgnd pin of AOZ1073 to maintain steady input voltage and ?ter out the pulsing input current. the voltage rating of input capacitor must be greater than maximum input v oltage plus ripple voltage. the input ripple voltage can be approximated by equation below: since the input current is discontinuous in a buck converter, the current stress on the input capacitor is another concern when selecting the capacitor. for a bu ck circuit, the rms value of input capacitor current can be calculated by: if we let m equal the conversion ratio: the relation between the input capacitor rms current and voltage conversion ratio is calculated and shown in figure 2 below. it can be seen that when v o is half of v in , c in is under the worst current stress. the worst current stress on c in is 0.5 x i o . figure 2. i cin vs. voltage conversion ratio ? v in i o fc in ------------------ - 1 v o v in ---------- ?? ?? ?? v o v in ---------- = i cin _rms i o v o v in ---------- 1 v o v in ---------- ?? ?? ?? = v o v in ---------- m = 0 0.1 0.2 0.3 0.4 0.5 0 0.5 1 m i cin_rms (m) i o
a oz1073 rev. 1.1 september 2008 www.aosmd.com page 9 of 15 f or reliable operation and best performance, the input capacitors must have current rating higher than i cin_rms at worst operating conditions. ceramic capacitors are preferred for input capacitors because of their low esr and high current rating. depending on the application circuits, other low esr tantalum capacitor may also be used. when selecting ceramic capacitors, x5r or x7r type dielectric ceramic capacitors should be used for their better temperature and voltage characteristics. note that the ripple current rating from capacitor manu- f actures are based on certain amount of life time. further de-rating may be necessary in practical design. inductor the inductor is used to supply constant current to output when it is driven by a switching voltage. for given input and output voltage, inductance and switching frequency together decide the inductor ripple current, which is: the peak inductor current is: high inductance gives low inductor ripple current but requires larger size inductor to avoid saturation. low r ipple current reduces inductor core losses. it also reduces rms current through inductor and switches, which results in less conduction loss. usually, peak to peak ripple current on inductor is designed to be 20% to 30% of output current. when selecting the inductor, make sure it is able to handle the peak current without saturation even at the highest operating temperature. the inductor takes the highest current in a buck circuit. the conduction loss on inductor need to be checked for thermal and ef?iency requirements. surface mount inductors in different shape and styles are av ailable from coilcraft, elytone and murata. shielded inductors are small and radiate less emi noise. but they cost more than unshielded inductors. the choice depends on emi requirement, price and size. output capacitor the output capacitor is selected based on the dc output v oltage rating, output ripple voltage speci?ation and r ipple current rating. the selected output capacitor must have a higher rated v oltage speci?ation than the maximum desired output v oltage including ripple. de-rating needs to be consid- ered for long term reliability. output ripple voltage speci?ation is another important f actor for selecting the output capacitor. in a buck con- ve r ter circuit, output ripple voltage is determined by inductor value, switching frequency, output capacitor v alue and esr. it can be calculated by the equation below: where, c o is output capacitor value, and esr co is the equivalent series resistance of the output capacitor. when low esr ceramic capacitor is used as output capacitor, the impedance of the capacitor at the switching frequency dominates. output ripple is mainly caused by capacitor value and inductor ripple current. the output r ipple voltage calculation can be simpli?d to: if the impedance of esr at switching frequency dominates, the output ripple voltage is mainly decided by capacitor esr and inductor ripple current. the output r ipple voltage calculation can be further simpli?d to: f or lower output ripple voltage across the entire operat- ing temperature range, x5r or x7r dielectric type of ceramic, or other low esr tantalum are recommended to be used as output capacitors. in a buck converter, output capacitor current is continuous. the rms current of output capacitor is decided by the peak to peak inductor ripple current. it can be calculated by: usually, the ripple current rating of the output capacitor is a smaller issue because of the low current stress. when the buck inductor is selected to be very small and induc- tor ripple current is high, the output capacitor could be ov erstressed. ? i l v o fl ----------- - 1 v o v in ---------- ?? ?? ?? = i lpeak i o ? i l 2 -------- - + = ? v o ? i l esr co 1 8 fc o -------------------------- - + ?? ?? = ? v o ? i l 1 8 fc o -------------------------- - ?? ?? = ? v o ? i l esr co = i co_rms ? i l 12 ---------- =
a oz1073 rev. 1.1 september 2008 www.aosmd.com page 10 of 15 loop compensation the AOZ1073 employs peak current mode control for easy use and fast transient response. peak current mode control eliminates the double pole effect of the output l&c ?ter. it greatly simpli?s the compensation loop design. with peak current mode control, the buck power stage can be simpli?d to be a one-pole and one-zero system in frequency domain. the pole is the dominant pole can be calculated by: the zero is an esr zero due to output capacitor and its esr. it is can be calculated by: where; c o is the output ?ter capacitor, r l is load resistor value, and esr co is the equivalent series resistance of output capacitor. the compensation design is actually to shape the converter control loop transfer function to get the desired gain and phase. several different types of compensation network can be used for the AOZ1073. in most cases, a series capacitor and resistor network connected to the comp pin sets the pole-zero and is adequate for a stable high-bandwidth control loop. in the AOZ1073, fb pin and comp pin are the inverting input and the output of internal error ampli?r. a series r and c compensation network connected to comp provides one pole and one zero. the pole is: where; g ea is the error ampli?r transconductance, which is 200 x 10 -6 a/v, g vea is the error ampli?r voltage; and c 2 is compensation capacitor in figure 1. the zero given by the external compensation network, capacitor c 2 and resistor r 3 , is located at: to design the compensation circuit, a target crossover frequency f c f or close loop must be selected. the system crossover frequency is where control loop has unity gain. the crossover is the also called the converter bandwidth. generally a higher bandwidth means faster response to load transient. however, the bandwidth should not be too high because of system stability concern. when design- ing the compensation loop, converter stability under all line and load condition must be considered. usually, it is recommended to set the bandwidth to be equal or less than 1/10 of switching frequency. the a oz1073 operates at a frequency range from 350khz to 600khz. it is recommended to choose a crossover frequency equal or less than 40khz. the strategy for choosing r c and c c is to set the cross over frequency with r c and set the compensator z ero with c c . using selected crossover frequency, f c , to calculate r 3 : where; where f c is desired crossover frequency. for best performance, f c is set to be about 1/10 of switching frequency, v fb is 0.8v, g ea is the error ampli?r transconductance, which is 200 x 10 -6 a/v, and g cs is the current sense circuit transconductance, which is 6.68 a/v the compensation capacitor c c and resistor r c together make a zero. this zero is put somewhere close to the dominate pole f p1 but lower than 1/5 of selected crossover frequency. c 2 can is selected by: the above equation can be simpli?d to: an easy-to-use application software which helps to design and simulate the compensation loop can be found at www .aosmd.com . f p 1 1 2 c o r l ----------------------------------- - = f z 1 1 2 c o esr co ------------------------------------------------- - = f p 2 g ea 2 c c g vea ------------------------------------------- = f z 2 1 2 c c r c ------------------------------------ - = f c 40 khz = r c f c v o v fb ----------- 2 c 2 g ea g cs ------------------------------ = c c 1.5 2 r 3 f p 1 ----------------------------------- = c c c o r l r 3 ---------------------- =
a oz1073 rev. 1.1 september 2008 www.aosmd.com page 11 of 15 thermal management and layout consideration in the AOZ1073 buck regulator circuit, high pulsing current ?ws through two circuit loops. the ?st loop starts from the input capacitors, to the v in pin, to the lx pins, to the ?ter inductor, to the output capacitor and load, and then return to the input capacitor through g round. current ?ws in the ?st loop when the high side s witch is on. the second loop starts from inductor, to the output capacitors and load, to the anode of schottky diode, to the cathode of schottky diode. current ?ws in the second loop when the low side diode is on. in pcb layout, minimizing the two loops area reduces the noise of this circuit and improves ef?iency. a ground plane is strongly recommended to connect input capaci- tor, output capacitor, and pgnd pin of the AOZ1073. in the AOZ1073 buck regulator circuit, the major power dissipating components are the AOZ1073 and the output inductor. the total power dissipation of converter circuit can be measured by input power minus output power. the power dissipation of inductor can be approximately calculated by output current and dcr of inductor. the actual junction temperature can be calculated with power dissipation in the AOZ1073 and thermal imped- ance from junction to ambient. the maximum junction temperature of AOZ1073 is 150?, which limits the maximum load current capability. please see the thermal de-rating curves for maximum load current of the AOZ1073 under different ambient temperature. the thermal performance of the AOZ1073 is strongly affected by the pcb layout. extra care should be taken by users during design process to ensure that the ic will operate under the recommended environmental conditions. the AOZ1073 is a standard so-8 package. layout tips are listed below for the best electric and thermal performance. figure 3 illustrates a pcb layout example of the AOZ1073. 1. do not use thermal relief connection to the v in and the pgnd pin. pour a maximized copper area to the pgnd pin and the vin pin to help thermal dissipation. 2. input capacitor should be connected as close as possible to the v in pin and the pgnd pin. 3. a ground plane is suggested. if a ground plane is not used, separate pgnd from agnd and connect them only at one point to avoid the pgnd pin noise coupling to the agnd pin. 4. make the current trace from the lx pins to l to c o to the pgnd as short as possible. 5. pour copper plane on all unused board area and connect it to stable dc nodes, like v in , gnd or v out . 6. the lx pins are connected to internal pfet drain. they are a low resistance thermal conduction path and the most noisy switching node. connect a copper plane to the lx pins to help thermal dissipation. this copper plane should not be too large otherwise switching noise may be coupled to other parts of the circuit. 7. keep sensitive signal traces far away from the lx pins. p total _loss v in i in v o i o = p inductor _loss i o 2 r inductor 1.1 = t junction p total _loss p inductor _loss () ja =
a oz1073 rev. 1.1 september 2008 www.aosmd.com page 12 of 15 figure 3. AOZ1073 (so-8) pcb layout pgnd vin agnd fb r2 c1 cd c2 cc rc c3 r1 l1 8 7 6 5 1 2 3 4 lx lx en comp vo
a oz1073 rev. 1.1 september 2008 www.aosmd.com page 13 of 15 pa ck ag e dimensions, so-8l notes: 1. all dimensions are in millimeters. 2. dimensions are inclusive of plating 3. package body sizes exclude mold flash and gate burrs. mold flash at the non-lead sides should be less than 6 mils. 4. dimension l is measured in gauge plane. 5. controlling dimension is millimeter, converted inch dimensions are not necessarily exact. symbols a a1 a2 b c d e1 e e h l dimensions in millimeters min. 1.35 0.10 1.25 0.31 0.17 4.80 3.80 5.80 0.25 0.40 0 d c l h x 45 7 (4x) b 2.20 5.74 0.80 unit: mm 1.27 a1 a2 a 0.1 gauge plane seating plane 0.25 e 8 1 e1 e nom. 1.65 ? 1.50 ? ? 4.90 3.90 1.27 bsc 6.00 ? ? ? max. 1.75 0.25 1.65 0.51 0.25 5.00 4.00 6.20 0.50 1.27 8 symbols a a1 a2 b c d e1 e e h l dimensions in inches min. 0.053 0.004 0.049 0.012 0.007 0.189 0.150 0.228 0.010 0.016 0 nom. 0.065 ? 0.059 ? ? 0.193 0.154 0.050 bsc 0.236 ? ? ? max. 0.069 0.010 0.065 0.020 0.010 0.197 0.157 0.244 0.020 0.050 8
a oz1073 rev. 1.1 september 2008 www.aosmd.com page 14 of 15 t ape and reel dimensions so-8 carrier tape so-8 reel so-8 tape leader/trailer & orientation tape size 12mm reel size ?330 m ?330.00 0.50 package so-8 (12mm) a0 6.40 0.10 b0 5.20 0.10 k0 2.10 0.10 d0 1.60 0.10 d1 1.50 0.10 e 12.00 0.10 e1 1.75 0.10 e2 5.50 0.10 p0 8.00 0.10 p1 4.00 0.10 p2 2.00 0.10 t 0.25 0.10 n ?97.00 0.10 k0 unit: mm b0 g m w1 s k h n w v r trailer tape 300mm min. or 75 empty pockets components tape orientation in pocket leader tape 500mm min. or 125 empty pockets a0 p1 p2 see note 5 see note 3 see note 3 feeding direction p0 e2 e1 e d0 t d1 w 13.00 0.30 w1 17.40 1.00 h ?13.00 +0.50/-0.20 k 10.60 s 2.00 0.50 g ? r ? v ?
a oz1073 rev. 1.1 september 2008 www.aosmd.com page 15 of 15 pa ck ag e marking AOZ1073ail (underlined, halogen free) z1073ai fay part number code assembly lot code fab & assembly location year & week code wlt as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose f ailure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a signi?ant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. this data sheet contains preliminary data; supplementary data may be published at a later date. alpha & omega semiconductor reserves the right to make changes at any time without notice. life support policy alpha & omega semiconductor products are not authorized for use as critical components in life support devices or systems.

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