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nxp semiconductors data sheet: technical data document number: imxrt1050iec rev. 1, 03/2018 mimxrt1051cvl5a mimxrt1052cvl5a mimxrt1051cvl5b MIMXRT1052CVL5B package information plastic package 196-pin mapbga, 10 x 10 mm, 0.65 mm pitch ordering information see table 1 on page 5 ? 2017-2018 nxp semiconductors. all rights reserved. 1 i.mx rt1050 introduction the i.mx rt1050 is a new processor family featuring nxp?s advanced implementation of the arm cortex ? -m7 core, which operates at speeds up to 528 mhz to provide high cpu performance and best real-time response. the i.mx rt1050 processor has 512 kb on-chip ram, which can be flexibly configured as tcm or general-purpose on-chip ram. the i.mx rt1050 integrates advanced power management module with dcdc and ldo that reduces complexity of external power supply and simplifies power sequencing. the i.mx rt1050 also provides va rious memory interfaces, including sdram, raw nand flash, nor flash, sd/emmc, quad spi, and a wide range of other interfaces for connecti ng peripherals, such as wlan, bluetooth?, gps, displays, and camera sensors. the i.mx rt1050 also has rich audio and video features, including lcd display, basic 2d graphics, camera interface, spdif, and i2s audio interface. i.mx rt1050 crossover processors for industrial products 1. i.mx rt1050 introduction . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1. features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2. ordering information . . . . . . . . . . . . . . . . . . . . . . . 5 2. architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3. modules list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1. special signal considerations . . . . . . . . . . . . . . . 14 3.2. recommended connections for unused analog interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1. chip-level conditions . . . . . . . . . . . . . . . . . . . . . . 17 4.2. system power and clocks . . . . . . . . . . . . . . . . . . 23 4.3. i/o parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.4. system modules . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.5. external memory interface . . . . . . . . . . . . . . . . . 38 4.6. display and graphics . . . . . . . . . . . . . . . . . . . . . . 48 4.7. audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.8. analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4.9. communication interfaces . . . . . . . . . . . . . . . . . . 60 4.10. timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5. boot mode configuration . . . . . . . . . . . . . . . . . . . . . . . . 75 5.1. boot mode configuration pins . . . . . . . . . . . . . . . 75 5.2. boot device interface allocation . . . . . . . . . . . . . . 75 6. package information and contact assignments . . . . . . . 80 6.1. 10 x 10 mm package information . . . . . . . . . . . . 80 7. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 2 nxp semiconductors i.mx rt1050 introduction the i.mx rt1050 is specifically us eful for applications such as: ? industrial human machine interfaces (hmi) ? motor control ? home appliance 1.1 features the i.mx rt1050 processors ar e based on arm cortex-m7 mpcore? platform, which has the following features: ? supports single arm cortex-m7 mpcore with: ? 32 kb l1 instruction cache ? 32 kb l1 data cache ? full featured floating point unit (fpu ) with support of the vfpv5 architecture ? support the armv7-m thumb instruction set ? integrated mpu, up to 16 individual protection regions ? up to 512 kb i-tcm and d-tcm in total ? frequency of 528 mhz ? cortex m7 coresight? components integration for debug ? frequency of the core, as per table 9, "operating ranges," on page 19 . the soc-level memory system consists of the following a dditional components: ? boot rom (96 kb) ? on-chip ram (512 kb) ? configurable ram size up to 512 kb shared with m7 tcm ? external memory interfaces: ? 8/16-bit sdram, up to sdram-166 ? 8/16-bit slc nand flash, with ecc handled in software ?sd/emmc ? spi nor flash ? parallel nor flas h with xip support ? single/dual channel quad spi flash with xip support ? timers and pwms: ? two general programmable timers (gpt) ? 4-channel generic 32-bit resolution timer ? each support standard capture and compare operation ? four periodical inte rrupt timer (pit) ? generic 16-bit resolution timer ? periodical interrupt generation ? four quad timers (qtimer)
i.mx rt1050 introduction i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 nxp semiconductors 3 ? 4-channel generic 16-bit resolution timer for each ? each support standard capture and compare operation ? quadrature decoder integrated ? four flexpwms ? up to 8 individual pwm channels for each ? 16-bit resolution pwm suitable for motor control applications ? four quadrature encoder/decoders each i.mx rt1050 processor enables the following inte rfaces to external devi ces (some of them are muxed and not available simultaneously): ? display interface: ? parallel rgb lcd interface ? support 8/16/24 bit interface ? support up to 1366 x 768 wxga resolution ? support index color with 256 entry x 24 bit color lut ? smart lcd display with 8/16-bit mpu/8080 interface ? audio: ? s/pdif input and output ? three synchronous audio in terface (sai) modules suppor ting i2s, ac97, tdm, and codec/dsp interfaces ? mqs interface for medium quality audio via gpio pads ? generic 2d graphics engine: ? bitblit ? flexible image composition options?alpha, chroma key ? image rotation (90 ? , 180 ? , 270 ? ) ? porter-daff operation ? image size ? color space conversion ? multiple pixel format support (rgb, yuv444, yuv422, yuv420, yuv400) ? standard 2d-dma operation ? camera sensors: ? support 24-bit, 16-bit, and 8-bit csi input ? connectivity: ? two usb 2.0 otg controllers wi th integrated phy interfaces ? two ultra secure digital host controller (usdhc) interfaces ? mmc 4.5 compliance with hs200 support up to 200 mb/sec ? sd/sdio 3.0 compliance with 200 mhz sd r signaling to support up to 100 mb/sec ? support for sdxc (extended capacity)
i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 4 nxp semiconductors i.mx rt1050 introduction ? one 10/100 m ethernet controller with support for ieee1588 ? eight universal async hronous receiver/transm itter (uarts) modules ? four i2c modules ? four spi modules ? two flexcan modules ? gpio and pin multiplexing: ? general-purpose input/output (gpio) modules with interrupt capability ? input/output multiplexing cont roller (iomuxc) to provide centralized pad control ?two flexios the i.mx rt1050 processors integrate advanc ed power management unit and controllers: ? full pmic integration. on-chip dcdc and ldo ? temperature sensor with programmable trip points ? gpc hardware power management controller the i.mx rt1050 processors s upport the following system debug: ? arm coresight debug and trace architecture ? trace port interface unit (tpiu) to support off-chip real-time trace ? support for 5-pin (jtag) and swd debug interfaces selected by efuse security functions are enabled and accelerated by the following hardware: ? high assurance boot (hab) ? data co-processor (dcp): ? aes-128, ecb, and cbc mode ? sha-1 and sha-256 ? crc-32 ? bus encryption engine (bee) ? aes-128, ecb, and ctr mode ? on-the-fly qspi flash decryption ? true random number generation (trng) ? secure non-volatile storage (snvs) ? secure real-time clock (rtc) ? zero master key (zmk) ? secure jtag controller (sjc) note the actual feature set depends on th e part numbers as described in table 1. functions such as display and camer a interfaces, connectivity interfaces, and security features are not offered on all derivatives.
i.mx rt1050 introduction i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 nxp semiconductors 5 1.2 ordering information table 1 provides examples of or derable part numbers covered by this data sheet. figure 1 describes the part number nomencl ature so that characteristics of a specific part number can be identified (for example, cores, frequency, temper ature grade, fuse options, and silicon revision). the primary characteristic which describe s which data sheet applies to a spec ific part is the temperature grade (junction) field. ? the i.mx rt1050 crossover processors for industrial products data sheet (imxrt1050iec) covers parts listed with a ?c (industrial temp)? ensure to have the proper data sheet for specific pa rt by verifying the temperat ure grade (junction) field and matching it to the proper data sheet. if there are any questions, vi sit the web page nxp.com/imxrtseries or contact an nxp repr esentative for details. table 1. ordering information part number feature package junction temperature t j ( ? c) mimxrt1051cvl5a mimxrt1051cvl5b features supports: ? 528 mhz, industrial grade for general purpose ? no lcd/pxp/csi ?can x2 ? ethernet ? emmc 4.5/sd 3.0 x2 ? usb otg x2 ?uart x8 ? sai x3 ?timer x4 ?pwm x4 ?i 2 c x4 ? spi x4 10 x 10 mm, 0.65 pitch, 196 mapbga -40 to +105 ? c mimxrt1052cvl5a MIMXRT1052CVL5B features supports: ? 528 mhz, industrial grade for general purpose ? with lcd/csi/pxp ?can x2 ? ethernet ? emmc 4.5/sd 3.0 x2 ? usb otg x2 ?uart x8 ? sai x3 ?timer x4 ?pwm x4 ?i 2 c x4 ? spi x4 10 x 10 mm, 0.65 pitch, 196 mapbga -40 to +105 ? c
i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 6 nxp semiconductors i.mx rt1050 introduction figure 1. part number nomenclature?i.mx rt1050 temperature + consumer: 0 to + 95 c d industrial: -40 to +105 c c frequency $ 400 mhz 4 500 mhz 5 600 mhz 6 700 mhz 7 800 mhz 8 1000 mhz a vv package type vl mapbga 10 x 10 mm, 0.65 mm qualification level m prototype samples p mass production m special s part # series xx i.mx rt rt silicon rev a a0 (maskset id: 00n04v) a a1 (maskset id: 01n04v) b tie % 1 reduced feature general purpose 2 full feature general purpose m imx x x @ % + vv $ a family @ first generation rt family 1 reserved 2 3 4 5 6 7 8 ## sub-family ## 02 rt1020 05 rt1050
architectural overview i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 nxp semiconductors 7 2 architectural overview the following subsections provide an architectural overview of th e i.mx rt1050 processor system. 2.1 block diagram figure 2 shows the functional modules in the i.mx rt1050 processor system 1 . . figure 2. i.mx rt1050 system block diagram 1. some modules shown in this block diagram are not offered on all derivatives. see ta b l e 1 for details. /v??vodu}?? ??<kzd ?z?]?zdd ?<zkd do?]u] }vv?]]?? ddex?l^?x?? ???<?? ???vodu}?? /??e hzd?? ^lw/&d?lz? 'w/k ^w/?e l ^???u}v??}o ^?:d' w>>lk^ zdvz?? vzvd /kdhy 'wd]u?? whwo?(}?u ?u}???rd ??</rz ??<rz &wh &o?^w/~orzvvoy^w/ ???vodu}??}v??}oo? ?r]?lr]?^zd w?oooekz&>^, ee&>^, w^zd dwh es/ h??}??<dd &o?e?? h^?xkd']?zw,z?? led ]?z/???? ~rzvvo?? dw?e ?ll?er]?w?ooo^/ ?er]?w?ooo> ?u } ?? ?rd ? ?</r z ??<r z & w h d w h es/ h ? ?}??<d d wyw ?'??z]?o??]}v z?]u^uk?o?uz}??]}v y???e?e yd]u? &o?wtd t?z}p?e w}?dvpuv? >k du?d}v]?}? ^?]?? ]?z??vze' ^?zd &? , /?^l^/?? ~erzvvo?e eevekzuk?o&o?zuvzd ~?rzvvo?e
i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 8 nxp semiconductors modules list 3 modules list the i.mx rt1050 processors contain a va riety of digital and analog modules. table 2 describes these modules in alphabetical order. table 2. i.mx rt1050 modules list block mnemonic block name subsystem brief description acmp1 acmp2 acmp3 acmp4 analog comparator analog the comparator (c mp) provides a circuit for comparing two analog input voltages. the comparator circuit is designed to operate across th e full range of the supply voltage (rail-to-rail operation). adc1 adc2 analog to digital converter analog the adc is a 12-bit general purpose analog to digital converter. aoi and-or-inverter cross trigger the aoi provides a universal boolean function generator using a four team sum of products expression with each product term containing true or complement values of the four selected inputs (a, b, c, d). arm arm platform arm the arm core platfo rm includes one cortex-m7 core. it includes associat ed sub-blocks, such as nested vectored interrupt controller (nvic), floating-point unit (fpu), memory prot ection unit (mpu), and coresight debug modules. bee bus encryption engine security on -the-fly flexspi flash decryption ccm gpc src clock control module, general power controller, system reset controller clocks, resets, and power control these modules are responsible for clock and reset distribution in the system, and also for the system power management. csi parallel csi multimedia peripherals the csi ip provides parallel csi standard camera interface port. the csi parallel data ports are up to 24 bits. it is designed to support 24-bit rgb888/yuv444, ccir656 video interface, 8-bit ycbcr, yuv or rgb, and 8-bit/10-bit/16-bit bayer data input. csu central security unit security the central security unit (csu) is responsible for setting comprehensive security policy within the i.mx rt1050 platform. dap debug access port system control peripherals the dap provides real-time access for the debugger without halting the core to: ? system memory and peripheral registers ? all debug configuration registers the dap also provides debugger access to jtag scan chains. the dap module is internal to the cortex-m7 core platform.
modules list i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 nxp semiconductors 9 dcdc dcdc converter analog the dcdc module is used for generating power supply for core logic. main features are: ? adjustable high efficiency regulator ? supports 3.0 v input voltage for a0 and 3.3 v input voltage for a1 ? supports nominal run and low power standby modes ? supports at 0.9 ~ 1.3 v output in run mode ? supports at 0.9 ~ 1.0 v output in standby mode ? over current and over voltage detection edma enhanced direct memory access system control peripherals there is an enhanced dma (edma) engine and two dma_mux. ? the edma is a 32 channel dma engine, which is capable of performing complex data transfers with minimal intervention from a host processor. ? the dma_mux is capable of multiplexing up to 128 dma request sources to the 32 dma channels of edma. enc quadrature encoder/decoder timer peripherals the enhanced quadrature encoder/decoder module provides interfacing capability to position/speed sensors. there are five input sign als: phasea, phaseb, index, trigger, and home. this module is used to decode shaft position, revolution count, and speed. enet ethernet controller connectivity peripherals the ethernet media access controller (mac) is designed to suppor t 10/100 mbit/s et hernet/ieee 802.3 networks. an external transceiver interface and transceiver function are required to complete the interface to the media. the module has dedicated hardware to support the ieee 1588 standar d. see the enet chapter of the refe rence manual for details. ewm external watchdog monitor timer peripherals the ewm modules is designed to monitor external circuits, as well as the software flow. this provides a back-up mechanism to the internal wdog that can reset the system. the ewm differs from the internal wdog in that it does not reset the system. the ewm, if allowed to time-out, provides an independent trigger pin that when asserted resets or places an external circuit into a safe mode. flexcan1 flexcan2 flexible controller area network connectivity peripherals the can protocol was primarily, but not only, designed to be used as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in the electromagnetic interference (emi) environment of a vehicle, cost-effectiveness and required bandwidth. the flexcan module is a full implementation of the can protocol specification, version 2.0 b, which supp orts both standard and extended message frames. table 2. i.mx rt1050 modules list (continued) block mnemonic block name subsystem brief description
i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 10 nxp semiconductors modules list flexio1 flexio2 flexible input/output connectivity and communications the flexio is capable of supporting a wide range of protocols including, but not limited to: uart, i2c, spi, i2s, camera interface, display interface, pwm waveform generation, etc. the module can remain functional when the chip is in a low power mode provided the clock it is using remain active. flexpwm1 flexpwm2 flexpwm3 flexpwm4 pulse width modulation timer peripherals the pulse-width modulator (pwm) contains four pwm sub-modules, each of which is set up to control a single half-bridge power stage. fault channel support is provided. the pwm module can generate various switching patterns, including highly sophisticated waveforms. flexram ram memories the i.mx rt1050 has 512 kb of on-chip ram which could be flexible allocat ed to i-tcm, d-tcm, and on-chip ram (ocram) in a 32 kb granularity. the flexram is the manager of the 512 kb on-chip ram array. major functions of this blocks are: interfacing to i-tcm and d-tcm of arm core and ocram controller; dynamic ram arrays allocati on for i-tcm, d-tcm, and ocram. flexspi quad serial peripheral interface connectivity and communications flexspi acts as an interface to one or two external serial flash devices, each with up to four bidirectional data lines. gpio1 gpio2 gpio3 gpio4 gpio5 general purpose i/o modules system control peripherals used for general purpose input/output to external ics. each gpio module supports up to 32 bits of i/o. gpt1 gpt2 general purpose timer timer peripherals each gpt is a 32-bit ?free-running? or ?set and forget? mode timer with programmable prescaler and compare and capture register. a timer counter value can be captured using an external ev ent and can be configured to trigger a capture event on either the leading or trailing edges of an input pulse. when the timer is configured to operate in ?set and forget ? mode, it is capable of providing precise interrupts at regular intervals with minimal processor interventio n. the counter has output compare logic to provide the status and interrupt at comparison. this timer can be configured to run either on an external clock or on an internal clock. kpp keypad port human machine interfaces the kpp is a 16-bit peripheral that can be used as a keypad matrix interface or as general purpose input/output (i/o). it suppor ts 8 x 8 external key pad matrix. main features are: ? multiple-key detection ? long key-press detection ? standby key-press detection ? supports a 2-point and 3-point contact key matrix table 2. i.mx rt1050 modules list (continued) block mnemonic block name subsystem brief description
modules list i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 nxp semiconductors 11 lcdif lcd interface multimedia peripherals the lcdif is a general purpose display controller used to drive a wide range of display devices varying in size and capabilities. the lcdif is designed to support dumb (synchronous 24-bit parallel rgb interface) and smart (asynchronous parallel mpu interface) lcd devices. lpi2c1 lpi2c2 lpi2c3 lpi2c4 low power inter-integrated circuit connectivity and communications the lpi2c is a low power inter-integrated circuit (i2c) module that supports an effi cient interface to an i2c bus as a master. the i2c provides a method of communication between a number of external devices. more detailed information, see section 4.9.2, ?lpi2c module timing parameters . lpspi1 lpspi2 lpspi3 lpspi4 low power serial peripheral interface connectivity and communications the lpspi is a low power se rial peripheral interface (spi) module that support an efficient interface to an spi bus as a master and/or a slave. ? it can continue operating while the chip is in stop modes, if an appropriate clock is available ? designed for low cpu overhead, with dma off loading of fifo register access lpuart1 lpuart2 lpuart3 lpuart4 lpuart5 lpuart6 lpuart7 lpuart8 uart interface connectivity peripherals each of the uart modules support the following serial data transmit/receive protocols and configurations: ? 7- or 8-bit data words, 1 or 2 stop bits, programmable parity (even, odd or none) ? programmable baud rates up to 5 mbps. mqs medium quality sound multimedia peripherals mqs is used to generate 2-channel medium quality pwm-like audio via two standard digital gpio pins. pxp pixel processing pipeline multimedia peripherals a high-performance pixel processor capable of 1 pixel/clock performance for combined operations, such as color-space conversion, alpha blending, and rotation. the pxp is enhanced with features specif ically for gray scale applications. in addition, the pxp supports traditional pixel/frame processing paths for still-image and video processing applications. quadtimer1 quadtimer2 quadtimer3 quadtimer4 quadtimer timer peripherals the quad-timer provides four time channels with a variety of controls affecting both individual and multi-channel features.specific features include up/down count, cascading of counters, programmable module, count once/repeat ed, counter preload, compare registers with preload, shared use of input signals, prescaler controls, independent capture/compare, fault input control, programmable input filters, and multi-channel synchronization. table 2. i.mx rt1050 modules list (continued) block mnemonic block name subsystem brief description
i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 12 nxp semiconductors modules list romcp rom controller with patch memories and memory controllers the romcp acts as an interface between the arm advanced high-performance bus and the rom. the on-chip rom is only used by the cortex-m7 core during boot up. size of the rom is 96 kb. rtc osc real time clock oscillator clock sources and control the rtc osc provides the clock source for the real-time clock module. the rtc osc module, in conjunction with an external crystal, generates a 32.678 khz reference clock for the rtc. rtwdog watch dog timer peripherals the rtwdg module is a high reliability independent timer that is available for system to use. it provides a safety feature to ensure software is executing as planned and the cpu is not stuck in an infinite loop or executing unintended code. if the wdog module is not serviced (refreshed) within a certain period, it resets the mcu. windowed refresh mode is supported as well. sai1 sai2 sai3 synchronous audio interface multimedia peripherals the sai module provides a synchronous audio interface (sai) that supports full duplex serial interfaces with frame synchronization, such as i2s, ac97, tdm, and codec/dsp interfaces. sa-trng standalone true random number generator security the sa-trng is hardware accelerator that generates a 512-bit entropy as needed by an entropy consuming module or by other post processing functions. semc smart external memory controller memory and memory controller the semc is a multi-standard memory controller optimized for both high-performance and low pin-count. it can support multiple external memories in the same application with shared address and data pins. the interface supported incl udes sdram, nor flash, sram, and nand flash, as well as 8080 display interface. sjc system jtag contro ller system control peripherals the sjc provides jtag interface, which complies with jtag tap standards, to internal logic. the i.mx rt1050 processors use jtag port for production, testing, and system debugging. in addition, the sjc provides bsr (boundary scan register) standard support, which complies with ieee 1149.1 and ieee 1149.6 standards. the jtag port is accessible during platform initial laboratory bring-up, for manufacturing tests and troubleshooting, as well as for software debugging by authorized entities. the i.mx rt1050 sjc incorporates three security modes for protecting against unauthorized accesses. modes are selected through efuse configuration. snvs secure non-volatile storage security secure non-volatile storage, including secure real time clock, security state machine, master key control, and violation/tamper detection and reporting. table 2. i.mx rt1050 modules list (continued) block mnemonic block name subsystem brief description
modules list i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 nxp semiconductors 13 spdif sony philips digital interconnect format multimedia peripherals a standard audio file transfer format, developed jointly by the sony and phillips corporations. has transmitter and receiver functionality. temp monitor temperature monitor analog the te mperature sensor implements a temperature sensor/conversion function based on a temperature-dependent voltage to time conversion. tsc touch screen human machine interfaces with touch controller to support 4-wire and 5-wire resistive touch panel. usbo2 universal serial bus 2.0 connectivity peripherals usbo2 (usb otg1 and usb otg2) contains: ? two high-speed otg 2.0 modules with integrated hs usb phys ? support eight transmit (tx) and eight receive (rx) endpoints, including endpoint 0 usdhc1 usdhc2 sd/mmc and sdxc enhanced multi-media card / secure digital host controller connectivity peripherals i.mx rt1050 specific soc characteristics: all four mmc/sd/sdio contro ller ips are identical and are based on the usdhc ip. they are: ? fully compliant with mmc command/response sets and physical layer as defined in the multimedia card system specification, v4.5/4.2/4.3/4.4/4.41/ including high-capacity (size > 2 gb) cards hc mmc. ? fully compliant with sd command/response sets and physical layer as defined in the sd memory card specifications, v3.0 including high-capacity sdxc cards up to 2 tb. ? fully compliant with sdio command/response sets and interrupt/read-wait mode as defined in the sdio card specification, part e1, v3.0 two ports support: ? 1-bit or 4-bit transfer m ode specifications for sd and sdio cards up to uhs-i sdr104 mode (104 mb/s max) ? 1-bit, 4-bit, or 8-bit transfer mode specifications for mmc cards up to 52 mhz in both sdr and ddr modes (104 mb/s max) ? 4-bit or 8-bit transfer mode specifications for emmc chips up to 200 mhz in hs200 mode (200 mb/s max) wdog1 wdog2 watch dog timer peripherals the watchdog (wdog) timer supports two comparison points during each counting period. each of the comparison points is configurable to evoke an interrupt to the arm core, and a second point evokes an external event on the wdog line. xbar cross bar cross trigger each crossbar s witch is an array of muxes with shared inputs. each mux output provides one output of the crossbar. the number of inputs and the number of muxes/outputs are user conf igurable and registers are provided to select which of the shared inputs are routed to each output. table 2. i.mx rt1050 modules list (continued) block mnemonic block name subsystem brief description
i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 14 nxp semiconductors modules list 3.1 special signal considerations table 3 lists special signal considerati ons for the i.mx rt1050 processors . the signal names are listed in alphabetical order. the package contact assign ments can be found in section 6, ?package information and contact assignments.? signal descriptions are provided in the i.mx rt1050 reference manual (imxrt1050_rm). table 3. special signal considerations signal name remarks ccm_clk1_p/ ccm_clk1_n one general purpose differential high speed clock input/output (lvds i/o) is provided. it can be used: ? to feed external reference clock to the plls and further to the modules inside soc. ? to output internal soc clock to be used outs ide the soc as either reference clock or as a functional clock for peripherals. see the i.mx rt1050 reference manual (imx6ulrm) for details on the respective clock trees. alternatively one may use single ended signal to drive clk1_p input. in this case corresponding clk1_n input should be tied to the constant voltage level equal 1/2 of the input signal swing. termination should be provided in case of high frequency signals. after initialization, the clk1 input/output can be di sabled (if not used). if unused either or both of the clk1_n/p pairs may remain unconnected. dcdc_pswitch pad is in dcdc_in domain and connected the ground to bypass dcdc. to enable dcdc function, assert to dcdc_in with at least 1ms delay for dcdc_in rising edge. rtc_xtali/rtc_xtalo if the user wishes to configure rt c_xtali and rtc_xtalo as an rtc oscillator, a 32.768 khz crystal, ( ? 100 k ? esr, 10 pf load) should be connected between rtc_xtali and rtc_xtalo. keep in mind the capacitors implemented on either side of the crystal are about twice the crystal load capacitor. to hit the exact oscillation frequency, the board capacitors need to be reduced to account for board and chip parasitics. the integrat ed oscillation amplifier is self biasing, but relatively weak. care must be taken to limit parasitic leakage from rtc_xtali and rtc_xtalo to either power or ground (>100 m ? ). this will debias the amplifier and cause a reduction of startup margin. typically rtc_xtali and rtc_xtalo should bias to approximately 0.5 v. if it is desired to feed an external low frequ ency clock into rtc_xtali the rtc_xtalo pin must remain unconnected or driven with a complimentary signal. the logic level of this forcing clock should not exceed vdd_snvs_cap level and the frequency should be <100 khz under typical conditions. in case when high accuracy real time clock are not required system may use internal low frequency ring oscillator. it is recommended to connect rtc_xtali to gnd and keep rtc_xtalo unconnected. xtali/xtalo a 24.0 mhz crystal should be connected between xtali and xtalo. the crystal must be rated for a maximum drive level of 250 ? w. an esr (equivalent series resistance) of typical 80 ? is recommended. nxp sdk software requires 24 mhz on xtali/xtalo. the crystal can be eliminated if an external 24 mh z oscillator is available in the system. in this case, xtalo must be directly driven by the ex ternal oscillator and xtali mounted with 18 pf capacitor. the logic level of this forcing clock cannot exceed nvcc_pll level. if this clock is used as a reference for usb, t hen there are strict frequency tolerance and jitter requirements. see osc24m chapter and relevant interface specif ications chapters for details. gpanaio this signal is reserved for nxp manufacturing use only. this output must remain unconnected.
modules list i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 nxp semiconductors 15 3.2 recommended connections for unused analog interfaces table 5 shows the recommended connecti ons for unused analog interfaces. jtag_ nnnn the jtag interface is summarized in table 4 . use of external resistors is unnecessary. however, if external resistors are used, the user must ensure that the on-chip pull-up/down configuration is followed. for example, do not use an external pull down on an input that has on-chip pull-up. jtag_tdo is configured with a keeper circuit such that the non-connected c ondition is eliminated if an external pull resistor is not present. an exte rnal pull resistor on jtag_tdo is detrimental and should be avoided. jtag_mod is referenced as sjc_mod in the i.mx rt1050 reference manual. both names refer to the same signal. jtag_mod must be extern ally connected to gnd for normal operation. termination to gnd through an external pull-down resistor (such as 1 k ? ) is allowed. jtag_mod set to hi configures the jtag interface to m ode compliant with ieee11 49.1 standard. jtag_mod set to low configures the jtag interface for common sw debug adding all the system taps to the chain. nc these signals are no connect (nc) and should be disconnected by the user. por_b this cold reset negative logic input resets all modules and logic in the ic. may be used in addition to internally generated power on reset signal (logical and, both internal and external signals are considered active low). onoff onoff can be configured in de bounce, off to on time, and max time-out configurations. the debounce and off to on time configurations suppor ts 0, 50, 100 and 500 ms. debounce is used to generate the power off interrupt. while in the on state, if onoff button is pressed longer than the debounce time, the power off interrupt is generated. off to on time supports the time it takes to request power on after a configured button press ti me has been reached. while in the off state, if onoff button is pressed longer than the off to on time, the state will transition from off to on. max time-out configuration supports 5, 10, 15 se conds and disable. max time-out configuration supports the time it takes to request power down after onoff button has been pressed for the defined time. test_mode test_mode is for nxp factory use. th e user must tie this pin directly to gnd. wakeup a gpio powered by snvs domain power supply which can be configured as wakeup source in snvs mode. table 4. jtag controller interface summary jtag i/o type on-chip termination jtag_tck input 47 k ? ? pull-up jtag_tms input 47 k ? ? pull-up jtag_tdi input 47 k ? ? pull-up jtag_tdo 3-state output keeper jtag_trstb input 47 k ? ? pull-up jtag_mod input 100 k ? ? pull-up table 3. special signal considerations (continued) signal name remarks
i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 16 nxp semiconductors modules list table 5. recommended connections for unused analog interfaces module pad name recommendations if unused ccm ccm_clk1_n, ccm_clk1_p not connected usb usb_otg1_chd_b, usb_otg1_dn, usb_otg1_dp, usb_otg1_vbus, usb_otg2_dn, usb_otg2 _dp, usb_otg2_vbus not connected adc vdda_adc_3p3 vdda_adc_3p3 must be powered even if the adc is not used.
electrical characteristics i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 nxp semiconductors 17 4 electrical characteristics this section provides the device and module-level electrical char acteristics for the i.mx rt1050 processors. 4.1 chip-level conditions this section provides the device-level el ectrical characteristics for the ic. see table 6 for a quick reference to the individual tables and sections. 4.1.1 absolute maximum ratings caution stress beyond those listed under table 7 may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any othe r conditions beyond those indicated under ?recommended operating conditions? is not implied. exposure to absolute-maximum-rated conditions for extended periods ma y affect device reliability. table 7 shows the absolute maximum operating ratings. table 6. i.mx rt1050 chip-level conditions for these characteristics topic appears absolute maximum ratings on page 17 10 x 10 mm (vm) thermal resistance on page 18 operating ranges on page 19 external clock sources on page 20 maximum supply currents on page 21 low power mode supply currents on page 22 usb phy current consumption on page 22 table 7. absolute maximum ratings parameter description symbol min max unit core supplies input voltage vdd_soc_in -0.3 1.26 v vdd_high_in supply voltage vdd_high_in -0.3 3.7 v power for dcdc dcdc_in -0.3 3.6 v supply input voltage to secure non-volatile storage and real time clock vdd_snvs_in -0.3 3.6 v usb vbus supply usb_otg1_vbus usb_otg2_vbus ? 5.5 v supply for 12-bit adc vdda_adc 3 3.6 v
i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 18 nxp semiconductors electrical characteristics 4.1.2 10 x 10 mm (vm) thermal resistance table 8 displays the 10 x 10 mm (vm) pa ckage thermal resistance data. io supply for gpio in sdio1 bank (3.3 v mode) nvcc_sd0 3 3.6 v io supply for gpio in sdio1 bank (1.8 v mode) 1.65 1.95 v io supply for gpio in sdio2 bank (3.3 v mode) nvcc_sd1 3 3.6 v io supply for gpio in sdio2 bank (1.8 v mode) 1.65 1.95 v io supply for gpio in emc bank (3.3 v mode) nvcc_emc 3 3.6 v io supply for gpio in emc bank (1.8 v mode) 1.65 1.95 v esd damage immunity: human body model (hbm) charge device model (cdm) vesd ? ? 1000 500 v input/output voltage range v in/vout -0.5 ovdd + 0.3 1 v storage temperature range t storage -40 150 o c 1 ovdd is the i/o supply voltage. table 8. 10 x 10 mm (vm) thermal resistance data rating test conditions symbol value unit notes junction to ambient natural convection single-layer board (1s) r ? ja 72.1 o c/w 1,2 1 junction temperature is a function of di e size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipa tion of other components on the board, and board thermal resistance. 2 per semi g38-87 and jedec jesd51-2 wit h the single layer board horizontal. junction to ambient natural convection four-layer board (2s2p) r ? ja 43.9 o c/w 1,2,3 3 per jedec jesd51-6 with the board horizontal. junction to ambient (@200 ft/min) single-layer board (1s) r ? jma 57.5 o c/w 1,3 junction to ambient (@200 ft/min) four-layer board (2s2p) r ? jma 39.0 o c/w 1,3 junction to board ? r ? jb 26.1 o c/w 4 4 thermal resistance between the die and the printed circuit bo ard per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. junction to case ? r ? jc 19.1 o c/w 5 5 thermal resistance between the die and th e case top surface as measured by the cold plate method (m il spec-883 method 1012.1). junction to package top natural convection ? jt 0.6 o c/w 6 6 thermal characterization parameter indicating the temperature difference between package top and the junction temperature per jedec jesd51-2. when greek letters are not available, th e thermal characterization para meter is written as psi-jt. junction to package bottom natural convection r ? jb_csb 22.3 o c/w 7 table 7. absolute maximum ratings (continued)
electrical characteristics i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 nxp semiconductors 19 4.1.3 operating ranges table 9 provides the operating ranges of the i.mx rt1050 processors. for details on the chip's power structure, see the ?power manageme nt unit (pmu)? chapter of the i.mx rt1050 reference manual (imxrt1050_rm). 7 thermal resistance between the die and the central solder balls on the bottom of the package based on simulation. table 9. operating ranges parameter description symbol operating conditions min typ max 1 unit comment run mode vdd_soc_in m7 core at 528 mhz 1.15 ? 1.26 v ? m7 core at 132 mhz 1.15 ? 1.26 m7 core at 24 mhz 0.925 ? 1.26 idle mode vdd_soc_in m7 core operation at 528 mhz or below 1.15 ? 1.26 v ? suspend (dsm) mode vdd_soc_in ? 0.925 ? 1.26 v refer to table 12 low power mode current and power consumption snvs mode vdd_soc_in ? 0 1.26 v ? power for dcdc dcdc_in ? 2.8 3.0 3.6 v ? vdd_high internal regulator vdd_high_in 2 ? 2.80 ? 3.6 v must match the range of voltages that the rechargeable backup battery supports. backup battery supply range vdd_snvs_in 3 ? 2.40 ? 3.6 v can be combined with vddhigh_in, if the system does not require keeping real time and other data on off state. usb supply voltages usb_otg1_vbus ? 4.40 ? 5.5 v ? usb_otg2_vbus ? 4.40 ? 5.5 v ? gpio supplies 4 nvcc_gpio ? 1.65 1.8, 2.8, 3.3 3.6 v all digital i/o supplies (nvcc_xxxx) must be powered (unless otherwise specified in this data sheet) under normal conditions whether the associated i/o pins are in use or not. nvcc_sd1 nvcc_sd2 nvcc_emc a/d converter vdda_adc_3p3 ? 3.0 3.15 3.6 v vdda_adc_3p3 must be powered even if the adc is not used. vdda_adc_3p3 cannot be powered when the other soc supplies (except vdd_snvs_in) are off.
i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 20 nxp semiconductors electrical characteristics 4.1.4 external clock sources each i.mx rt1050 processor has two external input system clocks: a low frequency (rtc_xtali) and a high frequency (xtali). the rtc_xtali is used for low-frequency functio ns. it supplies the clock for wake-up circuit, power-down real time clock operati on, and slow system and watch-dog counters. the clock input can be connected to either external oscillator or a crystal usi ng internal oscillator amplif ier. additionally, there is an internal ring oscillator, which can be used instead of the rtc_xt ali if accuracy is not important. the system clock input xtali is used to generate the main system cl ock. it supplies th e plls and other peripherals. the system clock input can be connected to either external oscillator or a crystal using internal oscillator amplifier. table 10 shows the interface frequency requirements. the typical valu es shown in table 10 are required for use with nxp sdk to ensure precise time keeping and usb operation. for rtc_xtali operati on, two clock sources are available. ? on-chip 40 khz ring oscillat or?this clock source has th e following characteristics: ? approximately 25 a more i dd than crystal oscillator ? approximately 50% tolerance temperature operating ranges junction temperature tj standard commercial -40 ? 105 o c see the application note, i.mx rt1050 product lifetime usage estimates for information on product lifetime (power-on years) for this processor. 1 applying the maximum voltage results in maximum power cons umption and heat generation. nxp recommends a voltage set point = (v min + the supply tolerance). this resu lt in an optimized power/speed ratio. 2 applying the maximum voltage results in shor ten lifetime. 3.6 v us age limited to < 1% of the use profile. reset of profile limi ted to below 3.49 v. 3 in setting vdd_snvs_in voltage with regards to charging currents and rtc, refer to the i.mx rt1050 hardware development guide (imxrt1050hdg). 4 applying the maximum voltage results in shorten lifetime. 3.6 v us age limited to < 1% of the use profile. rest of profile limit ed to below 3.49 v. table 10. external input clock frequency parameter description symbol min typ max unit rtc_xtali oscillator 1,2 1 external oscillator or a crystal with internal oscillator amplifier. 2 the required frequency stability of this clock source is application dependent. for recomm endations, see the hardware development guide for i.mx rt1050 crossover processors (imxrt1050hdg). f ckil ? 32.768 3 /32.0 3 recommended nominal frequency 32.768 khz. ?khz xtali oscillator 2,4 4 external oscillator or a fundamental frequen cy crystal with internal oscillator amplifier. f xtal ?24?mhz table 9. operating ranges (continued)
electrical characteristics i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 nxp semiconductors 21 ? no external component required ? starts up quicker than 32 khz crystal oscillator ? external crystal os cillator with on-chip support circuit: ? at power up, ring oscillator is utilized. after crystal oscill ator is stable, the clock circuit switches over to the crystal oscillator automatically. ? higher accuracy th an ring oscillator ? if no external crystal is present, then the ring oscillator is utilized the decision of choosing a clock source should be taken based on real-time clock use and precision time-out. 4.1.5 maximum supply currents the data shown in table 11 represent a use case designed specific ally to show the maximum current consumption possible. all cores ar e running at the defined maximum frequency and are limited to l1 cache accesses only to ensure no pipeline stalls. al though a valid condition, it wo uld have a very limited practical use case, if at all, and be limited to an extremely low duty cycle unless the intention were to specifically show the wors t case power consumption. see the i.mx rt1050 power consum ption measurement application no te for more details on typical power consumption under vari ous use case definitions. table 11. maximum supply currents power rail conditions max current unit dcdc_in max power for ff chip at 105 o c 100 ma vdd_high_in include internal loading in analog 50 ma vdd_snvs_in ? 250 ? a usb_otg1_vbus usb_otg2_vbus 25 ma for each active usb interface 50 ma vdda_adc_3p3 3.3 v power supply for 12-bit adc, 600 ? a typical, 750 ? a max, for each adc. 100 ohm max loading for touch panel, cause 33 ma current. 40 ma nvcc_gpio nvcc_sd0 nvcc_sd1 nvcc_emc imax = n x c x v x (0.5 x f) where: n?number of io pins supplied by the power line c?equivalent external capacitive load v?io voltage (0.5 x f)?data change rate. up to 0.5 of the clock rate (f) in this equation, imax is in amps, c in farads, v in volts, and f in hertz.
i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 22 nxp semiconductors electrical characteristics 4.1.6 low power mode supply currents table 12 shows the current core consumpt ion (not including i/o) of i.mx rt1050 processors in selected low power modes. 4.1.7 usb phy current consumption 4.1.7.1 power down mode in power down mode, everything is powered down, in cluding the usb vbus vali d detectors in typical condition. table 13 shows the usb interface current consumption in power down mode. table 12. low power mode current and power consumption mode test conditions supply typical 1 1 typical process material in fab units system idle ? ldo_2p5 set to 2.5 v, ldo_1p1 set to 1.1 v ? cpu in wfi, cpu clock gated ? 24 mhz xtal is on ? 528 pll is active, other plls are power down ? peripheral clock gated, but remain powered dcdc_in (3.0 v for a0 and 3.3 v for a1) 4.0 ma vdd_high_in (3.3 v) 4.7 vdd_snvs_in (3.3 v) 0.036 total 27.63 mw low power idle ? ldo_2p5 and ldo_1p1 are set to weak mode ? wfi, half flexram power down in power gate mode ? all plls are power down ? 24 mhz xtal is off, 24 mhz rcosc used as clock source ? peripheral clock gated, but remain powered dcdc_in (3.0 v for a0 and 3.3 v for a1) 2.2 ma vdd_high_in (3.3 v) 0.3 vdd_snvs_in (3.3 v) 0.042 to ta l 7 . 7 3 m w suspend (dsm) ? ldo_2p5 and ldo_1p1 are shut off ? cpu in power gate mode ? all plls are power down ? 24 mhz xtal is off, 24 mhz rcosc is off ? all clocks are shut off, except 32 khz rtc ? peripheral clock gated, but remain powered dcdc_in (3.0 v for a0 and 3.3 v for a1) 0.2 2 2 average current ma vdd_high_in (3.3 v) 0.037 vdd_snvs_in (3.3 v) 0.02 total 0.788 mw snvs (rtc) ? all soc digital logic, analog module are shut off ? 32 khz rtc is alive dcdc_in (0 v) 0 ma vdd_high_in (0 v) 0 vdd_snvs_in (3.3 v) 0.02 total 0.066 mw table 13. usb phy current consumption in power down mode vdd_usb_cap (3.0 v) vdd_high_cap (2.5 v) nvcc_pll (1.1 v) current 5.1 ? a 1.7 ? a < 0.5 ? a
electrical characteristics i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 nxp semiconductors 23 note the currents on the vdd_high_ cap and vdd_usb_cap were identified to be the voltage divider circuits in the usb-specific level shifters. 4.2 system power and clocks this section provide the information about the system power and clocks. 4.2.1 power supplies requir ements and restrictions the system design must comply with power-up sequence, power-down seque nce, and steady state guidelines as described in this section to guarantee the reliable operation of the device. any deviation from these sequences may result in the following situations: ? excessive current during power-up phase ? prevention of the device from booting ? irreversible damage to the pr ocessor (worst-case scenario) 4.2.1.1 power-up sequence the below restrictions must be followed: ? vdd_snvs_in supply must be turned on befo re any other power supply or be connected (shorted) with vdd_high_in supply. ? if a coin cell is used to power vdd_snvs_in, th en ensure that it is connected before any other supply is switched on. ? when internal dcdc is enabled, external delay circuit is required to delay the ?dcdc_pswitch? signal 1 ms after dcdc_in is stable. ? por_b should be held low dur ing the entire power up sequence. note the por_b input (if used) must be im mediately asserted at power-up and remain asserted until after the last power rail reaches its working voltage. in the absence of an external reset feed ing the por_b input, the internal por module takes control. see the i.mx rt1050 reference manual (imxrt1050_rm) for further details and to ensure that all necessary requirements are being met. note need to ensure that there is no back voltage (leakage) from any supply on the board towards the 3.3 v supply (f or example, from the external components that use both the 1.8 v and 3.3 v supplies). note usb_otg1_vbus, usb_otg2_vbu s, and vdda_adc_3p3 are not part of the power supply sequence and may be powered at any time.
i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 24 nxp semiconductors electrical characteristics 4.2.1.2 power-down sequence the following restricti ons must be followed: ? vdd_snvs_in supply must be turn ed off after any other power s upply or be connected (shorted) with vdd_high_in supply. ? if a coin cell is used to power vdd_snvs_in, then ensure that it is removed after any other supply is switched off. 4.2.1.3 power supplies usage all i/o pins should not be externally driven while the i/o power supply for the pin (nvcc_xxx) is off. this can cause internal latch-up a nd malfunctions due to reverse curren t flows. for info rmation about i/o power supply of each pin, s ee ?power rail? columns in pin list tables of section 6, ?package information and contact assignments.? 4.2.2 integrated ldo voltage regulator parameters various internal supplies can be powered on from inte rnal ldo voltage regulators. all the supply pins named *_cap must be connected to external capaci tors. the onboard ldos are intended for internal use only and should not be used to power any external circuitry. see the i.mx rt1050 reference manual (imxrt1050_rm) for details on the power tree scheme. note the *_cap signals should not be power ed externally. these signals are intended for internal ldo operation only. 4.2.2.1 digital regulators (ldo_snvs) there are one digital ldo regulator (? digital?, because of the logic loads that they drive, not because of their construction). the advantages of the regulator is to reduce the input supply variation because of its input supply ripple rejecti on and its on-die trimming. this translates into more stable voltage for the on-chip logics. the regulator has two basic modes: ? power gate. the regulation fet is switched full y off limiting the current draw from the supply. the analog part of the regulator is powered down here limiting th e power consumption. ? analog regulation mode. the regulation fet is c ontrolled such that the output voltage of the regulator equals the target voltage. for additional information, see the i.mx rt1050 reference manual (imxrt1050_rm). 4.2.2.2 regulators for analog modules 4.2.2.2.1 ldo_1p1 the ldo_1p1 regulator implements a programmable linear-regulator function from vdd_high_in (see table 9 for minimum and maximum input requirements) . typical programming operating range is 1.0 v
electrical characteristics i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 nxp semiconductors 25 to 1.2 v with the nominal default setting as 1.1 v. the ldo_1p1 supplies the usb phy, and plls. a programmable brown-out detector is included in the regulator that can be used by the system to determine when the load capability of the regulator is being ex ceeded to take the necessary steps. current-limiting can be enabled to allow for in-rus h current requirements during start- up, if needed. active-pull-down can also be enabled for systems requiring this feature. for information on external capacitor requirements fo r this regulator, see the hardware development guide for i.mx rt1050 crossover processors (imxrt1050hdg). for additional information, see the i.mx rt1050 reference manual (imxrt1050_rm). 4.2.2.2.2 ldo_2p5 the ldo_2p5 module implements a programmable linear-regulator f unction from vdd_high_in (see table 9 for minimum and maximum input requirements). typi cal programming operat ing range is 2.25 v to 2.75 v with the nominal defaul t setting as 2.5 v. ldo_2p5 supplies the usb phy, e-fuse module, and plls. a programmable brown-out detect or is included in the regulator that can be used by the system to determine when the load capability of the regulator is being exceeded, to take the necessary steps. current-limiting can be enabled to allow for in-r ush current requirements during start-up, if needed. active-pull-down can also be enab led for systems requiring this feat ure. an alternate self-biased low-precision weak-regulator is included that can be enabled for applications ne eding to keep the output voltage alive during low-power modes where the main re gulator driver and its a ssociated global bandgap reference module are disabl ed. the output of the weak -regulator is not programmable and is a function of the input supply as well as the load current. typically, with a 3 v input supply the weak-regulator output is 2.525 v and its output impeda nce is approximately 40 ? . for information on external capacitor requirements fo r this regulator, see the hardware development guide for i.mx rt1050 crossover processors (imxrt1050hdg). for additional information, see the i.mx rt1050 reference manual (imxrt1050rm). 4.2.2.2.3 ldo_usb the ldo_usb module implements a programmable linear-regulator function from the usb vusb voltages (4.4 v?5.5 v) to produce a nominal 3.0 v output voltage. a pr ogrammable brown-out detector is included in the regulator that can be used by the sy stem to determine when the load capability of the regulator is being exceeded, to take the necessary steps. this regul ator has a built in pow er-mux that allows the user to select to run the regulator from either usb vbus supply, when both are present. if only one of the usb vbus voltages is present, then, the regulat or automatically selects th is supply. current limit is also included to help the system meet in-rush current targets. for information on external capacitor re quirements for this regulator, see the hardware development guide for i.mx rt1050 crossover processors (imxrt1050hdg). for additional information, see the i.mx rt1050 reference manual (imxrt1050rm).
i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 26 nxp semiconductors electrical characteristics 4.2.2.2.4 dcdc dcdc can be configured to operate on power-save mode when the load current is less than 50 ma. during the power-save mode, the converter operates with reduc ed switching frequency in pfm mode and with a minimum quiescent current to maintain high efficiency. dcdc can detect the peak current in the p-channel switch. when the peak current exceeds the threshold, dcdc will give an alert signal, and the threshold can be configure d. by this way, dcdc can roughly detect the current loading. dcdc also includes the foll owing protection functions: ? over current protection. in run mode, dcdc shuts down when dete cting abnormal large current in the p-type power switch. ? over voltage protection. dcdc shuts down when detecting the output voltage is too high. ? low voltage detection. dcdc shuts down when detecting th e input voltage is too low. for additional information, see the i.mx rt1050 reference manual (imxrt1050rm). 4.2.3 pll?s electrical characteristics this section provides pll electrical characteristics. 4.2.3.1 audio/video pll?s electrical parameters 4.2.3.2 528 mhz pll table 14. audio/video pll?s electrical parameters parameter value clock output range 650 mhz ~1.3 ghz reference clock 24 mhz lock time <11250 reference cycles table 15. 528 mhz pll?s electrical parameters parameter value clock output range 528 mhz pll output reference clock 24 mhz lock time <11250 reference cycles
electrical characteristics i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 nxp semiconductors 27 4.2.3.3 ethernet pll 4.2.3.4 480 mhz pll 4.2.3.5 arm pll 4.2.4 on-chip oscillators 4.2.4.1 osc24m this block implements an amplifier that when combined with a suitable quartz crystal and external load capacitors implement an oscillator. th e oscillator is powered from nvcc_pll. the system crystal oscillator consists of a pierce-t ype structure running off the digital supply. a straight forward biased-inverter implementation is used. 4.2.4.2 osc32k this block implements an amplifier that when combined with a suitable quartz crystal and external load capacitors implement a low power oscillator. it also implements a power mux such that it can be powered from either a ~3 v backup battery (vdd_snvs_in) or vdd_high_in such as the oscillator consumes table 16. ethernet pll?s electrical parameters parameter value clock output range 1 ghz reference clock 24 mhz lock time <11250 reference cycles table 17. 480 mhz pll?s electrical parameters parameter value clock output range 480 mhz pll output reference clock 24 mhz lock time <383 reference cycles table 18. arm pll?s electrical parameters parameter value clock output range 648 mhz ~ 1296 mhz reference clock 24 mhz lock time <2250 reference cycles
i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 28 nxp semiconductors electrical characteristics power from vdd_high_in when that supply is available and transitions to the backup battery when vdd_high_in is lost. in addition, if the clock monitor dete rmines that the osc32k is not pres ent, then the source of the 32 k will automatically switch to a crude internal ring oscillator. the frequency range of this block is approximately 10?45 khz. it highly depends on the process, voltage, and temperature. the osc32k runs from vdd_snvs_cap supply, which comes from the vdd_high_in/vdd_snvs_in. the target battery is a ~3 v coin cell. proper choice of coin cell type is necessary for chosen vdd_high _in range. appropriate series resi stor (rs) must be used when connecting the coin cell. rs depends on the charge curr ent limit that depends on the chosen coin cell. for example, for panasonic ml621: ? average discharge voltage is 2.5 v ? maximum charge current is 0.6 ma for a charge voltage of 3.2 v, rs = (3.2-2.5)/0.6 m = 1.17 k. 4.3 i/o parameters this section provide parameters on i/o interfaces. 4.3.1 i/o dc parameters this section includes the dc parame ters of the following i/o types: table 19. osc32k main characteristics min typ max comments fosc ? 32.768 khz ? this frequency is nominal and determined mainly by the crystal selected. 32.0 k would work as well. current consumption ? 4 ? a ? the 4 ? a is the consumption of the oscilla tor alone (osc32k). total supply consumption will depend on what the di gital portion of the rtc consumes. the ring oscillator consumes 1 ? a when ring oscillator is inactive, 20 ? a when the ring oscillator is running. another 1.5 ? a is drawn from vdd_rtc in the power_detect block. so, the total current is 6.5 ? a on vdd_rtc when the ring oscillator is not running. bias resistor ? 14 m ? ? this integrated bias resistor sets the amplifier into a high gain state. any leakage through the esd network, ex ternal board leakage, or even a scope probe that is significant relative to this value will debias the amp. the debiasing will result in low gain, and will impact the circuit's ability to start up and maintain oscillations. crystal properties cload ? 10 pf ? usually crystals can be purchased tuned for different cloads. this cload value is typically 1/2 of the capacitanc es realized on the pcb on either side of the quartz. a higher cload will decrease oscillation margin, but increases current oscillating through the crystal. esr ? 50 k ? 100 k ? equivalent series resistance of the crystal. choosing a crystal with a higher value will decrease the oscillating margin.
electrical characteristics i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 nxp semiconductors 29 ? xtali and rtc_xtali (clock inputs) dc parameters ? general purpose i/o (gpio) ? lvds i/o dc parameters note the term ?nvcc_xxxx? in this section refers to the associated supply rail of an input or output. figure 3. circuit for parameters voh and vol for i/o cells 4.3.1.1 xtali and rtc_xtali (clock inputs) dc parameters table 20 shows the dc parameters for the clock inputs. 4.3.1.2 single voltage general pur pose i/o (gpio) dc parameters table 21 shows dc parameters for gp io pads. the parameters in table 21 are guaranteed per the operating ranges in table 9 , unless otherwise noted. table 20. xtali and rtc_xtali dc parameters 1 1 the dc parameters are for external clock input only. parameter symbol test conditions min max unit xtali high-level dc input voltage vih ? 0.8 x nvcc_pll nvcc_pll v xtali low-level dc input voltage vil ? 0 0.2 v rtc_xtali high-level dc input voltage vih ? 0.8 1.1 v rtc_xtali low-level dc input voltage vil ? 0 0.2 v
i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 30 nxp semiconductors electrical characteristics table 21. single voltage gpio dc parameters parameter symbol test conditions min max units high-level output voltage 1 1 overshoot and undershoot conditions (transitions above nv cc_xxxx and below gnd) on switching pads must be held below 0.6 v, and the duration of the overshoot/unde rshoot must not exceed 10% of the system clock cycle. overshoot/ undershoot must be controlled through printed circuit board layout, transmission line impedance ma tching, signal line termination, or othe r methods. non-compliance to this specification may affect device reliability or cause permanent damage to the device. v oh ioh= -0.1ma (ipp_dse=001,010) ioh= -1ma (ipp_dse=011,100,101,110,111) nvcc_xx xx-0.15 ?v low-level output voltage 1 vol iol= 0.1ma (ipp_dse=001,010) iol= 1ma (ipp_dse=011,100,101,110,111) ?0.15v high-level input voltage 1,2 2 to maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current dc level through to the target dc level, vil or vih. monotonic input transition time is from 0.1 ns to 1 s. vih ? 0.7*nvcc_ xxxx nvcc_xx xx v low-level input voltage 1,2 vil ? 0 0.3 x nvcc_xx xx v input hysteresis (nvcc_xxxx= 1. 8v) vhys_lowvdd nvcc_xxxx=1.8v 250 ? mv input hysteresis (nvcc_xxxx=3.3v ) vhys_highvdd nvcc_xxxx=3.3v 250 ? mv schmitt trigger vt+ 2,3 3 hysteresis of 250 mv is guaranteed over all operating conditions when hysteresis is enabled. vth+ ? 0.5 x nvcc_xx xx ?mv schmitt trigger vt- 2,3 vth- ? ? 0.5 x nvcc_xx xx mv pull-up resistor (22_k ? pu) rpu_22k vin=0v ? 212 ? a pull-up resistor (22_k ? pu) rpu_22k vin=nvcc_xxxx ? 1 ? a pull-up resistor (47_k ? pu) rpu_47k vin=0v ? 100 ? a pull-up resistor (47_k ? pu) rpu_47k vin=nvcc_xxxx ? 1 ? a pull-up resistor (100_k ? pu) rpu_100k vin=0v ? 48 ? a pull-up resistor (100_k ? pu) rpu_100k vin=nvcc_xxxx ? 1 ? a pull-down resistor (100_k ? pd) rpd_100k vin=nvcc_xxxx ? 48 ? a pull-down resistor (100_k ? pd) rpd_100k vin=0v ? 1 ? a input current (no pu/pd) iin vi = 0, vi = nvcc_xxxx -1 1 ? a keeper circuit resistance r_keepe r vi =0.3*nvcc_xxxx, vi = 0.7* nvcc_xxxx 105 175 k ?
electrical characteristics i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 nxp semiconductors 31 4.3.1.3 lvds i/o dc parameters the lvds interface complies with tia/eia 644-a standard. see tia/eia standard 644-a, ?electrical characteristics of low voltage differential signaling (lvd s) interface circuits? for details. table 22 shows the low voltage differential signaling (lvds) i/o dc parameters. 4.3.2 i/o ac parameters this section includes the ac parame ters of the following i/o types: ? general purpose i/o (gpio) figure 4 shows load circuit for output, and figure 5 show the output tran sition time waveform. figure 4. load circuit for output figure 5. output transition time waveform 4.3.2.1 general purpose i/o ac parameters the i/o ac parameters for gpio in slow and fast modes are presented in the table 23 and table 24 , respectively. note that the fast or slow i/o behavior is determined by the appropriate control bits in the iomuxc control registers. table 22. lvds i/o dc characteristics parameter symbol test co nditions min typ max unit output differential voltage vod rload-100 ? diff 250 350 450 mv output high voltage voh ioh = 0 ma 1.25 1.375 1.6 v output low voltage vol iol = 0 ma 0.9 1.025 1.25 v offset voltage vos ? 1.125 1.2 1.375 v te s t p o i n t from output under test cl cl includes package, probe and fixture capacitance 0v ovdd 20% 80% 80% 20% tr tf output (at pad)
i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 32 nxp semiconductors electrical characteristics 4.3.3 output buffer impedance parameters this section defines the i/o impeda nce parameters of the i.mx rt1050 processors for th e following i/o types: ? single voltage general purpose i/o (gpio) note gpio i/o output driver impedance is measured with ?long? transmission line of impedance ztl attached to i/ o pad and incident wave launched into transmission line. rpu/rpd and ztl fo rm a voltage divider that defines specific voltage of inci dent wave relative to nvcc_xxxx. output driver impedance is calculated from this voltage divider (see figure 6 ). table 23. general purpose i/o ac parameters 1.8 v mode parameter symbol test condition min typ max unit output pad transition times, rise/fall (max drive, ipp_dse=111) tr, tf 15 pf cload, slow slew rate 15 pf cload, fast slew rate ?? 2.72/2.79 1.51/1.54 ns output pad transition times, rise/fall (high drive, ipp_dse=101) tr, tf 15 pf cload, slow slew rate 15 pf cload, fast slew rate ?? 3.20/3.36 1.96/2.07 output pad transition times, rise/fall (medium drive, ipp_dse=100) tr, tf 15 pf cload, slow slew rate 15 pf cload, fast slew rate ?? 3.64/3.88 2.27/2.53 output pad transition times, rise/fall (low drive. ipp_dse=011) tr, tf 15 pf cload, slow slew rate 15 pf cload, fast slew rate ?? 4.32/4.50 3.16/3.17 input transition times 1 1 hysteresis mode is recommended for inputs with transition times greater than 25 ns. trm ? ? ? 25 ns table 24. general purpose i/o ac parameters 3.3 v mode parameter symbol test condition min typ max unit output pad transiti on times, rise/fall (max drive, ipp_dse=101) tr, tf 15 pf cload, slow slew rate 15 pf cload, fast slew rate ?? 1.70/1.79 1.06/1.15 ns ns output pad transiti on times, rise/fall (high drive, ipp_dse=011) tr, tf 15 pf cload, slow slew rate 15 pf cload, fast slew rate ?? 2.35/2.43 1.74/1.77 output pad transiti on times, rise/fall (medium drive, ipp_dse=010) tr, tf 15 pf cload, slow slew rate 15 pf cload, fast slew rate ?? 3.13/3.29 2.46/2.60 output pad transiti on times, rise/fall (low drive. ipp_dse=001) tr, tf 15 pf cload, slow slew rate 15 pf cload, fast slew rate ?? 5.14/5.57 4.77/5.15 input transition times 1 1 hysteresis mode is recommended for inputs with transition times greater than 25 ns. trm ? ? ? 25 ns
electrical characteristics i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 nxp semiconductors 33 figure 6. impedance matching load for measurement ipp_do cload = 1p ztl ? , l = 20 inches predriver pmos (rpu) nmos (rpd) pad ovdd ovss t,(ns) 0 u,(v) ovdd t,(ns) 0 vdd vin (do) vout (pad) u,(v) vref rpu = vovdd - vref1 vref1 ? ztl rpd = ? ztl vref2 vovdd - vref2 vref1 vref2
i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 34 nxp semiconductors electrical characteristics 4.3.3.1 single voltage gpio output buffer impedance table 25 shows the gpio output buffer impedance (nvcc_xxxx 1.8 v). table 26 shows the gpio output buffer impedance (nvcc_xxxx 3.3 v). 4.4 system modules this section contains the timing a nd electrical parameters for the modul es in the i.mx rt1050 processor. 4.4.1 reset timings parameters figure 7 shows the reset timing and table 27 lists the timing parameters. figure 7. reset timing diagram table 25. gpio output buffer ave rage impedance (nvcc_xxxx 1.8 v) parameter symbol drive strength (dse) typ value unit output driver impedance rdrv 001 010 011 100 101 110 111 260 130 88 65 52 43 37 ? table 26. gpio output buffer ave rage impedance (nvcc_xxxx 3.3 v) parameter symbol drive strength (dse) typ value unit output driver impedance rdrv 001 010 011 100 101 110 111 157 78 53 39 32 26 23 ? table 27. reset timing parameters id parameter min max unit cc1 duration of por_b to be qualified as valid. 1 ? rtc_xtali cycle por_b cc1 (input)
electrical characteristics i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 nxp semiconductors 35 4.4.2 wdog reset timing parameters figure 8 shows the wdog reset timing and table 28 lists the timing parameters. figure 8. wdogn_ b timing diagram note rtc_xtali is approximately 32 khz. rtc_xtali cycle is one period or approximately 30 ? s. note wdogn_b output signals (for each one of the watchdog modules) do not have dedicated pins, but are muxed out through the iomux. see the iomux manual for detailed information. 4.4.3 scan jtag controller (sjc) timing parameters figure 9 depicts the sjc test clock input timing. figure 10 depicts the sjc boundary scan timing. figure 11 depicts the sjc test access port. signal parameters are listed in table 29 . figure 9. test clock input timing diagram table 28. wdogn_b timing parameters id parameter min max unit cc3 duration of wdogn_b assertion 1 ? rtc_xtali cycle wdogn_b cc3 (output) jtag_tck (input) vm vm vih vil sj1 sj2 sj2 sj3 sj3
i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 36 nxp semiconductors electrical characteristics figure 10. boundary scan (jtag) timing diagram jtag_tck (input) data inputs data outputs data outputs data outputs vih vil input data valid output data valid output data valid sj4 sj5 sj6 sj7 sj6
electrical characteristics i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 nxp semiconductors 37 figure 11. test access port timing diagram figure 12. jtag_trst_b timing diagram table 29. jtag timing id parameter 1,2 all frequencies unit min max sj0 jtag_tck frequency of operation 1/(3?t dc ) 1 0.001 22 mhz sj1 jtag_tck cycle time in crystal mode 45 ? ns sj2 jtag_tck clock pulse width measured at v m 2 22.5 ? ns sj3 jtag_tck rise and fall times ? 3 ns sj4 boundary scan input data set-up time 5 ? ns sj5 boundary scan input data hold time 24 ? ns sj6 jtag_tck low to output data valid ? 40 ns sj7 jtag_tck low to output high impedance ? 40 ns sj8 jtag_tms, jtag_tdi data set-up time 5 ? ns jtag_tck (input) jtag_tdi (input) jtag_tdo (output) jtag_tdo (output) jtag_tdo (output) vih vil input data valid output data valid output data valid jtag_tms sj8 sj9 sj10 sj11 sj10 jtag_tck (input) jtag_trst_b (input) sj13 sj12
i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 38 nxp semiconductors electrical characteristics 4.5 external memory interface the following sections provide informat ion about external memory interfaces. 4.5.1 semc specifications the following sections provide information on semc interface. measurements are with a load of 15 pf and an input slew rate of 1 v/ns. 4.5.1.1 semc output timing there are async and sync m ode for semc output timing. 4.5.1.1.1 semc output timing in async mode table 30 shows semc output timing in async mode. sj9 jtag_tms, jtag_tdi data hold time 25 ? ns sj10 jtag_tck low to jtag_tdo data valid ? 44 ns sj11 jtag_tck low to jtag_tdo high impedance ? 44 ns sj12 jtag_trst_b assert time 100 ? ns sj13 jtag_trst_b set-up time to jtag_tck low 40 ? ns 1 t dc = target frequency of sjc 2 v m = mid-point voltage table 30. semc output timing in async mode symbol parameter min. max. unit comment frequency of operation ? 166 mhz t ck internal clock period 6 ? ns t avo address output valid time ? 2 ns these timing parameters apply to address and adv# for nor/psram in async mode. t aho address output hold time (tck - 2) 1 ?ns t advl adv# low time (tck - 1) 2 t dvo data output valid time ? 2 ns these timing parameters apply to data/cle/ale and we# for nand, apply to data/dm/cre for nor/psram, apply to data/dcx and wrx for dbi interface. t dho data output hold time (tck - 2) 3 ?ns t wel we# low time (tck - 1) 4 ns table 29. jtag timing (continued) id parameter 1,2 all frequencies unit min max
electrical characteristics i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 nxp semiconductors 39 figure 13 shows the output tim ing in async mode. figure 13. semc output timing in async mode 4.5.1.1.2 semc output timing in sync mode table 31 shows semc output timing in sync mode. 1 address output hold time is configurable by semc_*cr0.ah. ah field setting value is 0x0 in above table. when ah is set with value n, t aho min time should be ((n + 1) x t ck ). see the i.mx rt1050 reference manual (imxrt1050_rm) for more detail about semc_*cr0.ah register field. 2 adv# low time is configurable by semc_*cr0.as. as field sett ing value is 0x0 in above table. when as is set with value n, t adl min time should be ((n + 1) x t ck - 1). see the i.mx rt1050 reference manual (imxrt1050_rm) for more detail about semc_*cr0.as register field. 3 data output hold time is configurable by semc_*cr0.weh. weh field setting value is 0x0 in above table. when weh is set with value n, t dho min time should be ((n + 1) x t ck ). see the i.mx rt1050 reference manual (imxrt1050_rm) for more detail about semc_*cr0.weh register field. 4 we# low time is configurable by semc_*cr0.wel. wel field sett ing value is 0x0 in above table. when wel is set with value n, t wel min time should be ((n + 1) x t ck - 1). see the i.mx rt1050 reference manual (imxrt1050_rm) for more detail about semc_*cr0.wel register field. table 31. semc output timing in sync mode symbol parameter min. max. unit comment frequency of operation ? 166 mhz ? t ck internal clock period 6 ? ns ? )nternalclock !$$2 ! !$6 4 !6/ 4 !(/ $!4! 7% 4 #+ $ 4 $6/ 4 $(/
i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 40 nxp semiconductors electrical characteristics figure 14 shows the output timing in sync mode. figure 14. semc output timing in sync mode 4.5.1.2 semc input timing there are async and sync m ode for semc input timing. 4.5.1.2.1 semc input timing in async mode table 32 shows semc output timing in async mode. figure 15 shows the input ti ming in async mode. t dvo data output valid time 1 ? ns these timing parameters apply to address/data/dm/cke/control signals with semc_clk for sdram. t dho data output hold time -1 ? ns table 32. semc output timing in async mode symbol parameter min. max. unit comment t is data input setup 8.67 ? ns for nand/nor/psram/dbi, these timing parameters apply to re# and read data. t ih data input hold 0 ? ns table 31. semc output timing in sync mode (continued) symbol parameter min. max. unit comment 3%-#?#,+ $!4! $ 4 $(/ 4 $6/
electrical characteristics i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 nxp semiconductors 41 figure 15. semc input timing in async mode 4.5.1.2.2 semc input timing in sync mode table 33 and table 34 show semc input timing in sync mode. figure 16 shows the input timing in sync mode. table 33. semc input timing in sync mode (semc_mcr.dqsmd = 0x0) symbol parameter min. max. unit comment t is data input setup 8.67 ? ns ? t ih data input hold 0 ? ns table 34. semc input timing in sync mode (semc_mcr.dqsmd = 0x1) symbol parameter min. max. unit comment t is data input setup 0.6 ? ns ? t ih data input hold 1 ? ns $!4! $ /% /% $!4! $ $ $ 4 )3 4 )( 4 )3 4 )( .!.$non %$/modeand./2032!-timing .!.$%$/modetiming
i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 42 nxp semiconductors electrical characteristics figure 16. semc input timing in sync mode 4.5.2 flexspi parameters measurements are with a load 15 pf and input slew rate of 1 v/ns. 4.5.2.1 flexspi input/read timing there are four sources for the internal sample clock for flexspi read data: ? dummy read strobe generated by flexspi controller and loope d back internally (flexspi n _mcr0[rxclksrc] = 0x0) ? dummy read strobe generated by flexspi controller and loope d back through the dqs pad (flexspi n _mcr0[rxclksrc] = 0x1) ? read strobe provided by memory device and input from dqs pad (flexspi n _mcr0[rxclksrc] = 0x3) the following sections describe inpu t signal timing for each of these f our internal sample clock sources. 4.5.2.1.1 sdr mode with flexspi n _mcr0[rxclksrc] = 0x0, 0x1 table 35. flexspi input timing in sdr mode where flexspi n _mcr0[rxclksrc] = 0x0 symbol parameter min max unit ? frequency of operation ? 60 mhz t is setup time for incoming data 8.67 ? ns t ih hold time for incoming data 0 ? ns table 36. flexspi input timing in sdr mode where flexspi n _mcr0[rxclksrc] = 0x1 symbol parameter min max unit ? frequency of operation ? 133 mhz t is setup time for incoming data 2 ? ns t ih hold time for incoming data 1 ? ns 3%-#?#,+ $!4! $ 3%-#?$13 4 )3 4 )(
electrical characteristics i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 nxp semiconductors 43 figure 17. flexspi input timi ng in sdr mode where flexspi n _mcr0[rxclksrc] = 0x0, 0x1 note timing shown is based on the memory generating read data on the sck falling edge, and flexspi controller sampling read data on the falling edge. 4.5.2.1.2 sdr mode with flexspi n _mcr0[rxclksrc] = 0x3 there are two cases when the memory provides bot h read data and the read strobe in sdr mode: ? a1 - memory generates both read data and read strobe on sck rising edge (or falling edge) ? a2 - memory generates read data on sck falling edge and generates read strobe on sck rising edge sck rising edge figure 18. flexspi input timi ng in sdr mode where flexspi n _mcr0[rxclksrc] = 0x3 (case a1) table 37. flexspi input timing in sdr mode where flexspi n _mcr0[rxclksrc] = 0x3 (case a1) symbol parameter value unit min max frequency of operation ? 166 mhz t sckd time from sck to data valid ? ? ns t sckdqs time from sck to dqs ? ? ns t sckd - t sckdqs time delta between t sckd and t sckdqs -2 2 ns 7 ,6 7 ,+ 6&. 6,2>@ 7 ,6 7 ,+ ,qwhuqdo6dpsoh&orfn 7 6&.'46 6&. 6,2>@ '46 7 6&.' 7 6&.'46 7 6&.'
i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 44 nxp semiconductors electrical characteristics note timing shown is based on the memory ge nerating read data and read strobe on the sck rising edge. the flexspi c ontroller samples read data on the dqs falling edge. figure 19. flexspi input timi ng in sdr mode where flexspi n _mcr0[rxclksrc] = 0x3 (case a2) note timing shown is based on the memory generating read data on the sck falling edge and read strobe on the sc k rising edge. the flexspi controller samples read data on a half cy cle delayed dqs falling edge. 4.5.2.1.3 ddr mode with flexspi n _mcr0[rxclksrc] = 0x0, 0x1 table 38. flexspi input timing in sdr mode where flexspi n _mcr0[rxclksrc] = 0x3 (case a2) symbol parameter value unit min max frequency of operation ? 166 mhz t sckd time from sck to data valid ? ? ns t sckdqs time from sck to dqs ? ? ns t sckd - t sckdqs time delta between t sckd and t sckdqs -2 2 ns table 39. flexspi input timi ng in ddr mode where flexspi n _mcr0[rxclksrc] = 0x0 symbol parameter min max unit frequency of operation ? 30 mhz t is setup time for inco ming data 8.67 ? ns t ih hold time for incoming data 0 ? ns 7 6&.'46 7 6&.' 6&. 6,2>@ '46 ,qwhuqdo6dpsoh&orfn 7 6&.'46 7 6&.' 7 6&.'46 7 6&.'
electrical characteristics i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 nxp semiconductors 45 figure 20. flexspi i nput timing in ddr mode where flexspi n _mcr0[rxclksrc] = 0x0, 0x1 4.5.2.1.4 ddr mode with flexspi n _mcr0[rxclksrc] = 0x3 there are two cases when the memory provides bot h read data and the read strobe in ddr mode: ? b1 - memory generates both read data and read strobe on sck edge ? b2 - memory generates read data on sck edge and generates read strobe on sck2 edge table 40. flexspi input timi ng in ddr mode where flexspi n _mcr0[rxclksrc] = 0x1 symbol parameter min max unit frequency of operation ? 66 mhz t is setup time for incoming data 2 ? ns t ih hold time for incoming data 1 ? ns table 41. flexspi input timing in ddr mode where flexspi n _mcr0[rxclksrc] = 0x3 (case b1) symbol parameter min max unit frequency of operation ? 166 mhz t sckd time from sck to data valid ? ? ns t sckdqs time from sck to dqs ? ? ns t sckd - t sckdqs time delta between t sckd and t sckdqs -1 1 ns 7 ,6 7 ,+ 7 ,6 7 ,+ 6&/. 6,2>@ ,qwhuqdo6dpsoh&orfn
i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 46 nxp semiconductors electrical characteristics figure 21. flexspi input timing in ddr mode where flexspi n _mcr0[rxclksrc] = 0x3 (case b1) figure 22. flexspi input timing in ddr mode where flexspi n _mcr0[rxclksrc] = 0x3 (case b2) 4.5.2.2 flexspi output/write timing the following sections describe output signal timing for the flexspi controller including control signals and data outputs. 4.5.2.2.1 sdr mode table 42. flexspi input timing in ddr mode where flexspi n _mcr0[rxclksrc] = 0x3 (case b2) symbol parameter min max unit frequency of operation ? 166 mhz t sckd time from sck to data valid ? ? ns t sckd - t sckdqs time delta between t sckd and t sckdqs -1 1 ns table 43. flexspi output timing in sdr mode symbol parameter min max unit frequency of operation ? 166 1 mhz t ck sck clock period 6.0 ? ns t dvo output data valid time ? 1 ns t dho output data hold time -1 ? ns 7 6&.' 7 6&.'46 6,2>@ '46 6&. 7 6&.' 7 6&.'46 6&. 6,2>@ '46 6&.
electrical characteristics i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 nxp semiconductors 47 note t css and t csh are configured by the flexspi n _flsha x cr1 register, the default values are shown above. please refer to the i.mx rt1050 reference manual (imxrt1050_rm) for more details. figure 23. flexspi output timing in sdr mode 4.5.2.2.2 ddr mode note t css and t csh are configured by the flexspi n _flsha x cr1 register, the default values are shown above. please refer to the i.mx rt1050 reference manual (imxrt1050_rm) for more details. t css chip select output setup time 3 x t ck - 1 ? ns t csh chip select output hold time 3 x t ck + 2 ? ns 1 the actual maximum frequency supported is limited by the flexspi n _mcr0[rxclksrc] configuration used. please refer to the flexspi sdr input timing specifications. table 44. flexspi output timing in ddr mode symbol parameter min max unit frequency of operation 1 1 the actual maximum frequency su pported is limited by the flexspi n _mcr0[rxclksrc] configuration used. pleas e refer to the flexspi sdr input timing specifications. ? 166 mhz t ck sck clock period 6.0 ? ns t dvo output data valid time ? 2.2 ns t dho output data hold time 0.8 ? ns t css chip select output setup time 3 x t ck / 2 - 0.7 ? ns t csh chip select output hold time 3 x t ck / 2 + 0.8 ? ns table 43. flexspi output timing in sdr mode (continued) symbol parameter min max unit 7 &66 7 &. 7 &6+ 7 '92 7 '+2 7 '92 7 '+2 6&. &6 6,2>@
i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 48 nxp semiconductors electrical characteristics figure 24. flexspi output timing in ddr mode 4.6 display and graphics the following sections provide informat ion on display and graphic interfaces. 4.6.1 cmos sensor interface (csi) timing parameters the following sections describe the csi timing in gated and ungated clock modes. 4.6.1.0.1 gated clock mode timing figure 25 and figure 26 shows the gated clock mode timings for csi, and table 45 describes the timing parameters (p1?p7) shown in the figures. a fram e starts with a rising/ falling edge on csi_vsync (vsync), then csi_hsync (hsync) is asserted and holds for th e entire line. the pixel clock, csi_pixclk (pixclk), is valid as long as hsync is asserted. figure 25. csi gated clock mode?sensor data at falling edge, latch data at rising edge 7 &66 7 &. 7 '92 7 '+2 7 '92 7 '+2 7 &6+ 6&. &6 6,2>@ csi_pixclk csi_vsync csi_data[23:00] p5 p1 p3 p4 csi_hsync p2 p6 p7
electrical characteristics i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 nxp semiconductors 49 figure 26. csi gated clock mode?sensor data at rising edge, latch data at falling edge table 45. csi gated clock mode timing parameters id parameter symbol min. max. units p1 csi_vsync to csi_hsync time tv2h 33.5 ? ns p2 csi_hsync setup time thsu 1 ? ns p3 csi data setup time tdsu 1 ? ns p4 csi data hold time tdh 1 ? ns p5 csi pixel clock high time tclkh 3.75 ? ns p6 csi pixel clock low time tclkl 3.75 ? ns p7 csi pixel clock frequency fclk ? 80 mhz csi_pixclk csi_vsync csi_data[23:00] p6 p1 p3 p4 csi_hsync p2 p5 p7
i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 50 nxp semiconductors electrical characteristics 4.6.1.0.2 ungated clock mode timing figure 27 shows the ungated clock m ode timings of csi, and table 46 describes the timing parameters (p1?p6) that are shown in the figure. in ungated mode the csi_vsync and csi_pixclk signals are used, and the csi_hsync signal is ignored. figure 27. csi ungated clock mode?sensor data at falling edge, latch data at rising edge the csi enables the chip to connect directly to exte rnal cmos image sensors, which are classified as dumb or smart as follows: ? dumb sensors only support traditi onal sensor timing (vertical sync (vsync) and horizontal sync (hsync)) and output-only bayer and statistics data. ? smart sensors support ccir656 vi deo decoder formats and perfor m additional processing of the image (for example, image compression, image pr e-filtering, and various data output formats). table 46. csi ungated clock mode timing parameters id parameter symbol min. max. units p1 csi_vsync to pixel clock time tvsync 33.5 ? ns p2 csi data setup time tdsu 1 ? ns p3 csi data hold time tdh 1 ? ns p4 csi pixel clock high time tclkh 3.75 ? ns p5 csi pixel clock low time tclkl 3.75 ? ns p6 csi pixel clock frequency fclk ? 80 mhz csi_pixclk csi_vsync csi_data[23:00] p4 p1 p2 p3 p5 p6
electrical characteristics i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 nxp semiconductors 51 4.6.2 lcd controller (lcd if) timing parameters figure 28 shows the lcdif timing and table 47 lists the timing parameters. figure 28. lcd timing 4.7 audio this section provide informat ion about sai/i2s and spdif. 4.7.1 sai/i2s switching specifications this section provides the ac timings for the sai in master (clocks driv en) and slave (clocks input) modes. all timings are given fo r non-inverted serial cl ock polarity (sai_tcr[tsc kp] = 0, sai_rcr[rsckp] = 0) and non-inverted fram e sync (sai_tcr[tfsi] = 0, sai_rcr[rfsi] = 0). if th e polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal (sai_bclk) and/or the frame sync (s ai_fs) shown in the figures below. table 47. lcd timing parameters id parameter symbol min max unit l1 lcd pixel clock frequency tclk(lcd) ? 75 mhz l2 lcd pixel clock high (falling edge capture) tclkh(lcd) 3 ? ns l3 lcd pixel clock low (rising edge capture) tclkl(lcd) 3 ? ns l4 lcd pixel clock high to data valid (falling edge capture) td(clkh-dv) -1 1 ns l5 lcd pixel clock low to data valid (rising edge capture) td(clkl-dv) -1 1 ns l6 lcd pixel clock high to control signal valid (falling edge capture) td(clkh-ctrlv) -1 1 ns l7 lcd pixel clock low to control signal valid (rising edge capture) td(clkl-ctrlv) -1 1 ns / / / / /&'qb&/. idoolqjhgjhfdswxuh /&'qb&/. ulvlqjhgjhfdswxuh /&'qb'$7$>@ /&'q&rqwuro6ljqdov / / /
i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 52 nxp semiconductors electrical characteristics figure 29. sai timing?master modes table 48. master mode sai timing num characteristic min max unit s1 sai_mclk cycle time 2 x t sys ?ns s2 sai_mclk pulse width high/low 40% 60% mclk period s3 sai_bclk cycle time 4 x t sys ?ns s4 sai_bclk pulse width high/low 40% 60% bclk period s5 sai_bclk to sai_fs output valid ? 15 ns s6 sai_bclk to sai_fs output invalid 0 ? ns s7 sai_bclk to sai_txd valid ? 15 ns s8 sai_bclk to sai_txd invalid 0 ? ns s9 sai_rxd/sai_fs input setu p before sai_bclk 15 ? ns s10 sai_rxd/sai_fs input hold after sai_bclk 0 ? ns table 49. slave mode sai timing num characteristic min max unit s11 sai_bclk cycle time (input) 4 x t sys ?ns s12 sai_bclk pulse width high/low (input) 40% 60% bclk period s13 sai_fs input setup before sai_bclk 10 ? ns s14 sai_fa input hold after sai_bclk 2 ? ns s15 sai_bclk to sai_txd/sai_fs output valid ? 20 ns s16 sai_bclk to sai_txd/sa i_fs output invalid 0 ? ns
electrical characteristics i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 nxp semiconductors 53 figure 30. sai timing?slave mode 4.7.2 spdif timing parameters the sony/philips digital interconnect format (spdif) data is sent usi ng the bi-phase marking code. when encoding, the spdif data signal is modulated by a clock that is twice the bit ra te of the data signal. table 50 and figure 31 and figure 32 show spdif timing parameters for the sony/philips digital interconnect format (spdif), including the timing of the modulating rx clock (spdif_sr_clk) for spdif in rx mode and the timing of the modulating tx clock (spdif _st_clk) for spdif in tx mode. s17 sai_rxd setup before sai_bclk 10 ? ns s18 sai_rxd hold after sai_bclk 2 ? ns table 50. spdif timing parameters characteristics symbol timing parameter range unit min max spdif_in skew: asynchronous inputs, no specs apply ? ? 0.7 ns spdif_out output (load = 50pf) ? skew ? transition rising ? transition falling ? ? ? ? ? ? 1.5 24.2 31.3 ns spdif_out1 output (load = 30pf) ? skew ? transition rising ? transition falling ? ? ? ? ? ? 1.5 13.6 18.0 ns modulating rx clock (spdif_sr_clk) period srckp 40.0 ? ns table 49. slave mode sai timing num characteristic min max unit
i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 54 nxp semiconductors electrical characteristics figure 31. spdif_sr_clk timing diagram figure 32. spdif_st_clk timing diagram 4.8 analog the following sections provide in formation about analog interfaces. 4.8.1 dcdc table 51 introduces the dcdc electrical specifications. spdif_sr_clk high period srckph 16.0 ? ns spdif_sr_clk low period srckpl 16.0 ? ns modulating tx clock (spdif_st_clk) period stclkp 40.0 ? ns spdif_st_clk high period stclkph 16.0 ? ns spdif_st_clk low period stclkpl 16.0 ? ns table 51. dcdc electrical specifications mode buck mode, one output notes input voltage 2.9 v (a0); 3.3 v (a1) min = 2.8 v max = 3.0 v (a0) and 3.6 v a1) output voltage 1.1 v configurable 0.8 ~ 1.575 v with 25 mv one step in the run mode max loading 500 ma ? table 50. spdif timing parameters (continued) characteristics symbol timing parameter range unit min max spdif_sr_clk (output) v m v m srckp srckph srckpl spdif_st_clk (input) v m v m stclkp stclkph stclkpl
electrical characteristics i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 nxp semiconductors 55 4.8.2 a/d converter this section introduces information about a/d converter. 4.8.2.1 12-bit adc electrical characteristics the section provide information about 12-bit adc electrica l characteristics. 4.8.2.1.1 12-bit adc operating conditions loading in low power modes 200 ? a ~ 30 ma ? efficiency 90% max @150 ma low power mode open loop mode ripple is about 15 mv in run mode run mode ? always continuous mode ? support discontinuous mode configurable by register inductor 4.7 ? h? capacitor 33 ? f? over voltage protection 1.55 v detect vddsoc, when the voltage is higher than 1.6 v, shutdown dcdc. over current protection 1 a detect the peak current ? run mode: when the current is larger than 1 a, shutdown dcdc. low dcdc_in detection 2.6 v detect the dcdc_in, when battery is lower than 2.6 v, shutdown dcdc. table 52. 12-bit adc operating conditions characteristic conditions symb min typ 1 max unit comment supply voltage absolute v dda 3.0 - 3.6 v ? delta to vdd (vdd-vdda) 2 ? v dda -100 0 100 mv ? ground voltage delta to vss (vss-vssad) ? v ssad -100 0 100 mv ? ref voltage high ? v dda 1.13 v dda v dda v ? ref voltage low ? v ss v ssad v ssad v ssad v ? input voltage ? v adin v refl ?v refh v ? input capacitance 8/10/12 bit modes c adin ?1.52 pf ? table 51. dcdc electrical specifications (continued) mode buck mode, one output notes
i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 56 nxp semiconductors electrical characteristics figure 33. 12-bit adc input impedance equivalency diagram input resistance adlpc=0, adhsc=1 r adin ?5 7 kohms ? adlpc=0, adhsc=0 ? 12.5 15 kohms ? adlpc=1, adhsc=0 ? 25 30 kohms ? analog source resistance 12 bit mode f adck = 40mhz adlsmp=0, adsts=10, adhsc=1 r as ? ? 1 kohms t samp =150 ns r as depends on sample time setting (adlsmp, adsts) and adc power mode (adhsc, adlpc). see charts for minimum sample time vs r as adc conversion clock frequency adlpc=0, adhsc=1 12 bit mode f adck 4 ? 40 mhz ? adlpc=0, adhsc=0 12 bit mode 4 ? 30 mhz ? adlpc=1, adhsc=0 12 bit mode 4 ? 20 mhz ? 1 typical values assume vddad = 3.0 v, temp = 25c, f adck =20 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 2 dc potential differences table 52. 12-bit adc operating conditions (continued) characteristic conditions symb min typ 1 max unit comment
electrical characteristics i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 nxp semiconductors 57 12-bit adc characteristics table 53. 12-bit adc characteristics (v refh = v dda , v refl = v ssad ) characteristic conditions 1 symb min typ 2 max unit comment supply current adlpc=1, adhsc=0 i dda ? 350 ? a adlsmp=0 adsts=10 adco=1 adlpc=0, adhsc=0 460 adlpc=0, adhsc=1 750 supply current stop, reset, module off i dda ?1.42 a ? adc asynchronous clock source adhsc=0 f adack ? 10 ? mhz t adack = 1/f adack adhsc=1 ? 20 ? sample cycles adlsmp=0, adsts=00 csamp ? 2 ? cycles ? adlsmp=0, adsts=01 4 adlsmp=0, adsts=10 6 adlsmp=0, adsts=11 8 adlsmp=1, adsts=00 12 adlsmp=1, adsts=01 16 adlsmp=1, adsts=10 20 adlsmp=1, adsts=11 24
i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 58 nxp semiconductors electrical characteristics conversion cycles adlsmp=0 adsts=00 cconv ? 28 ? cycles ? adlsmp=0 adsts=01 30 adlsmp=0 adsts=10 32 adlsmp=0 adsts=11 34 adlsmp=1 adsts=00 38 adlsmp=1 adsts=01 42 adlsmp=1 adsts=10 46 adlsmp=1, adsts=11 50 conversion time adlsmp=0 adsts=00 tconv ? 0.7 ? s fadc=40 mhz adlsmp=0 adsts=01 0.75 adlsmp=0 adsts=10 0.8 adlsmp=0 adsts=11 0.85 adlsmp=1 adsts=00 0.95 adlsmp=1 adsts=01 1.05 adlsmp=1 adsts=10 1.15 adlsmp=1, adsts=11 1.25 total unadjusted error 12 bit mode tue ? 3.4 ? lsb 1 lsb = (v refh - v refl )/2 n avge = 1, avgs = 11 10 bit mode ? 1.5 ? 8 bit mode ? 1.2 ? differential non-linearity 12 bit mode dnl ? 0.76 ? lsb avge = 1, avgs = 11 10bit mode ? 0.36 ? 8 bit mode ? 0.14 ? table 53. 12-bit adc characteristics (v refh = v dda , v refl = v ssad ) (continued) characteristic conditions 1 symb min typ 2 max unit comment
electrical characteristics i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 nxp semiconductors 59 note the adc electrical spec would be met with the calibration enabled configuration. 4.8.3 acmp table 54 lists the acmp elect rical specifications. integral non-linearity 12 bit mode inl ? 2.78 ? lsb avge = 1, avgs = 11 10bit mode ? 0.61 ? 8 bit mode ? 0.14 ? zero-scale error 12 bit mode e zs ? -1.14 ? lsb avge = 1, avgs = 11 10bit mode ? -0.25 ? 8 bit mode ? -0.19 ? full-scale error 12 bit mode e fs ? -1.06 ? lsb avge = 1, avgs = 11 10bit mode ? -0.03 ? 8 bit mode ? -0.02 ? effective number of bits 12 bit mode enob 10.1 10.7 ? bits avge = 1, avgs = 11 signal to noise plus distortion see enob sinad sinad = 6.02 x enob + 1.76 db avge = 1, avgs = 11 1 all accuracy numbers assume the adc is calibrated with v refh =v ddad 2 typical values assume v ddad = 3.0 v, temp = 25c, f adck =20 mhz unless otherwise stated. typical values are for reference only and are not tested in production. table 54. comparator and 6-bit dac electrical specifications symbol description min. typ. max. unit v dd supply voltage 3.0 ? 3.6 v i ddhs supply current, high-speed mode (en = 1, pmode = 1) ? 347 ? ? a i ddls supply current, low-speed mode (en = 1, pmode = 0) ?42? ? a v ain analog input voltage v ss ?v dd v v aio analog input offset voltage ? ? 21 mv table 53. 12-bit adc characteristics (v refh = v dda , v refl = v ssad ) (continued) characteristic conditions 1 symb min typ 2 max unit comment
i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 60 nxp semiconductors electrical characteristics 4.9 communication interfaces the following sections provide the info rmation about communication interfaces. 4.9.1 lpspi timing parameters the low power serial peripheral interface (lpspi) prov ides a synchronous serial bus with master and slave operations. many of the transf er attributes are progr ammable. the following tables provide timing characteristics for cla ssic lpspi timing modes. all timing is shown with respect to 20% v dd and 80% v dd thresholds, unless note d, as well as input signal transitions of 3 ns and a 30 pf maximum load on all lpspi pins. v h analog comparator hysteresis 1 mv ? cr0[hystctr] = 00 ? 1 2 ? cr0[hystctr] = 01 ? 21 54 ? cr0[hystctr] = 10 ? 42 108 ? cr0[hystctr] = 11 ? 64 184 v cmpoh output high v dd - 0.5 ? ? v v cmpoi output low ? ? 0.5 v t dhs propagation delay, high-speed mode (en = 1, pmode = 1) 2 ?2540ns t dls propagation delay, low-speed mode (en = 1, pmode = 0) 2 ?5090ns t dinit analog comparator initialization delay 3 ?1.5? ? s i dac6b 6-bit dac current adder (enabled) ? 5 ? ? a r dac6b 6-bit dac reference inputs ? v dd ?v inl dac6b 6-bit dac integral non-linearity -0.3 ? 0.3 lsb 4 dnl dac6b 6-bit dac differential non-linearity -0.15 ? 0.15 lsb 4 1 typical hysteresis is measured with input voltage range limited to 0.7 to v dd - 0.7 v in high speed mode. 2 signal swing is 100 mv. 3 comparator initialization delay is defined as the time betwe en software writes to the enable comparator module and the comparator output setting to a stable level. 4 1 lsb = v reference / 64 table 54. comparator and 6-bit dac el ectrical specifications (continued) symbol description min. typ. max. unit
electrical characteristics i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 nxp semiconductors 61 figure 34. lpspi master mode timing (cpha = 0) table 55. lpspi master mode timing number symbol descripti on min. max. units note 1f op frequency of operation f periph / 2048 f periph / 2 hz 1 1 absolute maximum frequency of operat ion (fop) is 30 mhz. t he clock driver in the lpspi module for f periph must be guaranteed this limit is not exceeded. 2t spsck spsck period 2 x t periph 2048 x t periph ns 2 2 t periph = 1 / f periph 3t lead enable lead time 1/2 ? t spsck ? 4t lag enable lag time 1/2 ? t spsck ? 5t wspsck clock (spsck) high or low time t periph - 30 1024 x t periph ns ? 6t su data setup time (inputs) 18 ? ns ? 7t hi data hold time (inputs) 0 ? ns ? 8t v data valid (after spsck edge( ? 15 ns ? 9t ho data hold time (outputs) 0 ? ns ? 10 t ri t fi rise time input fall time input ?t periph - 25 ns ? 11 t ro t fo rise time output fall time output ?25ns? 287387 06%,1 /6%,1 06%287 /6%287 &32/ 636&. 636&. &32/ /6%) )ru/6%) elwrughulv/6%elwelw 06% ,ifrqiljxuhgdvdqrxwsxw 66 287387 287387 026, 287387 0,62 ,1387 %,7 %,7
i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 62 nxp semiconductors electrical characteristics figure 35. lpspi master mode timing (cpha = 1) table 56. lpspi slave mode timing number symbol descripti on min. max. units note 1f op frequency of operation 0 f periph / 2 hz 1 1 absolute maximum frequency of operat ion (fop) is 30 mhz. t he clock driver in the lpspi module for f periph must be guaranteed this limit is not exceeded. 2t spsck spsck period 4 x t periph ?ns 2 2 t periph = 1 / f periph 3t lead enable lead time 1 ? t periph ? 4t lag enable lag time 1 ? t periph ? 5t wspsck clock (spsck) high or low time t periph - 30 ? ns ? 6t su data setup time (inputs) 2.5 ? ns ? 7t hi data hold time (inputs) 3.5 ? ns ? 8t a slave access time ? t periph ns 3 3 time to data active from high-impedance state 9t dis slave miso disable time ? t periph ns 4 4 hold time to high-impedance state 10 t v data valid (after spsck edge) ? 31 ns ? 11 t ho data hold time (outputs) 0 ? ns ? 12 t ri t fi rise time input fall time input ?t periph - 25 ns ? 13 t ro t fo rise time input fall time input ?25ns? 06%,1 %,7 0$67(506%287 0$67(5/6%287 3257'$7$ 3257'$7$ ,ifrqiljxuhgdvrxwsxw /6%) )ru/6%) elwrughulv/6%elwelw 06% 287387 &32/ 636&. 636&. &32/ 66 287387 287387 026, 287387 0,62 ,1387 /6%,1 %,7
electrical characteristics i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 nxp semiconductors 63 figure 36. lpspi slave mode timing (cpha = 0) figure 37. lpspi slave mode timing (cpha = 1) 06%,1 %,7 6/$9(06% 6/$9(/6%287 6(( 127( vhh qrwh ,1387 &32/ 636&. 636&. &32/ 66 ,1387 ,1387 026, ,1387 0,62 287387 /6%,1 %,7 06%,1 %,7 06%287 6/$9(/6%287 6/$9( vhh qrwh ,1387 &32/ 636&. 636&. &32/ 66 ,1387 ,1387 026, ,1387 0,62 287387 /6%,1 %,7
i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 64 nxp semiconductors electrical characteristics 4.9.2 lpi2c module timing parameters this section describes the timing parameters of the lpi2c module. 4.9.3 ultra high speed sd/sdio/ mmc host interface (usdhc) ac timing this section describes the electrical informat ion of the usdhc, which includes sd/emmc4.3 (single data rate) timing, emmc4.4/4.41/4.5 (dual date rate) timing and sd r104/50(sd3.0) timing. 4.9.3.1 sd/emmc4.3 (single data rate) ac timing figure 38 depicts the timing of sd/emmc4.3, and table 58 lists the sd/emmc4.3 ti ming characteristics. figure 38. sd/emmc4.3 timing table 57. lpi2c module timing parameters symbol description min max unit notes f scl scl clock frequency standard mode (sm) 0 100 khz 1, 2 1 hs-mode is only supported in slave mode. 2 see general switching specifications. fast mode (fm) 0 400 fast mode plus (fm+) 0 1000 ultra fast mode (ufm) 0 5000 high speed mode (hs-mode) 0 3400 sd1 sd3 sd5 sd4 sd7 sdx_clk sd2 sd8 sd6 output from usdhc to card input from card to usdhc sdx_data[7:0] sdx_data[7:0]
electrical characteristics i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 nxp semiconductors 65 4.9.3.2 emmc4.4/4.41 (dual data rate) ac timing figure 39 depicts the timi ng of emmc4.4/4.41. table 59 lists the emmc4.4/4.41 ti ming characteristics. be aware that only data is sampled on both e dges of the clock (not applicable to cmd). table 58. sd/emmc4.3 interface timing specification id parameter symbols min max unit card input clock sd1 clock frequency (low speed) f pp 1 1 in low speed mode, card clock must be lower than 400 khz, voltage ranges from 2.7 to 3.6 v. 0 400 khz clock frequency (sd/sdio full speed/high speed) f pp 2 2 in normal (full) speed mode for sd/sdio card, clock frequency can be any value between 0 ? 25 mhz. in high-speed mode, clock frequency can be any value between 0 ? 50 mhz. 0 25/50 mhz clock frequency (mmc full speed/high speed) f pp 3 3 in normal (full) speed mode for mmc card, clock frequency can be any value between 0 ? 20 mhz. in high-speed mode, clock frequency can be any value between 0 ? 52 mhz. 0 20/52 mhz clock frequency (identification mode) f od 100 400 khz sd2 clock low time t wl 7?ns sd3 clock high time t wh 7?ns sd4 clock rise time t tlh ?3ns sd5 clock fall time t thl ?3ns usdhc output/card inputs sd_cmd, sdx_datax (reference to clk) sd6 usdhc output delay t od -6.6 3.6 ns usdhc input/card outp uts sd_cmd, sdx_datax (reference to clk) sd7 usdhc input setup time t isu 2.5 ? ns sd8 usdhc input hold time 4 4 to satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns. t ih 1.5 ? ns
i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 66 nxp semiconductors electrical characteristics figure 39. emmc4.4/4.41 timing table 59. emmc4.4/4.41 in terface timing specification id parameter symbols min max unit card input clock sd1 clock frequency (emmc4.4/4.41 ddr) f pp 052mhz sd1 clock frequency (sd3.0 ddr) f pp 050mhz usdhc output / card inputs sd_cmd, sdx_datax (reference to clk) sd2 usdhc output delay t od 2.5 7.1 ns usdhc input / card outputs sd_cmd , sdx_datax (reference to clk) sd3 usdhc input setup time t isu 1.7 ? ns sd4 usdhc input hold time t ih 1.5 ? ns sd1 sd2 sd3 output from esdhcv3 to card input from card to esdhcv3 sdx_data[7:0] sdx_clk sd4 sd2 ...... ...... sdx_data[7:0]
electrical characteristics i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 nxp semiconductors 67 4.9.3.3 sdr50/sdr104 ac timing figure 40 depicts the timing of sdr50/sdr104, and table 60 lists the sdr50/sdr104 timing characteristics. figure 40. sdr50/sdr104 timing table 60. sdr50/sdr104 interface timing specification id parameter symbols min max unit card input clock sd1 clock frequency period t clk 5.0 ? ns sd2 clock low time t cl 0.46 x t clk 0.54 x t clk ns sd3 clock high time t ch 0.46 x t clk 0.54 x t clk ns usdhc output/card inputs sd_cmd, sdx_datax in sdr50 (reference to clk) sd4 usdhc output delay t od ?3 1 ns usdhc output/card inputs sd_cmd, sdx_datax in sdr104 (reference to clk) sd5 usdhc output delay t od ?1.6 1 ns usdhc input/card outputs sd_cmd, sdx_datax in sdr50 (reference to clk) sd6 usdhc input setup time t isu 2.5 ? ns sd7 usdhc input hold time t ih 1.5 ? ns usdhc input/card outputs sd_cmd, sdx_datax in sdr104 (reference to clk) 1 1 data window in sdr104 mode is variable. sd8 card output data window t odw 0.5 x t clk ?ns 6&. elwrxwsxwiurpx6'+&wrfdug elwlqsxwiurpfdugwrx6'+& 6' 6' 6' 6'6' 6' 6' 6'
i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 68 nxp semiconductors electrical characteristics 4.9.3.4 hs200 mode timing figure 41 depicts the timing of hs200 mode, and table 61 lists the hs200 timing characteristics. figure 41. hs200 mode timing 4.9.3.5 bus operation conditio n for 3.3 v and 1.8 v signaling signaling level of sd/emmc4.3 a nd emmc4.4/4.41 modes is 3.3 v. si gnaling level of sdr104/sdr50 mode is 1.8 v. the dc parameters for the nvcc _sd1 supply are identical to those shown in table 21, "single voltage gpio dc parameters," on page 30 . 4.9.4 ethernet controller (enet) ac electrical specifications the following timing specs are defined at the chip i/o pin and must be tr anslated appropria tely to arrive at timing specs/constraint s for the physical interface. table 61. hs200 interfac e timing specification id parameter symbols min max unit card input clock sd1 clock frequency period t clk 5.0 ? ns sd2 clock low time t cl 0.46 x t clk 0.54 x t clk ns sd3 clock high time t ch 0.46 x t clk 0.54 x t clk ns usdhc output/card inputs sd_cmd, sdx_datax in hs200 (reference to clk) sd5 usdhc output delay t od ?1.6 0.74 ns usdhc input/card outputs sd_cmd, sdx_datax in hs200 (reference to clk) 1 1 hs200 is for 8 bits while sdr104 is for 4 bits. sd8 card output data window t odw 0.5 x t clk ?ns 6&. elwrxwsxwiurpx6'+&wrh00& elwlqsxwiurph00&wrx6'+& 6' 6'6' 6' 6' 6'
electrical characteristics i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 nxp semiconductors 69 4.9.4.1 enet mii mode timing this subsection describes mii receive, transmit, as ynchronous inputs, and serial management signal timings. 4.9.4.1.1 mii receive signal timing (enet_rx_data3,2,1,0, enet_rx_en, enet_rx_er, and enet_rx_clk) the receiver functions correctly up to an enet_rx_clk maximum frequency of 25 mhz + 1%. there is no minimum frequency requirement. additionally, the processor clock frequency must exceed twice the enet_rx_clk frequency. figure 42 shows mii receive signal timings. table 62 describes the timing para meters (m1?m4) shown in the figure. figure 42. mii receive signal timing diagram 1 enet_rx_en, enet_rx_clk, and enet0_rxd0 have the same timing in 10 mbps 7-wire interface mode. 4.9.4.1.2 mii transmit si gnal timing (enet_tx_d ata3,2,1,0, enet_tx_en, enet_tx_er, and enet_tx_clk) the transmitter functions correctly up to an enet_tx_clk maximum frequency of 25 mhz + 1%. there is no minimum frequency requi rement. additionally, the processo r clock frequency must exceed twice the enet_tx_clk frequency. table 62. mii receive signal timing id characteristic 1 min. max. unit m1 enet_rx_data3,2,1,0, en et_rx_en, enet_rx_er to enet_rx_clk setup 5? ns m2 enet_rx_clk to enet_rx_ data3,2,1,0, enet_rx_en, enet_rx_er hold 5? ns m3 enet_rx_clk pulse width hi gh 35% 65% enet_rx_clk period m4 enet_rx_clk pulse width low 35% 65% enet_rx_clk period enet_rx_clk (input) enet_rx_data3,2,1,0 m3 m4 m1 m2 enet_rx_er enet_rx_en (inputs)
i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 70 nxp semiconductors electrical characteristics figure 43 shows mii transm it signal timings. table 63 describes the timing pa rameters (m5?m8) shown in the figure. figure 43. mii transmit signal timing diagram 1 enet_tx_en, enet_tx_clk, and en et0_txd0 have the same timing in 10-mbps 7-wire interface mode. 4.9.4.1.3 mii asynchronou s inputs signal timing (e net_crs and enet_col) figure 44 shows mii asynchronous input timings. table 64 describes the timing pa rameter (m9) shown in the figure. figure 44. mii asynchronous inputs timing diagram 1 enet_col has the same timing in 10-mbit 7-wire interface mode. table 63. mii transmit signal timing id characteristic 1 min. max. unit m5 enet_tx_clk to enet_tx_ data3,2,1,0, enet_tx_en, enet_tx_er invalid 5? ns m6 enet_tx_clk to enet_tx_ data3,2,1,0, enet_tx_en, enet_tx_er valid ?20 ns m7 enet_tx_clk pulse width high 35% 65% enet_tx_clk period m8 enet_tx_clk pulse width low 35% 65% enet_tx_clk period table 64. mii asynchronous inputs signal timing id characteristic min. max. unit m9 1 enet_crs to enet_col minimum pulse width 1.5 ? enet_tx_clk period enet_tx_clk (input) enet_tx_data3,2,1,0 m7 m8 m5 m6 enet_tx_er enet_tx_en (outputs) enet_crs, enet_col m9
electrical characteristics i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 nxp semiconductors 71 4.9.4.1.4 mii serial mana gement channel timing (e net_mdio and enet_mdc) the mdc frequency is designed to be equal to or less than 2.5 mhz to be compatible with the ieee 802.3 mii specification. however the enet can function correctly with a maximum mdc frequency of 15 mhz. figure 45 shows mii asynchr onous input timings. table 65 describes the timing parameters (m10?m15) shown in the figure. figure 45. mii serial management channel timing diagram 4.9.4.2 rmii mode timing in rmii mode, enet_clk is used as the ref_cl k, which is a 50 mhz 50 ppm continuous reference clock. enet_rx_en is used as the enet_rx_en in rmii. other signals under rmii mode include enet_tx_en, enet_tx_data[1:0] , enet_rx_data[1:0] and enet_rx_er. table 65. mii serial management channel timing id characteristic min. max. unit m10 enet_mdc falling edge to enet_mdio output invalid (min. propagation delay) 0? ns m11 enet_mdc falling edge to enet_mdio output valid (max. propagation delay) ?5 ns m12 enet_mdio (input) to enet_mdc rising edge setup 18 ? ns m13 enet_mdio (input) to enet_mdc rising edge hold 0 ? ns m14 enet_mdc pulse width high 40% 60% enet_mdc period m15 enet_mdc pulse width low 40% 60% enet_mdc period enet_mdc (output) enet_mdio (output) m14 m15 m10 m11 m12 m13 enet_mdio (input)
i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 72 nxp semiconductors electrical characteristics figure 46 shows rmii mode timings. table 66 describes the timing parame ters (m16?m21) shown in the figure. figure 46. rmii mode si gnal timing diagram 4.9.5 flexible controller area netw ork (flexcan) ac electrical specifications please refer to section 4.3.2.1, ?general purpose i/o ac parameters . 4.9.6 lpuart electrical specifications please refer to section 4.3.2.1, ?general purpose i/o ac parameters . table 66. rmii signal timing id characteristic min. max. unit m16 enet_clk pulse width high 35% 65% enet_clk period m17 enet_clk pulse width low 35% 65% enet_clk period m18 enet_clk to enet 0_txd[1:0], enet_tx_data invalid 4 ? ns m19 enet_clk to enet 0_txd[1:0], enet_tx_data valid ? 13 ns m20 enet_rx_datad[1:0], enet_r x_en(enet_rx_en), enet_rx_er to enet_clk setup 2? ns m21 enet_clk to enet_rx_datad[ 1:0], enet_rx_en, enet_rx_er hold 2? ns enet_clk (input) enet_tx_en m16 m17 m18 m19 m20 m21 enet_rx_data[1:0] enet_tx_data (output) enet_rx_er enet_rx_en (input)
electrical characteristics i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 nxp semiconductors 73 4.9.7 usb phy parameters this section describes the usb-otg phy parameters. the usb phy meets the electrical compliance requireme nts defined in the univer sal serial bus revision 2.0 otg with the following amendments. ? usb engineering change notice ? title: 5v short circuit withstand requirement change ? applies to: universal serial bus specification, revision 2.0 ? errata for usb revision 2.0 april 27, 2000 as of 12/7/2000 ? usb engineering change notice ? title: pull-up/pull-down resistors ? applies to: universal serial bus specification, revision 2.0 ? usb engineering change notice ? title: suspend current limit changes ? applies to: universal serial bus specification, revision 2.0 ? usb engineering change notice ? title: usb 2.0 phase locked sofs ? applies to: universal serial bus specification, revision 2.0 ? on-the-go and embedded host supplement to the usb revision 2.0 specification ? revision 2.0 plus errata and ecn june 4, 2010 ? battery charging specificati on (available from usb-if) ? revision 1.2, december 7, 2010 ? portable device only 4.10 timers this section provide information on timers. 4.10.1 pulse width modulator (pwm) characteristics this section describes the electrical information of the pwm. 4.10.2 quad timer timing table 68 listed the timing parameters. table 67. pwm timing parameters parameter symbo min typ max unit pwm clock frequency ? 80 ? 120 mhz power-up time t pu ?25? ? s
i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 74 nxp semiconductors electrical characteristics figure 47. quad timer timing table 68. quad timer timing characteristic symbo min 1 1 t = clock cycle. for 60 mhz operation, t = 16.7 ns. max unit see figure timer input period t in 2t + 6 ? ns timer input high/low period t inhl 1t + 3 ? ns timer output period t out 33 ? ns timer output high/low period t outhl 16.7 ? ns 4 /54 4 /54(, 4 /54(, 4 ). 4 ).(, 4 ).(, 4imer)nputs 4imer/utputs
boot mode configuration i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 nxp semiconductors 75 5 boot mode configuration this section provides information on boot mode configuration pins allo cation and boot devices interfaces allocation. 5.1 boot mode configuration pins table 69 provides boot options, functionalit y, fuse values, and associated pi ns. several input pins are also sampled at reset and can be used to override fuse values, depending on the va lue of bt_fuse_sel fuse. the boot option pins are in effect when bt_fuse_sel fuse is ?0? (cleared, which is the case for an unblown fuse). for detailed boot m ode options configured by the boot mode pins, see the i.mx rt1050 fuse map document and the system boot chapter in i.mx rt1050 referenc e manual (imxrt1050_rm) . 5.2 boot device interface allocation the following tables list th e interfaces that can be us ed by the boot process in acc ordance with the specific boot mode configuration. th e tables also describe the interface? s specific modes and iomuxc allocation, which are configured during boot when appropriate. table 69. fuses and associated pins used for boot pad default setting on reset efuse name details gpio_ad_b0_04 100 k pull-down boot_mode0 gpio_ad_b0_05 100 k pull-down boot_mode1 gpio_b0_04 100 k pull-down bt_cfg[0] boot options, pin value overrides fuse settings for bt_fuse_sel = ?0?. signal configuration as fuse override input at power up. these are special i/o lines that control the boot up configuration during product development. in production, the boot configuration can be controlled by fuses. gpio_b0_05 100 k pull-down bt_cfg[1] gpio_b0_06 100 k pull-down bt_cfg[2] gpio_b0_07 100 k pull-down bt_cfg[3] gpio_b0_08 100 k pull-down bt_cfg[4] gpio_b0_09 100 k pull-down bt_cfg[5] gpio_b0_10 100 k pull-down bt_cfg[6] gpio_b0_11 100 k pull-down bt_cfg[7] gpio_b0_12 100 k pull-down bt_cfg[8] gpio_b0_13 100 k pull-down bt_cfg[9] gpio_b0_14 100 k pull-down bt_cfg[10] gpio_b0_15 100 k pull-down bt_cfg[11] table 70. boot trough nand pad name io function alt comments gpio_emc_00 semc.data[0] alt 0 ? gpio_emc_01 semc.data[1] alt 0 ? gpio_emc_02 semc.data[2] alt 0 ?
i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 76 nxp semiconductors boot mode configuration gpio_emc_03 semc.data[3] alt 0 ? gpio_emc_04 semc.data[4] alt 0 ? gpio_emc_05 semc.data[5] alt 0 ? gpio_emc_06 semc.data[6] alt 0 ? gpio_emc_07 semc.data[7] alt 0 ? gpio_emc_30 semc.data[8] alt 0 ? gpio_emc_31 semc.data[9] alt 0 ? gpio_emc_32 semc.data[10] alt 0 ? gpio_emc_33 semc.data[11] alt 0 ? gpio_emc_34 semc.data[12] alt 0 ? gpio_emc_35 semc.data[13] alt 0 ? gpio_emc_36 semc.data[14] alt 0 ? gpio_emc_37 semc.data[15] alt 0 ? gpio_emc_18 semc.addr[9] alt 0 ? gpio_emc_19 semc.addr[11] alt 0 ? gpio_emc_20 semc.addr[12] alt 0 ? gpio_emc_22 semc.ba1 alt 0 ? gpio_emc_41 semc.csx[0] alt 0 ? table 71. boot trough nor pad name io function alt comments gpio_emc_00 semc.data[0] alt 0 ? gpio_emc_01 semc.data[1] alt 0 ? gpio_emc_02 semc.data[2] alt 0 ? gpio_emc_03 semc.data[3] alt 0 ? gpio_emc_04 semc.data[4] alt 0 ? gpio_emc_05 semc.data[5] alt 0 ? gpio_emc_06 semc.data[6] alt 0 ? gpio_emc_07 semc.data[7] alt 0 ? gpio_emc_30 semc.data[8] alt 0 ? gpio_emc_31 semc.data[9] alt 0 ? gpio_emc_32 semc.data[10] alt 0 ? gpio_emc_33 semc.data[11] alt 0 ? table 70. boot trough nand
boot mode configuration i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 nxp semiconductors 77 gpio_emc_34 semc.data[12] alt 0 ? gpio_emc_35 semc.data[13] alt 0 ? gpio_emc_36 semc.data[14] alt 0 ? gpio_emc_37 semc.data[15] alt 0 ? gpio_emc_09 semc.addr[0] alt 0 ? gpio_emc_10 semc.addr[1] alt 0 ? gpio_emc_11 semc.addr[2] alt 0 ? gpio_emc_12 semc.addr[3] alt 0 ? gpio_emc_13 semc.addr[4] alt 0 ? gpio_emc_14 semc.addr[5] alt 0 ? gpio_emc_15 semc.addr[6] alt 0 ? gpio_emc_16 semc.addr[7] alt 0 ? gpio_emc_19 semc.addr[11] alt 0 ? gpio_emc_20 semc.addr[12] alt 0 ? gpio_emc_21 semc.ba0 alt 0 ? gpio_emc_22 semc.ba1 alt 0 ? gpio_emc_41 semc.csx[0] alt 0 ? table 72. boot through flexspi pad name io function mux mode comments gpio_sd_b1_00 flexspi.b_data[3] alt 1 ? gpio_sd_b1_01 flexspi.b_data[2] alt 1 ? gpio_sd_b1_02 flexspi.b_data[1] alt 1 ? gpio_sd_b1_03 flexspi.b_data[0] alt 1 ? gpio_sd_b1_04 flexspi.b_sclk alt 1 ? gpio_sd_b0_05 flexspi.b_dqs alt 4 ? gpio_sd_b0_04 flexspi.b_ss0_b alt 4 ? gpio_sd_b0_01 flexspi.b_ss1_b alt 6 ? gpio_sd_b1_05 flexspi.a_dqs alt 1 ? gpio_sd_b1_06 flexspi.a_ss0_b alt 1 ? gpio_sd_b0_00 flexspi.a_ss1_b alt 6 ? gpio_sd_b1_07 flexspi.a_sclk alt 1 ? gpio_sd_b1_08 flexspi.a_data[0] alt 1 ? gpio_sd_b1_09 flexspi.a_data[1] alt 1 ? table 71. boot trough nor
i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 78 nxp semiconductors boot mode configuration gpio_sd_b1_10 flexspi.a_data[2] alt 1 ? gpio_sd_b1_11 flexspi.a_data[3] alt 1 ? table 73. boot through sd1 pad name io function mux mode comments gpio_sd_b0_00 usdhc1.cmd alt 0 ? gpio_sd_b0_01 usdhc1.clk alt 0 ? gpio_sd_b0_02 usdhc1.data0 alt 0 ? gpio_sd_b0_03 usdhc1.data1 alt 0 ? gpio_sd_b0_04 usdhc1.data2 alt 0 ? gpio_sd_b0_05 usdhc1.data3 alt 0 ? table 74. boot through sd2 pad name io function mux mode comments gpio_sd_b1_00 usdhc2.data3 alt 0 ? gpio_sd_b1_01 usdhc2.data2 alt 0 ? gpio_sd_b1_02 usdhc2.data1 alt 0 ? gpio_sd_b1_03 usdhc2.data0 alt 0 ? gpio_sd_b1_04 usdhc2.clk alt 0 ? gpio_sd_b1_05 usdhc2.cmd alt 0 ? gpio_sd_b1_06 usdhc2.reset_b alt 0 ? gpio_sd_b1_08 usdhc2.data4 alt 0 ? gpio_sd_b1_09 usdhc2.data5 alt 0 ? gpio_sd_b1_10 usdhc2.data6 alt 0 ? gpio_sd_b1_11 usdhc2.data7 alt 0 ? table 75. boot through spi-1 pad name io function mux mode comments gpio_sd_b0_00 lpspi1.sck alt 4 ? gpio_sd_b0_02 lpspi1.sdo alt 4 ? gpio_sd_b0_03 lpspi1.sdi alt 4 ? gpio_sd_b0_01 lpspi1.pcs0 alt 4 ? table 72. boot through flexspi (continued) pad name io function mux mode comments
boot mode configuration i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 nxp semiconductors 79 table 76. boot through spi-2 pad name io function mux mode comments gpio_sd_b1_07 lpspi2.sck alt 4 ? gpio_sd_b1_08 lpspi2.sdo alt 4 ? gpio_sd_b1_09 lpspi2.sdi alt 4 ? gpio_sd_b1_06 lpspi2.pcs0 alt 4 ? table 77. boot through spi-3 pad name io function mux mode comments gpio_ad_b0_00 lpspi3.sck alt 7 ? gpio_ad_b0_01 lpspi3.sdo alt 7 ? gpio_ad_b0_02 lpspi3.sdi alt 7 ? gpio_sd_b0_03 lpspi3.pcs0 alt 7 ? table 78. boot through spi-4 pad name io function mux mode comments gpio_b0_03 lpspi4.sck alt 3 ? gpio_b0_02 lpspi4.sdo alt 3 ? gpio_b0_01 lpspi4.sdi alt 3 ? gpio_b0_00 lpspi4.pcs0 alt 3 ? table 79. boot through uart1 pad name io function mux mode comments gpio_ad_b0_12 lpuart1.tx alt 2 ? gpio_ad_b0_13 lpuart1.rx alt 2 ? gpio_ad_b0_14 lpuart1.cts_b alt 2 ? gpio_ad_b0_15 lpuart1.rts_b alt 2 ? table 80. boot through uart2 pad name io function mux mode comments gpio_ad_b1_00 lpuart2.cts_b alt 2 ? gpio_ad_b1_01 lpuart2.rts_b alt 2 ? gpio_ad_b1_02 lpuart2.tx alt 2 ? gpio_ad_b1_03 lpuart2.rx alt 2 ?
i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 80 nxp semiconductors package information and contact assignments 6 package information and contact assignments this section includes the contact assignment information and mechanical package drawing. 6.1 10 x 10 mm package information 6.1.1 10 x 10 mm, 0.65 mm pitch, ball matrix figure 48 shows the top, bottom, and side views of the 10 x 10 mm mapbga package.
package information and contact assignments i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 nxp semiconductors 81 figure 48. 10 x 10 mm bga, case x package top, bottom, and side views
i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 82 nxp semiconductors package information and contact assignments 6.1.2 10 x 10 mm supplies contact assi gnments and functional contact assignments table 81 shows the device connection list for groun d, sense, and reference contact signals. table 82 shows an alpha-sorted list of functional contact assignments for the 10 x 10 mm package. table 81. 10 x 10 mm supplies contact assignment supply rail name ball(s) position(s) remark dcdc_in l1, l2 ? dcdc_in_q k4 ? dcdc_gnd n1, n2 ? dcdc_lp m1, m2 ? dcdc_pswitch k3 ? dcdc_sense j5 ? gpanaio n10 ? ngnd_kel0 k9 ? nvcc_emc e6, f5 ? nvcc_gpio e9, f10, j10 ? nvcc_pll p10 ? nvcc_sd0 j6 ? nvcc_sd1 k5 ? vdda_adc_3p3 n14 ? vdd_high_cap p8 ? vdd_high_in p12 ? vdd_snvs_cap m10 ? vdd_snvs_in m9 ? vdd_soc_in f6, f7, f8, f9, g6, g9, h6, h9, j9 ? vdd_usb_cap k8 ? vss a1, a14, b5, b10, e2, e13, g7, g8, h7, h8, j7, j8, k2, k13, l9, n5, n8, p1, p14 ? table 82. 10 x 10 mm functional contact assignments ball name 10 x 10 ball power group ball type default setting default mode default function input/ output value ccm_clk1_n p13 ? ? ? ccm_clk1_n ? ? ccm_clk1_p n13 ? ? ? ccm_clk1_p ? ?
package information and contact assignments i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 nxp semiconductors 83 gpio_ad_b0_00 m14 nvcc_gpio digital gpio alt5 gpio1.io[0] input keeper gpio_ad_b0_01 h10 nvcc_gpio digital gpio alt5 gpio1.io[1] input keeper gpio_ad_b0_02 m11 nvcc_gpio digital gpio alt5 gpio1.io[2] input keeper gpio_ad_b0_03 g11 nvcc_gpio digital gpio alt5 gpio1.io[3] input keeper gpio_ad_b0_04 f11 nvcc_gpio digital gpio alt0 src.boot.mod e[0] input 100 k pd gpio_ad_b0_05 g14 nvcc_gpio digital gpio alt0 src.boot.mod e[1] input 100 k pd gpio_ad_b0_06 e14 nvcc_gpio digital gpio alt0 jtag.mux.tms input 47 k pu gpio_ad_b0_07 f12 nvcc_gpio digital gpio alt0 jtag.mux.tck input 47 k pu gpio_ad_b0_08 f13 nvcc_gpio digital gpio alt0 jtag.mux.mod input 100 k pu gpio_ad_b0_09 f14 nvcc_gpio digital gpio alt0 jtag.mux.tdi input 47 k pu gpio_ad_b0_10 g13 nvcc_gpio digital gpio alt0 jtag.mux.tdo input keeper gpio_ad_b0_11 g10 nvcc_gpio digital gpio alt0 jtag.mux.trstb input 47 k pu gpio_ad_b0_12 k14 nvcc_gpio digital gpio alt5 gpio1.io[12] input keeper gpio_ad_b0_13 l14 nvcc_gpio digital gpio alt5 gpio1.io[13] input keeper gpio_ad_b0_14 h14 nvcc_gpio digital gpio alt5 gpio1.io[14] input keeper gpio_ad_b0_15 l10 nvcc_gpio digital gpio alt5 gpio1.io[15] input keeper gpio_ad_b1_00 j11 nvcc_gpio digital gpio alt5 gpio1.io[16] input keeper gpio_ad_b1_01 k11 nvcc_gpio digital gpio alt5 gpio1.io[17] input keeper gpio_ad_b1_02 l11 nvcc_gpio digital gpio alt5 gpio1.io[18] input keeper gpio_ad_b1_03 m12 nvcc_gpio digital gpio alt5 gpio1.io[19] input keeper gpio_ad_b1_04 l12 nvcc_gpio digital gpio alt5 gpio1.io[20] input keeper table 82. 10 x 10 mm functional contact assignments (continued)
i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 84 nxp semiconductors package information and contact assignments gpio_ad_b1_05 k12 nvcc_gpio digital gpio alt5 gpio1.io[21] input keeper gpio_ad_b1_06 j12 nvcc_gpio digital gpio alt5 gpio1.io[22] input keeper gpio_ad_b1_07 k10 nvcc_gpio digital gpio alt5 gpio1.io[23] input keeper gpio_ad_b1_08 h13 nvcc_gpio digital gpio alt5 gpio1.io[24] input keeper gpio_ad_b1_09 m13 nvcc_gpio digital gpio alt5 gpio1.io[25] input keeper gpio_ad_b1_10 l13 nvcc_gpio digital gpio alt5 gpio1.io[26] input keeper gpio_ad_b1_11 j13 nvcc_gpio digital gpio alt5 gpio1.io[27] input keeper gpio_ad_b1_12 h12 nvcc_gpio digital gpio alt5 gpio1.io[28] input keeper gpio_ad_b1_13 h11 nvcc_gpio digital gpio alt5 gpio1.io[29] input keeper gpio_ad_b1_14 g12 nvcc_gpio digital gpio alt5 gpio1.io[30] input keeper gpio_ad_b1_15 j14 nvcc_gpio digital gpio alt5 gpio1.io[31] input keeper gpio_b0_00 d7 nvcc_gpio digital gpio alt5 gpio2.io[0] input keeper gpio_b0_01 e7 nvcc_gpio digital gpio alt5 gpio2.io[1] input keeper gpio_b0_02 e8 nvcc_gpio digital gpio alt5 gpio2.io[2] input keeper gpio_b0_03 d8 nvcc_gpio digital gpio alt5 gpio2.io[3] input keeper gpio_b0_04 c8 nvcc_gpio digital gpio alt5 gpio2.io[4] input keeper gpio_b0_05 b8 nvcc_gpio digital gpio alt5 gpio2.io[5] input keeper gpio_b0_06 a8 nvcc_gpio digital gpio alt5 gpio2.io[6] input keeper gpio_b0_07 a9 nvcc_gpio digital gpio alt5 gpio2.io[7] input keeper gpio_b0_08 b9 nvcc_gpio digital gpio alt5 gpio2.io[8] input keeper gpio_b0_09 c9 nvcc_gpio digital gpio alt5 gpio2.io[9] input keeper table 82. 10 x 10 mm functional contact assignments (continued)
package information and contact assignments i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 nxp semiconductors 85 gpio_b0_10 d9 nvcc_gpio digital gpio alt5 gpio2.io[10] input keeper gpio_b0_11 a10 nvcc_gpio digital gpio alt5 gpio2.io[11] input keeper gpio_b0_12 c10 nvcc_gpio digital gpio alt5 gpio2.io[12] input keeper gpio_b0_13 d10 nvcc_gpio digital gpio alt5 gpio2.io[13] input keeper gpio_b0_14 e10 nvcc_gpio digital gpio alt5 gpio2.io[14] input keeper gpio_b0_15 e11 nvcc_gpio digital gpio alt5 gpio2.io[15] input keeper gpio_b1_00 a11 nvcc_gpio digital gpio alt5 gpio2.io[16] input keeper gpio_b1_01 b11 nvcc_gpio digital gpio alt5 gpio2.io[17] input keeper gpio_b1_02 c11 nvcc_gpio digital gpio alt5 gpio2.io[18] input keeper gpio_b1_03 d11 nvcc_gpio digital gpio alt5 gpio2.io[19] input keeper gpio_b1_04 e12 nvcc_gpio digital gpio alt5 gpio2.io[20] input keeper gpio_b1_05 d12 nvcc_gpio digital gpio alt5 gpio2.io[21] input keeper gpio_b1_06 c12 nvcc_gpio digital gpio alt5 gpio2.io[22] input keeper gpio_b1_07 b12 nvcc_gpio digital gpio alt5 gpio2.io[23] input keeper gpio_b1_08 a12 nvcc_gpio digital gpio alt5 gpio2.io[24] input keeper gpio_b1_09 a13 nvcc_gpio digital gpio alt5 gpio2.io[25] input keeper gpio_b1_10 b13 nvcc_gpio digital gpio alt5 gpio2.io[26] input keeper gpio_b1_11 c13 nvcc_gpio digital gpio alt5 gpio2.io[27] input keeper gpio_b1_12 d13 nvcc_gpio digital gpio alt5 gpio2.io[28] input keeper gpio_b1_13 d14 nvcc_gpio digital gpio alt5 gpio2.io[29] input keeper gpio_b1_14 c14 nvcc_gpio digital gpio alt5 gpio2.io[30] input keeper table 82. 10 x 10 mm functional contact assignments (continued)
i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 86 nxp semiconductors package information and contact assignments gpio_b1_15 b14 nvcc_gpio digital gpio alt5 gpio2.io[31] input keeper gpio_emc_00 e3 nvcc_emc digital gpio alt5 gpio4.io[0] input keeper gpio_emc_01 f3 nvcc_emc digital gpio alt5 gpio4.io[1] input keeper gpio_emc_02 f4 nvcc_emc digital gpio alt5 gpio4.io[2] input keeper gpio_emc_03 g4 nvcc_emc digital gpio alt5 gpio4.io[3] input keeper gpio_emc_04 f2 nvcc_emc digital gpio alt5 gpio4.io[4] input keeper gpio_emc_05 g5 nvcc_emc digital gpio alt5 gpio4.io[5] input keeper gpio_emc_06 h5 nvcc_emc digital gpio alt5 gpio4.io[6] input keeper gpio_emc_07 h4 nvcc_emc digital gpio alt5 gpio4.io[7] input keeper gpio_emc_08 h3 nvcc_emc digital gpio alt5 gpio4.io[8] input keeper gpio_emc_09 c2 nvcc_emc digital gpio alt5 gpio4.io[9] input keeper gpio_emc_10 g1 nvcc_emc digital gpio alt5 gpio4.io[10] input keeper gpio_emc_11 g3 nvcc_emc digital gpio alt5 gpio4.io[11] input keeper gpio_emc_12 h1 nvcc_emc digital gpio alt5 gpio4.io[12] input keeper gpio_emc_13 a6 nvcc_emc digital gpio alt5 gpio4.io[13] input keeper gpio_emc_14 b6 nvcc_emc digital gpio alt5 gpio4.io[14] input keeper gpio_emc_15 b1 nvcc_emc digital gpio alt5 gpio4.io[15] input keeper gpio_emc_16 a5 nvcc_emc digital gpio alt5 gpio4.io[16] input keeper gpio_emc_17 a4 nvcc_emc digital gpio alt5 gpio4.io[17] input keeper gpio_emc_18 b2 nvcc_emc digital gpio alt5 gpio4.io[18] input keeper gpio_emc_19 b4 nvcc_emc digital gpio alt5 gpio4.io[19] input keeper table 82. 10 x 10 mm functional contact assignments (continued)
package information and contact assignments i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 nxp semiconductors 87 gpio_emc_20 a3 nvcc_emc digital gpio alt5 gpio4.io[20] input keeper gpio_emc_21 c1 nvcc_emc digital gpio alt5 gpio4.io[21] input keeper gpio_emc_22 f1 nvcc_emc digital gpio alt5 gpio4.io[22] input keeper gpio_emc_23 g2 nvcc_emc digital gpio alt5 gpio4.io[23] input keeper gpio_emc_24 d3 nvcc_emc digital gpio alt5 gpio4.io[24] input keeper gpio_emc_25 d2 nvcc_emc digital gpio alt5 gpio4.io[25] input keeper gpio_emc_26 b3 nvcc_emc digital gpio alt5 gpio4.io[26] input keeper gpio_emc_27 a2 nvcc_emc digital gpio alt5 gpio4.io[27] input 100 k pd gpio_emc_28 d1 nvcc_emc digital gpio alt5 gpio4.io[28] input keeper gpio_emc_29 e1 nvcc_emc digital gpio alt5 gpio4.io[29] input keeper gpio_emc_30 c6 nvcc_emc digital gpio alt5 gpio4.io[30] input keeper gpio_emc_31 c5 nvcc_emc digital gpio alt5 gpio4.io[31] input keeper gpio_emc_32 d5 nvcc_emc digital gpio alt5 gpio3.io[18] input keeper gpio_emc_33 c4 nvcc_emc digital gpio alt5 gpio3.io[19] input keeper gpio_emc_34 d4 nvcc_emc digital gpio alt5 gpio3.io[20] input keeper gpio_emc_35 e5 nvcc_emc digital gpio alt5 gpio3.io[21] input keeper gpio_emc_36 c3 nvcc_emc digital gpio alt5 gpio3.io[22] input keeper gpio_emc_37 e4 nvcc_emc digital gpio alt5 gpio3.io[23] input keeper gpio_emc_38 d6 nvcc_emc digital gpio alt5 gpio3.io[24] input keeper gpio_emc_39 b7 nvcc_emc digital gpio alt5 gpio3.io[25] input keeper gpio_emc_40 a7 nvcc_emc digital gpio alt5 gpio3.io[26] input keeper table 82. 10 x 10 mm functional contact assignments (continued)
i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 88 nxp semiconductors package information and contact assignments gpio_emc_41 c7 nvcc_emc digital gpio alt5 gpio3.io[27] input keeper gpio_sd_b0_00 j4 nvcc_sd0 digital gpio alt5 gpio3.io[12] input keeper gpio_sd_b0_01 j3 nvcc_sd0 digital gpio alt5 gpio3.io[13] input keeper gpio_sd_b0_02 j1 nvcc_sd0 digital gpio alt5 gpio3.io[14] input keeper gpio_sd_b0_03 k1 nvcc_sd0 digital gpio alt5 gpio3.io[15] input keeper gpio_sd_b0_04 h2 nvcc_sd0 digital gpio alt5 gpio3.io[16] input keeper gpio_sd_b0_05 j2 nvcc_sd0 digital gpio alt5 gpio3.io[17] input keeper gpio_sd_b1_00 l5 nvcc_sd1 digital gpio alt5 gpio3.io[0] input keeper gpio_sd_b1_01 m5 nvcc_sd1 digital gpio alt5 gpio3.io[1] input keeper gpio_sd_b1_02 m3 nvcc_sd1 digital gpio alt5 gpio3.io[2] input keeper gpio_sd_b1_03 m4 nvcc_sd1 digital gpio alt5 gpio3.io[3] input keeper gpio_sd_b1_04 p2 nvcc_sd1 digital gpio alt5 gpio3.io[4] input keeper gpio_sd_b1_05 n3 nvcc_sd1 digital gpio alt5 gpio3.io[5] input keeper gpio_sd_b1_06 l3 nvcc_sd1 digital gpio alt5 gpio3.io[6] input keeper gpio_sd_b1_07 l4 nvcc_sd1 digital gpio alt5 gpio3.io[7] input keeper gpio_sd_b1_08 p3 nvcc_sd1 digital gpio alt5 gpio3.io[8] input keeper gpio_sd_b1_09 n4 nvcc_sd1 digital gpio alt5 gpio3.io[9] input keeper gpio_sd_b1_10 p4 nvcc_sd1 digital gpio alt5 gpio3.io[01] input keeper gpio_sd_b1_11 p5 nvcc_sd1 digital gpio alt5 gpio3.io[11] input keeper onoff m6 vdd_snvs_in digital gpio alt0 onoff input 100 k pu pmic_on_req k7 vdd_snvs_in digital gpio alt0 snvs_lp.pmic_on_re q output 100 k pu table 82. 10 x 10 mm functional contact assignments (continued)
package information and contact assignments i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 nxp semiconductors 89 pmic_stby_req l7 vdd_snvs_in digital gpio alt0 ccm.pmic_vstby_re q output 100 k pu (pke disabled) por_b m7 vdd_snvs_in digital gpio alt0 src.por_b input 100 k pu rtc_xtali n9 ? ? ? ? ? ? rtc_xtalo p9 ? ? ? ? ? ? test_mode k6 vdd_snvs_in digital gpio alt0 tcu.test_mode input 100 k pu usb_otg1_chd_b n12 ? ? ? ? ? ? usb_otg1_dn m8 ? ? ? ? ? ? usb_otg1_dp l8 ? ? ? ? ? ? usb_otg1_vbus n6 ? ? ? ? ? ? usb_otg2_dn n7 ? ? ? ? ? ? usb_otg2_dp p7 ? ? ? ? ? ? usb_otg2_vbus p6 ? ? ? ? ? ? xtali p11 ? ? ? ? ? ? xtalo n11 ? ? ? ? ? ? wakeup l6 vdd_snvs_in digital gpio alt5 gpio5.io[0] input 100 k pu table 82. 10 x 10 mm functional contact assignments (continued)
i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 90 nxp semiconductors package information and contact assignments 6.1.3 10 x 10 mm, 0.65 mm pitch, ball map table 83 shows the 10 x 10 mm, 0.65 mm pitch ball map for the i.mx rt1050. table 83. 10 x 10 mm, 0.65 mm pitch, ball map 1 2 3 4 5 6 7 8 9 10 11 12 13 14 a vss gpio_emc_27 gpio_emc_20 gpio_emc_17 gpio_emc_16 gpio_emc_13 gpio_emc_40 gpio_b0_06 gpio_b0_07 gpio_b0_11 gpio_b1_00 gpio_b1_08 gpio_b1_09 vss a b gpio_emc_15 gpio_emc_18 gpio_emc_26 gpio_emc_19 vss gpio_emc_14 gpio_emc_39 gpio_b0_05 gpio_b0_08 vss gpio_b1_01 gpio_b1_07 gpio_b1_10 gpio_b1_15 b c gpio_emc_21 gpio_emc_09 gpio_emc_36 gpio_emc_33 gpio_emc_31 gpio_emc_30 gpio_emc_41 gpio_b0_04 gpio_b0_09 gpio_b0_12 gpio_b1_02 gpio_b1_06 gpio_b1_11 gpio_b1_14 c d gpio_emc_28 gpio_emc_25 gpio_emc_24 gpio_emc_34 gpio_emc_32 gpio_emc_38 gpio_b0_00 gpio_b0_03 gpio_b0_10 gpio_b0_13 gpio_b1_03 gpio_b1_05 gpio_b1_12 gpio_b1_13 d e gpio_emc_29 vss gpio_emc_00 gpio_emc_37 gpio_emc_35 nvcc_emc gpio_b0_01 gpio_b0_02 nvcc_gpio gpio_b0_14 gpio_b0_15 gpio_b1_04 vss gpio_ad_b0_06 e f gpio_emc_22 gpio_emc_04 gpio_emc_01 gpio_emc_02 nvcc_emc vdd_soc_in vdd_soc_in vdd_soc_in vdd_soc_in nvcc_gpio gpio_ad_b0_04 gpio_ad_b0_07 gpio_ad_b0_08 gpio_ad_b0_09 f g gpio_emc_10 gpio_emc_23 gpio_emc_11 gpio_emc_03 gpio_emc_05 vdd_soc_in vss vss vdd_soc_in gpio_ad_b0_11 gpio_ad_b0_03 gpio_ad_b1_14 gpio_ad_b0_10 gpio_ad_b0_05 g
package information and contact assignments i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 nxp semiconductors 91 h gpio_emc_12 gpio_sd_b0_04 gpio_emc_08 gpio_emc_07 gpio_emc_06 vdd_soc_in vss vss vdd_soc_in gpio_ad_b0_01 gpio_ad_b1_13 gpio_ad_b1_12 gpio_ad_b1_08 gpio_ad_b0_14 h j gpio_sd_b0_02 gpio_sd_b0_05 gpio_sd_b0_01 gpio_sd_b0_00 dcdc_sense nvcc_sd0 vss vss vdd_soc_in nvcc_gpio gpio_ad_b1_00 gpio_ad_b1_06 gpio_ad_b1_11 gpio_ad_b1_15 j k gpio_sd_b0_03 vss dcdc_pswitch dcdc__in_q nvcc_sd1 test_mode pmic_on_req vdd_usb_cap ngnd_kel0 gpio_ad_b1_07 gpio_ad_b1_01 gpio_ad_b1_05 vss gpio_ad_b0_12 k l dcdc_in dcdc_in gpio_sd_b1_06 gpio_sd_b1_07 gpio_sd_b1_00 wakeup pmic_stby_req usb_otg1_dp vss gpio_ad_b0_15 gpio_ad_b1_02 gpio_ad_b1_04 gpio_ad_b1_10 gpio_ad_b0_13 l m dcdc_lp dcdc_lp gpio_sd_b1_02 gpio_sd_b1_03 gpio_sd_b1_01 onoff por_b usb_otg1_dn vdd_snvs_in vdd_snvs_cap gpio_ad_b0_02 gpio_ad_b1_03 gpio_ad_b1_09 gpio_ad_b0_00 m n dcdc_gnd dcdc_gnd gpio_sd_b1_05 gpio_sd_b1_09 vss usb_otg1_vbus usb_otg2_dn vss rtc_xtali gpanaio xtalo usb_otg1_chd_b ccm_clk1_p vdda_adc_3p3 n p vss gpio_sd_b1_04 gpio_sd_b1_08 gpio_sd_b1_10 gpio_sd_b1_11 usb_otg2_vbus usb_otg2_dp vdd_high_cap rtc_xtalo nvcc_pll xtali vdd_high_in ccm_clk1_n vss p 1 2 3 4 5 6 7 8 9 10 11 12 13 14 table 83. 10 x 10 mm, 0.65 mm pitch, ball map (continued)
i.mx rt1050 crossover processors for industrial products, rev. 1, 03/2018 92 nxp semiconductors revision history 7 revision history table 84 provides a revision history for this data sheet. table 84. i.mx rt1050 data sheet document revision history rev. number date substantive change(s) rev. 1 03/2018 ? updated the frequency and lcd display resolution in the section 1.1, ?features ? updated the table 1 ordering information ? updated the figure 1, "part number nomenclature?i.mx rt1050" ? added 24-bit parallel csi in the figure 2, "i.mx rt1050 system block diagram" ? updated the sjc description and dcdc input voltage in the table 2 i.mx rt1050 modules list ? removed adc_vref from the table 5 recommended connections for unused analog interfaces ? updated the dcdc power supply in the table 7 absolute maximum ratings and table 9 operating ranges ? updated the test conditions dcdc supply voltage in the table 12 low power mode current and power consumption ? updated the table 34 semc input timing in sync mode (semc_mcr.dqsmd = 0x1) ? updated the parameters in the section 4.5.2, ?fle xspi parameters ? updated the table 51 dcdc electrical specifications ? updated the table 52 12-bit adc operating conditions ? updated the notes of the table 55 lpspi master mode timing and the table 56 lpspi slave mode timing rev. 0 10/2017 ? initial version
information in this document is provided solely to enable system and software implementers to use nxp products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. nxp reserves the right to make changes without further notice to any products herein. nxp makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does nxp assume any liability arising out of the application or use of any product or circ uit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in nxp data sheets and/or specif ications can and do vary in different applications, and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer? customer?s technical experts. nxp does not convey any license under its patent rights nor the rights of others. nxp sells products pursuant to standard terms and conditions of sale, which can be found at the following address: nxp.com/salestermsandconditions. how to reach us: home page: nxp.com web support: nxp.com/support nxp, the nxp logo, freescale, the freescale logo, and the energy efficient solutions logo are trademarks of nxp b.v. all other product or service names are the property of their respective owners. arm and cortex are trademarks of arm limited (or its subsidiaries) in the eu and/or elsewhere. all rights reserved. ? 2017-2018 nxp b.v. document number: imxrt1050iec rev. 1 03/2018

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