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june 2013 docid023658 rev 2 1/33 AN4163 application note evl4984-350w: 350 w ccm pfc pr e-regulator with the l4984d by hiroshi an drea fusillo introduction this application note describes the demonstration board evl4984-350w, based on the ?continuous conduction mode? pfc (ccm) cont roller, the l4984d, and presents the results of its bench evaluation. the board implements a 350 w, wide-range input, pfc pre- conditioner suitable for all smps from 150 w to those in the kilowatt range which must meet the iec61000-3-2 or the jeita-miti regulation. figure 1. evl4984-350w demonstration board www.st.com
contents AN4163 2/33 docid023658 rev 2 contents 1 main characteristics and circ uit description . . . . . . . . . . . . . . . . . . . . . 5 2 test results and significant wavef orms . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 harmonic content measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 inductor current in fot and l4984d thd optimizer . . . . . . . . . . . . . . . . .11 2.3 switching frequency and timer pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4 voltage feed-forward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.5 startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.6 overvoltage and open-loop protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.7 power management/housekeeping functions . . . . . . . . . . . . . . . . . . . . . 21 3 thermal measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4 conducted emission pre-compliance test -peak detection . . . . . . . . . 25 5 bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6 pfc coil specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.1 general description and characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.3 mechanical aspect and pin numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.4 manufacturer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
docid023658 rev 2 3/33 AN4163 list of figures 33 list of figures figure 1. evl4984-350w demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2. evl4984-350w ccm pfc demonstration board elec trical schematic. . . . . . . . . . . . . . . . . 7 figure 3. evl4984-350w: compliance to en61000-3-2 standa rd at full load . . . . . . . . . . . . . . . . . . . 8 figure 4. evl4984-350w: compliance to jeita-miti standard at full load. . . . . . . . . . . . . . . . . . . . . 8 figure 5. evl4984-350w: compliance to en61000-3-2 standa rd at 70 w load . . . . . . . . . . . . . . . . . 8 figure 6. evl4984-350w: compliance to jeita-miti standar d at 70 w load . . . . . . . . . . . . . . . . . . . 8 figure 7. evl4984-350w input current waveform at 100 v - 60 hz - 350 w load. . . . . . . . . . . . . . . . 9 figure 8. evl4984-350w input current waveform at 230 v - 50 hz - 350 w load. . . . . . . . . . . . . . . . 9 figure 9. evl4984-350w input current waveform at 100 v - 60 hz - half load . . . . . . . . . . . . . . . . . . 9 figure 10. evl4984-350w input current waveform at 230 v - 50 hz - half load . . . . . . . . . . . . . . . . . . 9 figure 11. evl4984-350w input current waveform at 100 v - 60 hz ? 70 w load . . . . . . . . . . . . . . . 10 figure 12. evl4984-350w input current waveform at 230 v - 50 hz ? 70 w load . . . . . . . . . . . . . . . 10 figure 13. power factor vs. v in and load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 14. thd vs. v in and load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 15. efficiency vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 16. average efficiency a cc. to es-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 17. static v out regulation vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 18. evl4984-350w inductor current ripple envelope at 115 v ac - 60 hz - full load . . . . . . . . . 12 figure 19. evl4984-350w inductor current ripple (detail) at 115 v ac - 60 hz - full load . . . . . . . . . . . 12 figure 20. evl4984-350w inductor current ripple envelope at 230 v ac - 50 hz - full load . . . . . . . . . 12 figure 21. evl4984-350w inductor current ripple (detail) at 230 v ac - 50 hz - full load . . . . . . . . . . . 12 figure 22. evl4984-350w 115 v ac - 60 hz - normal working condition . . . . . . . . . . . . . . . . . . . . . . . 14 figure 23. evl4984-350w input current shape at 100 v ac - 60 hz - c ff = 470 nf, r ff = 390 kw . . 15 figure 24. evl4984-350w input current shape at 100 v ac - 60 hz - c ff = 1 f, r ff = 1 mw. . . . . . 15 figure 25. evl4984-350w input mains surge from 90 v ac to 140 v ac - full load - c ff = 1 mf. . . . . . 16 figure 26. l6562 fot input mains surge from 90 v ac to 140 v ac - full load - no v ff input . . . . . . . . 16 figure 27. evl4984-350w input mains dip from 140 v ac to 90 v ac - full load - c ff = 1 mf . . . . . . . . 16 figure 28. l6562 fot input mains dip from 140 v ac to 90 v ac - full load - no vff input. . . . . . . . . . 16 figure 29. evl4984-350w start-up at 90 v ac -60 hz - full load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 30. evl4984-350w start-up at 265 v ac -50 hz - full load . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 31. v in 115 v ac - startup by v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 32. v in 115 v ac - startup by v cc - details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 33. v in 115 v ac startup by vpfc_ok_e (burst mode like) on l4984d . . . . . . . . . . . . . . . . . . 18 figure 34. evl4984-350w startup attempt at 80 v ac - 60 hz - full load . . . . . . . . . . . . . . . . . . . . . . . 18 figure 35. v in 90 v ac - startup at full load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 36. v in 115 v ac - startup at full load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 37. evl6563s-400w startup with slow input voltage increasing - full load . . . . . . . . . . . . . . . 20 figure 38. evl6563s-400w turn-off with slow input volt age decreasing - full load. . . . . . . . . . . . . . . 20 figure 39. evl4984-350w startup at 265 v -50 hz - 30 ma lo ad . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 40. evl4984-350w open loop at 115 v ac - 60 hz - full load . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 41. interface circuits that le t dc-dc converter?s controller ic disa ble the l4984d . . . . . . . . . . . 22 figure 42. thermal map at 115 v ac - 60 hz - full load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 43. thermal map at 230 v ac - 50 hz - full load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 44. 115 v ac and full load - phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 45. 115 v ac and full load - neutral. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 46. 230 v ac and full load - phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 47. 230 v ac and full load - neutral. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
list of figures AN4163 4/33 docid023658 rev 2 figure 48. electrical diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 49. pfc coil mechanical aspect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
docid023658 rev 2 5/33 AN4163 main characteristics and circuit description 33 1 main characteristics and circuit description the main characteristics of the smps are listed below: ? input mains range: 90 to 265 v ac ? minimum line frequency (f l ): 47 hz ? regulated output voltage: 400 v ? rated output power: 350 w ? maximum 2f l output voltage ripple: 12.5 v (peak- to-peak) ? hold-up time: 20 ms (vdrop after hold-up time: 300 v) ? switching frequency: 70 khz ? minimum efficiency: 94% (at v in = 90 v ac , p out = 350 w) ? pcb: single-sided, 70 m, cem-1, 112 x 114 mm the power stage of the pfc is a traditional boost pfc converter, connec ted to the output of the rectifier bridge d2. it is comprised of the boost inductor l3, the power switch, formed by the parallel of mosfets q1 and q2, the diode d3 and the output capacitors c3 and c4. the 300 v varistor rv1, connected between th e line and the neutral, protects the circuit against high input voltage transients while the fuse f1 disconnects the mains in case of short-circuit. to meet the emc standards, the board is equipped with an input emi filter cutting the switching noise coming from the boost stage. in particular l2 filters the common-mode emissions while l1, c1, c2 reduce the differential-mode emissions. the l4984d has to be supplied by an external power supply, connected between pin #1 (vcc) and pin #2 (gnd) of j3. the capacitor c14 connected to the timer (#7) pin determines the switching frequency. the resistor divider r12, r16, r22 and r24 provides to the l4984d multiplier (mult, pin #3) the information of the instantaneous mains voltage that is used to modulate the peak current of the boost, the t off duration and is fed to the vff block. the resistors r6, r8, r13 with r17 and r18 are dedicated to sense the output voltage and feed to the inverting input of the error amplifier (inv, pin #1) the feedback information necessary to keep the output voltage regulate d. between the inv (#1) and comp (#2) pins, the components c8, r21 and c11 form the error amplifier compensation network in order to keep the required loop stability. the inductor peak current is sensed by resist ors r27, r30, r31 placed in series to the mosfets? source and the derived signal is fe d into the current sense pin (cs, #4) of the l4984d via the filter by r29 and c13. c1 5 and r28, connected to the vff pin (#5), complete an internal peak-holding circuit providing the information on the rms mains voltage, deriving a dc voltage equal to the peak of the mult pin (#3) voltage, which is fed to the multiplier to compensate the control loop gain dependence on the mains voltage. the brownout function is also implemented using the vff pin. a voltage below 0.8 v on the vff pin (#5) shuts down (no latch) the ic and brings its consumption to a considerably lower level. the l4984d starts as the voltage at the pin rises above 0.88 v. the divider r5, r10, r14 and r23 provides to the l4984d pfc_ok pin (#7) the information of the output voltage level, to trigger the dynamic ovp protection, preventing the output voltage from excessive values during the load tr ansients due to the slow response caused
main characteristics and circuit description AN4163 6/33 docid023658 rev 2 by the intrinsic narrow bandwidth of pfc systems. if the voltage on the pfc_ok pin (#7) exceeds 2.5 v, the l4984d stops switching and re starts as the voltage on the pin falls below 2.4 v. the open-loop protection (also called feedback failure protection) monitors the pfc_ok (#7) and inv (#1) pins. if the voltage of t he pfc_ok pin (#7) exceeds 2.5 v, and at the same time the voltage on inv pin (#1) falls be low 1.66 v, a feedback failure is assumed and the device is latched off. normal operation can be resumed only by cycling vcc (pin #10), bringing its value lower than v ccrestart (6 v, typ.), before rising up to the turn-on threshold v ccon (12 v, typ.). additionally a remote on/off control input is present. if the voltage on the pfc_ok pin (#7) is tied below the pfc_ok disable threshold (v pfc_ok_d , 0.23 v typ.), the l4984d is shut down and the operation is restarted when the voltage on the pfc_ok pin (#7) increases above the pfc_ok enable threshold (v pfc_ok_e , 0.27 v typ.). the l4984d operation can be also disabled or enabled to manage properly light load or failure by the d2d via the pfc_ok pin (#7), using pin #3 of j3 (on/off).
docid023658 rev 2 7/33 AN4163 main characteristics and circuit description 33 figure 2. evl4984-350w ccm pfc demonstration board electrical schematic am13391v1 3/7 1 2 3 j3 22-27-2031 2 1 3 4 + _ ~ ~ d2 d15xb60h jpx2 r6 2m2 c5 470n-x2 r8 2m2 c6 1uf-x2 1 2 4 3 l2 3mh - 7a 1 2 j1 f1 fuse t6.3a r32 10r jpx5 l4 2743005112 d3 stth8s06fp r2 ntc 1r0-s237 c3 100uf - 450v +400vout 1 2 3 4 5 j2 +400vdc rtn +400vdc rtn nc 2 5 11 9 l3 700uh hs1 heat-sink c16 2n2 90-264vac r18 160k r30 0r33 2 1 3 q2 stf21n65m5 c2 1uf-520v d1 1n5406 r1 750k r12 3m9 r16 3m9 jpx3 r24 100k r28 1m0 2 1 3 q1 stf21n65m5 r19 6r8 r20 3r9 r31 0r33 d6 ll4148 r33 100r r27 0r33 r25 6r8 r26 3r9 r17 56k r5 3m3 c17 470nf-520v r10 3m3 r23 56k r14 3m3 c12 2n2 c1 220nf-520v c15 1uf r3 750k c13 330pf c14 680pf c9 470n c8 68n c11 680n r21 100k r4 750k r22 4m7 vcc gnd on/off c4 100uf - 450v hs2 heat-sink jpx4 r13 2m2 l1 70uh - 7a inv 1 comp 2 mu lt 3 cs 4 vff 5 pfc-ok 6 ti mer 7 gnd 8 gd 9 vcc 10 u1 l4984d rv1 300vac jpx1 z1 pcb rev. 1 c10 100uf-35v d7 ll4148 r29 1k0
test results and significant waveforms AN4163 8/33 docid023658 rev 2 2 test results and significant waveforms 2.1 harmonic content measurement one of the main purposes of a pfc pre-conditi oner is the correction of input current distortion, decreasing the harmonic contents be low the limits of the re levant regulations. therefore, this demonstration board has been tested according to the european standard en61000-3-2 class-d and japanese standard jeita-miti class-d, at full load at both the nominal input voltage mains. as shown in figure 3 to figure 6 , the circuit can reduce the harmonics well below the limits of both regulations from full load down to light load. an output power of 70 w has been chosen because it is close to the lower power limit at which the harmonics have to be limited according to the above-mentioned standards. figure 3. evl4984-350w: compliance to en61000-3-2 standard at full load figure 4. evl4984-350w: compliance to jeita- miti standard at full load am13392v1 vin = 230 vac - 50 hz pout = 350 w thd = 16.7 %, pf = 0.976 am13393v1 vin = 100 vac - 50 hz pout = 350 w thd = 4.13 %, pf = 0.999 figure 5. evl4984-350w: compliance to en61000-3-2 standard at 70 w load figure 6. evl4984-350w: compliance to jeita- miti standard at 70 w load am13394v1 vin = 230 vac - 50 hz pout = 70 w thd = 17.5 %, pf = 0.814 am13395v1 vin = 100 vac - 50 hz pout = 70 w thd = 9.9 %, pf = 0.989
docid023658 rev 2 9/33 AN4163 test results and significant waveforms 33 for user reference, waveforms of the input current and voltage at the nominal input voltage mains and different load conditions are shown in figure 7 to figure 10 . figure 7. evl4984-350w input current waveform at 100 v - 60 hz - 350 w load figure 8. evl4984-350w input current waveform at 230 v - 50 hz - 350 w load am13396v1 am13397v1 figure 9. evl4984-350w input current waveform at 100 v - 60 hz - half load figure 10. evl4984-350w input current waveform at 230 v - 50 hz - half load am13398v1 am13399v1
test results and significant waveforms AN4163 10/33 docid023658 rev 2 the power factor (pf) and the total harmonic distortion (thd) have also been measured with the results given in figure 13 and figure 14 . as shown, the pf at full load and half load remains above 0.9 over the input voltage mains range, while when the circuit is delivering 70 w, it decreases at high mains range. thd is within 20% until 230 v and at the maximum mains voltage (265 v ac ) it increases at the maximum input voltage. the measured efficiency is shown in figure 15 , measured according to the es-2 requirements: it is very good at all load and li ne conditions. at full load it is always higher than 94%, making this design suitable for high-efficiency power supplies. the average efficiency calculated according to the es-2 requirements at different nominal mains voltages are shown in figure 16 . figure 11. evl4984-350w input current waveform at 100 v - 60 hz ? 70 w load figure 12. evl4984-350w input current waveform at 230 v - 50 hz ? 70 w load am13400v1 am13401v1 figure 13. power factor vs. v in and load figure 14. thd vs. v in and load am13402v1 0.75 0.8 0.85 0.9 0.95 1 90 100 115 130 180 230 265 pf vin [vrms] 350 w 175 w 70 w 0% 5% 10% 15% 20% 25% 30% 90 100 115 130 180 230 265 thd [%] vin [vrms] 350 w 175 w 70 w am13403v1
docid023658 rev 2 11/33 AN4163 test results and significant waveforms 33 the measured output voltage at differen t lines and static load is given in figure 17 . as shown, the voltage is very stable over the entire input voltage and output load range. figure 17. static v out regulation vs. output power 2.2 inductor current in fo t and l4984d thd optimizer figure 18 through figure 21 represent the waveform of the inductor current at different voltage mains. as shown in figure 18 and figure 20 , the inductor current waveform over a line half-period is very similar to that of an average ccm pfc. comparing figure 18 to figure 20 showing the inductor ripple envelope at 115 v ac and 230 v respectively, it is possible to notice the different ripple currents and how the converter operates in either ccm or dcm depending on the input voltage and the load. at 115 v ac the borderline between dcm and ccm occurs close to the zero-crossing of the current sine wave, so the inductor is working in ccm for almost all the line period while at 230 v ac the borderlines between dcm and ccm move toward the top of the circuit and the boost inductor works in ccm only in a portion centered around the peak of the sine wave. figure 15. efficiency vs. output power figure 16. average efficiency acc. to es-2 am13404v2 efficiency output power 92% 93% 94% 95% 96% 97% 98% 100% 75% 50% 25% 10% eff @ 100vac - 50hz eff @ 115vac - 60hz eff @ 230vac - 50hz am13482v1 93 93.5 94 94.5 95 95.5 96 96.5 97 97.5 avg efficieny [%] ac input voltage [vrms] avg. eff. @ 100 vac - 50hz avg. eff. @ 115 vac - 60hz avg. eff. @ 230 vac - 50hz am13483v1 394 395 396 397 398 399 400 25% 50% 75% 100% output voltage output power pf @ 100vac - 50hz pf @ 115vac - 60hz pf @ 230vac - 50hz
test results and significant waveforms AN4163 12/33 docid023658 rev 2 on both the drain voltage traces shown in figure 19 and figure 20 , close to the zero- crossing points of the sine wave, it is poss ible to note the action of the thd optimizer embedded in the l4984d, minimizing the conducti on dead-angle occurring on the ac input current near the zero-crossings of the line volta ge (crossover distortion). in this way, the thd (total harmonic distortion) of the current is considerably reduced. a major cause of this distortion is the inability of the syste m to transfer energy effectively when the instantaneous line voltage is very low. this effect is magnified by the high-frequency filter capacitor placed after the bridge rectifier, which retains some residual voltage that causes the diodes of the bridge rectifier to be reverse-biased and the input current flow to temporarily stop. figure 18. evl4984-350w inductor current ripple envelope at 115 v ac - 60 hz - full load figure 19. evl4984-350w inductor current ripple (detail) at 115 v ac - 60 hz - full load am13405v1 ch1: q1/q2 drain voltage ch4: l4 inductor current ripple envelope am13406v1 ch1: q1/q2 drain voltage ch4: l4 inductor current ripple envelope figure 20. evl4984-350w inductor current ripple envelope at 230 v ac - 50 hz - full load figure 21. evl4984-350w inductor current ripple (detail) at 230 v ac - 50 hz - full load am13407v1 ch1: q1/q2 drain voltage ch4: l4 inductor current ripple envelope am13408v1 ch1: q1/q2 drain voltage ch4: l4 inductor current ripple envelope
docid023658 rev 2 13/33 AN4163 test results and significant waveforms 33 to overcome this issue the device forces the pfc pre-regulator to process more energy near the line voltage zero-crossings as comp ared to that commanded by the control loop. this will result in both minimizing the time inte rval where energy transfer is lacking and fully discharging the high-frequency filter capacitor after the bridge. essentially, the circuit artificially increases the on-time of the power switch with a positive offset added to the output of the multiplier in th e proximity of the line voltage zero-crossings. this offset is reduced as the instantaneous line voltage increa ses, so that it beco mes negligible as the line voltage moves toward the top of the sinusoid and it is modulated by the voltage on the vff pin, so as to have little offset at low li ne, where energy transfer at zero-crossings is typically quite good, and a larger offset at high line where the energy transfer gets worse. to derive maximum benefit from the thd opt imizer circuit, the high-frequency filter capacitors after the bridge re ctifier should be minimized, compatible with emi filtering needs. a large capacitance, in fact, introduces a conduction dead-angle of the ac input current in itself, thus reducing the ef fectiveness of the optimizer circuit. 2.3 switching frequency and timer pin with the l4984d the switching frequency is determined by a capacitor connected between the timer pin and ground, charged by an accurate internal generator (i timer ) of 156 a (typ.) during the off-time, generating a voltage ramp. as shown in figure 22 when the voltage ramp on timer equals the voltage on the mult pin, connecte d through a resistive divider to the rectified mains to get a sinusoidal voltage reference, the off-time of the power mosfet is terminat ed, the gate driver (gd) pin is driven high and the ramp resets at zero. the timing capacitor c t is then selected with the follo wing formula desc ribed in the l4984d datasheet: equation 1 where f sw is the switching frequency and k p the ratio of the resistive divider on the mult pin, calculated considering the maximum value of the multiplier input, that is the voltage measured on the mult pin at maximum mains voltage. the switching frequency f sw is not constant but is modulated at tw ice the line frequency ripple 2f l appearing across the output capacitor c out , spreading the spectrum of the electrical noise injected back into the power line and facilitating t he compliance with conducted emi emis sion regulations. the switching frequency chosen for this design is around 70 khz, so the capacitor on the timer pin needed to obtain the desired frequency is: equation 2 an np0 capacitor with commercial value of 680 pf has been selected for the timer capacitor. for further details on the calculation procedure of the entire converter, please refer to an4149, ?designing a ccm pfc pre-regulator based on the l4984d?. timer t psw i c kvoutf ? ? t 3 156 a c 695pf 8 10 400v 70khz ? ? ?? ?? ?
test results and significant waveforms AN4163 14/33 docid023658 rev 2 figure 22. evl4984-350w 115 v ac - 60 hz - normal working condition 2.4 voltage feed-forward the power stage gain of pfc pre-regulators varies with the square of the rms input voltage. this applies as well to the crossover frequency fc of the overall open-loop gain because the gain has a single pole characteri stic. this leads to large trade-offs in the design. for example, setting the gain of the er ror amplifier to get fc = 20 hz at 264 v ac means having fc = 4 hz at 88 v ac , resulting in sluggish control dynamics. additionally, the slow control loop causes large transient current flow during rapid line or load changes that are limited by the dynamics of the multiplier out put. this limit is cons idered when selecting the sense resistor to let the full load power pass under minimum line voltage conditions, with some margin. however, a fixed current limit allows excessive power input at high line, whereas a fixed power limit requires the current limit to vary inversely with the line voltage. the voltage feed-forward function can comp ensate for the gain variation with the line voltage and allow overcoming all of the above-mentioned issues. it consists of deriving a voltage proportional to the input rms voltage, feeding this voltage in to a squarer/divider circuit (1/v 2 corrector) and providing the resulting si gnal to the multiplier that generates the current reference for the inner current control loop. in this way a change of the line voltage will cause an inversely prop ortional change of the half sine amplitude at t he output of the multiplier so that the current reference is adapted to the new operating conditions with (ideally) no need for invoking the slow dynamics of the error amplifier. additionally, the loop gain will be constant throughout the input vo ltage range, which improves significantly dynamic behavior at low line and simplifies loop design. the l4984d implements voltage feed-forward with a technique that makes use of just two external parts and that limits the feed-forward time constant trade-off issue to only one direction. a capacitor c ff (c15) and a resistor r ff (r28), both connected to the v ff pin (#5), complete an internal peak-holding circuit that provides a dc voltage equal to the peak of the rectified sine wave applied on the mult pin (#3). r ff provides a means to discharge c ff when the line voltage decreases. however, a drawback of the v ff technique is an increase of the harmonics. deriving a voltage proportional to the rms line voltage im plies a form of integration, which has its own time constant. if it is too small, the volt age generated will be affected by a considerable am13409v1 ch1: mult - pin #3 ch2: timer - pin #7 ch3: gd - pin #9
docid023658 rev 2 15/33 AN4163 test results and significant waveforms 33 amount of ripple at twice the mains frequency causing distortion of the current reference (resulting in high thd and poor pf). if it is too large, there will be a considerable delay in setting the right amount of feed-forward, result ing in excessive overshoot and undershoot of the pre-regulator's output voltage in response to large line voltage changes. clearly, a trade- off is required. for reference, in figure 23 and figure 24 the comparison of the input current shape and the measurement of the thd and 3 rd harmonic amplitude for different c ff values taken from a similar board using the former l4984d are shown. to overcome this issue the new l4984d has int egrated an innovative circuitry which allows getting a fast transient response for whichever voltage change occurs on the mains, both surges and drops. thus, in case of sudden line voltage rise, c ff will be rapidly charged through the low imped ance of the internal diode and no appreciable overshoot will be visible at the pre-regulator's output. in case of line voltage drop, an internal ?mains drop? detector enables a low impedance switch which suddenly discharges c ff avoiding a long settling time before reaching the new voltage level. consequently an acceptably low steady-state ripple and low current distortion can be achieved without any considerable undershoot or overshoot on the pre-regulator?s output like in systems with no feed-forward compensation. in figure 25 the behavior of the evl4984-350w demonstration board in case of an input voltage surge from 90 to 140 v ac has been analyzed. as shown the v ff function provides for the stability of the output voltage which is no t affected by the input voltage surge. thanks to the v ff function, the compensation of the input voltage variation is very fast and the output voltage remains stable at its nominal value, as opposed to figure 26 , which shows the behavior of a pfc using the l6562 working in fot and delivering 400 w in case of a mains surge. the controller cannot compensate it and the output voltage stability depends on the feedback loop only. unfortunately, as pr eviously stated, its bandwidth is narrow and thus the output voltage has a signific ant deviation from the nominal value. figure 23. evl4984-350w input current shape at 100 v ac - 60 hz - c ff = 470 nf, r ff = 390 k ? figure 24. evl4984-350w input current shape at 100 v ac - 60 hz - c ff = 1 f, r ff =1 m ? am13410v1 thd [%]: 3.6 % - 3 rd harmonic: 0.07 a ch3: vff - pin #5 ch4: input current am13411v1 thd [%]: 2.8 % - 3 rd harmonic: 0.057 a ch3: vff - pin #5 ch4: input current
test results and significant waveforms AN4163 16/33 docid023658 rev 2 figure 27 shows the circuit behavior in case of ma ins dip: as previously described, the internal circuitry detects the drop of t he mains voltage and it activates the c ff internal fast discharge. as visible, in that case the outp ut voltage changes, but after few mains cycle it comes back to the nominal value. the situation is different if we check the behavior of a pfc using the l6562a with fot and delivering 400 w: in case of a mains dip from 140 vac to 90 vac, the output voltage requires a longer time to restore the original value. testing with a wider voltage variation (e.g. 265 v ac to 90 v ac ), the output voltage variation of a pfc without the voltage feed-forward fast discharging is much more emphasized. figure 25. evl4984-350w input mains surge from 90 v ac to 140 v ac - full load - c ff = 1 ? f figure 26. l6562 fot input mains surge from 90 v ac to 140 v ac - full load - no v ff input am13412v1 ch1: output voltage ch2: mult - pin #3 ch3: vff - pin #5 ch4: input current am13413v1 ch1: output voltage ch2: input rectified mains voltage ch4: input current figure 27. evl4984-350w input mains dip from 140 v ac to 90 v ac - full load - c ff = 1 ? f figure 28. l6562 fot input mains dip from 140 v ac to 90 v ac - full load - no v ff input am13414v1 ch1: output voltage ch2: mult - pin #3 ch1: vff - pin #5 ch4: input current am13415v1 ch1: output voltage ch2: input rectified mains voltage ch4: input current
docid023658 rev 2 17/33 AN4163 test results and significant waveforms 33 2.5 startup figure 29 and figure 30 represent the output voltage wa veform during the startup of the circuit when the mains is plugged in and the external v cc voltage is applied between pin 3 (v cc ) and pin 1 (gnd) of j3. when the v cc voltage rises up to the turn-on threshold, the l4984d starts the operation. the good phase margin of the compensation network allows a clean startup, without overshoots. to reduce inrush energy at startup or after an auto-restart protection tripping, the l4984d uses an internal soft-start function. the function is perfo rmed by internally pulling the voltage on pin mult towards an asymptotic level located at about 4.1 v as the device wakes up. this has a twofold effect: on one hand, the out put of the multiplier will be lowered through the voltag e feed-forward function, thus programming a lower peak current; on the other hand, the off-time of the power switch is considerably prolonged with respect to the normal values programmed by the capacitor connected to pin timer. in this way, both the current inrush and the risk of saturating the boost inductor at startup are minimized. after 300 s from its activation the pull-up is released. the voltage on pin mult decays with the time constant determined by the resistor divider that biases t he pin and the bypass capacitor typically connected between t he pin and ground. at the same time c ff is discharged by turning on the low impedance discharge switch. in this way the programmed current by the multiplier is mi nimized and increases according to the previously mentioned v ff time constant. figure 29. evl4984-350w start-up at 90 v ac -60 hz - full load figure 30. evl4984-350w start-up at 265 v ac -50 hz - full load am13416v1 ch1: pfc output voltage ch2: vcc - pin #10 ch4: gd - pin #9 am13417v1 ch1: pfc output voltage ch2: vcc - pin #10 ch4: gd - pin #9
test results and significant waveforms AN4163 18/33 docid023658 rev 2 as shown in figure 31 and figure 32 , once v cc reaches the v ccon voltage, the mult pin is pulled up to 4.2 v (4.1v typ. in the datasheet). after 300 us, the v ff capacitor starts discharging and the mosfet starts switching. after startup t off is properly extended as long as the mult voltage is higher than the steady state value, then progressively decreased to the value determined by the timer capacitance and mult instantaneous voltage. when the device is disabled and enabled more than one time (burst mode), the pfc_ok is released after the first startup. in this conditi on, the l4984d does not activate the soft-start procedure, as required in case the burst mode pulses are enabled by a downstream converter via the pfc_stop pin. the l4984d restarts almost immediately after releasing the pfc_ok pin and gd begins operation just after a t off period. figure 31. v in 115 v ac - startup by v cc figure 32. v in 115 v ac - startup by v cc - details am13418v1 ch1: gd - pin #9 ch2: mult - pin #3 ch2: vff - pin #5 ch4: vcc - pin #10 am13419v1 ch1: gd - pin #9 ch2: mult - pin #3 ch2: vff - pin #5 ch4: vcc - pin #10 figure 33. v in 115 v ac startup by vpfc_ok_e (burst mode like) on l4984d figure 34. evl4984-350w startup attempt at 80 v ac - 60 hz - full load am13420v1 ch1: gd - pin #9 ch2: pfc_ok - pin #6 ch2: vff - pin #5 ch4: mult - pin #3 am13421v1 ch1: pfc output voltage ch2: vcc - pin #10 ch2: vff - pin #5 ch4: gd - pin #9
docid023658 rev 2 19/33 AN4163 test results and significant waveforms 33 for reference, the waveform of the inductor cu rrent during startup has been captured at 90 vac and full load ( figure 35 and figure 36 ). as can be noted, the inductor current does not exhibit any flux accumulation, which sometime s may occur working in ccm. in that case, a higher margin in the pfc inductor calculation has to be considered. a dangerous event for any pfc is operating with an insufficient input voltage. this condition may cause overheating of the power section due to an excess of rms current. to prevent the pfc from this abnormal operation a brownout protection is needed. it is basically an unlatched shutdown function that has to be activated when a condition of mains undervoltage is detected.the br ownout function is implement ed in the l4984d by the vff pin (#5). a voltage below the disable threshold (v dis , 0.8 v typ.) on the vff shuts down (no latch) the ic and brings its consumption to a considerably lower level. the l4984d restarts as the voltage at the pin rises above 0.88 v which is the enable threshold (v en , 0.88 v typ.). as shown in figure 34 the startup is inhibited as the voltage on vff is below 0.8 v, and the pfc is not allowed to start up. in figure 37 and figure 38 the waveforms of the circuit during operation of the brownout protection are captured. in both cases the mains voltage was increased or decreasing slo wly: as visible, both at turn-on or turn-off there are no bouncing or starting attempts by the converter. figure 35. v in 90 v ac - startup at full load figure 36. v in 115 v ac - startup at full load am13482v2 ch2: mult - pin #3 ch2: vff - pin #5 ch4: inductor current am13483v2 ch2: mult - pin #3 ch2: vff - pin #5 ch4: inductor current
test results and significant waveforms AN4163 20/33 docid023658 rev 2 figure 39. evl4984-350w startup at 265 v -50 hz - 30 ma load the startup behavior at light load (10 w) , powering the l4984d by an external v cc (15 v), is shown in figure 39 . it can be noted that the l4984d is working in burst-mode and the pfc keeps the output voltage regulated. 2.6 overvoltage and open-loop protection normally, the voltage control loop keeps the output voltage v out of the pfc pre-regulator close to its nominal value, set by the ratio of the resistors of the output divider (the resistors r6, r8, r13 with r17 and r18). the pin pfc_ok (#6) of the device has been dedicated to monitor the output voltage v out with a separate resistor divider (r5+r10+r14 and r23) in order to detect the ovp condition. this divider is selected so that the voltage at the pin figure 37. evl6563s-400w startup with slow input voltage increasing - full load figure 38. evl6563s-400w turn-off with slow input voltage decreasing - full load am13422v1 ch1: drain voltage ch2: vcc - pin #10 ch2: mult - pin #3 ch4: output voltage am13423v1 ch1: drain voltage ch2: vcc - pin #10 ch2: mult - pin #3 ch4: output voltage am13424v1 ch1: q1/q2 drain voltage ch2: vcc - pin #10 ch2: gd - pin #9 ch4: pfc output voltage
docid023658 rev 2 21/33 AN4163 test results and significant waveforms 33 reaches 2.5 v when the output voltage exceeds a preset value, usually larger than the maximum v out that can be expected, also including worst-case load/line transients. when the ovp condition is detected, the gate dr ive activity is immediately stopped until the voltage on the pin pfc_ok drops below 2.4 v. notice that r5, r10, r14 and r23 can be selected without any constraints. the unique criterion is that both dividers have to sink a current from the output bus which needs to be significantly higher than the current biasing the error amplifier and pfc_ok comparator. figure 40. evl4984-350w open loop at 115 v ac - 60 hz - full load the ovp function described above is able to handle ?normal? overvoltage conditions, i.e. those resulting from an abrupt load/line change or occurring at startup. in case the overvoltage is generated by a feedback disconnection, for instance, when the upper resistor of the output divider (r6) fails open , the open-loop protection is needed. the open-loop protection is implemented by the pfc_ok (#6) and inv (#1) pins. if the voltage of the pfc_ok pin exceeds 2.5 v, and at the same time the voltage on inv pin (#1) falls below 1.66 v a feedback fa ilure is assumed, and the device is latched off, stopping the gate drive activity. the pin pfc_ok doubles its function as a non-latched ic disable: a voltage below 0.23 v will shut down the ic, reducing its cons umption below 2 ma. to restart the l4984d simply let the voltage at the pin rise above 0.27 v. note that this function offers a complete protection against not only feedback loop failures or erroneous settings, but also against a failure of the protection itself. either resistor of the pfc_ok divider failing short or open or a pfc_ ok pin floating will result in shutting down the l4984d and stopping the pre-regulator. the event of an open loop is captured in figure 40 , we can notice the pr otection intervention latching the operation of the l4984d. the operation can be resumed by recycling v cc . 2.7 power management/h ousekeeping functions a communication line with the control ic of the cascaded dc-dc converter can be established via the disable function included in th e pfc_ok pin. typically this line is used to allow the pwm controller of the cascaded dc-dc converter to shut down the l4984d in am13425v1 ch1: q1/q2 drain voltage ch2: inv - pin #1 ch2: pfc_ok - pin #6 ch4: pfc output voltage
test results and significant waveforms AN4163 22/33 docid023658 rev 2 case of light load and to minimize the no-load input consumption. should the residual consumption of the chip be an issue, it is al so possible to cut down the supply voltage. interface circuits like those are shown in figure 41 . needless to say, this operation assumes that the cascaded dc-dc converter stage works as the master and the pfc stage as the slave or, in other words, that the dc-dc stage starts first, it powers both controllers and enables/disables the operation of the pfc stage. figure 41. interface circuits that let dc-dc converter?s controller ic disable the l4984d table 1 summarizes all the operating conditions that cause the device to stop working. am13426v1 l4984d l4984d l6591 l6699 pfc_stop pfc_stop pfc_ok pfc_ok 9 6 8 6 table 1. summary of l4984d idle states condition caused or revealed by ic behavior restart condition typical ic consumption ss activation uvlo v cc < v ccoff disabled vcc > v ccon 65 a yes standby v pfc_ok < v pfc_ok_d stop switching v pfc_ok > v pfc_ok_e 2.2 ma no ac brownout v vff < v dis stop switching v vff > v en 1.5 ma yes ovp v pfc_ok > v pfc_ok_s stop switching v pfc_ok < v pfc_ok_r 2.2 ma no feedback failure v pfc_ok > v pfc_ok_s and v inv < 1.66 v latched-off vcc < vcc restart then vcc > vcc on 180 a yes low consumption v comp < 2.4v burst mode v comp > 2.4v 2.2 ma no saturated boost inductor vcs > v cs_th stop switching auto restart after 300 s 4 ma no
docid023658 rev 2 23/33 AN4163 thermal measurements 33 3 thermal measurements in order to check the design reliability, a thermal mapping by means of an ir camera was done. figure 42 and figure 43 show thermal measurements of the on-board components at nominal input voltages and full load. some pointers visible on th e pictures placed across key components show the relevant temperature. table 2 provides the correlation between the measured points and components, for both th ermal maps. the ambient temperature during both measurements was 25 c. according to th ese measurement results, all components of the board are working within their temperature limits. figure 42. thermal map at 115 v ac - 60 hz - full load figure 43. thermal map at 230 v ac - 50 hz - full load am13427v1 am13428v1
thermal measurements AN4163 24/33 docid023658 rev 2 table 2. measured temperature table at 115 v ac and 230 v ac - full load point component temperature at 115 v ac temperature at 230 v ac a d2 70.9 c 50.2 c b l1 54.9 c 41.1 c c l3 ? core 62.0 c 48.0 c d l3 ? winding 68.5 c 50.5 c e rsense 80.0 c 51.3 c f q1 74.5 c 59.1 c g q2 82.0 c 63.2 c h d3 88.1 c 66.9 c i r2 111.4 c 74.9 c
docid023658 rev 2 25/33 AN4163 conducted emission pre-compliance test-peak detection 33 4 conducted emission pre-compliance test-peak detection in figure 44 to figure 47 the peak measurements of the conducted noise at full load and nominal mains voltages are given. the limits shown on the diagrams are relevant to the en55022 class-b, the most popular standard for european equipment using a two-wire mains connection. as visible in the diagrams, in all test conditions there is a good margin of the measurements with respect to the limits. figure 44. 115 v ac and full load - phase figure 45. 115 v ac and full load - neutral am13429v1 am13430v1 figure 46. 230 v ac and full load - phase figure 47. 230 v ac and full load - neutral am13431v1 am13432v1
bill of material AN4163 26/33 docid023658 rev 2 5 bill of material table 3. evl4984-350w ccm pfc dem onstration board bill of material description part type/ part value case style/ package description supplier c1 220 nf - 520 v 7.5 x 26.5 mm 520 v - flm cap - b32673t5224 epcos c2 1 ? f - 520 v 10.5 x 26.5 mm 520 v - flm cap - b32673z5105 epcos c3 100 ? f - 450 v dia. 18 x 40 mm 450 v - aluminium elcap - kxg series - 105 c nippon chemi-con c4 100 ? f - 450 v dia. 18 x 40 mm 450v - aluminium elcap - kxg series - 105 c nippon chemi-con c5 470n - x2 10.5 x 26.5 mm x2 - flm cap - b32923a3474m epcos c6 1 ? f - x2 11 x 26.5 mm x2 - flm cap - b32923c3105 epcos c8 68n 0805 100 v cercap - general purpose - x7r - 10% avx c9 470n 1206 100 v cercap - general purpose - x7r - 10% kemet c10 100 ? f-35 v dia. 8 x 11 mm 50 v - aluminium elcap - yxf series - 105 c rubycon c11 680n 0805 25 v cercap - general purpose - x7r - 10% kemet c12 10n 0805 50 v cercap - general purpose - x7r - 10% kemet c13 330 pf 0805 50 v cercap - general purpose - cog - 5% epcos c14 680 pf 0805 50 v cercap - general purpose - cog - 5% epcos c15 1 ? f 1206 50 v cercap - general purpose - x7r - 10% tdk c16 2n2 0805 50 v cercap - general purpose - x7r - 10% kemet c17 470 nf - 520 v 7 x 26.5 mm 520 v - flm cap - b32673z5474k*** epcos d1 1n5406 do-201 rectifier - general purpose vishay d2 d15xb60h dwg single phase bridge rectifier shindengen d3 stth8s06fp to-220 ultrafast high-voltage rectifier st d6 ll4148 minimelf high-speed signal diode vishay d7 ll4148 minimelf high-speed signal diode vishay f1 fuse t6.3a 4 x 8.5 mm pitch 5.08 mm subminiature fuse 392/te5 - time delay 6.3 a littelfuse hs1 heatsink dwg heatsink for d2 meccal hs2 heatsink dwg heatsink for q1, q2 and d3 meccal j1 09-65-2038 dwg kk pcb conn. - straight - pitch 3.96 mm - 3 pins (central removed) molex j2 10-16-1051 dwg kk pcb conn. - straight - pitch 5.08 mm - 5 pins (central removed) molex j3 22-27-2031 dwg kk pcb connector, straight, pitch 2.54 mm - 3 pins molex
docid023658 rev 2 27/33 AN4163 bill of material 33 jpx1 shorted wire wire jumper jpx2 shorted wire wire jumper jpx3 shorted wire wire jumper jpx4 shorted wire wire jumper jpx5 shorted wire wire jumper l1 70 ? h - 7 a dwg dm inductor - 1119.0013 magnetica l2 3 mh - 7 a dwg emi filter - 1606.0007 magnetica l3 700 ? h dwg pfc inductor - 2097.0002 magnetica l4 2743005112 dwg ferrite bead dia. 3.5 x 6 mm vertical fair rite q1 stf21n65m5 to-220fp n-channel power mosfet st q2 stf21n65m5 to-220fp n-channel power mosfet st r1 750k 1206 smd standard film res. - 1/4 w - 5% - 250 ppm/c vishay r2 ntc 1r0- s237 dia. 15 x 7 p. 7.5 mm ntc resistor p/n b57237s0109m000 epcos r3 750k 1206 smd standard film res. - 1/4 w - 5% - 250 ppm/c vishay r4 750k 1206 smd standard film res. - 1/4 w - 5% - 250ppm/c vishay r5 3m3 1206 smd standard film res. - 1/4 w - 1% - 100 ppm/c vishay r6 2m2 1206 smd standard film res. - 1/4 w - 1% - 100 ppm/c vishay r8 2m2 1206 smd standard film res. - 1/4 w - 1% - 100 ppm/c vishay r10 3m3 1206 smd standard film res. - 1/4 w - 1% - 100 ppm/c vishay r12 1m0 1206 smd standard film res. - 1/4 w - 1% - 100 ppm/c vishay r13 2m2 1206 smd standard film res. - 1/4 w - 1% - 100 ppm/c vishay r14 3m3 1206 smd standard film res. - 1/4 w - 1% - 100 ppm/c vishay r16 1m0 1206 smd standard film res. - 1/4 w - 1% - 100 ppm/c vishay r17 56 k 1206 smd standard film res. - 1/4 w - 1% - 100 ppm/c vishay r18 160 k 1206 smd standard film res. - 1/4 w - 1% - 100 ppm/c vishay r19 6r8 0805 smd standard film res. - 1/8 w - 5% - 250 ppm/c vishay r20 3r9 0805 smd standard film res. - 1/8 w - 5% - 250 ppm/c vishay r21 100 k 0805 smd standard film res. - 1/8 w - 5% - 250 ppm/c vishay r22 1m0 1206 smd standard film res. - 1/4 w - 1% - 100 ppm/c vishay r23 56 k 0805 smd standard film res. - 1/8 w - 1% - 100 ppm/c vishay r24 24 k 0805 smd standard film res. - 1/8 w - 5% - 250 ppm/c vishay r25 6r8 0805 smd standard film res. - 1/8 w - 5% - 250 ppm/c vishay r26 3r9 0805 smd standard film res. - 1/8 w - 5% - 250 ppm/c vishay table 3. evl4984-350w ccm pfc demonstration board bill of material (continued) description part type/ part value case style/ package description supplier
bill of material AN4163 28/33 docid023658 rev 2 r27 0r33 pth rsmf1tb - metal film res. - 1 w - 2% - 250 ppm/c akaneohm r28 1m0 0805 smd standard film res - 1/8 w - 1% - 100 ppm/c vishay r29 1 k0 0805 smd standard film res - 1/8 w - 5% - 250 ppm/c vishay r30 0r33 pth rsmf1tb - metal film res - 1 w - 2% - 250 ppm/c akaneohm r31 0r33 pth rsmf1tb - metal film res - 1 w - 2% - 250 ppm/c akaneohm r32 10r 0805 smd standard film res - 1/8 w - 5% - 250 ppm/c vishay r33 100r 1206 smd standard film res - 1/4 w - 5% - 250 ppm/c vishay rv1 300 v ac dia. 15 x 5 p. 7.5 mm 300 v metal oxide varistor - b72214s0301k101 epcos u1 l4984d ssop10 ccm pfc controller st z1 pcb rev. 1 table 3. evl4984-350w ccm pfc demonstration board bill of material (continued) description part type/ part value case style/ package description supplier
docid023658 rev 2 29/33 AN4163 pfc coil specification 33 6 pfc coil specification 6.1 general description and characteristics ? application type: consumer, home appliance ? inductor type: open ? coil former: vertical type, 6 + 6 pins ? max. temp. rise: 45 c ? max. operating ambient temp.: 60 c ? unit finishing: varnished 6.2 electrical characteristics ? converter topology: ccm boost pfc preregulator ? core type: pq35/35-pc44 or equivalent (center-leg gapped) ? operating freq. range: 70 khz - 135 khz ? primary inductance: 700 h 15% at 1 khz-0.25 v (measured between pins 5 - 2) ? primary rms current 3.5 a ? primary peak current 7.5 a figure 48. electrical diagram am13433v1 table 4. winding characteristics windings start pins end pins number of turns wire type wire diameter aux 9 11 5 (spaced) litz ? g2 0.28 ? prim 5 2 70 single ? g2 litz 0.2 ? x 30
pfc coil specification AN4163 30/33 docid023658 rev 2 6.3 mechanical aspect and pin numbering ? maximum height from pcb: 38 mm ? coil former type: vertical, 6 + 6 pins (pin 12 is removed) ? pin distance: 5.08 mm ? row distance: 30.48 mm ? external copper shield: not in sulated, wound around the ferrite core and including the coil former; it is connected to pin 11 by a soldered solid wire figure 49. pfc coil mechanical aspect 6.4 manufacturer ? magnetica di r. volpini - italy ? pfc inductor p/n: 2097.0002 am13434v1
docid023658 rev 2 31/33 AN4163 references 33 7 references ? l4984d - ccm pfc controller datasheet ? an4149 - designing a ccm pfc pre-regulator based on the l4984
revision history AN4163 32/33 docid023658 rev 2 8 revision history table 5. document revision history date revision changes 05-mar-2013 1 initial release. 20-jun-2013 2 updated title in cover page. added cross-references to section 2.1 and section 4 . updated figure 15 . corrected units in section 6.1 . minor corrections throughout document.
docid023658 rev 2 33/33 AN4163 33 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not authorized for use in weapons. nor are st products designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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