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gs88018/32/36ct-xxx 512k x 18, 256k x 32, 256k x 36 9mb sync burst srams 333 mhz ? 150 mhz 2.5 v or 3.3 v v dd 2.5 v or 3.3 v i/o 100-pin tqfp commercial temp rev: 1.04 6/2012 1/23 ? 2011, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. features ? ft pin for user-configurable flow through or pipeline operation ? single cycle deselect (scd) operation ? 2.5 v or 3.3 v +10%/?10% core power supply ? 2.5 v or 3.3 v i/o supply ? lbo pin for linear or interleaved burst mode ? internal input resistors on mode pins allow floating mode pins ? default to interleaved pipeline mode ? byte write ( bw ) and/or global write ( gw ) operation ? internal self-timed write cycle ? automatic power-down for portable applications ? jedec-standard 100- lead tqfp package ? rohs-compliant 100-lead tqfp package available functional description applications the gs88018/32/36ct is a 9,437,184-bit (8,388,608-bit for x32 version) high performance synchronous sram with a 2-bit burst address counter. al thou gh of a type originally developed for level 2 cache applications supporting high performance cpus, the device now finds application in synchronous sram applications, ranging from dsp main store to networking chip set support. controls addresses, data i/os, chip enables ( e1 , e2, e3 ), address burst control inputs ( adsp , adsc , adv ), and write control inputs ( bx , bw , gw ) are synchronous and are controlled by a positive-edge-triggered clock input (ck). output enable ( g ) and power down control (zz) ar e asynchronous inputs. burst cycles can be initiated with either adsp or adsc inputs. in burst mode, subsequent burst addresses are generated internally and are controlled by adv . the burst address counter may be configured to count in either linear or interleave order with the linear burst order ( lbo ) input. the burst function need not be used . new addresses can be loaded on every cycle with no degradation of chip performance. flow through/pipeline reads the function of the data output register can be controlled by the user via the ft mode pin (pin 14). holding the ft mode pin low places the ram in flow through mode, causing output data to bypass the data output register. holding ft high places the ram in pipeline mode, activating the rising- edge-triggered data output register. scd pipelined reads the gs88018/32/36ct is a scd (single cycle deselect) pi pelined synchronous sram. dcd (dual cycle deselect) versions are also available. scd srams pipeline deselect commands one stage less than read commands. scd rams begin turning off their outputs immediately after the deselect command has been captured in the input registers. byte write and global write byte write operation is performed by using byte write enable ( bw ) input combined with one or more individual byte write signals ( bx ). in addition, global write ( gw ) is available for writing all bytes at one time, regardless of the byte write control inputs. sleep mode low power (sleep mode) is attained through the assertion (h igh) of the zz signal, or by stopping the clock (ck). memory data is retained during sleep mode. core and interface voltages the gs88018/32/36ct operates on a 2.5 v or 3.3 v power supp ly. all input are 3.3 v and 2.5 v compatible. separate output power (v ddq ) pins are used to decouple output noise from the internal ci rcuits and are 3.3 v and 2.5 v compatible. parameter synopsis -333 -300 -250 -200 -150 unit pipeline 3-1-1-1 t kq tcycle 2.5 3.0 2.5 3.3 2.5 4.0 3.0 5.0 3.8 6.7 ns ns curr (x18) cu rr (x32/x36) 240 280 225 260 195 225 170 195 140 160 ma ma flow through 2-1-1-1 t kq tcycle 4.5 4.5 5.0 5.0 5.5 5.5 6.5 6.5 7.5 7.5 ns ns curr (x18) cu rr (x32/x36) 180 205 165 190 160 180 140 160 128 145 ma ma
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 v ddq v ss dq b dq b v ss v ddq dq b dq b v dd nc v ss dq b dq b6 v ddq v ss dq b dq b dqp b v ss v ddq v ddq v ss dq a dq a v ss v ddq dq a dq a v ss nc v dd zz dq a dq a v ddq v ss dq a dq a v ss v ddq lbo a a a a a 1 a 0 nc nc v ss v dd nc a a a a a a a a a e 1 e 2 nc nc b b b a e 3 ck gw bw v dd v ss g adsc adsp adv a a a 512k x 18 top view dqp a a nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc 10099989796959493929190898887868584838281 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 ft gs88018/32/36ct-xxx rev: 1.04 6/2012 2/23 ? 2011, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs88018c 100-pin tqfp pinout note: pins marked with nc can be tied to either v dd or v ss . these pins can also be left floating.
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 v ddq v ss dq c dq c v ss v ddq dq c dq c v dd nc v ss dq d dq d v ddq v ss dq d dq d dq d v ss v ddq v ddq v ss dq b dq b v ss v ddq dq b dq b v ss nc v dd zz dq a dq a v ddq v ss dq a dq a v ss v ddq lbo a a a a a 1 a 0 nc nc v ss v dd nc a a a a a a a a a e 1 e 2 b d b c b b b a e 3 ck gw bw v dd v ss g adsc adsp adv a a a 256k x 32 top view dq b nc dq b dq b dq b dq a dq a dq a dq a nc dq c dq c dq c dq d dq d dq d nc dq c nc 10099989796959493929190898887868584838281 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 ft gs88018/32/36ct-xxx rev: 1.04 6/2012 3/23 ? 2011, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs88032c 100-pin tqfp pinout note: pins marked with nc can be tied to either vdd or vss. these pins can also be left floating.
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 v ddq v ss dq c dq c v ss v ddq dq c dq c v dd nc v ss dq d dq d v ddq v ss dq d dq d dq d v ss v ddq v ddq v ss dq b dq b v ss v ddq dq b dq b v ss nc v dd zz dq a dq a v ddq v ss dq a dq a v ss v ddq lbo a a a a a 1 a 0 nc nc v ss v dd nc a a a a a a a a a e 1 e 2 b d b c b b b a e 3 ck gw bw v dd v ss g adsc adsp adv a a a 256k x 36 top view dq b dqp b dq b dq b dq b dq a dq a dq a dq a dqp a dq c dq c dq c dq d dq d dq d dqp d dq c dqp c 10099989796959493929190898887868584838281 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 ft gs88018/32/36ct-xxx rev: 1.04 6/2012 4/23 ? 2011, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs88036c 100-pin tqfp pinout note: pins marked with nc can be tied to either vdd or vss. these pins can also be left floating.
tqfp pin description symbol type description a 0 , a 1 i address field lsbs and address counter preset inputs a i address inputs dq a dq b dq c dq d i/o data input and output pin nc ? no connect bw i byte write ?w rites all enabled bytes; active low b a , b b, b c , b d i byte write enable for dq a , dq b data i/os; active low ck i clock input signal; active high gw i global write enable ?w rites all bytes; active low e 1 , e 3 i chip enable; active low e 2 i chip enable; active high g i output enable; active low adv i burst address counter advance enable; active low adsp , adsc i address strobe (processor, cache controller); active low zz i sleep mode control; active high ft i flow through or pipeline mode; active low lbo i linear burst order mode; active low v dd i core power supply v ss i i/o and core ground v ddq i output driver power supply gs88018/32/36ct-xxx rev: 1.04 6/2012 5/23 ? 2011, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com.
gs88018/32/36ct-xxx rev: 1.04 6/2012 6/23 ? 2011, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. a1 a0 a0 a1 d0 d1 q1 q0 counter load dq dq register register dq register dq register dq register dq register dq register dq register dq register dq register a0 ? an lbo adv ck adsc adsp gw bw e 1 g zz power down control memory array 36 36 4 a qd e 2 e 3 dqx1 ? dqx9 note: only x36 version shown for simplicity. 1 b a b b b c b d ft gs88018/32/36c block diagram
mode pin functions mode name pin name state function burst order control lbo l linear burst h interleaved burst output register control ft l flow through h or nc pipeline power down control zz l or nc active h standby, i dd = i sb gs88018/32/36ct-xxx rev: 1.04 6/2012 7/23 ? 2011, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. note: there is a pull-up device on the ft pin and a pull-down device on the zz pin , so this input pin can be unconnected and the chip will operate in the default states as specified in the above tables. note: the burst counter wraps to initial state on the 5th clock. note: the burst counter wraps to initial state on the 5th clock. linear burst sequence a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 10 11 00 3rd address 10 11 00 01 4th address 11 00 01 10 interleaved burst sequence a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 00 11 10 3rd address 10 11 00 01 4th address 11 10 01 00 burst counter sequences
gs88018/32/36ct-xxx rev: 1.04 6/2012 8/23 ? 2011, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. byte write truth table function gw bw b a b b b c b d notes read h h x x x x 1 write no bytes h l h h h h 1 write byte a h l l h h h 2, 3 write byte b h l h l h h 2, 3 write byte c h l h h l h 2, 3, 4 write byte d h l h h h l 2, 3, 4 write all bytes h l l l l l 2, 3, 4 write all bytes l x x x x x notes: 1. all byte outputs are active in read cycles regardl ess of the state of byte w rite enable inputs, b a , b b , b c and/or b d . 2. byte write enable inputs b a , b b , b c and/or b d may be used in any combination with bw to write single or multiple bytes. 3. all byte i/os remain high-z during all write operations regardless of the stat e of byte write enable inputs. 4. bytes ? c ? and ? d ? are only available on the x32 and x36 versions.
synchronous truth table operation address used state diagram key e 1 e 2 e 3 adsp adsc adv w dq 3 deselect cycle, power down none x l x h x l x x high-z deselect cycle, power down none x l l x x l x x high-z deselect cycle, power down none x l x h l x x x high-z deselect cycle, power down none x l l x l x x x high-z deselect cycle, power down none x h x x x l x x high-z read cycle, begin burst external r l h l l x x x q read cycle, begin burst external r l h l h l x f q write cycle, begin burst external w l h l h l x t d read cycle, continue burst next cr x x x h h l f q read cycle, continue burst next cr h x x x h l f q write cycle, continue burst next cw x x x h h l t d write cycle, continue burst next cw h x x x h l t d read cycle, suspend burst current x x x h h h f q read cycle, suspend burst current h x x x h h f q write cycle, suspend burst current x x x h h h t d write cycle, suspend burst current h x x x h h t d notes: 1. x = don?t care, h = high, l = low 2. e = t (true) if e 2 = 1 and e 1 = e 3 = 0; e = f (false) if e 2 = 0 or e 1 = 1 or e 3 = 1 3. w = t (true) and f (false) is defined in the byte write truth table preceding. 4. g is an asynchronous input. g can be driven high at any time to disable active output drivers. g low can only enable active drivers (shown as ?q? in the truth table above). 5. all input combinations shown above are tested and supported. input combinations shown in gray boxes need not be used to acco m plish basic synchronous or synchronous burst oper ations and may be avoided for simplicity. 6. tying adsp high and adsc low allows simple non-burst synchronous operations. see bold items above. 7. tying adsp high and adv low while using adsc to load new addresses allows simple burst operations. see italic items above. gs88018/32/36ct-xxx rev: 1.04 6/2012 9/23 ? 2011, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com.
first write first read burst write burst read deselect r w cr cw x x wr r wr x x x simple synchronous operation simple burst synchronous operation cr r cw cr cr notes: 1. the diagram shows only supported (tested) synchr onous state transitions. the diagram presumes g is tied low. 2. the upper portion of the diagram assume s active use of only the enable (e1 ) and write (b a , b b , b c , b d , bw , and gw ) control inputs, and that adsp is tied high and adsc is tied low. 3. the upper and lower portions of the diagram together a ssume active use of only the enable, write, and adsc control inputs, and assumes adsp is tied high and adv is tied low. gs88018/32/36ct-xxx rev: 1.04 6/2012 10/23 ? 2011, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. simplified state diagram
first write first read burst write burst read deselect r w cr cw x x wr r w r x x x cr r cw cr cr w cw w cw notes: 1. the diagram shows supported (tested) synchronous state transit ions plus supported transitions that depend upon the use of g . 2. use of ?dummy reads ? (read cycles with g high) may be used to make the transition from read cycles to write cycles without passing through a deselect cycle. dummy read cycles increment the address counter just like normal read cycles. 3. transitions shown in gray tone assume g has been pulsed high long enough to turn the ram?s drivers off and for incoming data to meet data input set up time. gs88018/32/36ct-xxx rev: 1.04 6/2012 11/23 ? 2011, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. simplified state diagram with g
absolute maximum ratings (all voltages reference to v ss ) symbol description value unit v dd voltage on v dd pins ? 0 .5 to 4.6 v v ddq voltage in v ddq pins ? 0 .5 to 4.6 v v i/o1 voltage on i/o pins ? 0.5 to v dd +0.5 ( 4.6 v max.) v v i/o2 voltage on i/o pins ? 0 .5 to v ddq +0.5 ( 4.6 v max.) v v in voltage on other input pins ? 0.5 to v dd +0.5 ( 4.6 v max.) v i in input current on any pin +/ ? 20 ma i out output current on any i/o pin +/ ? 20 ma p d package power dissipation 1.5 w t stg storage temperature ? 55 to 125 o c t bias temperature under bias ? 55 to 125 o c gs88018/32/36ct-xxx rev: 1.04 6/2012 12/23 ? 2011, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. notes: 1. permanent damage to the device may occur if the absolute maximu m ratin gs are exceeded. operation should be restricted to reco m - mended operating conditions. exposure to condi tio ns exceeding the absolute maximum ratings, for an extended period of time, may affect reliability of this component. 2. both v i/o1 and v i/o2 must be met. power supply voltage ranges parameter symbol min. typ. max. unit 3.3 v supply voltage v dd3 3.0 3.3 3.6 v 2.5 v supply voltage v dd2 2.3 2.5 2.7 v 3.3 v v ddq i/o supply voltage v ddq3 3.0 3.3 v dd v 2.5 v v ddq i/o supply voltage v ddq2 2.3 2.5 v dd v note: v ddq must be less than or equal to v dd + 0.3 v at all times.
gs88018/32/36ct-xxx rev: 1.04 6/2012 13/23 ? 2011, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. v dd3 range logic levels parameter symbol min. typ. max. unit input high voltage v ih 2.0 ? v dd + 0.3 v input high voltage for data i/o pins v ih(i/o)1 2.0 ? v dd + 0.3 v input high voltage for data i/o pins v ih(i/o)2 2.0 ? v ddq + 0.3 v input low voltage v il ? 0.3 ? 0.8 v notes: 1. v ih (max) must be met for any instantaneous value of v dd . 2. v ih(i/o)1 (max) must be met for any instantaneous value of v dd . 3. v ih(i/o)2 (max) must be met for any instantaneous value of v ddq . 4. v dd needs to power-up before or at the same time as v ddq to make sure v ih (max) is not exceeded. v dd2 range logic levels parameter symbol min. typ. max. unit input high voltage v ih 0.6*v dd ? v dd + 0.3 v input high voltage for data i/o pins v ih(i/o)1 0.6*v dd ? v dd + 0.3 v input high voltage for data i/o pins v ih(i/o)2 0.6*v dd ? v ddq + 0.3 v input low voltage v il ? 0.3 ? 0.3*v dd v notes: 1. v ih (max) must be met for any instantaneous value of v dd . 2. v ih(i/o)1 (max) must be met for any instantaneous value of v dd . 3. v ih(i/o)2 (max) must be met for any instantaneous value of v ddq . 4. v dd needs to power-up before or at the same time as v ddq to make sure v ih (max) is not exceeded. recommended operating temperatures parameter symbol min. typ. max. unit ambient temperature (commercial range versions) t a 0 25 70 c note: unless otherwise noted, all performance s pecifications quoted are eva luated for worst case in the temperature range marked on the device. thermal impedance package test pcb substrate ja (c/w) airflow = 0 m/s ja (c/w) airflow = 1 m/s ja (c/w) airflow = 2 m/s jb (c/w) jc (c/w) 100 tqfp 4-layer 38.7 33.5 31.9 27.6 10.6 notes: 1. thermal impedance data is based on a number of samples from multiple lots and should be viewed as a typical number . 2. please refer to jedec standard jesd51-6. 3. the characteristics of the test fixture pcb influence reported the rmal characteristics of the device. be advised that a good thermal path to the pcb can result in cooling or heating of the ram depending on pcb temperature.
gs88018/32/36ct-xxx rev: 1.04 6/2012 14/23 ? 2011, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. 20% tkc v ss ? 2.0 v 50% v ss v ih undershoot measurement and timing overshoot measure ment and timing 20% tkc v dd + 2.0 v 50% v dd v il note: input under/overshoot voltage must be ? 2 v > vi < v ddn +2 v not to exceed 4.6 v maximum, with a pulse width not to exceed 20% tkc. capacitance o c, f = 1 mh z , v dd = 2.5 v) parameter symbol test conditions typ. max. unit input capacitance c in v in = 0 v 4 5 pf input/output capacitance c i/o v out = 0 v 6 7 pf note: these parameters are sample tested. ac test conditions parameter conditions input high level v dd ? 0.2 v input low level 0.2 v input slew rate 1 v/ns input reference level v dd /2 output reference level v ddq /2 output load fig. 1 notes: 1. include scope and jig capacitance. 2. test conditions as specified with output loading as sho wn in fig. 1 unless otherwise noted. 3. device is deselected as defined by the truth table. dq v ddq/2 50 30pf * output load 1 * distributed test jig capacitance (t a = 25
dc electrical characteristics parameter symbol test conditions min max input leakage current (except mode pins) i il v in = 0 to v dd ? 1 ua 1 ua zz input current i in1 v dd v in v ih 0 v v in v ih ? 1 ua ? 1 u a 1 ua 100 ua ft input current i in2 v dd v in v il 0 v v in v il ? 100 ua ? 1 u a 1 ua 1 ua output leakage current i ol output disable, v out = 0 to v dd ? 1 ua 1 ua output high voltage v oh2 i oh = ? 8 ma, v ddq = 2.375 v 1.7 v ? output high voltage v oh3 i oh = ? 8 ma, v ddq = 3.135 v 2.4 v ? output low voltage v ol i ol = 8 ma ? 0.4 v gs88018/32/36ct-xxx rev: 1.04 6/2012 15/23 ? 2011, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com.
operating currents parameter test conditions mode symbol -333 -300 -250 -200 -150 unit 0 to 70c 0 to 70c 0 to 70c 0 to 70c 0 to 70c operating current device selected; all other inputs v ih or v il output open (x32/ x36 ) pipeline i dd i ddq 240 40 225 35 195 30 170 25 140 20 ma flow th rough i dd i ddq 180 25 165 25 155 25 140 20 130 15 ma (x18) pipeline i dd i ddq 220 20 205 20 180 15 155 15 130 10 ma flow th rough i dd i ddq 165 15 150 15 145 15 130 10 120 8 ma standby current zz v dd ? 0.2 v ? pipeline i sb 25 25 25 25 25 ma flow th rough i sb 25 25 25 25 25 ma deselect current device deselected; all other inputs v ih or v il ? pipeline i dd 70 65 65 65 60 ma flow th rough i dd 70 65 65 65 60 ma gs88018/32/36ct-xxx rev: 1.04 6/2012 16/23 ? 2011, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. notes: 1. i dd and i ddq apply to any combination of v dd3 , v dd2 , v ddq3 , and v ddq2 operation. 2. all parameters listed are worst case scenario.
ac electrical characteristics parameter symbol -333 -300 -250 -200 -150 unit min max min max min max min max min max pipeline clock cycle time tkc 3.0 ? 3.3 ? 4.0 ? 5.0 ? 6.7 ? ns clock to output valid tkq ? 2.5 ? 2.5 ? 2.5 ? 3.0 ? 3.8 ns clock to output invalid tkqx 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns clock to output in low-z tlz 1 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns setup time ts 1.0 ? 1.0 ? 1.2 ? 1.4 ? 1.5 ? ns hold time th 0.1 ? 0.1 ? 0.2 ? 0.4 ? 0.5 ? ns flow through clock cycle time tkc 4.5 ? 5.0 ? 5.5 ? 6.5 ? 7.5 ? ns clock to output valid tkq ? 4.5 ? 5.0 ? 5.5 ? 6.5 ? 7.5 ns clock to output invalid tkqx 2.0 ? 2.0 ? 2.0 ? 2.0 ? 2.0 ? ns clock to output in low-z tlz 1 2.0 ? 2.0 ? 2.0 ? 2.0 ? 2.0 ? ns setup time ts 1.3 ? 1.4 ? 1.5 ? 1.5 ? 1.5 ? ns hold time th 0.3 ? 0.4 ? 0.5 ? 0.5 ? 0.5 ? ns clock high time tkh 1.0 ? 1.0 ? 1.3 ? 1.3 ? 1.5 ? ns clock low time tkl 1.2 ? 1.2 ? 1.5 ? 1.5 ? 1.7 ? ns clock to output in high-z thz 1 1.5 2.5 1.5 2.5 1.5 2.5 1.5 3.0 1.5 3.0 ns g to output valid toe ? 2.5 ? 2.5 ? 2.5 ? 3.0 ? 3.8 ns g to output in low-z tolz 1 0 ? 0 ? 0 ? 0 ? 0 ? ns g to output in high-z tohz 1 ? 2.5 ? 2.5 ? 2.5 ? 3.0 ? 3.8 ns zz setup time tzzs 2 5 ? 5 ? 5 ? 5 ? 5 ? ns zz hold time tzzh 2 1 ? 1 ? 1 ? 1 ? 1 ? ns zz recovery tzzr 20 ? 20 ? 20 ? 20 ? 20 ? ns gs88018/32/36ct-xxx rev: 1.04 6/2012 17/23 ? 2011, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. notes: 1. these parameters are sampled and are not 100% tested. 2. zz is an asynchronous signal. however, in order to be recognized on any given clock cycle, zz must meet the specified setup a nd hold times as specified above.
gs88018/32/36ct-xxx rev: 1.04 6/2012 18/23 ? 2011, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. pipeline mode timing begin read a cont cont deselect write b read c read c+1 read c+2 read c+3 cont deselect thz tkqx tkq tlz th ts tohz toe th ts th ts th ts th ts th ts ts th ts th ts th ts burst readburst read single write tkctkc tkltkl tkh single write single read tkh single read q(a) d(b) q(c) q(c+1) q(c+2) q(c+3) ab c deselected with e1 e1 masks adsp e2 and e3 only sampled with adsp and adsc adsc initiated read ck adsp adsc adv a0?an gw bw ba ?bd e1 e2 e3 g dqa?dqd
gs88018/32/36ct-xxx rev: 1.04 6/2012 19/23 ? 2011, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. flow thro ugh mode timing begin read a cont cont write b read c read c+1 read c+2 read c+3 read c cont deselect thz tkqx tkq tlz th ts tohz toe th ts th ts th ts th ts th ts th ts th ts th ts th ts th ts tkctkc tkltkl tkhtkh ab c q(a) d(b) q(c) q(c+1) q(c+2) q(c+3) q(c) e2 and e3 only sampled with adsc adsc initiated read deselected with e1 fixed high ck adsp adsc adv a0?an gw bw ba ?bd e1 e2 e3 g dqa?dqd
gs88018/32/36ct-xxx rev: 1.04 6/2012 20/23 ? 2011, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. sleep mode during normal operation, zz must be pulled low, either by the us er or by its internal pull down resistor. when zz is pulled hig h, the sram will enter a power sleep mode after 2 cycles. at this time, internal stat e of the sram is preserved. when zz returns t o low, the sram operates normally after zz recovery time. sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to i sb 2. the duration of sleep mode is dictated by the length of time the zz is in a high state. after entering sleep mode, all inputs except zz become disabled and all outputs go to high-z the zz pin is an async hronous, active high input that cau ses the device to enter sleep mo de. when the zz pin is driven high, i sb 2 is guaranteed after the time tzzi is met. because zz is an asynchronous input, pending operations or operations in progress may not be properly completed if zz is asserted. therefore, sleep mode must not be initiat ed until valid pending operations are completed. similarly, when exitin g sleep mode during tzzr, only a deselect or read commands may be applied while the sram is recovering from sleep mode. sleep mode timing diagram tzzr tzzh tzzs hold setup tkltkl tkhtkh tkctkc ck adsp adsc zz application tips single and dual cycle deselect scd devices (like this one) force the use of ?dummy read cycles? (read cycles that ar e launched normally bu t that are ended wit h the output drivers inactive) in a fully sy nchronous environment. dumm y read cycles waste performance but their use usually assures there will be no bus c ontention in transitions from reads to writes or between banks of rams. dcd srams do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings) but greater care mu st be exercised to avoid excessive bus contention.
gs88018/32/36ct-xxx rev: 1.04 6/2012 21/23 ? 2011, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. tqfp package draw ing (package t) d1 d e1 e pin 1 b e c l l1 a2 a1 y notes: 1. all dimensions are in millimeters (mm). 2. package width and length do not include mold protrusion. symbol description min. nom. max a1 standoff 0.05 0.10 0.15 a2 body thickness 1.35 1.40 1.45 b lead width 0.20 0.30 0.40 c lead thickness 0.09 ? 0.20 d terminal dimension 21.9 22.0 22.1 d1 package body 19.9 20.0 20.1 e terminal dimension 15.9 16.0 16.1 e1 package body 13.9 14.0 14.1 e lead pitch ? 0.65 ? l foot length 0.45 0.60 0.75 l1 lead length ? 1.00 ? y coplanarity 0.10 lead angle 0 ? 7
gs88018/32/36ct-xxx rev: 1.04 6/2012 22/23 ? 2011, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. ordering information for gsi synchronous burst rams org part number 1 type package speed 2 (mhz/ns) t a 3 512k x 18 gs88018ct-333 pipeline/flow through tqfp 333/4.5 c 512k x 18 gs88018ct-300 pipeline/flow through tqfp 300/5 c 512k x 18 gs88018ct-250 pipeline/flow through tqfp 250/5.5 c 512k x 18 gs88018ct-200 pipeline/flow through tqfp 200/6.5 c 512k x 18 gs88018ct-150 pipeline/flow through tqfp 150/7.5 c 256k x 32 gs88032ct-333 pipeline/flow through tqfp 333/4.5 c 256k x 32 gs88032ct-300 pipeline/flow through tqfp 300/5 c 256k x 32 GS88032CT-250 pipeline/flow through tqfp 250/5.5 c 256k x 32 gs88032ct-200 pipeline/flow through tqfp 200/6.5 c 256k x 32 gs88032ct-150 pipeline/flow through tqfp 150/7.5 c 256k x 36 gs88036ct-333 pipeline/flow through tqfp 333/4.5 c 256k x 36 gs88036ct-300 pipeline/flow through tqfp 300/5 c 256k x 36 gs88036ct-250 pipeline/flow through tqfp 250/5.5 c 256k x 36 gs88036ct-200 pipeline/flow through tqfp 200/6.5 c 256k x 36 gs88036ct-150 pipeline/flow through tqfp 150/7.5 c 512k x 18 gs88018cgt-333 pipeline/flow through rohs-compliant tqfp 333/4.5 c 512k x 18 gs88018cgt-300 pipeline/flow through rohs-compliant tqfp 300/5 c 512k x 18 gs88018cgt-250 pipeline/flow through rohs-compliant tqfp 250/5.5 c 512k x 18 gs88018cgt-200 pipeline/flow through rohs-compliant tqfp 200/6.5 c 512k x 18 gs88018cgt-150 pipeline/flow through rohs-compliant tqfp 150/7.5 c 256k x 32 gs88032cgt-333 pipeline/flow through rohs-compliant tqfp 333/4.5 c 256k x 32 gs88032cgt-300 pipeline/flow through rohs-compliant tqfp 300/5 c 256k x 32 gs88032cgt-250 pipeline/flow through rohs-compliant tqfp 250/5.5 c 256k x 32 gs88032cgt-200 pipeline/flow through rohs-compliant tqfp 200/6.5 c 256k x 32 gs88032cgt-150 pipeline/flow through rohs-compliant tqfp 150/7.5 c 256k x 36 gs88036cgt-333 pipeline/flow through rohs-compliant tqfp 333/4.5 c 256k x 36 gs88036cgt-300 pipeline/flow through rohs-compliant tqfp 300/5 c 256k x 36 gs88036cgt-250 pipeline/flow through rohs-compliant tqfp 250/5.5 c 256k x 36 gs88036cgt-200 pipeline/flow through rohs-compliant tqfp 200/6.5 c 256k x 36 gs88036cgt-150 pipeline/flow through rohs-compliant tqfp 150/7.5 c notes: 1. customers requiring delivery in tape and reel should add the character ?t? to the end of the part number . example: gs88018ct- 150t. 2. the speed column indicates the cycle frequenc y (mhz) of the device in pipeline mode and the latency (ns) in flow through mod e. each device is pipeline/flow through mode-selectable by the user. 3. t a = c = commercial temperature range. 4. gsi offers other versions this type of device in many differ ent configurations and with a vari ety of different features, onl y some of which are covered in this data sheet. see the gsi technology web site ( www.gsitechnology.com ) for a complete listing of current offerings.
9mb sync sram datasheet revision history file name types of changes format or content revision 880xxc_r1 ? creation of new datasheet 880xxc_r1_01 content ? update to mp datasheet 880xxc_r1_02 content ? updated absolute maximum ratings ? deleted conditional text 880xxc_r1_03 content ? updated absolute maximum ratings ? added thermal information ? updated ordering information 880xxc_r1_04_com content ? updated absolute maximum ratings ? removed ind temp references gs88018/32/36ct-xxx rev: 1.04 6/2012 23/23 ? 2011, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com.
mouser electronics authorized distributor click to view pricing, inventory, delivery & lifecycle information: gsi technology: ? gs88018cgt-150? gs88018cgt-250? gs88018cgt-333? gs88018cgt-300? gs88032cgt-300? gs88036cgt- 250? gs88032cgt-200? gs88032cgt-250? gs88032cgt-333? gs88032cgt-150? gs88036cgt-200? gs88036cgt-333? gs88036cgt-150? gs88018cgt-200? gs88036cgt-300

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