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| stellaris ? lm3s9gn5 microcontroller data sheet copyright ? 2007-2014 texas instruments incorporated ds-lm3s9gn5-15852.2743 spms248c texas instruments-production data
copyright copyright ? 2007-2014 texas instruments incorporated all rights reserved. stellaris and stellarisware ? are registered trademarks of texas instruments incorporated. arm and thumb are registered trademarks and cortex is a trademark of arm limited. other names and brands may be claimed as the property of others. production data information is current as of publication date. products conform to specifcations per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. texas instruments incorporated 108 wild basin, suite 350 austin, tx 78746 http://www.ti.com/stellaris http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm july 03, 2014 2 texas instruments-production data table of contents revision history ............................................................................................................................. 40 about this document .................................................................................................................... 43 audience .............................................................................................................................................. 43 about this manual ................................................................................................................................ 43 related documents ............................................................................................................................... 43 documentation conventions .................................................................................................................. 44 1 architectural overview .......................................................................................... 46 1.1 overview ...................................................................................................................... 46 1.2 target applications ........................................................................................................ 48 1.3 features ....................................................................................................................... 48 1.3.1 arm cortex-m3 processor core .................................................................................... 48 1.3.2 on-chip memory ........................................................................................................... 50 1.3.3 external peripheral interface ......................................................................................... 51 1.3.4 serial communications peripherals ................................................................................ 53 1.3.5 system integration ........................................................................................................ 58 1.3.6 advanced motion control ............................................................................................... 63 1.3.7 analog .......................................................................................................................... 65 1.3.8 jtag and arm serial wire debug ................................................................................ 67 1.3.9 packaging and temperature .......................................................................................... 68 1.4 hardware details .......................................................................................................... 68 2 the cortex-m3 processor ...................................................................................... 69 2.1 block diagram .............................................................................................................. 70 2.2 overview ...................................................................................................................... 71 2.2.1 system-level interface .................................................................................................. 71 2.2.2 integrated configurable debug ...................................................................................... 71 2.2.3 trace port interface unit (tpiu) ..................................................................................... 72 2.2.4 cortex-m3 system component details ........................................................................... 72 2.3 programming model ...................................................................................................... 73 2.3.1 processor mode and privilege levels for software execution ........................................... 73 2.3.2 stacks .......................................................................................................................... 73 2.3.3 register map ................................................................................................................ 74 2.3.4 register descriptions .................................................................................................... 75 2.3.5 exceptions and interrupts .............................................................................................. 88 2.3.6 data types ................................................................................................................... 88 2.4 memory model .............................................................................................................. 88 2.4.1 memory regions, types and attributes ........................................................................... 90 2.4.2 memory system ordering of memory accesses .............................................................. 91 2.4.3 behavior of memory accesses ....................................................................................... 91 2.4.4 software ordering of memory accesses ......................................................................... 92 2.4.5 bit-banding ................................................................................................................... 93 2.4.6 data storage ................................................................................................................ 95 2.4.7 synchronization primitives ............................................................................................. 96 2.5 exception model ........................................................................................................... 97 2.5.1 exception states ........................................................................................................... 98 2.5.2 exception types ............................................................................................................ 98 3 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 2.5.3 exception handlers ..................................................................................................... 101 2.5.4 vector table ................................................................................................................ 101 2.5.5 exception priorities ...................................................................................................... 102 2.5.6 interrupt priority grouping ............................................................................................ 103 2.5.7 exception entry and return ......................................................................................... 103 2.6 fault handling ............................................................................................................. 105 2.6.1 fault types ................................................................................................................. 106 2.6.2 fault escalation and hard faults .................................................................................. 106 2.6.3 fault status registers and fault address registers ...................................................... 107 2.6.4 lockup ....................................................................................................................... 107 2.7 power management .................................................................................................... 107 2.7.1 entering sleep modes ................................................................................................. 108 2.7.2 wake up from sleep mode .......................................................................................... 108 2.8 instruction set summary .............................................................................................. 109 3 cortex-m3 peripherals ......................................................................................... 112 3.1 functional description ................................................................................................. 112 3.1.1 system timer (systick) ............................................................................................... 112 3.1.2 nested vectored interrupt controller (nvic) .................................................................. 113 3.1.3 system control block (scb) ........................................................................................ 115 3.1.4 memory protection unit (mpu) ..................................................................................... 115 3.2 register map .............................................................................................................. 120 3.3 system timer (systick) register descriptions .............................................................. 122 3.4 nvic register descriptions .......................................................................................... 126 3.5 system control block (scb) register descriptions ........................................................ 139 3.6 memory protection unit (mpu) register descriptions .................................................... 168 4 jtag interface ...................................................................................................... 178 4.1 block diagram ............................................................................................................ 179 4.2 signal description ....................................................................................................... 179 4.3 functional description ................................................................................................. 180 4.3.1 jtag interface pins ..................................................................................................... 180 4.3.2 jtag tap controller ................................................................................................... 182 4.3.3 shift registers ............................................................................................................ 182 4.3.4 operational considerations .......................................................................................... 183 4.4 initialization and configuration ..................................................................................... 185 4.5 register descriptions .................................................................................................. 186 4.5.1 instruction register (ir) ............................................................................................... 186 4.5.2 data registers ............................................................................................................ 188 5 system control ..................................................................................................... 190 5.1 signal description ....................................................................................................... 190 5.2 functional description ................................................................................................. 190 5.2.1 device identification .................................................................................................... 191 5.2.2 reset control .............................................................................................................. 191 5.2.3 non-maskable interrupt ............................................................................................... 196 5.2.4 power control ............................................................................................................. 196 5.2.5 clock control .............................................................................................................. 197 5.2.6 system control ........................................................................................................... 203 5.3 initialization and configuration ..................................................................................... 205 5.4 register map .............................................................................................................. 205 july 03, 2014 4 texas instruments-production data table of contents 5.5 register descriptions .................................................................................................. 207 6 internal memory ................................................................................................... 298 6.1 block diagram ............................................................................................................ 298 6.2 functional description ................................................................................................. 298 6.2.1 sram ........................................................................................................................ 299 6.2.2 rom .......................................................................................................................... 299 6.2.3 flash memory ............................................................................................................. 301 6.3 register map .............................................................................................................. 306 6.4 flash memory register descriptions (flash control offset) ............................................ 308 6.5 memory register descriptions (system control offset) .................................................. 320 7 micro direct memory access (dma) ................................................................ 344 7.1 block diagram ............................................................................................................ 345 7.2 functional description ................................................................................................. 345 7.2.1 channel assignments .................................................................................................. 346 7.2.2 priority ........................................................................................................................ 347 7.2.3 arbitration size ............................................................................................................ 347 7.2.4 request types ............................................................................................................ 348 7.2.5 channel configuration ................................................................................................. 349 7.2.6 transfer modes ........................................................................................................... 350 7.2.7 transfer size and increment ........................................................................................ 359 7.2.8 peripheral interface ..................................................................................................... 359 7.2.9 software request ........................................................................................................ 359 7.2.10 interrupts and errors .................................................................................................... 360 7.3 initialization and configuration ..................................................................................... 360 7.3.1 module initialization ..................................................................................................... 360 7.3.2 configuring a memory-to-memory transfer ................................................................... 361 7.3.3 configuring a peripheral for simple transmit ................................................................ 362 7.3.4 configuring a peripheral for ping-pong receive ............................................................ 364 7.3.5 configuring channel assignments ................................................................................ 366 7.4 register map .............................................................................................................. 366 7.5 dma channel control structure ................................................................................. 368 7.6 dma register descriptions ........................................................................................ 375 8 general-purpose input/outputs (gpios) ........................................................... 405 8.1 signal description ....................................................................................................... 405 8.2 functional description ................................................................................................. 410 8.2.1 data control ............................................................................................................... 412 8.2.2 interrupt control .......................................................................................................... 413 8.2.3 mode control .............................................................................................................. 414 8.2.4 commit control ........................................................................................................... 414 8.2.5 pad control ................................................................................................................. 415 8.2.6 identification ............................................................................................................... 415 8.3 initialization and configuration ..................................................................................... 415 8.4 register map .............................................................................................................. 416 8.5 register descriptions .................................................................................................. 418 9 external peripheral interface (epi) ..................................................................... 461 9.1 epi block diagram ...................................................................................................... 462 9.2 signal description ....................................................................................................... 463 5 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 9.3 functional description ................................................................................................. 465 9.3.1 non-blocking reads .................................................................................................... 466 9.3.2 dma operation ........................................................................................................... 467 9.4 initialization and configuration ..................................................................................... 467 9.4.1 sdram mode ............................................................................................................. 468 9.4.2 host bus mode ........................................................................................................... 472 9.4.3 general-purpose mode ............................................................................................... 483 9.5 register map .............................................................................................................. 491 9.6 register descriptions .................................................................................................. 492 10 general-purpose timers ...................................................................................... 536 10.1 block diagram ............................................................................................................ 537 10.2 signal description ....................................................................................................... 537 10.3 functional description ................................................................................................. 540 10.3.1 gptm reset conditions .............................................................................................. 541 10.3.2 timer modes ............................................................................................................... 541 10.3.3 dma operation ........................................................................................................... 548 10.3.4 accessing concatenated register values ..................................................................... 548 10.4 initialization and configuration ..................................................................................... 548 10.4.1 one-shot/periodic timer mode .................................................................................... 549 10.4.2 real-time clock (rtc) mode ...................................................................................... 549 10.4.3 input edge-count mode ............................................................................................... 550 10.4.4 input edge timing mode .............................................................................................. 550 10.4.5 pwm mode ................................................................................................................. 551 10.5 register map .............................................................................................................. 551 10.6 register descriptions .................................................................................................. 552 11 watchdog timers ................................................................................................. 583 11.1 block diagram ............................................................................................................ 584 11.2 functional description ................................................................................................. 584 11.2.1 register access timing ............................................................................................... 585 11.3 initialization and configuration ..................................................................................... 585 11.4 register map .............................................................................................................. 585 11.5 register descriptions .................................................................................................. 586 12 analog-to-digital converter (adc) ..................................................................... 608 12.1 block diagram ............................................................................................................ 609 12.2 signal description ....................................................................................................... 610 12.3 functional description ................................................................................................. 612 12.3.1 sample sequencers .................................................................................................... 612 12.3.2 module control ............................................................................................................ 613 12.3.3 hardware sample averaging circuit ............................................................................. 615 12.3.4 analog-to-digital converter .......................................................................................... 616 12.3.5 differential sampling ................................................................................................... 620 12.3.6 internal temperature sensor ........................................................................................ 622 12.3.7 digital comparator unit ............................................................................................... 623 12.4 initialization and configuration ..................................................................................... 627 12.4.1 module initialization ..................................................................................................... 627 12.4.2 sample sequencer configuration ................................................................................. 628 12.5 register map .............................................................................................................. 628 12.6 register descriptions .................................................................................................. 630 july 03, 2014 6 texas instruments-production data table of contents 13 universal asynchronous receivers/transmitters (uarts) ............................. 689 13.1 block diagram ............................................................................................................ 690 13.2 signal description ....................................................................................................... 690 13.3 functional description ................................................................................................. 692 13.3.1 transmit/receive logic ............................................................................................... 693 13.3.2 baud-rate generation ................................................................................................. 693 13.3.3 data transmission ...................................................................................................... 694 13.3.4 serial ir (sir) ............................................................................................................. 694 13.3.5 iso 7816 support ....................................................................................................... 695 13.3.6 modem handshake support ......................................................................................... 696 13.3.7 lin support ................................................................................................................ 697 13.3.8 fifo operation ........................................................................................................... 698 13.3.9 interrupts .................................................................................................................... 699 13.3.10 loopback operation .................................................................................................... 700 13.3.11 dma operation ........................................................................................................... 700 13.4 initialization and configuration ..................................................................................... 700 13.5 register map .............................................................................................................. 701 13.6 register descriptions .................................................................................................. 703 14 synchronous serial interface (ssi) .................................................................... 753 14.1 block diagram ............................................................................................................ 754 14.2 signal description ....................................................................................................... 754 14.3 functional description ................................................................................................. 755 14.3.1 bit rate generation ..................................................................................................... 756 14.3.2 fifo operation ........................................................................................................... 756 14.3.3 interrupts .................................................................................................................... 756 14.3.4 frame formats ........................................................................................................... 757 14.3.5 dma operation ........................................................................................................... 764 14.4 initialization and configuration ..................................................................................... 765 14.5 register map .............................................................................................................. 766 14.6 register descriptions .................................................................................................. 767 15 inter-integrated circuit (i 2 c) interface ................................................................ 795 15.1 block diagram ............................................................................................................ 796 15.2 signal description ....................................................................................................... 796 15.3 functional description ................................................................................................. 797 15.3.1 i 2 c bus functional overview ........................................................................................ 797 15.3.2 available speed modes ............................................................................................... 799 15.3.3 interrupts .................................................................................................................... 800 15.3.4 loopback operation .................................................................................................... 801 15.3.5 command sequence flow charts ................................................................................ 802 15.4 initialization and configuration ..................................................................................... 809 15.5 register map .............................................................................................................. 810 15.6 register descriptions (i 2 c master) ............................................................................... 811 15.7 register descriptions (i 2 c slave) ................................................................................. 824 16 inter-integrated circuit sound (i 2 s) interface .................................................... 833 16.1 block diagram ............................................................................................................ 834 16.2 signal description ....................................................................................................... 834 16.3 functional description ................................................................................................. 836 7 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 16.3.1 transmit ..................................................................................................................... 837 16.3.2 receive ...................................................................................................................... 841 16.4 initialization and configuration ..................................................................................... 843 16.5 register map .............................................................................................................. 844 16.6 register descriptions .................................................................................................. 845 17 controller area network (can) module ............................................................. 870 17.1 block diagram ............................................................................................................ 871 17.2 signal description ....................................................................................................... 871 17.3 functional description ................................................................................................. 872 17.3.1 initialization ................................................................................................................. 873 17.3.2 operation ................................................................................................................... 874 17.3.3 transmitting message objects ..................................................................................... 875 17.3.4 configuring a transmit message object ........................................................................ 875 17.3.5 updating a transmit message object ........................................................................... 876 17.3.6 accepting received message objects .......................................................................... 877 17.3.7 receiving a data frame .............................................................................................. 877 17.3.8 receiving a remote frame .......................................................................................... 877 17.3.9 receive/transmit priority ............................................................................................. 878 17.3.10 configuring a receive message object ........................................................................ 878 17.3.11 handling of received message objects ........................................................................ 879 17.3.12 handling of interrupts .................................................................................................. 881 17.3.13 test mode ................................................................................................................... 882 17.3.14 bit timing configuration error considerations ............................................................... 884 17.3.15 bit time and bit rate ................................................................................................... 884 17.3.16 calculating the bit timing parameters .......................................................................... 886 17.4 register map .............................................................................................................. 889 17.5 can register descriptions .......................................................................................... 890 18 ethernet controller .............................................................................................. 921 18.1 block diagram ............................................................................................................ 921 18.2 signal description ....................................................................................................... 922 18.3 functional description ................................................................................................. 924 18.3.1 mac operation ........................................................................................................... 924 18.3.2 media independent interface ........................................................................................ 928 18.3.3 interrupts .................................................................................................................... 931 18.3.4 dma operation ........................................................................................................... 931 18.4 initialization and configuration ..................................................................................... 932 18.4.1 software configuration ................................................................................................ 932 18.5 register map .............................................................................................................. 932 18.6 ethernet mac register descriptions ............................................................................. 933 19 universal serial bus (usb) controller ............................................................... 957 19.1 block diagram ............................................................................................................ 958 19.2 signal description ....................................................................................................... 958 19.3 functional description ................................................................................................. 960 19.3.1 operation as a device ................................................................................................. 960 19.3.2 operation as a host .................................................................................................... 965 19.3.3 otg mode .................................................................................................................. 969 19.3.4 dma operation ........................................................................................................... 971 19.4 initialization and configuration ..................................................................................... 972 july 03, 2014 8 texas instruments-production data table of contents 19.4.1 pin configuration ......................................................................................................... 972 19.4.2 endpoint configuration ................................................................................................ 973 19.5 register map .............................................................................................................. 973 19.6 register descriptions .................................................................................................. 984 20 analog comparators .......................................................................................... 1096 20.1 block diagram ........................................................................................................... 1097 20.2 signal description ..................................................................................................... 1097 20.3 functional description ............................................................................................... 1098 20.3.1 internal reference programming ................................................................................ 1099 20.4 initialization and configuration .................................................................................... 1100 20.5 register map ............................................................................................................ 1101 20.6 register descriptions ................................................................................................. 1102 21 pulse width modulator (pwm) .......................................................................... 1110 21.1 block diagram ........................................................................................................... 1111 21.2 signal description ..................................................................................................... 1112 21.3 functional description ............................................................................................... 1115 21.3.1 pwm timer ............................................................................................................... 1115 21.3.2 pwm comparators .................................................................................................... 1116 21.3.3 pwm signal generator .............................................................................................. 1117 21.3.4 dead-band generator ............................................................................................... 1118 21.3.5 interrupt/adc-trigger selector ................................................................................... 1118 21.3.6 synchronization methods .......................................................................................... 1119 21.3.7 fault conditions ........................................................................................................ 1120 21.3.8 output control block .................................................................................................. 1120 21.4 initialization and configuration .................................................................................... 1121 21.5 register map ............................................................................................................ 1122 21.6 register descriptions ................................................................................................. 1125 22 quadrature encoder interface (qei) ................................................................. 1188 22.1 block diagram ........................................................................................................... 1188 22.2 signal description ..................................................................................................... 1189 22.3 functional description ............................................................................................... 1190 22.4 initialization and configuration .................................................................................... 1193 22.5 register map ............................................................................................................ 1193 22.6 register descriptions ................................................................................................. 1194 23 pin diagram ........................................................................................................ 1211 24 signal tables ...................................................................................................... 1213 24.1 100-pin lqfp package pin tables ............................................................................. 1214 24.1.1 signals by pin number .............................................................................................. 1214 24.1.2 signals by signal name ............................................................................................. 1227 24.1.3 signals by function, except for gpio ......................................................................... 1239 24.1.4 gpio pins and alternate functions ............................................................................ 1248 24.1.5 possible pin assignments for alternate functions ....................................................... 1251 24.2 108-ball bga package pin tables .............................................................................. 1255 24.2.1 signals by pin number .............................................................................................. 1255 24.2.2 signals by signal name ............................................................................................. 1269 24.2.3 signals by function, except for gpio ......................................................................... 1280 24.2.4 gpio pins and alternate functions ............................................................................ 1289 9 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 24.2.5 possible pin assignments for alternate functions ....................................................... 1292 24.3 connections for unused signals ................................................................................. 1295 25 operating characteristics ................................................................................. 1297 26 electrical characteristics .................................................................................. 1298 26.1 maximum ratings ...................................................................................................... 1298 26.2 recommended operating conditions ......................................................................... 1298 26.3 load conditions ........................................................................................................ 1299 26.4 jtag and boundary scan .......................................................................................... 1299 26.5 power and brown-out ............................................................................................... 1301 26.6 reset ........................................................................................................................ 1302 26.7 on-chip low drop-out (ldo) regulator ..................................................................... 1303 26.8 clocks ...................................................................................................................... 1303 26.8.1 pll specifications ..................................................................................................... 1303 26.8.2 piosc specifications ................................................................................................ 1304 26.8.3 internal 30-khz oscillator specifications ..................................................................... 1304 26.8.4 main oscillator specifications ..................................................................................... 1305 26.8.5 system clock specification with adc operation .......................................................... 1306 26.8.6 system clock specification with usb operation .......................................................... 1306 26.9 sleep modes ............................................................................................................. 1306 26.10 flash memory ........................................................................................................... 1306 26.11 input/output characteristics ....................................................................................... 1307 26.12 external peripheral interface (epi) .............................................................................. 1307 26.13 analog-to-digital converter (adc) .............................................................................. 1313 26.14 synchronous serial interface (ssi) ............................................................................. 1314 26.15 inter-integrated circuit (i 2 c) interface ......................................................................... 1316 26.16 inter-integrated circuit sound (i 2 s) interface ............................................................... 1317 26.17 ethernet controller .................................................................................................... 1318 26.18 universal serial bus (usb) controller ......................................................................... 1320 26.19 analog comparator ................................................................................................... 1321 26.20 current consumption ................................................................................................. 1321 26.20.1 nominal power consumption ..................................................................................... 1321 26.20.2 maximum current consumption ................................................................................. 1322 a register quick reference ................................................................................. 1323 b ordering and contact information ................................................................... 1378 b.1 ordering information .................................................................................................. 1378 b.2 part markings ............................................................................................................ 1378 b.3 kits ........................................................................................................................... 1378 b.4 support information ................................................................................................... 1379 c package information .......................................................................................... 1380 c.1 100-pin lqfp package ............................................................................................. 1380 c.1.1 package dimensions ................................................................................................. 1380 c.1.2 tray dimensions ....................................................................................................... 1382 c.1.3 tape and reel dimensions ........................................................................................ 1382 c.2 108-ball bga package .............................................................................................. 1384 c.2.1 package dimensions ................................................................................................. 1384 c.2.2 tray dimensions ....................................................................................................... 1386 c.2.3 tape and reel dimensions ........................................................................................ 1387 july 03, 2014 10 texas instruments-production data table of contents list of figures figure 1-1. stellaris lm3s9gn5 microcontroller high-level block diagram .............................. 47 figure 2-1. cpu block diagram ............................................................................................. 71 figure 2-2. tpiu block diagram ............................................................................................ 72 figure 2-3. cortex-m3 register set ........................................................................................ 74 figure 2-4. bit-band mapping ................................................................................................ 95 figure 2-5. data storage ....................................................................................................... 96 figure 2-6. vector table ...................................................................................................... 102 figure 2-7. exception stack frame ...................................................................................... 104 figure 3-1. srd use example ............................................................................................. 118 figure 4-1. jtag module block diagram .............................................................................. 179 figure 4-2. test access port state machine ......................................................................... 182 figure 4-3. idcode register format ................................................................................... 188 figure 4-4. bypass register format ................................................................................... 189 figure 4-5. boundary scan register format ......................................................................... 189 figure 5-1. basic rst configuration .................................................................................... 193 figure 5-2. external circuitry to extend power-on reset ....................................................... 193 figure 5-3. reset circuit controlled by switch ...................................................................... 194 figure 5-4. power architecture ............................................................................................ 197 figure 5-5. main clock tree ................................................................................................ 199 figure 6-1. internal memory block diagram .......................................................................... 298 figure 7-1. dma block diagram ......................................................................................... 345 figure 7-2. example of ping-pong dma transaction ........................................................... 352 figure 7-3. memory scatter-gather, setup and configuration ................................................ 354 figure 7-4. memory scatter-gather, dma copy sequence .................................................. 355 figure 7-5. peripheral scatter-gather, setup and configuration ............................................. 357 figure 7-6. peripheral scatter-gather, dma copy sequence ............................................... 358 figure 8-1. digital i/o pads ................................................................................................. 411 figure 8-2. analog/digital i/o pads ...................................................................................... 412 figure 8-3. gpiodata write example ................................................................................. 413 figure 8-4. gpiodata read example ................................................................................. 413 figure 9-1. epi block diagram ............................................................................................. 463 figure 9-2. sdram non-blocking read cycle ...................................................................... 471 figure 9-3. sdram normal read cycle ............................................................................... 471 figure 9-4. sdram write cycle ........................................................................................... 472 figure 9-5. example schematic for muxed host-bus 16 mode ............................................... 478 figure 9-6. host-bus read cycle, mode = 0x1, wrhigh = 0, rdhigh = 0 .......................... 480 figure 9-7. host-bus write cycle, mode = 0x1, wrhigh = 0, rdhigh = 0 .......................... 481 figure 9-8. host-bus write cycle with multiplexed address and data, mode = 0x0, wrhigh = 0, rdhigh = 0 ............................................................................................... 481 figure 9-9. host-bus write cycle with multiplexed address and data and ale with dual csn .................................................................................................................. 482 figure 9-10. continuous read mode accesses ...................................................................... 482 figure 9-11. write followed by read to external fifo ............................................................ 483 figure 9-12. two-entry fifo ................................................................................................. 483 figure 9-13. single-cycle write access, frm50=0, frmcnt=0, wrcyc=0 ........................... 487 11 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller figure 9-14. two-cycle read, write accesses, frm50=0, frmcnt=0, rdcyc=1, wrcyc=1 ........................................................................................................ 487 figure 9-15. read accesses, frm50=0, frmcnt=0, rdcyc=1 ............................................ 488 figure 9-16. frame signal operation, frm50=0 and frmcnt=0 ......................................... 488 figure 9-17. frame signal operation, frm50=0 and frmcnt=1 ......................................... 488 figure 9-18. frame signal operation, frm50=0 and frmcnt=2 ......................................... 489 figure 9-19. frame signal operation, frm50=1 and frmcnt=0 ......................................... 489 figure 9-20. frame signal operation, frm50=1 and frmcnt=1 ......................................... 489 figure 9-21. frame signal operation, frm50=1 and frmcnt=2 ......................................... 489 figure 9-22. irdy signal operation, frm50=0, frmcnt=0, and rd2cyc=1 ......................... 490 figure 9-23. epi clock operation, clkgate=1, wr2cyc=0 ................................................. 491 figure 9-24. epi clock operation, clkgate=1, wr2cyc=1 ................................................. 491 figure 10-1. gptm module block diagram ............................................................................ 537 figure 10-2. timer daisy chain ............................................................................................. 543 figure 10-3. input edge-count mode example ....................................................................... 545 figure 10-4. 16-bit input edge-time mode example ............................................................... 546 figure 10-5. 16-bit pwm mode example ................................................................................ 547 figure 11-1. wdt module block diagram .............................................................................. 584 figure 12-1. implementation of two adc blocks .................................................................... 609 figure 12-2. adc module block diagram ............................................................................... 610 figure 12-3. adc sample phases ......................................................................................... 614 figure 12-4. doubling the adc sample rate .......................................................................... 615 figure 12-5. skewed sampling .............................................................................................. 615 figure 12-6. sample averaging example ............................................................................... 616 figure 12-7. adc input equivalency diagram ......................................................................... 617 figure 12-8. internal voltage conversion result ..................................................................... 618 figure 12-9. external voltage conversion result with 3.0-v setting ......................................... 619 figure 12-10. external voltage conversion result with 1.0-v setting ......................................... 619 figure 12-11. differential sampling range, v in_odd = 1.5 v ...................................................... 621 figure 12-12. differential sampling range, v in_odd = 0.75 v .................................................... 621 figure 12-13. differential sampling range, v in_odd = 2.25 v .................................................... 622 figure 12-14. internal temperature sensor characteristic ......................................................... 623 figure 12-15. low-band operation (cic=0x0 and/or ctc=0x0) ................................................ 625 figure 12-16. mid-band operation (cic=0x1 and/or ctc=0x1) ................................................. 626 figure 12-17. high-band operation (cic=0x3 and/or ctc=0x3) ................................................ 627 figure 13-1. uart module block diagram ............................................................................. 690 figure 13-2. uart character frame ..................................................................................... 693 figure 13-3. irda data modulation ......................................................................................... 695 figure 13-4. lin message ..................................................................................................... 697 figure 13-5. lin synchronization field ................................................................................... 698 figure 14-1. ssi module block diagram ................................................................................. 754 figure 14-2. ti synchronous serial frame format (single transfer) ........................................ 758 figure 14-3. ti synchronous serial frame format (continuous transfer) ................................ 758 figure 14-4. freescale spi format (single transfer) with spo=0 and sph=0 .......................... 759 figure 14-5. freescale spi format (continuous transfer) with spo=0 and sph=0 .................. 759 figure 14-6. freescale spi frame format with spo=0 and sph=1 ......................................... 760 figure 14-7. freescale spi frame format (single transfer) with spo=1 and sph=0 ............... 761 figure 14-8. freescale spi frame format (continuous transfer) with spo=1 and sph=0 ........ 761 july 03, 2014 12 texas instruments-production data table of contents figure 14-9. freescale spi frame format with spo=1 and sph=1 ......................................... 762 figure 14-10. microwire frame format (single frame) ........................................................ 763 figure 14-11. microwire frame format (continuous transfer) ............................................. 764 figure 14-12. microwire frame format, ssifss input setup and hold requirements ............ 764 figure 15-1. i 2 c block diagram ............................................................................................. 796 figure 15-2. i 2 c bus configuration ........................................................................................ 797 figure 15-3. start and stop conditions ............................................................................. 798 figure 15-4. complete data transfer with a 7-bit address ....................................................... 798 figure 15-5. r/s bit in first byte ............................................................................................ 799 figure 15-6. data validity during bit transfer on the i 2 c bus ................................................... 799 figure 15-7. master single transmit .................................................................................. 803 figure 15-8. master single receive ..................................................................................... 804 figure 15-9. master transmit with repeated start ........................................................... 805 figure 15-10. master receive with repeated start ............................................................. 806 figure 15-11. master receive with repeated start after transmit with repeated start .............................................................................................................. 807 figure 15-12. master transmit with repeated start after receive with repeated start .............................................................................................................. 808 figure 15-13. slave command sequence ................................................................................ 809 figure 16-1. i 2 s block diagram ............................................................................................. 834 figure 16-2. i 2 s data transfer ............................................................................................... 837 figure 16-3. left-justified data transfer ................................................................................ 837 figure 16-4. right-justified data transfer .............................................................................. 837 figure 17-1. can controller block diagram ............................................................................ 871 figure 17-2. can data/remote frame .................................................................................. 873 figure 17-3. message objects in a fifo buffer ...................................................................... 881 figure 17-4. can bit time .................................................................................................... 885 figure 18-1. ethernet controller ............................................................................................. 921 figure 18-2. ethernet mac block diagram ............................................................................. 922 figure 18-3. ethernet frame ................................................................................................. 924 figure 18-4. management frame format ............................................................................... 930 figure 19-1. usb module block diagram ............................................................................... 958 figure 20-1. analog comparator module block diagram ....................................................... 1097 figure 20-2. structure of comparator unit ............................................................................ 1099 figure 20-3. comparator internal reference structure .......................................................... 1099 figure 21-1. pwm module diagram ..................................................................................... 1112 figure 21-2. pwm generator block diagram ........................................................................ 1112 figure 21-3. pwm count-down mode .................................................................................. 1117 figure 21-4. pwm count-up/down mode ............................................................................. 1117 figure 21-5. pwm generation example in count-up/down mode .......................................... 1118 figure 21-6. pwm dead-band generator ............................................................................. 1118 figure 22-1. qei block diagram .......................................................................................... 1189 figure 22-2. quadrature encoder and velocity predivider operation ...................................... 1192 figure 23-1. 100-pin lqfp package pin diagram ................................................................ 1211 figure 23-2. 108-ball bga package pin diagram (top view) ................................................. 1212 figure 26-1. load conditions ............................................................................................... 1299 figure 26-2. jtag test clock input timing ........................................................................... 1300 figure 26-3. jtag test access port (tap) timing ................................................................ 1300 13 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller figure 26-4. power-on reset timing ................................................................................... 1301 figure 26-5. brown-out reset timing .................................................................................. 1301 figure 26-6. power-on reset and voltage parameters ......................................................... 1302 figure 26-7. external reset timing (rst ) ............................................................................ 1302 figure 26-8. software reset timing ..................................................................................... 1302 figure 26-9. watchdog reset timing ................................................................................... 1303 figure 26-10. mosc failure reset timing ............................................................................. 1303 figure 26-11. sdram initialization and load mode register timing ........................................ 1308 figure 26-12. sdram read timing ....................................................................................... 1308 figure 26-13. sdram write timing ....................................................................................... 1309 figure 26-14. host-bus 8/16 mode read timing ..................................................................... 1310 figure 26-15. host-bus 8/16 mode write timing ..................................................................... 1310 figure 26-16. host-bus 8/16 mode muxed read timing .......................................................... 1311 figure 26-17. host-bus 8/16 mode muxed write timing .......................................................... 1311 figure 26-18. general-purpose mode read and write timing ................................................. 1312 figure 26-19. general-purpose mode irdy timing ................................................................. 1312 figure 26-20. adc input equivalency diagram ....................................................................... 1314 figure 26-21. ssi timing for ti frame format (frf=01), single transfer timing measurement .................................................................................................. 1315 figure 26-22. ssi timing for microwire frame format (frf=10), single transfer ............... 1315 figure 26-23. ssi timing for spi frame format (frf=00), with sph=1 ................................... 1316 figure 26-24. i 2 c timing ....................................................................................................... 1317 figure 26-25. i 2 s master mode transmit timing ..................................................................... 1317 figure 26-26. i 2 s master mode receive timing ...................................................................... 1318 figure 26-27. i 2 s slave mode transmit timing ....................................................................... 1318 figure 26-28. i 2 s slave mode receive timing ........................................................................ 1318 figure c-1. stellaris lm3s9gn5 100-pin lqfp package dimensions .................................. 1380 figure c-2. 100-pin lqfp tray dimensions ........................................................................ 1382 figure c-3. 100-pin lqfp tape and reel dimensions ......................................................... 1383 figure c-4. stellaris lm3s9gn5 108-ball bga package dimensions ................................... 1384 figure c-5. 108-ball bga tray dimensions ......................................................................... 1386 figure c-6. 108-ball bga tape and reel dimensions .......................................................... 1387 july 03, 2014 14 texas instruments-production data table of contents list of tables table 1. revision history .................................................................................................. 40 table 2. documentation conventions ................................................................................ 44 table 2-1. summary of processor mode, privilege level, and stack use ................................ 74 table 2-2. processor register map ....................................................................................... 75 table 2-3. psr register combinations ................................................................................. 80 table 2-4. memory map ....................................................................................................... 88 table 2-5. memory access behavior ..................................................................................... 91 table 2-6. sram memory bit-banding regions .................................................................... 93 table 2-7. peripheral memory bit-banding regions ............................................................... 93 table 2-8. exception types .................................................................................................. 99 table 2-9. interrupts .......................................................................................................... 100 table 2-10. exception return behavior ................................................................................. 105 table 2-11. faults ............................................................................................................... 106 table 2-12. fault status and fault address registers ............................................................ 107 table 2-13. cortex-m3 instruction summary ......................................................................... 109 table 3-1. core peripheral register regions ....................................................................... 112 table 3-2. memory attributes summary .............................................................................. 115 table 3-3. tex, s, c, and b bit field encoding ................................................................... 118 table 3-4. cache policy for memory attribute encoding ....................................................... 119 table 3-5. ap bit field encoding ........................................................................................ 119 table 3-6. memory region attributes for stellaris microcontrollers ........................................ 119 table 3-7. peripherals register map ................................................................................... 120 table 3-8. interrupt priority levels ...................................................................................... 147 table 3-9. example size field values ................................................................................ 175 table 4-1. jtag_swd_swo signals (100lqfp) ................................................................ 179 table 4-2. jtag_swd_swo signals (108bga) ................................................................. 180 table 4-3. jtag port pins state after power-on reset or rst assertion .............................. 181 table 4-4. jtag instruction register commands ................................................................. 186 table 5-1. system control & clocks signals (100lqfp) ...................................................... 190 table 5-2. system control & clocks signals (108bga) ........................................................ 190 table 5-3. reset sources ................................................................................................... 191 table 5-4. clock source options ........................................................................................ 198 table 5-5. possible system clock frequencies using the sysdiv field ............................... 200 table 5-6. examples of possible system clock frequencies using the sysdiv2 field .......... 200 table 5-7. examples of possible system clock frequencies with div400=1 ......................... 201 table 5-8. system control register map ............................................................................. 205 table 5-9. rcc2 fields that override rcc fields ............................................................... 227 table 6-1. flash memory protection policy combinations .................................................... 302 table 6-2. user-programmable flash memory resident registers ....................................... 306 table 6-3. flash register map ............................................................................................ 306 table 7-1. dma channel assignments .............................................................................. 346 table 7-2. request type support ....................................................................................... 348 table 7-3. control structure memory map ........................................................................... 349 table 7-4. channel control structure .................................................................................. 349 table 7-5. dma read example: 8-bit peripheral ................................................................ 359 table 7-6. dma interrupt assignments .............................................................................. 360 15 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 7-7. channel control structure offsets for channel 30 ................................................ 361 table 7-8. channel control word configuration for memory transfer example ...................... 361 table 7-9. channel control structure offsets for channel 7 .................................................. 362 table 7-10. channel control word configuration for peripheral transmit example .................. 363 table 7-11. primary and alternate channel control structure offsets for channel 8 ................. 364 table 7-12. channel control word configuration for peripheral ping-pong receive example ............................................................................................................ 365 table 7-13. dma register map .......................................................................................... 367 table 8-1. gpio pins with non-zero reset values .............................................................. 406 table 8-2. gpio pins and alternate functions (100lqfp) ................................................... 406 table 8-3. gpio pins and alternate functions (108bga) ..................................................... 408 table 8-4. gpio pad configuration examples ..................................................................... 415 table 8-5. gpio interrupt configuration example ................................................................ 416 table 8-6. gpio pins with non-zero reset values .............................................................. 417 table 8-7. gpio register map ........................................................................................... 417 table 8-8. gpio pins with non-zero reset values .............................................................. 429 table 8-9. gpio pins with non-zero reset values .............................................................. 435 table 8-10. gpio pins with non-zero reset values .............................................................. 437 table 8-11. gpio pins with non-zero reset values .............................................................. 440 table 8-12. gpio pins with non-zero reset values .............................................................. 447 table 9-1. external peripheral interface signals (100lqfp) ................................................. 463 table 9-2. external peripheral interface signals (108bga) ................................................... 464 table 9-3. epi sdram signal connections ......................................................................... 469 table 9-4. capabilities of host bus 8 and host bus 16 modes .............................................. 473 table 9-5. epi host-bus 8 signal connections .................................................................... 474 table 9-6. epi host-bus 16 signal connections .................................................................. 476 table 9-7. epi general purpose signal connections ........................................................... 485 table 9-8. external peripheral interface (epi) register map ................................................. 491 table 10-1. available ccp pins ............................................................................................ 537 table 10-2. general-purpose timers signals (100lqfp) ....................................................... 538 table 10-3. general-purpose timers signals (108bga) ......................................................... 539 table 10-4. general-purpose timer capabilities .................................................................... 541 table 10-5. counter values when the timer is enabled in periodic or one-shot modes .......... 542 table 10-6. 16-bit timer with prescaler configurations ......................................................... 542 table 10-7. counter values when the timer is enabled in rtc mode .................................... 543 table 10-8. counter values when the timer is enabled in input edge-count mode ................. 544 table 10-9. counter values when the timer is enabled in input event-count mode ................ 545 table 10-10. counter values when the timer is enabled in pwm mode ................................... 547 table 10-11. timers register map .......................................................................................... 551 table 11-1. watchdog timers register map .......................................................................... 586 table 12-1. adc signals (100lqfp) .................................................................................... 610 table 12-2. adc signals (108bga) ...................................................................................... 611 table 12-3. samples and fifo depth of sequencers ............................................................ 612 table 12-4. differential sampling pairs ................................................................................. 620 table 12-5. adc register map ............................................................................................. 628 table 13-1. uart signals (100lqfp) .................................................................................. 691 table 13-2. uart signals (108bga) .................................................................................... 691 table 13-3. flow control mode ............................................................................................. 697 july 03, 2014 16 texas instruments-production data table of contents table 13-4. uart register map ........................................................................................... 702 table 14-1. ssi signals (100lqfp) ...................................................................................... 755 table 14-2. ssi signals (108bga) ........................................................................................ 755 table 14-3. ssi register map .............................................................................................. 766 table 15-1. i2c signals (100lqfp) ...................................................................................... 796 table 15-2. i2c signals (108bga) ........................................................................................ 796 table 15-3. examples of i 2 c master timer period versus speed mode ................................... 800 table 15-4. inter-integrated circuit (i 2 c) interface register map ............................................. 810 table 15-5. write field decoding for i2cmcs[3:0] field ......................................................... 816 table 16-1. i2s signals (100lqfp) ...................................................................................... 835 table 16-2. i2s signals (108bga) ........................................................................................ 835 table 16-3. i 2 s transmit fifo interface ................................................................................ 838 table 16-4. crystal frequency (values from 3.5795 mhz to 5 mhz) ........................................ 839 table 16-5. crystal frequency (values from 5.12 mhz to 8.192 mhz) ..................................... 839 table 16-6. crystal frequency (values from 10 mhz to 14.3181 mhz) .................................... 840 table 16-7. crystal frequency (values from 16 mhz to 16.384 mhz) ...................................... 840 table 16-8. i 2 s receive fifo interface ................................................................................. 842 table 16-9. audio formats configuration .............................................................................. 844 table 16-10. inter-integrated circuit sound (i 2 s) interface register map ................................... 845 table 17-1. controller area network signals (100lqfp) ........................................................ 872 table 17-2. controller area network signals (108bga) ......................................................... 872 table 17-3. message object configurations .......................................................................... 878 table 17-4. can protocol ranges ........................................................................................ 885 table 17-5. canbit register values .................................................................................... 885 table 17-6. can register map ............................................................................................. 889 table 18-1. ethernet signals (100lqfp) ............................................................................... 922 table 18-2. ethernet signals (108bga) ................................................................................ 923 table 18-3. tx & rx fifo organization ............................................................................... 926 table 18-4. receive signal encoding ................................................................................... 928 table 18-5. transmit signal encoding ................................................................................... 929 table 18-6. ethernet register map ....................................................................................... 933 table 19-1. usb signals (100lqfp) .................................................................................... 959 table 19-2. usb signals (108bga) ...................................................................................... 959 table 19-3. remainder (maxload/4) .................................................................................. 971 table 19-4. actual bytes read ............................................................................................. 971 table 19-5. packet sizes that clear rxrdy ........................................................................ 972 table 19-6. universal serial bus (usb) controller register map ............................................ 973 table 20-1. analog comparators signals (100lqfp) ........................................................... 1097 table 20-2. analog comparators signals (108bga) ............................................................. 1098 table 20-3. internal reference voltage and acrefctl field values ................................... 1100 table 20-4. analog comparators register map ................................................................... 1101 table 21-1. pwm signals (100lqfp) ................................................................................. 1113 table 21-2. pwm signals (108bga) ................................................................................... 1114 table 21-3. pwm register map .......................................................................................... 1122 table 22-1. qei signals (100lqfp) .................................................................................... 1189 table 22-2. qei signals (108bga) ..................................................................................... 1190 table 22-3. qei register map ............................................................................................ 1194 table 24-1. gpio pins with default alternate functions ...................................................... 1213 17 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 24-2. signals by pin number ..................................................................................... 1214 table 24-3. signals by signal name ................................................................................... 1227 table 24-4. signals by function, except for gpio ............................................................... 1239 table 24-5. gpio pins and alternate functions ................................................................... 1248 table 24-6. possible pin assignments for alternate functions .............................................. 1251 table 24-7. signals by pin number ..................................................................................... 1255 table 24-8. signals by signal name ................................................................................... 1269 table 24-9. signals by function, except for gpio ............................................................... 1280 table 24-10. gpio pins and alternate functions ................................................................... 1289 table 24-11. possible pin assignments for alternate functions .............................................. 1292 table 24-12. connections for unused signals (100-pin lqfp) ............................................... 1296 table 24-13. connections for unused signals (108-ball bga) ................................................ 1296 table 25-1. temperature characteristics ............................................................................. 1297 table 25-2. thermal characteristics ................................................................................... 1297 table 25-3. esd absolute maximum ratings ...................................................................... 1297 table 26-1. maximum ratings ............................................................................................ 1298 table 26-2. recommended dc operating conditions .......................................................... 1298 table 26-3. jtag characteristics ....................................................................................... 1299 table 26-4. power characteristics ...................................................................................... 1301 table 26-5. reset characteristics ....................................................................................... 1302 table 26-6. ldo regulator characteristics ......................................................................... 1303 table 26-7. phase locked loop (pll) characteristics ......................................................... 1303 table 26-8. actual pll frequency ...................................................................................... 1304 table 26-9. piosc clock characteristics ............................................................................ 1304 table 26-10. 30-khz clock characteristics ............................................................................ 1304 table 26-11. main oscillator clock characteristics ................................................................ 1305 table 26-12. supported mosc crystal frequencies .............................................................. 1305 table 26-13. system clock characteristics with adc operation ............................................. 1306 table 26-14. system clock characteristics with usb operation ............................................. 1306 table 26-15. sleep modes ac characteristics ....................................................................... 1306 table 26-16. flash memory characteristics ........................................................................... 1306 table 26-17. gpio module characteristics ............................................................................ 1307 table 26-18. epi sdram characteristics ............................................................................. 1307 table 26-19. epi sdram interface characteristics ............................................................... 1307 table 26-20. epi host-bus 8 and host-bus 16 interface characteristics ................................. 1309 table 26-21. epi general-purpose interface characteristics .................................................. 1311 table 26-22. adc characteristics ......................................................................................... 1313 table 26-23. adc module external reference characteristics ............................................... 1314 table 26-24. adc module internal reference characteristics ................................................ 1314 table 26-25. ssi characteristics .......................................................................................... 1314 table 26-26. i 2 c characteristics ........................................................................................... 1316 table 26-27. i 2 s master clock (receive and transmit) .......................................................... 1317 table 26-28. i 2 s slave clock (receive and transmit) ............................................................ 1317 table 26-29. i 2 s master mode .............................................................................................. 1317 table 26-30. i 2 s slave mode ................................................................................................ 1318 table 26-31. ethernet station management .......................................................................... 1318 table 26-32. 100base-tx transmitter characteristics .......................................................... 1319 table 26-33. 100base-tx transmitter characteristics (informative) ....................................... 1319 july 03, 2014 18 texas instruments-production data table of contents table 26-34. 100base-tx receiver characteristics .............................................................. 1319 table 26-35. 10base-t transmitter characteristics .............................................................. 1319 table 26-36. 10base-t transmitter characteristics (informative) ........................................... 1320 table 26-37. 10base-t receiver characteristics .................................................................. 1320 table 26-38. isolation transformers ...................................................................................... 1320 table 26-39. usb controller characteristics ......................................................................... 1321 table 26-40. analog comparator characteristics ................................................................... 1321 table 26-41. analog comparator voltage reference characteristics ...................................... 1321 table 26-42. nominal power consumption ........................................................................... 1321 table 26-43. detailed current specifications ......................................................................... 1322 19 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller list of registers the cortex-m3 processor ............................................................................................................. 69 register 1: cortex general-purpose register 0 (r0) ........................................................................... 76 register 2: cortex general-purpose register 1 (r1) ........................................................................... 76 register 3: cortex general-purpose register 2 (r2) ........................................................................... 76 register 4: cortex general-purpose register 3 (r3) ........................................................................... 76 register 5: cortex general-purpose register 4 (r4) ........................................................................... 76 register 6: cortex general-purpose register 5 (r5) ........................................................................... 76 register 7: cortex general-purpose register 6 (r6) ........................................................................... 76 register 8: cortex general-purpose register 7 (r7) ........................................................................... 76 register 9: cortex general-purpose register 8 (r8) ........................................................................... 76 register 10: cortex general-purpose register 9 (r9) ........................................................................... 76 register 11: cortex general-purpose register 10 (r10) ....................................................................... 76 register 12: cortex general-purpose register 11 (r11) ........................................................................ 76 register 13: cortex general-purpose register 12 (r12) ....................................................................... 76 register 14: stack pointer (sp) ........................................................................................................... 77 register 15: link register (lr) ............................................................................................................ 78 register 16: program counter (pc) ..................................................................................................... 79 register 17: program status register (psr) ........................................................................................ 80 register 18: priority mask register (primask) .................................................................................... 84 register 19: fault mask register (faultmask) .................................................................................. 85 register 20: base priority mask register (basepri) ............................................................................ 86 register 21: control register (control) ........................................................................................... 87 cortex-m3 peripherals ................................................................................................................. 112 register 1: systick control and status register (stctrl), offset 0x010 ........................................... 123 register 2: systick reload value register (streload), offset 0x014 .............................................. 125 register 3: systick current value register (stcurrent), offset 0x018 ........................................... 126 register 4: interrupt 0-31 set enable (en0), offset 0x100 .................................................................. 127 register 5: interrupt 32-54 set enable (en1), offset 0x104 ................................................................ 128 register 6: interrupt 0-31 clear enable (dis0), offset 0x180 .............................................................. 129 register 7: interrupt 32-54 clear enable (dis1), offset 0x184 ............................................................ 130 register 8: interrupt 0-31 set pending (pend0), offset 0x200 ........................................................... 131 register 9: interrupt 32-54 set pending (pend1), offset 0x204 ......................................................... 132 register 10: interrupt 0-31 clear pending (unpend0), offset 0x280 ................................................... 133 register 11: interrupt 32-54 clear pending (unpend1), offset 0x284 .................................................. 134 register 12: interrupt 0-31 active bit (active0), offset 0x300 ............................................................. 135 register 13: interrupt 32-54 active bit (active1), offset 0x304 ........................................................... 136 register 14: interrupt 0-3 priority (pri0), offset 0x400 ......................................................................... 137 register 15: interrupt 4-7 priority (pri1), offset 0x404 ......................................................................... 137 register 16: interrupt 8-11 priority (pri2), offset 0x408 ....................................................................... 137 register 17: interrupt 12-15 priority (pri3), offset 0x40c .................................................................... 137 register 18: interrupt 16-19 priority (pri4), offset 0x410 ..................................................................... 137 register 19: interrupt 20-23 priority (pri5), offset 0x414 ..................................................................... 137 register 20: interrupt 24-27 priority (pri6), offset 0x418 ..................................................................... 137 register 21: interrupt 28-31 priority (pri7), offset 0x41c .................................................................... 137 register 22: interrupt 32-35 priority (pri8), offset 0x420 ..................................................................... 137 july 03, 2014 20 texas instruments-production data table of contents register 23: interrupt 36-39 priority (pri9), offset 0x424 ..................................................................... 137 register 24: interrupt 40-43 priority (pri10), offset 0x428 ................................................................... 137 register 25: interrupt 44-47 priority (pri11), offset 0x42c ................................................................... 137 register 26: interrupt 48-51 priority (pri12), offset 0x430 ................................................................... 137 register 27: interrupt 52-54 priority (pri13), offset 0x434 ................................................................... 137 register 28: software trigger interrupt (swtrig), offset 0xf00 .......................................................... 139 register 29: auxiliary control (actlr), offset 0x008 .......................................................................... 140 register 30: cpu id base (cpuid), offset 0xd00 ............................................................................... 142 register 31: interrupt control and state (intctrl), offset 0xd04 ........................................................ 143 register 32: vector table offset (vtable), offset 0xd08 .................................................................... 146 register 33: application interrupt and reset control (apint), offset 0xd0c ......................................... 147 register 34: system control (sysctrl), offset 0xd10 ....................................................................... 149 register 35: configuration and control (cfgctrl), offset 0xd14 ....................................................... 151 register 36: system handler priority 1 (syspri1), offset 0xd18 ......................................................... 153 register 37: system handler priority 2 (syspri2), offset 0xd1c ........................................................ 154 register 38: system handler priority 3 (syspri3), offset 0xd20 ......................................................... 155 register 39: system handler control and state (syshndctrl), offset 0xd24 .................................... 156 register 40: configurable fault status (faultstat), offset 0xd28 ..................................................... 160 register 41: hard fault status (hfaultstat), offset 0xd2c .............................................................. 166 register 42: memory management fault address (mmaddr), offset 0xd34 ........................................ 167 register 43: bus fault address (faultaddr), offset 0xd38 .............................................................. 168 register 44: mpu type (mputype), offset 0xd90 ............................................................................. 169 register 45: mpu control (mpuctrl), offset 0xd94 .......................................................................... 170 register 46: mpu region number (mpunumber), offset 0xd98 ....................................................... 172 register 47: mpu region base address (mpubase), offset 0xd9c ................................................... 173 register 48: mpu region base address alias 1 (mpubase1), offset 0xda4 ....................................... 173 register 49: mpu region base address alias 2 (mpubase2), offset 0xdac ...................................... 173 register 50: mpu region base address alias 3 (mpubase3), offset 0xdb4 ....................................... 173 register 51: mpu region attribute and size (mpuattr), offset 0xda0 ............................................... 175 register 52: mpu region attribute and size alias 1 (mpuattr1), offset 0xda8 .................................. 175 register 53: mpu region attribute and size alias 2 (mpuattr2), offset 0xdb0 .................................. 175 register 54: mpu region attribute and size alias 3 (mpuattr3), offset 0xdb8 .................................. 175 system control ............................................................................................................................ 190 register 1: device identification 0 (did0), offset 0x000 ..................................................................... 208 register 2: brown-out reset control (pborctl), offset 0x030 ........................................................ 210 register 3: raw interrupt status (ris), offset 0x050 .......................................................................... 211 register 4: interrupt mask control (imc), offset 0x054 ...................................................................... 213 register 5: masked interrupt status and clear (misc), offset 0x058 .................................................. 215 register 6: reset cause (resc), offset 0x05c ................................................................................ 217 register 7: run-mode clock configuration (rcc), offset 0x060 ......................................................... 219 register 8: xtal to pll translation (pllcfg), offset 0x064 ............................................................. 224 register 9: gpio high-performance bus control (gpiohbctl), offset 0x06c ................................... 225 register 10: run-mode clock configuration 2 (rcc2), offset 0x070 .................................................... 227 register 11: main oscillator control (moscctl), offset 0x07c ........................................................... 230 register 12: deep sleep clock configuration (dslpclkcfg), offset 0x144 ........................................ 231 register 13: precision internal oscillator calibration (piosccal), offset 0x150 ................................... 233 register 14: i 2 s mclk configuration (i2smclkcfg), offset 0x170 ..................................................... 234 register 15: device identification 1 (did1), offset 0x004 ..................................................................... 236 21 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 16: device capabilities 0 (dc0), offset 0x008 ........................................................................ 238 register 17: device capabilities 1 (dc1), offset 0x010 ........................................................................ 239 register 18: device capabilities 2 (dc2), offset 0x014 ........................................................................ 242 register 19: device capabilities 3 (dc3), offset 0x018 ........................................................................ 244 register 20: device capabilities 4 (dc4), offset 0x01c ....................................................................... 247 register 21: device capabilities 5 (dc5), offset 0x020 ........................................................................ 249 register 22: device capabilities 6 (dc6), offset 0x024 ........................................................................ 251 register 23: device capabilities 7 (dc7), offset 0x028 ........................................................................ 252 register 24: device capabilities 8 adc channels (dc8), offset 0x02c ................................................ 256 register 25: device capabilities 9 adc digital comparators (dc9), offset 0x190 ................................. 259 register 26: non-volatile memory information (nvmstat), offset 0x1a0 ............................................. 261 register 27: run mode clock gating control register 0 (rcgc0), offset 0x100 ................................... 262 register 28: sleep mode clock gating control register 0 (scgc0), offset 0x110 ................................. 265 register 29: deep sleep mode clock gating control register 0 (dcgc0), offset 0x120 ....................... 268 register 30: run mode clock gating control register 1 (rcgc1), offset 0x104 ................................... 270 register 31: sleep mode clock gating control register 1 (scgc1), offset 0x114 ................................. 274 register 32: deep-sleep mode clock gating control register 1 (dcgc1), offset 0x124 ....................... 278 register 33: run mode clock gating control register 2 (rcgc2), offset 0x108 ................................... 282 register 34: sleep mode clock gating control register 2 (scgc2), offset 0x118 ................................. 285 register 35: deep sleep mode clock gating control register 2 (dcgc2), offset 0x128 ....................... 288 register 36: software reset control 0 (srcr0), offset 0x040 ............................................................. 291 register 37: software reset control 1 (srcr1), offset 0x044 ............................................................. 293 register 38: software reset control 2 (srcr2), offset 0x048 ............................................................. 296 internal memory ........................................................................................................................... 298 register 1: flash memory address (fma), offset 0x000 .................................................................... 309 register 2: flash memory data (fmd), offset 0x004 ......................................................................... 310 register 3: flash memory control (fmc), offset 0x008 ..................................................................... 311 register 4: flash controller raw interrupt status (fcris), offset 0x00c ............................................ 314 register 5: flash controller interrupt mask (fcim), offset 0x010 ........................................................ 315 register 6: flash controller masked interrupt status and clear (fcmisc), offset 0x014 ..................... 316 register 7: flash memory control 2 (fmc2), offset 0x020 ................................................................. 317 register 8: flash write buffer valid (fwbval), offset 0x030 ............................................................. 318 register 9: flash control (fctl), offset 0x0f8 ................................................................................. 319 register 10: flash write buffer n (fwbn), offset 0x100 - 0x17c .......................................................... 320 register 11: rom control (rmctl), offset 0x0f0 .............................................................................. 321 register 12: flash memory protection read enable 0 (fmpre0), offset 0x130 and 0x200 ................... 322 register 13: flash memory protection program enable 0 (fmppe0), offset 0x134 and 0x400 ............... 323 register 14: boot configuration (bootcfg), offset 0x1d0 ................................................................. 324 register 15: user register 0 (user_reg0), offset 0x1e0 .................................................................. 326 register 16: user register 1 (user_reg1), offset 0x1e4 .................................................................. 327 register 17: user register 2 (user_reg2), offset 0x1e8 .................................................................. 328 register 18: user register 3 (user_reg3), offset 0x1ec ................................................................. 329 register 19: flash memory protection read enable 1 (fmpre1), offset 0x204 .................................... 330 register 20: flash memory protection read enable 2 (fmpre2), offset 0x208 .................................... 331 register 21: flash memory protection read enable 3 (fmpre3), offset 0x20c ................................... 332 register 22: flash memory protection read enable 4 (fmpre4), offset 0x210 .................................... 333 register 23: flash memory protection read enable 5 (fmpre5), offset 0x214 .................................... 334 register 24: flash memory protection read enable 6 (fmpre6), offset 0x218 .................................... 335 july 03, 2014 22 texas instruments-production data table of contents register 25: flash memory protection read enable 7 (fmpre7), offset 0x21c ................................... 336 register 26: flash memory protection program enable 1 (fmppe1), offset 0x404 ............................... 337 register 27: flash memory protection program enable 2 (fmppe2), offset 0x408 ............................... 338 register 28: flash memory protection program enable 3 (fmppe3), offset 0x40c ............................... 339 register 29: flash memory protection program enable 4 (fmppe4), offset 0x410 ............................... 340 register 30: flash memory protection program enable 5 (fmppe5), offset 0x414 ............................... 341 register 31: flash memory protection program enable 6 (fmppe6), offset 0x418 ............................... 342 register 32: flash memory protection program enable 7 (fmppe7), offset 0x41c ............................... 343 micro direct memory access (dma) ........................................................................................ 344 register 1: dma channel source address end pointer (dmasrcendp), offset 0x000 ...................... 369 register 2: dma channel destination address end pointer (dmadstendp), offset 0x004 ................ 370 register 3: dma channel control word (dmachctl), offset 0x008 .................................................. 371 register 4: dma status (dmastat), offset 0x000 ............................................................................ 376 register 5: dma configuration (dmacfg), offset 0x004 ................................................................... 378 register 6: dma channel control base pointer (dmactlbase), offset 0x008 .................................. 379 register 7: dma alternate channel control base pointer (dmaaltbase), offset 0x00c .................... 380 register 8: dma channel wait-on-request status (dmawaitstat), offset 0x010 ............................. 381 register 9: dma channel software request (dmaswreq), offset 0x014 ......................................... 382 register 10: dma channel useburst set (dmauseburstset), offset 0x018 .................................... 383 register 11: dma channel useburst clear (dmauseburstclr), offset 0x01c ................................. 384 register 12: dma channel request mask set (dmareqmaskset), offset 0x020 .............................. 385 register 13: dma channel request mask clear (dmareqmaskclr), offset 0x024 ........................... 386 register 14: dma channel enable set (dmaenaset), offset 0x028 ................................................... 387 register 15: dma channel enable clear (dmaenaclr), offset 0x02c ............................................... 388 register 16: dma channel primary alternate set (dmaaltset), offset 0x030 .................................... 389 register 17: dma channel primary alternate clear (dmaaltclr), offset 0x034 ................................. 390 register 18: dma channel priority set (dmaprioset), offset 0x038 ................................................. 391 register 19: dma channel priority clear (dmaprioclr), offset 0x03c .............................................. 392 register 20: dma bus error clear (dmaerrclr), offset 0x04c ........................................................ 393 register 21: dma channel assignment (dmachasgn), offset 0x500 ................................................. 394 register 22: dma channel interrupt status (dmachis), offset 0x504 .................................................. 395 register 23: dma peripheral identification 0 (dmaperiphid0), offset 0xfe0 ......................................... 396 register 24: dma peripheral identification 1 (dmaperiphid1), offset 0xfe4 ......................................... 397 register 25: dma peripheral identification 2 (dmaperiphid2), offset 0xfe8 ......................................... 398 register 26: dma peripheral identification 3 (dmaperiphid3), offset 0xfec ........................................ 399 register 27: dma peripheral identification 4 (dmaperiphid4), offset 0xfd0 ......................................... 400 register 28: dma primecell identification 0 (dmapcellid0), offset 0xff0 ........................................... 401 register 29: dma primecell identification 1 (dmapcellid1), offset 0xff4 ........................................... 402 register 30: dma primecell identification 2 (dmapcellid2), offset 0xff8 ........................................... 403 register 31: dma primecell identification 3 (dmapcellid3), offset 0xffc ........................................... 404 general-purpose input/outputs (gpios) ................................................................................... 405 register 1: gpio data (gpiodata), offset 0x000 ............................................................................ 419 register 2: gpio direction (gpiodir), offset 0x400 ......................................................................... 420 register 3: gpio interrupt sense (gpiois), offset 0x404 .................................................................. 421 register 4: gpio interrupt both edges (gpioibe), offset 0x408 ........................................................ 422 register 5: gpio interrupt event (gpioiev), offset 0x40c ................................................................ 423 register 6: gpio interrupt mask (gpioim), offset 0x410 ................................................................... 424 register 7: gpio raw interrupt status (gpioris), offset 0x414 ........................................................ 425 23 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 8: gpio masked interrupt status (gpiomis), offset 0x418 ................................................... 426 register 9: gpio interrupt clear (gpioicr), offset 0x41c ................................................................ 428 register 10: gpio alternate function select (gpioafsel), offset 0x420 ............................................ 429 register 11: gpio 2-ma drive select (gpiodr2r), offset 0x500 ........................................................ 431 register 12: gpio 4-ma drive select (gpiodr4r), offset 0x504 ........................................................ 432 register 13: gpio 8-ma drive select (gpiodr8r), offset 0x508 ........................................................ 433 register 14: gpio open drain select (gpioodr), offset 0x50c ......................................................... 434 register 15: gpio pull-up select (gpiopur), offset 0x510 ................................................................ 435 register 16: gpio pull-down select (gpiopdr), offset 0x514 ........................................................... 437 register 17: gpio slew rate control select (gpioslr), offset 0x518 ................................................ 439 register 18: gpio digital enable (gpioden), offset 0x51c ................................................................ 440 register 19: gpio lock (gpiolock), offset 0x520 ............................................................................ 442 register 20: gpio commit (gpiocr), offset 0x524 ............................................................................ 443 register 21: gpio analog mode select (gpioamsel), offset 0x528 ................................................... 445 register 22: gpio port control (gpiopctl), offset 0x52c ................................................................. 447 register 23: gpio peripheral identification 4 (gpioperiphid4), offset 0xfd0 ....................................... 449 register 24: gpio peripheral identification 5 (gpioperiphid5), offset 0xfd4 ....................................... 450 register 25: gpio peripheral identification 6 (gpioperiphid6), offset 0xfd8 ....................................... 451 register 26: gpio peripheral identification 7 (gpioperiphid7), offset 0xfdc ...................................... 452 register 27: gpio peripheral identification 0 (gpioperiphid0), offset 0xfe0 ....................................... 453 register 28: gpio peripheral identification 1 (gpioperiphid1), offset 0xfe4 ....................................... 454 register 29: gpio peripheral identification 2 (gpioperiphid2), offset 0xfe8 ....................................... 455 register 30: gpio peripheral identification 3 (gpioperiphid3), offset 0xfec ...................................... 456 register 31: gpio primecell identification 0 (gpiopcellid0), offset 0xff0 .......................................... 457 register 32: gpio primecell identification 1 (gpiopcellid1), offset 0xff4 .......................................... 458 register 33: gpio primecell identification 2 (gpiopcellid2), offset 0xff8 .......................................... 459 register 34: gpio primecell identification 3 (gpiopcellid3), offset 0xffc ......................................... 460 external peripheral interface (epi) ............................................................................................. 461 register 1: epi configuration (epicfg), offset 0x000 ....................................................................... 493 register 2: epi main baud rate (epibaud), offset 0x004 ................................................................. 494 register 3: epi sdram configuration (episdramcfg), offset 0x010 .............................................. 496 register 4: epi host-bus 8 configuration (epihb8cfg), offset 0x010 ............................................... 498 register 5: epi host-bus 16 configuration (epihb16cfg), offset 0x010 ........................................... 501 register 6: epi general-purpose configuration (epigpcfg), offset 0x010 ........................................ 505 register 7: epi host-bus 8 configuration 2 (epihb8cfg2), offset 0x014 .......................................... 510 register 8: epi host-bus 16 configuration 2 (epihb16cfg2), offset 0x014 ....................................... 513 register 9: epi general-purpose configuration 2 (epigpcfg2), offset 0x014 ................................... 516 register 10: epi address map (epiaddrmap), offset 0x01c ............................................................. 517 register 11: epi read size 0 (epirsize0), offset 0x020 .................................................................... 519 register 12: epi read size 1 (epirsize1), offset 0x030 .................................................................... 519 register 13: epi read address 0 (epiraddr0), offset 0x024 ............................................................ 520 register 14: epi read address 1 (epiraddr1), offset 0x034 ............................................................ 520 register 15: epi non-blocking read data 0 (epirpstd0), offset 0x028 ............................................. 521 register 16: epi non-blocking read data 1 (epirpstd1), offset 0x038 ............................................. 521 register 17: epi status (epistat), offset 0x060 ................................................................................ 523 register 18: epi read fifo count (epirfifocnt), offset 0x06c ...................................................... 525 register 19: epi read fifo (epireadfifo), offset 0x070 ................................................................ 526 register 20: epi read fifo alias 1 (epireadfifo1), offset 0x074 .................................................... 526 july 03, 2014 24 texas instruments-production data table of contents register 21: epi read fifo alias 2 (epireadfifo2), offset 0x078 .................................................... 526 register 22: epi read fifo alias 3 (epireadfifo3), offset 0x07c ................................................... 526 register 23: epi read fifo alias 4 (epireadfifo4), offset 0x080 .................................................... 526 register 24: epi read fifo alias 5 (epireadfifo5), offset 0x084 .................................................... 526 register 25: epi read fifo alias 6 (epireadfifo6), offset 0x088 .................................................... 526 register 26: epi read fifo alias 7 (epireadfifo7), offset 0x08c ................................................... 526 register 27: epi fifo level selects (epififolvl), offset 0x200 ........................................................ 527 register 28: epi write fifo count (epiwfifocnt), offset 0x204 ...................................................... 529 register 29: epi interrupt mask (epiim), offset 0x210 ......................................................................... 530 register 30: epi raw interrupt status (epiris), offset 0x214 .............................................................. 531 register 31: epi masked interrupt status (epimis), offset 0x218 ........................................................ 533 register 32: epi error and interrupt status and clear (epieisc), offset 0x21c .................................... 534 general-purpose timers ............................................................................................................. 536 register 1: gptm configuration (gptmcfg), offset 0x000 .............................................................. 553 register 2: gptm timer a mode (gptmtamr), offset 0x004 ........................................................... 554 register 3: gptm timer b mode (gptmtbmr), offset 0x008 ........................................................... 556 register 4: gptm control (gptmctl), offset 0x00c ........................................................................ 558 register 5: gptm interrupt mask (gptmimr), offset 0x018 .............................................................. 561 register 6: gptm raw interrupt status (gptmris), offset 0x01c ..................................................... 563 register 7: gptm masked interrupt status (gptmmis), offset 0x020 ................................................ 566 register 8: gptm interrupt clear (gptmicr), offset 0x024 .............................................................. 569 register 9: gptm timer a interval load (gptmtailr), offset 0x028 ................................................ 571 register 10: gptm timer b interval load (gptmtbilr), offset 0x02c ................................................ 572 register 11: gptm timer a match (gptmtamatchr), offset 0x030 .................................................. 573 register 12: gptm timer b match (gptmtbmatchr), offset 0x034 ................................................. 574 register 13: gptm timer a prescale (gptmtapr), offset 0x038 ....................................................... 575 register 14: gptm timer b prescale (gptmtbpr), offset 0x03c ...................................................... 576 register 15: gptm timera prescale match (gptmtapmr), offset 0x040 ........................................... 577 register 16: gptm timerb prescale match (gptmtbpmr), offset 0x044 ........................................... 578 register 17: gptm timer a (gptmtar), offset 0x048 ....................................................................... 579 register 18: gptm timer b (gptmtbr), offset 0x04c ....................................................................... 580 register 19: gptm timer a value (gptmtav), offset 0x050 ............................................................... 581 register 20: gptm timer b value (gptmtbv), offset 0x054 .............................................................. 582 watchdog timers ......................................................................................................................... 583 register 1: watchdog load (wdtload), offset 0x000 ...................................................................... 587 register 2: watchdog value (wdtvalue), offset 0x004 ................................................................... 588 register 3: watchdog control (wdtctl), offset 0x008 ..................................................................... 589 register 4: watchdog interrupt clear (wdticr), offset 0x00c .......................................................... 591 register 5: watchdog raw interrupt status (wdtris), offset 0x010 .................................................. 592 register 6: watchdog masked interrupt status (wdtmis), offset 0x014 ............................................. 593 register 7: watchdog test (wdttest), offset 0x418 ....................................................................... 594 register 8: watchdog lock (wdtlock), offset 0xc00 ..................................................................... 595 register 9: watchdog peripheral identification 4 (wdtperiphid4), offset 0xfd0 ................................. 596 register 10: watchdog peripheral identification 5 (wdtperiphid5), offset 0xfd4 ................................. 597 register 11: watchdog peripheral identification 6 (wdtperiphid6), offset 0xfd8 ................................. 598 register 12: watchdog peripheral identification 7 (wdtperiphid7), offset 0xfdc ................................ 599 register 13: watchdog peripheral identification 0 (wdtperiphid0), offset 0xfe0 ................................. 600 register 14: watchdog peripheral identification 1 (wdtperiphid1), offset 0xfe4 ................................. 601 25 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 15: watchdog peripheral identification 2 (wdtperiphid2), offset 0xfe8 ................................. 602 register 16: watchdog peripheral identification 3 (wdtperiphid3), offset 0xfec ................................. 603 register 17: watchdog primecell identification 0 (wdtpcellid0), offset 0xff0 .................................... 604 register 18: watchdog primecell identification 1 (wdtpcellid1), offset 0xff4 .................................... 605 register 19: watchdog primecell identification 2 (wdtpcellid2), offset 0xff8 .................................... 606 register 20: watchdog primecell identification 3 (wdtpcellid3 ), offset 0xffc .................................. 607 analog-to-digital converter (adc) ............................................................................................. 608 register 1: adc active sample sequencer (adcactss), offset 0x000 ............................................. 631 register 2: adc raw interrupt status (adcris), offset 0x004 ........................................................... 632 register 3: adc interrupt mask (adcim), offset 0x008 ..................................................................... 634 register 4: adc interrupt status and clear (adcisc), offset 0x00c .................................................. 636 register 5: adc overflow status (adcostat), offset 0x010 ............................................................ 639 register 6: adc event multiplexer select (adcemux), offset 0x014 ................................................. 641 register 7: adc underflow status (adcustat), offset 0x018 ........................................................... 646 register 8: adc sample sequencer priority (adcsspri), offset 0x020 ............................................. 647 register 9: adc sample phase control (adcspc), offset 0x024 ...................................................... 649 register 10: adc processor sample sequence initiate (adcpssi), offset 0x028 ................................. 651 register 11: adc sample averaging control (adcsac), offset 0x030 ................................................. 653 register 12: adc digital comparator interrupt status and clear (adcdcisc), offset 0x034 ................. 654 register 13: adc control (adcctl), offset 0x038 ............................................................................. 656 register 14: adc sample sequence input multiplexer select 0 (adcssmux0), offset 0x040 ............... 657 register 15: adc sample sequence control 0 (adcssctl0), offset 0x044 ........................................ 659 register 16: adc sample sequence result fifo 0 (adcssfifo0), offset 0x048 ................................ 662 register 17: adc sample sequence result fifo 1 (adcssfifo1), offset 0x068 ................................ 662 register 18: adc sample sequence result fifo 2 (adcssfifo2), offset 0x088 ................................ 662 register 19: adc sample sequence result fifo 3 (adcssfifo3), offset 0x0a8 ............................... 662 register 20: adc sample sequence fifo 0 status (adcssfstat0), offset 0x04c ............................. 663 register 21: adc sample sequence fifo 1 status (adcssfstat1), offset 0x06c ............................. 663 register 22: adc sample sequence fifo 2 status (adcssfstat2), offset 0x08c ............................ 663 register 23: adc sample sequence fifo 3 status (adcssfstat3), offset 0x0ac ............................ 663 register 24: adc sample sequence 0 operation (adcssop0), offset 0x050 ...................................... 665 register 25: adc sample sequence 0 digital comparator select (adcssdc0), offset 0x054 .............. 667 register 26: adc sample sequence input multiplexer select 1 (adcssmux1), offset 0x060 ............... 669 register 27: adc sample sequence input multiplexer select 2 (adcssmux2), offset 0x080 ............... 669 register 28: adc sample sequence control 1 (adcssctl1), offset 0x064 ........................................ 670 register 29: adc sample sequence control 2 (adcssctl2), offset 0x084 ........................................ 670 register 30: adc sample sequence 1 operation (adcssop1), offset 0x070 ...................................... 672 register 31: adc sample sequence 2 operation (adcssop2), offset 0x090 ..................................... 672 register 32: adc sample sequence 1 digital comparator select (adcssdc1), offset 0x074 .............. 673 register 33: adc sample sequence 2 digital comparator select (adcssdc2), offset 0x094 .............. 673 register 34: adc sample sequence input multiplexer select 3 (adcssmux3), offset 0x0a0 ............... 675 register 35: adc sample sequence control 3 (adcssctl3), offset 0x0a4 ........................................ 676 register 36: adc sample sequence 3 operation (adcssop3), offset 0x0b0 ..................................... 677 register 37: adc sample sequence 3 digital comparator select (adcssdc3), offset 0x0b4 .............. 678 register 38: adc digital comparator reset initial conditions (adcdcric), offset 0xd00 ..................... 679 register 39: adc digital comparator control 0 (adcdcctl0), offset 0xe00 ....................................... 684 register 40: adc digital comparator control 1 (adcdcctl1), offset 0xe04 ....................................... 684 register 41: adc digital comparator control 2 (adcdcctl2), offset 0xe08 ....................................... 684 july 03, 2014 26 texas instruments-production data table of contents register 42: adc digital comparator control 3 (adcdcctl3), offset 0xe0c ...................................... 684 register 43: adc digital comparator control 4 (adcdcctl4), offset 0xe10 ....................................... 684 register 44: adc digital comparator control 5 (adcdcctl5), offset 0xe14 ....................................... 684 register 45: adc digital comparator control 6 (adcdcctl6), offset 0xe18 ....................................... 684 register 46: adc digital comparator control 7 (adcdcctl7), offset 0xe1c ...................................... 684 register 47: adc digital comparator range 0 (adcdccmp0), offset 0xe40 ....................................... 687 register 48: adc digital comparator range 1 (adcdccmp1), offset 0xe44 ....................................... 687 register 49: adc digital comparator range 2 (adcdccmp2), offset 0xe48 ....................................... 687 register 50: adc digital comparator range 3 (adcdccmp3), offset 0xe4c ...................................... 687 register 51: adc digital comparator range 4 (adcdccmp4), offset 0xe50 ....................................... 687 register 52: adc digital comparator range 5 (adcdccmp5), offset 0xe54 ....................................... 687 register 53: adc digital comparator range 6 (adcdccmp6), offset 0xe58 ....................................... 687 register 54: adc digital comparator range 7 (adcdccmp7), offset 0xe5c ...................................... 687 universal asynchronous receivers/transmitters (uarts) ..................................................... 689 register 1: uart data (uartdr), offset 0x000 ............................................................................... 704 register 2: uart receive status/error clear (uartrsr/uartecr), offset 0x004 ........................... 706 register 3: uart flag (uartfr), offset 0x018 ................................................................................ 709 register 4: uart irda low-power register (uartilpr), offset 0x020 ............................................. 712 register 5: uart integer baud-rate divisor (uartibrd), offset 0x024 ............................................ 713 register 6: uart fractional baud-rate divisor (uartfbrd), offset 0x028 ....................................... 714 register 7: uart line control (uartlcrh), offset 0x02c ............................................................... 715 register 8: uart control (uartctl), offset 0x030 ......................................................................... 717 register 9: uart interrupt fifo level select (uartifls), offset 0x034 ........................................... 721 register 10: uart interrupt mask (uartim), offset 0x038 ................................................................. 723 register 11: uart raw interrupt status (uartris), offset 0x03c ...................................................... 727 register 12: uart masked interrupt status (uartmis), offset 0x040 ................................................. 731 register 13: uart interrupt clear (uarticr), offset 0x044 ............................................................... 735 register 14: uart dma control (uartdmactl), offset 0x048 .......................................................... 737 register 15: uart lin control (uartlctl), offset 0x090 ................................................................. 738 register 16: uart lin snap shot (uartlss), offset 0x094 ............................................................... 739 register 17: uart lin timer (uartltim), offset 0x098 ..................................................................... 740 register 18: uart peripheral identification 4 (uartperiphid4), offset 0xfd0 ..................................... 741 register 19: uart peripheral identification 5 (uartperiphid5), offset 0xfd4 ..................................... 742 register 20: uart peripheral identification 6 (uartperiphid6), offset 0xfd8 ..................................... 743 register 21: uart peripheral identification 7 (uartperiphid7), offset 0xfdc ..................................... 744 register 22: uart peripheral identification 0 (uartperiphid0), offset 0xfe0 ...................................... 745 register 23: uart peripheral identification 1 (uartperiphid1), offset 0xfe4 ...................................... 746 register 24: uart peripheral identification 2 (uartperiphid2), offset 0xfe8 ...................................... 747 register 25: uart peripheral identification 3 (uartperiphid3), offset 0xfec ..................................... 748 register 26: uart primecell identification 0 (uartpcellid0), offset 0xff0 ........................................ 749 register 27: uart primecell identification 1 (uartpcellid1), offset 0xff4 ........................................ 750 register 28: uart primecell identification 2 (uartpcellid2), offset 0xff8 ........................................ 751 register 29: uart primecell identification 3 (uartpcellid3), offset 0xffc ........................................ 752 synchronous serial interface (ssi) ............................................................................................ 753 register 1: ssi control 0 (ssicr0), offset 0x000 .............................................................................. 768 register 2: ssi control 1 (ssicr1), offset 0x004 .............................................................................. 770 register 3: ssi data (ssidr), offset 0x008 ...................................................................................... 772 register 4: ssi status (ssisr), offset 0x00c ................................................................................... 773 27 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 5: ssi clock prescale (ssicpsr), offset 0x010 .................................................................. 775 register 6: ssi interrupt mask (ssiim), offset 0x014 ......................................................................... 776 register 7: ssi raw interrupt status (ssiris), offset 0x018 .............................................................. 777 register 8: ssi masked interrupt status (ssimis), offset 0x01c ........................................................ 779 register 9: ssi interrupt clear (ssiicr), offset 0x020 ....................................................................... 781 register 10: ssi dma control (ssidmactl), offset 0x024 ................................................................. 782 register 11: ssi peripheral identification 4 (ssiperiphid4), offset 0xfd0 ............................................. 783 register 12: ssi peripheral identification 5 (ssiperiphid5), offset 0xfd4 ............................................. 784 register 13: ssi peripheral identification 6 (ssiperiphid6), offset 0xfd8 ............................................. 785 register 14: ssi peripheral identification 7 (ssiperiphid7), offset 0xfdc ............................................ 786 register 15: ssi peripheral identification 0 (ssiperiphid0), offset 0xfe0 ............................................. 787 register 16: ssi peripheral identification 1 (ssiperiphid1), offset 0xfe4 ............................................. 788 register 17: ssi peripheral identification 2 (ssiperiphid2), offset 0xfe8 ............................................. 789 register 18: ssi peripheral identification 3 (ssiperiphid3), offset 0xfec ............................................ 790 register 19: ssi primecell identification 0 (ssipcellid0), offset 0xff0 ............................................... 791 register 20: ssi primecell identification 1 (ssipcellid1), offset 0xff4 ............................................... 792 register 21: ssi primecell identification 2 (ssipcellid2), offset 0xff8 ............................................... 793 register 22: ssi primecell identification 3 (ssipcellid3), offset 0xffc ............................................... 794 inter-integrated circuit (i 2 c) interface ........................................................................................ 795 register 1: i 2 c master slave address (i2cmsa), offset 0x000 ........................................................... 812 register 2: i 2 c master control/status (i2cmcs), offset 0x004 ........................................................... 813 register 3: i 2 c master data (i2cmdr), offset 0x008 ......................................................................... 818 register 4: i 2 c master timer period (i2cmtpr), offset 0x00c ........................................................... 819 register 5: i 2 c master interrupt mask (i2cmimr), offset 0x010 ......................................................... 820 register 6: i 2 c master raw interrupt status (i2cmris), offset 0x014 ................................................. 821 register 7: i 2 c master masked interrupt status (i2cmmis), offset 0x018 ........................................... 822 register 8: i 2 c master interrupt clear (i2cmicr), offset 0x01c ......................................................... 823 register 9: i 2 c master configuration (i2cmcr), offset 0x020 ............................................................ 824 register 10: i 2 c slave own address (i2csoar), offset 0x800 ............................................................ 825 register 11: i 2 c slave control/status (i2cscsr), offset 0x804 ........................................................... 826 register 12: i 2 c slave data (i2csdr), offset 0x808 ........................................................................... 828 register 13: i 2 c slave interrupt mask (i2csimr), offset 0x80c ........................................................... 829 register 14: i 2 c slave raw interrupt status (i2csris), offset 0x810 ................................................... 830 register 15: i 2 c slave masked interrupt status (i2csmis), offset 0x814 .............................................. 831 register 16: i 2 c slave interrupt clear (i2csicr), offset 0x818 ............................................................ 832 inter-integrated circuit sound (i 2 s) interface ............................................................................ 833 register 1: i 2 s transmit fifo data (i2stxfifo), offset 0x000 .......................................................... 846 register 2: i 2 s transmit fifo configuration (i2stxfifocfg), offset 0x004 ...................................... 847 register 3: i 2 s transmit module configuration (i2stxcfg), offset 0x008 .......................................... 848 register 4: i 2 s transmit fifo limit (i2stxlimit), offset 0x00c ........................................................ 850 register 5: i 2 s transmit interrupt status and mask (i2stxism), offset 0x010 ..................................... 851 register 6: i 2 s transmit fifo level (i2stxlev), offset 0x018 .......................................................... 852 register 7: i 2 s receive fifo data (i2srxfifo), offset 0x800 .......................................................... 853 register 8: i 2 s receive fifo configuration (i2srxfifocfg), offset 0x804 ...................................... 854 register 9: i 2 s receive module configuration (i2srxcfg), offset 0x808 ........................................... 855 register 10: i 2 s receive fifo limit (i2srxlimit), offset 0x80c ......................................................... 858 july 03, 2014 28 texas instruments-production data table of contents register 11: i 2 s receive interrupt status and mask (i2srxism), offset 0x810 ..................................... 859 register 12: i 2 s receive fifo level (i2srxlev), offset 0x818 ........................................................... 860 register 13: i 2 s module configuration (i2scfg), offset 0xc00 ............................................................ 861 register 14: i 2 s interrupt mask (i2sim), offset 0xc10 ......................................................................... 863 register 15: i 2 s raw interrupt status (i2sris), offset 0xc14 ............................................................... 865 register 16: i 2 s masked interrupt status (i2smis), offset 0xc18 ......................................................... 867 register 17: i 2 s interrupt clear (i2sic), offset 0xc1c ......................................................................... 869 controller area network (can) module ..................................................................................... 870 register 1: can control (canctl), offset 0x000 ............................................................................. 892 register 2: can status (cansts), offset 0x004 ............................................................................... 894 register 3: can error counter (canerr), offset 0x008 ................................................................... 897 register 4: can bit timing (canbit), offset 0x00c .......................................................................... 898 register 5: can interrupt (canint), offset 0x010 ............................................................................. 899 register 6: can test (cantst), offset 0x014 .................................................................................. 900 register 7: can baud rate prescaler extension (canbrpe), offset 0x018 ....................................... 902 register 8: can if1 command request (canif1crq), offset 0x020 ................................................ 903 register 9: can if2 command request (canif2crq), offset 0x080 ................................................ 903 register 10: can if1 command mask (canif1cmsk), offset 0x024 .................................................. 904 register 11: can if2 command mask (canif2cmsk), offset 0x084 .................................................. 904 register 12: can if1 mask 1 (canif1msk1), offset 0x028 ................................................................ 907 register 13: can if2 mask 1 (canif2msk1), offset 0x088 ................................................................ 907 register 14: can if1 mask 2 (canif1msk2), offset 0x02c ................................................................ 908 register 15: can if2 mask 2 (canif2msk2), offset 0x08c ................................................................ 908 register 16: can if1 arbitration 1 (canif1arb1), offset 0x030 ......................................................... 910 register 17: can if2 arbitration 1 (canif2arb1), offset 0x090 ......................................................... 910 register 18: can if1 arbitration 2 (canif1arb2), offset 0x034 ......................................................... 911 register 19: can if2 arbitration 2 (canif2arb2), offset 0x094 ......................................................... 911 register 20: can if1 message control (canif1mctl), offset 0x038 .................................................. 913 register 21: can if2 message control (canif2mctl), offset 0x098 .................................................. 913 register 22: can if1 data a1 (canif1da1), offset 0x03c ................................................................. 916 register 23: can if1 data a2 (canif1da2), offset 0x040 ................................................................. 916 register 24: can if1 data b1 (canif1db1), offset 0x044 ................................................................. 916 register 25: can if1 data b2 (canif1db2), offset 0x048 ................................................................. 916 register 26: can if2 data a1 (canif2da1), offset 0x09c ................................................................. 916 register 27: can if2 data a2 (canif2da2), offset 0x0a0 ................................................................. 916 register 28: can if2 data b1 (canif2db1), offset 0x0a4 ................................................................. 916 register 29: can if2 data b2 (canif2db2), offset 0x0a8 ................................................................. 916 register 30: can transmission request 1 (cantxrq1), offset 0x100 ................................................ 917 register 31: can transmission request 2 (cantxrq2), offset 0x104 ................................................ 917 register 32: can new data 1 (cannwda1), offset 0x120 ................................................................. 918 register 33: can new data 2 (cannwda2), offset 0x124 ................................................................. 918 register 34: can message 1 interrupt pending (canmsg1int), offset 0x140 ..................................... 919 register 35: can message 2 interrupt pending (canmsg2int), offset 0x144 ..................................... 919 register 36: can message 1 valid (canmsg1val), offset 0x160 ....................................................... 920 register 37: can message 2 valid (canmsg2val), offset 0x164 ....................................................... 920 ethernet controller ...................................................................................................................... 921 register 1: ethernet mac raw interrupt status/acknowledge (macris/maciack), offset 0x000 ....... 934 register 2: ethernet mac interrupt mask (macim), offset 0x004 ....................................................... 937 29 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 3: ethernet mac receive control (macrctl), offset 0x008 ................................................ 939 register 4: ethernet mac transmit control (mactctl), offset 0x00c ............................................... 941 register 5: ethernet mac data (macdata), offset 0x010 ................................................................. 943 register 6: ethernet mac individual address 0 (macia0), offset 0x014 ............................................. 945 register 7: ethernet mac individual address 1 (macia1), offset 0x018 ............................................. 946 register 8: ethernet mac threshold (macthr), offset 0x01c .......................................................... 947 register 9: ethernet mac management control (macmctl), offset 0x020 ........................................ 949 register 10: ethernet mac management divider (macmdv), offset 0x024 .......................................... 950 register 11: ethernet mac management address (macmadd), offset 0x028 ...................................... 951 register 12: ethernet mac management transmit data (macmtxd), offset 0x02c ............................. 952 register 13: ethernet mac management receive data (macmrxd), offset 0x030 .............................. 953 register 14: ethernet mac number of packets (macnp), offset 0x034 ............................................... 954 register 15: ethernet mac transmission request (mactr), offset 0x038 ........................................... 955 register 16: ethernet mac timer support (macts), offset 0x03c ...................................................... 956 universal serial bus (usb) controller ....................................................................................... 957 register 1: usb device functional address (usbfaddr), offset 0x000 ............................................ 985 register 2: usb power (usbpower), offset 0x001 ......................................................................... 986 register 3: usb transmit interrupt status (usbtxis), offset 0x002 ................................................... 989 register 4: usb receive interrupt status (usbrxis), offset 0x004 ................................................... 991 register 5: usb transmit interrupt enable (usbtxie), offset 0x006 .................................................. 993 register 6: usb receive interrupt enable (usbrxie), offset 0x008 .................................................. 995 register 7: usb general interrupt status (usbis), offset 0x00a ........................................................ 997 register 8: usb interrupt enable (usbie), offset 0x00b .................................................................. 1000 register 9: usb frame value (usbframe), offset 0x00c .............................................................. 1003 register 10: usb endpoint index (usbepidx), offset 0x00e ............................................................ 1004 register 11: usb test mode (usbtest), offset 0x00f ..................................................................... 1005 register 12: usb fifo endpoint 0 (usbfifo0), offset 0x020 ........................................................... 1007 register 13: usb fifo endpoint 1 (usbfifo1), offset 0x024 ........................................................... 1007 register 14: usb fifo endpoint 2 (usbfifo2), offset 0x028 ........................................................... 1007 register 15: usb fifo endpoint 3 (usbfifo3), offset 0x02c ........................................................... 1007 register 16: usb fifo endpoint 4 (usbfifo4), offset 0x030 ........................................................... 1007 register 17: usb fifo endpoint 5 (usbfifo5), offset 0x034 ........................................................... 1007 register 18: usb fifo endpoint 6 (usbfifo6), offset 0x038 ........................................................... 1007 register 19: usb fifo endpoint 7 (usbfifo7), offset 0x03c ........................................................... 1007 register 20: usb fifo endpoint 8 (usbfifo8), offset 0x040 ........................................................... 1007 register 21: usb fifo endpoint 9 (usbfifo9), offset 0x044 ........................................................... 1007 register 22: usb fifo endpoint 10 (usbfifo10), offset 0x048 ....................................................... 1007 register 23: usb fifo endpoint 11 (usbfifo11), offset 0x04c ....................................................... 1007 register 24: usb fifo endpoint 12 (usbfifo12), offset 0x050 ....................................................... 1007 register 25: usb fifo endpoint 13 (usbfifo13), offset 0x054 ....................................................... 1007 register 26: usb fifo endpoint 14 (usbfifo14), offset 0x058 ....................................................... 1007 register 27: usb fifo endpoint 15 (usbfifo15), offset 0x05c ....................................................... 1007 register 28: usb device control (usbdevctl), offset 0x060 .......................................................... 1009 register 29: usb transmit dynamic fifo sizing (usbtxfifosz), offset 0x062 ................................ 1011 register 30: usb receive dynamic fifo sizing (usbrxfifosz), offset 0x063 ................................ 1011 register 31: usb transmit fifo start address (usbtxfifoadd), offset 0x064 ................................ 1012 register 32: usb receive fifo start address (usbrxfifoadd), offset 0x066 ................................ 1012 register 33: usb connect timing (usbcontim), offset 0x07a ........................................................ 1013 july 03, 2014 30 texas instruments-production data table of contents register 34: usb otg vbus pulse timing (usbvplen), offset 0x07b ............................................ 1014 register 35: usb full-speed last transaction to end of frame timing (usbfseof), offset 0x07d .... 1015 register 36: usb low-speed last transaction to end of frame timing (usblseof), offset 0x07e .... 1016 register 37: usb transmit functional address endpoint 0 (usbtxfuncaddr0), offset 0x080 ......... 1017 register 38: usb transmit functional address endpoint 1 (usbtxfuncaddr1), offset 0x088 ......... 1017 register 39: usb transmit functional address endpoint 2 (usbtxfuncaddr2), offset 0x090 ......... 1017 register 40: usb transmit functional address endpoint 3 (usbtxfuncaddr3), offset 0x098 ......... 1017 register 41: usb transmit functional address endpoint 4 (usbtxfuncaddr4), offset 0x0a0 ......... 1017 register 42: usb transmit functional address endpoint 5 (usbtxfuncaddr5), offset 0x0a8 ......... 1017 register 43: usb transmit functional address endpoint 6 (usbtxfuncaddr6), offset 0x0b0 ......... 1017 register 44: usb transmit functional address endpoint 7 (usbtxfuncaddr7), offset 0x0b8 ......... 1017 register 45: usb transmit functional address endpoint 8 (usbtxfuncaddr8), offset 0x0c0 ........ 1017 register 46: usb transmit functional address endpoint 9 (usbtxfuncaddr9), offset 0x0c8 ........ 1017 register 47: usb transmit functional address endpoint 10 (usbtxfuncaddr10), offset 0x0d0 ..... 1017 register 48: usb transmit functional address endpoint 11 (usbtxfuncaddr11), offset 0x0d8 ..... 1017 register 49: usb transmit functional address endpoint 12 (usbtxfuncaddr12), offset 0x0e0 ..... 1017 register 50: usb transmit functional address endpoint 13 (usbtxfuncaddr13), offset 0x0e8 ..... 1017 register 51: usb transmit functional address endpoint 14 (usbtxfuncaddr14), offset 0x0f0 ..... 1017 register 52: usb transmit functional address endpoint 15 (usbtxfuncaddr15), offset 0x0f8 ..... 1017 register 53: usb transmit hub address endpoint 0 (usbtxhubaddr0), offset 0x082 ..................... 1019 register 54: usb transmit hub address endpoint 1 (usbtxhubaddr1), offset 0x08a .................... 1019 register 55: usb transmit hub address endpoint 2 (usbtxhubaddr2), offset 0x092 ..................... 1019 register 56: usb transmit hub address endpoint 3 (usbtxhubaddr3), offset 0x09a .................... 1019 register 57: usb transmit hub address endpoint 4 (usbtxhubaddr4), offset 0x0a2 .................... 1019 register 58: usb transmit hub address endpoint 5 (usbtxhubaddr5), offset 0x0aa .................... 1019 register 59: usb transmit hub address endpoint 6 (usbtxhubaddr6), offset 0x0b2 .................... 1019 register 60: usb transmit hub address endpoint 7 (usbtxhubaddr7), offset 0x0ba .................... 1019 register 61: usb transmit hub address endpoint 8 (usbtxhubaddr8), offset 0x0c2 .................... 1019 register 62: usb transmit hub address endpoint 9 (usbtxhubaddr9), offset 0x0ca .................... 1019 register 63: usb transmit hub address endpoint 10 (usbtxhubaddr10), offset 0x0d2 ................ 1019 register 64: usb transmit hub address endpoint 11 (usbtxhubaddr11), offset 0x0da ................ 1019 register 65: usb transmit hub address endpoint 12 (usbtxhubaddr12), offset 0x0e2 ................ 1019 register 66: usb transmit hub address endpoint 13 (usbtxhubaddr13), offset 0x0ea ................ 1019 register 67: usb transmit hub address endpoint 14 (usbtxhubaddr14), offset 0x0f2 ................. 1019 register 68: usb transmit hub address endpoint 15 (usbtxhubaddr15), offset 0x0fa ................ 1019 register 69: usb transmit hub port endpoint 0 (usbtxhubport0), offset 0x083 ........................... 1021 register 70: usb transmit hub port endpoint 1 (usbtxhubport1), offset 0x08b ........................... 1021 register 71: usb transmit hub port endpoint 2 (usbtxhubport2), offset 0x093 ........................... 1021 register 72: usb transmit hub port endpoint 3 (usbtxhubport3), offset 0x09b ........................... 1021 register 73: usb transmit hub port endpoint 4 (usbtxhubport4), offset 0x0a3 ........................... 1021 register 74: usb transmit hub port endpoint 5 (usbtxhubport5), offset 0x0ab .......................... 1021 register 75: usb transmit hub port endpoint 6 (usbtxhubport6), offset 0x0b3 ........................... 1021 register 76: usb transmit hub port endpoint 7 (usbtxhubport7), offset 0x0bb .......................... 1021 register 77: usb transmit hub port endpoint 8 (usbtxhubport8), offset 0x0c3 .......................... 1021 register 78: usb transmit hub port endpoint 9 (usbtxhubport9), offset 0x0cb .......................... 1021 register 79: usb transmit hub port endpoint 10 (usbtxhubport10), offset 0x0d3 ....................... 1021 register 80: usb transmit hub port endpoint 11 (usbtxhubport11), offset 0x0db ....................... 1021 register 81: usb transmit hub port endpoint 12 (usbtxhubport12), offset 0x0e3 ....................... 1021 31 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 82: usb transmit hub port endpoint 13 (usbtxhubport13), offset 0x0eb ...................... 1021 register 83: usb transmit hub port endpoint 14 (usbtxhubport14), offset 0x0f3 ....................... 1021 register 84: usb transmit hub port endpoint 15 (usbtxhubport15), offset 0x0fb ....................... 1021 register 85: usb receive functional address endpoint 1 (usbrxfuncaddr1), offset 0x08c ......... 1023 register 86: usb receive functional address endpoint 2 (usbrxfuncaddr2), offset 0x094 ......... 1023 register 87: usb receive functional address endpoint 3 (usbrxfuncaddr3), offset 0x09c ......... 1023 register 88: usb receive functional address endpoint 4 (usbrxfuncaddr4), offset 0x0a4 ......... 1023 register 89: usb receive functional address endpoint 5 (usbrxfuncaddr5), offset 0x0ac ......... 1023 register 90: usb receive functional address endpoint 6 (usbrxfuncaddr6), offset 0x0b4 ......... 1023 register 91: usb receive functional address endpoint 7 (usbrxfuncaddr7), offset 0x0bc ......... 1023 register 92: usb receive functional address endpoint 8 (usbrxfuncaddr8), offset 0x0c4 ......... 1023 register 93: usb receive functional address endpoint 9 (usbrxfuncaddr9), offset 0x0cc ........ 1023 register 94: usb receive functional address endpoint 10 (usbrxfuncaddr10), offset 0x0d4 ..... 1023 register 95: usb receive functional address endpoint 11 (usbrxfuncaddr11), offset 0x0dc ..... 1023 register 96: usb receive functional address endpoint 12 (usbrxfuncaddr12), offset 0x0e4 ..... 1023 register 97: usb receive functional address endpoint 13 (usbrxfuncaddr13), offset 0x0ec ..... 1023 register 98: usb receive functional address endpoint 14 (usbrxfuncaddr14), offset 0x0f4 ...... 1023 register 99: usb receive functional address endpoint 15 (usbrxfuncaddr15), offset 0x0fc ..... 1023 register 100: usb receive hub address endpoint 1 (usbrxhubaddr1), offset 0x08e ..................... 1025 register 101: usb receive hub address endpoint 2 (usbrxhubaddr2), offset 0x096 ..................... 1025 register 102: usb receive hub address endpoint 3 (usbrxhubaddr3), offset 0x09e ..................... 1025 register 103: usb receive hub address endpoint 4 (usbrxhubaddr4), offset 0x0a6 ..................... 1025 register 104: usb receive hub address endpoint 5 (usbrxhubaddr5), offset 0x0ae .................... 1025 register 105: usb receive hub address endpoint 6 (usbrxhubaddr6), offset 0x0b6 ..................... 1025 register 106: usb receive hub address endpoint 7 (usbrxhubaddr7), offset 0x0be .................... 1025 register 107: usb receive hub address endpoint 8 (usbrxhubaddr8), offset 0x0c6 .................... 1025 register 108: usb receive hub address endpoint 9 (usbrxhubaddr9), offset 0x0ce .................... 1025 register 109: usb receive hub address endpoint 10 (usbrxhubaddr10), offset 0x0d6 ................. 1025 register 110: usb receive hub address endpoint 11 (usbrxhubaddr11), offset 0x0de ................. 1025 register 111: usb receive hub address endpoint 12 (usbrxhubaddr12), offset 0x0e6 ................. 1025 register 112: usb receive hub address endpoint 13 (usbrxhubaddr13), offset 0x0ee ................ 1025 register 113: usb receive hub address endpoint 14 (usbrxhubaddr14), offset 0x0f6 ................. 1025 register 114: usb receive hub address endpoint 15 (usbrxhubaddr15), offset 0x0fe ................. 1025 register 115: usb receive hub port endpoint 1 (usbrxhubport1), offset 0x08f ........................... 1027 register 116: usb receive hub port endpoint 2 (usbrxhubport2), offset 0x097 ........................... 1027 register 117: usb receive hub port endpoint 3 (usbrxhubport3), offset 0x09f ........................... 1027 register 118: usb receive hub port endpoint 4 (usbrxhubport4), offset 0x0a7 ........................... 1027 register 119: usb receive hub port endpoint 5 (usbrxhubport5), offset 0x0af ........................... 1027 register 120: usb receive hub port endpoint 6 (usbrxhubport6), offset 0x0b7 ........................... 1027 register 121: usb receive hub port endpoint 7 (usbrxhubport7), offset 0x0bf ........................... 1027 register 122: usb receive hub port endpoint 8 (usbrxhubport8), offset 0x0c7 ........................... 1027 register 123: usb receive hub port endpoint 9 (usbrxhubport9), offset 0x0cf ........................... 1027 register 124: usb receive hub port endpoint 10 (usbrxhubport10), offset 0x0d7 ....................... 1027 register 125: usb receive hub port endpoint 11 (usbrxhubport11), offset 0x0df ....................... 1027 register 126: usb receive hub port endpoint 12 (usbrxhubport12), offset 0x0e7 ....................... 1027 register 127: usb receive hub port endpoint 13 (usbrxhubport13), offset 0x0ef ....................... 1027 register 128: usb receive hub port endpoint 14 (usbrxhubport14), offset 0x0f7 ....................... 1027 register 129: usb receive hub port endpoint 15 (usbrxhubport15), offset 0x0ff ....................... 1027 july 03, 2014 32 texas instruments-production data table of contents register 130: usb maximum transmit data endpoint 1 (usbtxmaxp1), offset 0x110 ......................... 1029 register 131: usb maximum transmit data endpoint 2 (usbtxmaxp2), offset 0x120 ........................ 1029 register 132: usb maximum transmit data endpoint 3 (usbtxmaxp3), offset 0x130 ........................ 1029 register 133: usb maximum transmit data endpoint 4 (usbtxmaxp4), offset 0x140 ........................ 1029 register 134: usb maximum transmit data endpoint 5 (usbtxmaxp5), offset 0x150 ........................ 1029 register 135: usb maximum transmit data endpoint 6 (usbtxmaxp6), offset 0x160 ........................ 1029 register 136: usb maximum transmit data endpoint 7 (usbtxmaxp7), offset 0x170 ........................ 1029 register 137: usb maximum transmit data endpoint 8 (usbtxmaxp8), offset 0x180 ........................ 1029 register 138: usb maximum transmit data endpoint 9 (usbtxmaxp9), offset 0x190 ........................ 1029 register 139: usb maximum transmit data endpoint 10 (usbtxmaxp10), offset 0x1a0 .................... 1029 register 140: usb maximum transmit data endpoint 11 (usbtxmaxp11), offset 0x1b0 ..................... 1029 register 141: usb maximum transmit data endpoint 12 (usbtxmaxp12), offset 0x1c0 .................... 1029 register 142: usb maximum transmit data endpoint 13 (usbtxmaxp13), offset 0x1d0 .................... 1029 register 143: usb maximum transmit data endpoint 14 (usbtxmaxp14), offset 0x1e0 .................... 1029 register 144: usb maximum transmit data endpoint 15 (usbtxmaxp15), offset 0x1f0 ..................... 1029 register 145: usb control and status endpoint 0 low (usbcsrl0), offset 0x102 ............................... 1031 register 146: usb control and status endpoint 0 high (usbcsrh0), offset 0x103 ............................. 1035 register 147: usb receive byte count endpoint 0 (usbcount0), offset 0x108 ................................. 1037 register 148: usb type endpoint 0 (usbtype0), offset 0x10a .......................................................... 1038 register 149: usb nak limit (usbnaklmt), offset 0x10b ................................................................ 1039 register 150: usb transmit control and status endpoint 1 low (usbtxcsrl1), offset 0x112 ............. 1040 register 151: usb transmit control and status endpoint 2 low (usbtxcsrl2), offset 0x122 ............. 1040 register 152: usb transmit control and status endpoint 3 low (usbtxcsrl3), offset 0x132 ............. 1040 register 153: usb transmit control and status endpoint 4 low (usbtxcsrl4), offset 0x142 ............. 1040 register 154: usb transmit control and status endpoint 5 low (usbtxcsrl5), offset 0x152 ............. 1040 register 155: usb transmit control and status endpoint 6 low (usbtxcsrl6), offset 0x162 ............. 1040 register 156: usb transmit control and status endpoint 7 low (usbtxcsrl7), offset 0x172 ............. 1040 register 157: usb transmit control and status endpoint 8 low (usbtxcsrl8), offset 0x182 ............. 1040 register 158: usb transmit control and status endpoint 9 low (usbtxcsrl9), offset 0x192 ............. 1040 register 159: usb transmit control and status endpoint 10 low (usbtxcsrl10), offset 0x1a2 ......... 1040 register 160: usb transmit control and status endpoint 11 low (usbtxcsrl11), offset 0x1b2 ......... 1040 register 161: usb transmit control and status endpoint 12 low (usbtxcsrl12), offset 0x1c2 ........ 1040 register 162: usb transmit control and status endpoint 13 low (usbtxcsrl13), offset 0x1d2 ........ 1040 register 163: usb transmit control and status endpoint 14 low (usbtxcsrl14), offset 0x1e2 ......... 1040 register 164: usb transmit control and status endpoint 15 low (usbtxcsrl15), offset 0x1f2 ......... 1040 register 165: usb transmit control and status endpoint 1 high (usbtxcsrh1), offset 0x113 ............ 1045 register 166: usb transmit control and status endpoint 2 high (usbtxcsrh2), offset 0x123 ........... 1045 register 167: usb transmit control and status endpoint 3 high (usbtxcsrh3), offset 0x133 ........... 1045 register 168: usb transmit control and status endpoint 4 high (usbtxcsrh4), offset 0x143 ........... 1045 register 169: usb transmit control and status endpoint 5 high (usbtxcsrh5), offset 0x153 ........... 1045 register 170: usb transmit control and status endpoint 6 high (usbtxcsrh6), offset 0x163 ........... 1045 register 171: usb transmit control and status endpoint 7 high (usbtxcsrh7), offset 0x173 ........... 1045 register 172: usb transmit control and status endpoint 8 high (usbtxcsrh8), offset 0x183 ........... 1045 register 173: usb transmit control and status endpoint 9 high (usbtxcsrh9), offset 0x193 ........... 1045 register 174: usb transmit control and status endpoint 10 high (usbtxcsrh10), offset 0x1a3 ....... 1045 register 175: usb transmit control and status endpoint 11 high (usbtxcsrh11), offset 0x1b3 ........ 1045 register 176: usb transmit control and status endpoint 12 high (usbtxcsrh12), offset 0x1c3 ....... 1045 register 177: usb transmit control and status endpoint 13 high (usbtxcsrh13), offset 0x1d3 ....... 1045 33 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 178: usb transmit control and status endpoint 14 high (usbtxcsrh14), offset 0x1e3 ....... 1045 register 179: usb transmit control and status endpoint 15 high (usbtxcsrh15), offset 0x1f3 ........ 1045 register 180: usb maximum receive data endpoint 1 (usbrxmaxp1), offset 0x114 ......................... 1049 register 181: usb maximum receive data endpoint 2 (usbrxmaxp2), offset 0x124 ......................... 1049 register 182: usb maximum receive data endpoint 3 (usbrxmaxp3), offset 0x134 ......................... 1049 register 183: usb maximum receive data endpoint 4 (usbrxmaxp4), offset 0x144 ......................... 1049 register 184: usb maximum receive data endpoint 5 (usbrxmaxp5), offset 0x154 ......................... 1049 register 185: usb maximum receive data endpoint 6 (usbrxmaxp6), offset 0x164 ......................... 1049 register 186: usb maximum receive data endpoint 7 (usbrxmaxp7), offset 0x174 ......................... 1049 register 187: usb maximum receive data endpoint 8 (usbrxmaxp8), offset 0x184 ......................... 1049 register 188: usb maximum receive data endpoint 9 (usbrxmaxp9), offset 0x194 ......................... 1049 register 189: usb maximum receive data endpoint 10 (usbrxmaxp10), offset 0x1a4 ..................... 1049 register 190: usb maximum receive data endpoint 11 (usbrxmaxp11), offset 0x1b4 ..................... 1049 register 191: usb maximum receive data endpoint 12 (usbrxmaxp12), offset 0x1c4 ..................... 1049 register 192: usb maximum receive data endpoint 13 (usbrxmaxp13), offset 0x1d4 ..................... 1049 register 193: usb maximum receive data endpoint 14 (usbrxmaxp14), offset 0x1e4 ..................... 1049 register 194: usb maximum receive data endpoint 15 (usbrxmaxp15), offset 0x1f4 ..................... 1049 register 195: usb receive control and status endpoint 1 low (usbrxcsrl1), offset 0x116 ............. 1051 register 196: usb receive control and status endpoint 2 low (usbrxcsrl2), offset 0x126 ............. 1051 register 197: usb receive control and status endpoint 3 low (usbrxcsrl3), offset 0x136 ............. 1051 register 198: usb receive control and status endpoint 4 low (usbrxcsrl4), offset 0x146 ............. 1051 register 199: usb receive control and status endpoint 5 low (usbrxcsrl5), offset 0x156 ............. 1051 register 200: usb receive control and status endpoint 6 low (usbrxcsrl6), offset 0x166 ............. 1051 register 201: usb receive control and status endpoint 7 low (usbrxcsrl7), offset 0x176 ............. 1051 register 202: usb receive control and status endpoint 8 low (usbrxcsrl8), offset 0x186 ............. 1051 register 203: usb receive control and status endpoint 9 low (usbrxcsrl9), offset 0x196 ............. 1051 register 204: usb receive control and status endpoint 10 low (usbrxcsrl10), offset 0x1a6 ......... 1051 register 205: usb receive control and status endpoint 11 low (usbrxcsrl11), offset 0x1b6 .......... 1051 register 206: usb receive control and status endpoint 12 low (usbrxcsrl12), offset 0x1c6 ......... 1051 register 207: usb receive control and status endpoint 13 low (usbrxcsrl13), offset 0x1d6 ......... 1051 register 208: usb receive control and status endpoint 14 low (usbrxcsrl14), offset 0x1e6 ......... 1051 register 209: usb receive control and status endpoint 15 low (usbrxcsrl15), offset 0x1f6 ......... 1051 register 210: usb receive control and status endpoint 1 high (usbrxcsrh1), offset 0x117 ............ 1056 register 211: usb receive control and status endpoint 2 high (usbrxcsrh2), offset 0x127 ............ 1056 register 212: usb receive control and status endpoint 3 high (usbrxcsrh3), offset 0x137 ............ 1056 register 213: usb receive control and status endpoint 4 high (usbrxcsrh4), offset 0x147 ............ 1056 register 214: usb receive control and status endpoint 5 high (usbrxcsrh5), offset 0x157 ............ 1056 register 215: usb receive control and status endpoint 6 high (usbrxcsrh6), offset 0x167 ............ 1056 register 216: usb receive control and status endpoint 7 high (usbrxcsrh7), offset 0x177 ............ 1056 register 217: usb receive control and status endpoint 8 high (usbrxcsrh8), offset 0x187 ............ 1056 register 218: usb receive control and status endpoint 9 high (usbrxcsrh9), offset 0x197 ............ 1056 register 219: usb receive control and status endpoint 10 high (usbrxcsrh10), offset 0x1a7 ........ 1056 register 220: usb receive control and status endpoint 11 high (usbrxcsrh11), offset 0x1b7 ........ 1056 register 221: usb receive control and status endpoint 12 high (usbrxcsrh12), offset 0x1c7 ........ 1056 register 222: usb receive control and status endpoint 13 high (usbrxcsrh13), offset 0x1d7 ........ 1056 register 223: usb receive control and status endpoint 14 high (usbrxcsrh14), offset 0x1e7 ........ 1056 register 224: usb receive control and status endpoint 15 high (usbrxcsrh15), offset 0x1f7 ........ 1056 register 225: usb receive byte count endpoint 1 (usbrxcount1), offset 0x118 ............................. 1061 july 03, 2014 34 texas instruments-production data table of contents register 226: usb receive byte count endpoint 2 (usbrxcount2), offset 0x128 ............................ 1061 register 227: usb receive byte count endpoint 3 (usbrxcount3), offset 0x138 ............................ 1061 register 228: usb receive byte count endpoint 4 (usbrxcount4), offset 0x148 ............................ 1061 register 229: usb receive byte count endpoint 5 (usbrxcount5), offset 0x158 ............................ 1061 register 230: usb receive byte count endpoint 6 (usbrxcount6), offset 0x168 ............................ 1061 register 231: usb receive byte count endpoint 7 (usbrxcount7), offset 0x178 ............................ 1061 register 232: usb receive byte count endpoint 8 (usbrxcount8), offset 0x188 ............................ 1061 register 233: usb receive byte count endpoint 9 (usbrxcount9), offset 0x198 ............................ 1061 register 234: usb receive byte count endpoint 10 (usbrxcount10), offset 0x1a8 ........................ 1061 register 235: usb receive byte count endpoint 11 (usbrxcount11), offset 0x1b8 ......................... 1061 register 236: usb receive byte count endpoint 12 (usbrxcount12), offset 0x1c8 ........................ 1061 register 237: usb receive byte count endpoint 13 (usbrxcount13), offset 0x1d8 ........................ 1061 register 238: usb receive byte count endpoint 14 (usbrxcount14), offset 0x1e8 ........................ 1061 register 239: usb receive byte count endpoint 15 (usbrxcount15), offset 0x1f8 ........................ 1061 register 240: usb host transmit configure type endpoint 1 (usbtxtype1), offset 0x11a ................. 1063 register 241: usb host transmit configure type endpoint 2 (usbtxtype2), offset 0x12a ................. 1063 register 242: usb host transmit configure type endpoint 3 (usbtxtype3), offset 0x13a ................. 1063 register 243: usb host transmit configure type endpoint 4 (usbtxtype4), offset 0x14a ................. 1063 register 244: usb host transmit configure type endpoint 5 (usbtxtype5), offset 0x15a ................. 1063 register 245: usb host transmit configure type endpoint 6 (usbtxtype6), offset 0x16a ................. 1063 register 246: usb host transmit configure type endpoint 7 (usbtxtype7), offset 0x17a ................. 1063 register 247: usb host transmit configure type endpoint 8 (usbtxtype8), offset 0x18a ................. 1063 register 248: usb host transmit configure type endpoint 9 (usbtxtype9), offset 0x19a ................. 1063 register 249: usb host transmit configure type endpoint 10 (usbtxtype10), offset 0x1aa ............. 1063 register 250: usb host transmit configure type endpoint 11 (usbtxtype11), offset 0x1ba ............. 1063 register 251: usb host transmit configure type endpoint 12 (usbtxtype12), offset 0x1ca ............. 1063 register 252: usb host transmit configure type endpoint 13 (usbtxtype13), offset 0x1da ............. 1063 register 253: usb host transmit configure type endpoint 14 (usbtxtype14), offset 0x1ea ............. 1063 register 254: usb host transmit configure type endpoint 15 (usbtxtype15), offset 0x1fa ............. 1063 register 255: usb host transmit interval endpoint 1 (usbtxinterval1), offset 0x11b ..................... 1065 register 256: usb host transmit interval endpoint 2 (usbtxinterval2), offset 0x12b ..................... 1065 register 257: usb host transmit interval endpoint 3 (usbtxinterval3), offset 0x13b ..................... 1065 register 258: usb host transmit interval endpoint 4 (usbtxinterval4), offset 0x14b ..................... 1065 register 259: usb host transmit interval endpoint 5 (usbtxinterval5), offset 0x15b ..................... 1065 register 260: usb host transmit interval endpoint 6 (usbtxinterval6), offset 0x16b ..................... 1065 register 261: usb host transmit interval endpoint 7 (usbtxinterval7), offset 0x17b ..................... 1065 register 262: usb host transmit interval endpoint 8 (usbtxinterval8), offset 0x18b ..................... 1065 register 263: usb host transmit interval endpoint 9 (usbtxinterval9), offset 0x19b ..................... 1065 register 264: usb host transmit interval endpoint 10 (usbtxinterval10), offset 0x1ab ................. 1065 register 265: usb host transmit interval endpoint 11 (usbtxinterval11), offset 0x1bb .................. 1065 register 266: usb host transmit interval endpoint 12 (usbtxinterval12), offset 0x1cb ................. 1065 register 267: usb host transmit interval endpoint 13 (usbtxinterval13), offset 0x1db ................. 1065 register 268: usb host transmit interval endpoint 14 (usbtxinterval14), offset 0x1eb ................. 1065 register 269: usb host transmit interval endpoint 15 (usbtxinterval15), offset 0x1fb ................. 1065 register 270: usb host configure receive type endpoint 1 (usbrxtype1), offset 0x11c ................. 1067 register 271: usb host configure receive type endpoint 2 (usbrxtype2), offset 0x12c ................. 1067 register 272: usb host configure receive type endpoint 3 (usbrxtype3), offset 0x13c ................. 1067 register 273: usb host configure receive type endpoint 4 (usbrxtype4), offset 0x14c ................. 1067 35 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 274: usb host configure receive type endpoint 5 (usbrxtype5), offset 0x15c ................. 1067 register 275: usb host configure receive type endpoint 6 (usbrxtype6), offset 0x16c ................. 1067 register 276: usb host configure receive type endpoint 7 (usbrxtype7), offset 0x17c ................. 1067 register 277: usb host configure receive type endpoint 8 (usbrxtype8), offset 0x18c ................. 1067 register 278: usb host configure receive type endpoint 9 (usbrxtype9), offset 0x19c ................. 1067 register 279: usb host configure receive type endpoint 10 (usbrxtype10), offset 0x1ac ............. 1067 register 280: usb host configure receive type endpoint 11 (usbrxtype11), offset 0x1bc ............. 1067 register 281: usb host configure receive type endpoint 12 (usbrxtype12), offset 0x1cc ............. 1067 register 282: usb host configure receive type endpoint 13 (usbrxtype13), offset 0x1dc ............. 1067 register 283: usb host configure receive type endpoint 14 (usbrxtype14), offset 0x1ec ............. 1067 register 284: usb host configure receive type endpoint 15 (usbrxtype15), offset 0x1fc ............. 1067 register 285: usb host receive polling interval endpoint 1 (usbrxinterval1), offset 0x11d ........... 1069 register 286: usb host receive polling interval endpoint 2 (usbrxinterval2), offset 0x12d ........... 1069 register 287: usb host receive polling interval endpoint 3 (usbrxinterval3), offset 0x13d ........... 1069 register 288: usb host receive polling interval endpoint 4 (usbrxinterval4), offset 0x14d ........... 1069 register 289: usb host receive polling interval endpoint 5 (usbrxinterval5), offset 0x15d ........... 1069 register 290: usb host receive polling interval endpoint 6 (usbrxinterval6), offset 0x16d ........... 1069 register 291: usb host receive polling interval endpoint 7 (usbrxinterval7), offset 0x17d ........... 1069 register 292: usb host receive polling interval endpoint 8 (usbrxinterval8), offset 0x18d ........... 1069 register 293: usb host receive polling interval endpoint 9 (usbrxinterval9), offset 0x19d ........... 1069 register 294: usb host receive polling interval endpoint 10 (usbrxinterval10), offset 0x1ad ...... 1069 register 295: usb host receive polling interval endpoint 11 (usbrxinterval11), offset 0x1bd ....... 1069 register 296: usb host receive polling interval endpoint 12 (usbrxinterval12), offset 0x1cd ...... 1069 register 297: usb host receive polling interval endpoint 13 (usbrxinterval13), offset 0x1dd ...... 1069 register 298: usb host receive polling interval endpoint 14 (usbrxinterval14), offset 0x1ed ...... 1069 register 299: usb host receive polling interval endpoint 15 (usbrxinterval15), offset 0x1fd ....... 1069 register 300: usb request packet count in block transfer endpoint 1 (usbrqpktcount1), offset 0x304 .......................................................................................................................... 1071 register 301: usb request packet count in block transfer endpoint 2 (usbrqpktcount2), offset 0x308 .......................................................................................................................... 1071 register 302: usb request packet count in block transfer endpoint 3 (usbrqpktcount3), offset 0x30c ......................................................................................................................... 1071 register 303: usb request packet count in block transfer endpoint 4 (usbrqpktcount4), offset 0x310 .......................................................................................................................... 1071 register 304: usb request packet count in block transfer endpoint 5 (usbrqpktcount5), offset 0x314 .......................................................................................................................... 1071 register 305: usb request packet count in block transfer endpoint 6 (usbrqpktcount6), offset 0x318 .......................................................................................................................... 1071 register 306: usb request packet count in block transfer endpoint 7 (usbrqpktcount7), offset 0x31c ......................................................................................................................... 1071 register 307: usb request packet count in block transfer endpoint 8 (usbrqpktcount8), offset 0x320 .......................................................................................................................... 1071 register 308: usb request packet count in block transfer endpoint 9 (usbrqpktcount9), offset 0x324 .......................................................................................................................... 1071 register 309: usb request packet count in block transfer endpoint 10 (usbrqpktcount10), offset 0x328 .......................................................................................................................... 1071 register 310: usb request packet count in block transfer endpoint 11 (usbrqpktcount11), offset 0x32c ......................................................................................................................... 1071 july 03, 2014 36 texas instruments-production data table of contents register 311: usb request packet count in block transfer endpoint 12 (usbrqpktcount12), offset 0x330 .......................................................................................................................... 1071 register 312: usb request packet count in block transfer endpoint 13 (usbrqpktcount13), offset 0x334 .......................................................................................................................... 1071 register 313: usb request packet count in block transfer endpoint 14 (usbrqpktcount14), offset 0x338 .......................................................................................................................... 1071 register 314: usb request packet count in block transfer endpoint 15 (usbrqpktcount15), offset 0x33c ......................................................................................................................... 1071 register 315: usb receive double packet buffer disable (usbrxdpktbufdis), offset 0x340 ........... 1073 register 316: usb transmit double packet buffer disable (usbtxdpktbufdis), offset 0x342 .......... 1075 register 317: usb external power control (usbepc), offset 0x400 .................................................... 1077 register 318: usb external power control raw interrupt status (usbepcris), offset 0x404 ............... 1080 register 319: usb external power control interrupt mask (usbepcim), offset 0x408 .......................... 1081 register 320: usb external power control interrupt status and clear (usbepcisc), offset 0x40c ....... 1082 register 321: usb device resume raw interrupt status (usbdrris), offset 0x410 .......................... 1083 register 322: usb device resume interrupt mask (usbdrim), offset 0x414 ..................................... 1084 register 323: usb device resume interrupt status and clear (usbdrisc), offset 0x418 .................. 1085 register 324: usb general-purpose control and status (usbgpcs), offset 0x41c ............................. 1086 register 325: usb vbus droop control (usbvdc), offset 0x430 ....................................................... 1087 register 326: usb vbus droop control raw interrupt status (usbvdcris), offset 0x434 .................. 1088 register 327: usb vbus droop control interrupt mask (usbvdcim), offset 0x438 ............................. 1089 register 328: usb vbus droop control interrupt status and clear (usbvdcisc), offset 0x43c .......... 1090 register 329: usb id valid detect raw interrupt status (usbidvris), offset 0x444 ............................. 1091 register 330: usb id valid detect interrupt mask (usbidvim), offset 0x448 ........................................ 1092 register 331: usb id valid detect interrupt status and clear (usbidvisc), offset 0x44c .................... 1093 register 332: usb dma select (usbdmasel), offset 0x450 .............................................................. 1094 analog comparators ................................................................................................................. 1096 register 1: analog comparator masked interrupt status (acmis), offset 0x000 ................................ 1103 register 2: analog comparator raw interrupt status (acris), offset 0x004 ..................................... 1104 register 3: analog comparator interrupt enable (acinten), offset 0x008 ....................................... 1105 register 4: analog comparator reference voltage control (acrefctl), offset 0x010 ..................... 1106 register 5: analog comparator status 0 (acstat0), offset 0x020 ................................................... 1107 register 6: analog comparator status 1 (acstat1), offset 0x040 ................................................... 1107 register 7: analog comparator status 2 (acstat2), offset 0x060 ................................................... 1107 register 8: analog comparator control 0 (acctl0), offset 0x024 ................................................... 1108 register 9: analog comparator control 1 (acctl1), offset 0x044 ................................................... 1108 register 10: analog comparator control 2 (acctl2), offset 0x064 ................................................... 1108 pulse width modulator (pwm) .................................................................................................. 1110 register 1: pwm master control (pwmctl), offset 0x000 .............................................................. 1126 register 2: pwm time base sync (pwmsync), offset 0x004 ......................................................... 1128 register 3: pwm output enable (pwmenable), offset 0x008 ........................................................ 1129 register 4: pwm output inversion (pwminvert), offset 0x00c ..................................................... 1131 register 5: pwm output fault (pwmfault), offset 0x010 .............................................................. 1133 register 6: pwm interrupt enable (pwminten), offset 0x014 ......................................................... 1135 register 7: pwm raw interrupt status (pwmris), offset 0x018 ...................................................... 1137 register 8: pwm interrupt status and clear (pwmisc), offset 0x01c .............................................. 1140 register 9: pwm status (pwmstatus), offset 0x020 .................................................................... 1143 register 10: pwm fault condition value (pwmfaultval), offset 0x024 ........................................... 1145 37 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 11: pwm enable update (pwmenupd), offset 0x028 ......................................................... 1147 register 12: pwm0 control (pwm0ctl), offset 0x040 ...................................................................... 1151 register 13: pwm1 control (pwm1ctl), offset 0x080 ...................................................................... 1151 register 14: pwm2 control (pwm2ctl), offset 0x0c0 ..................................................................... 1151 register 15: pwm3 control (pwm3ctl), offset 0x100 ...................................................................... 1151 register 16: pwm0 interrupt and trigger enable (pwm0inten), offset 0x044 ................................... 1156 register 17: pwm1 interrupt and trigger enable (pwm1inten), offset 0x084 ................................... 1156 register 18: pwm2 interrupt and trigger enable (pwm2inten), offset 0x0c4 ................................... 1156 register 19: pwm3 interrupt and trigger enable (pwm3inten), offset 0x104 ................................... 1156 register 20: pwm0 raw interrupt status (pwm0ris), offset 0x048 ................................................... 1159 register 21: pwm1 raw interrupt status (pwm1ris), offset 0x088 ................................................... 1159 register 22: pwm2 raw interrupt status (pwm2ris), offset 0x0c8 .................................................. 1159 register 23: pwm3 raw interrupt status (pwm3ris), offset 0x108 ................................................... 1159 register 24: pwm0 interrupt status and clear (pwm0isc), offset 0x04c .......................................... 1161 register 25: pwm1 interrupt status and clear (pwm1isc), offset 0x08c .......................................... 1161 register 26: pwm2 interrupt status and clear (pwm2isc), offset 0x0cc .......................................... 1161 register 27: pwm3 interrupt status and clear (pwm3isc), offset 0x10c .......................................... 1161 register 28: pwm0 load (pwm0load), offset 0x050 ...................................................................... 1163 register 29: pwm1 load (pwm1load), offset 0x090 ...................................................................... 1163 register 30: pwm2 load (pwm2load), offset 0x0d0 ...................................................................... 1163 register 31: pwm3 load (pwm3load), offset 0x110 ...................................................................... 1163 register 32: pwm0 counter (pwm0count), offset 0x054 ............................................................... 1164 register 33: pwm1 counter (pwm1count), offset 0x094 ............................................................... 1164 register 34: pwm2 counter (pwm2count), offset 0x0d4 .............................................................. 1164 register 35: pwm3 counter (pwm3count), offset 0x114 ............................................................... 1164 register 36: pwm0 compare a (pwm0cmpa), offset 0x058 ............................................................ 1165 register 37: pwm1 compare a (pwm1cmpa), offset 0x098 ............................................................ 1165 register 38: pwm2 compare a (pwm2cmpa), offset 0x0d8 ............................................................ 1165 register 39: pwm3 compare a (pwm3cmpa), offset 0x118 ............................................................. 1165 register 40: pwm0 compare b (pwm0cmpb), offset 0x05c ............................................................ 1166 register 41: pwm1 compare b (pwm1cmpb), offset 0x09c ............................................................ 1166 register 42: pwm2 compare b (pwm2cmpb), offset 0x0dc ........................................................... 1166 register 43: pwm3 compare b (pwm3cmpb), offset 0x11c ............................................................ 1166 register 44: pwm0 generator a control (pwm0gena), offset 0x060 ............................................... 1167 register 45: pwm1 generator a control (pwm1gena), offset 0x0a0 ............................................... 1167 register 46: pwm2 generator a control (pwm2gena), offset 0x0e0 ............................................... 1167 register 47: pwm3 generator a control (pwm3gena), offset 0x120 ............................................... 1167 register 48: pwm0 generator b control (pwm0genb), offset 0x064 ............................................... 1170 register 49: pwm1 generator b control (pwm1genb), offset 0x0a4 ............................................... 1170 register 50: pwm2 generator b control (pwm2genb), offset 0x0e4 ............................................... 1170 register 51: pwm3 generator b control (pwm3genb), offset 0x124 ............................................... 1170 register 52: pwm0 dead-band control (pwm0dbctl), offset 0x068 ............................................... 1173 register 53: pwm1 dead-band control (pwm1dbctl), offset 0x0a8 ............................................... 1173 register 54: pwm2 dead-band control (pwm2dbctl), offset 0x0e8 ............................................... 1173 register 55: pwm3 dead-band control (pwm3dbctl), offset 0x128 ............................................... 1173 register 56: pwm0 dead-band rising-edge delay (pwm0dbrise), offset 0x06c ............................ 1174 register 57: pwm1 dead-band rising-edge delay (pwm1dbrise), offset 0x0ac ............................ 1174 register 58: pwm2 dead-band rising-edge delay (pwm2dbrise), offset 0x0ec ............................ 1174 july 03, 2014 38 texas instruments-production data table of contents register 59: pwm3 dead-band rising-edge delay (pwm3dbrise), offset 0x12c ............................ 1174 register 60: pwm0 dead-band falling-edge-delay (pwm0dbfall), offset 0x070 ............................ 1175 register 61: pwm1 dead-band falling-edge-delay (pwm1dbfall), offset 0x0b0 ............................ 1175 register 62: pwm2 dead-band falling-edge-delay (pwm2dbfall), offset 0x0f0 ............................ 1175 register 63: pwm3 dead-band falling-edge-delay (pwm3dbfall), offset 0x130 ............................ 1175 register 64: pwm0 fault source 0 (pwm0fltsrc0), offset 0x074 .................................................. 1176 register 65: pwm1 fault source 0 (pwm1fltsrc0), offset 0x0b4 .................................................. 1176 register 66: pwm2 fault source 0 (pwm2fltsrc0), offset 0x0f4 .................................................. 1176 register 67: pwm3 fault source 0 (pwm3fltsrc0), offset 0x134 .................................................. 1176 register 68: pwm0 fault source 1 (pwm0fltsrc1), offset 0x078 .................................................. 1178 register 69: pwm1 fault source 1 (pwm1fltsrc1), offset 0x0b8 .................................................. 1178 register 70: pwm2 fault source 1 (pwm2fltsrc1), offset 0x0f8 .................................................. 1178 register 71: pwm3 fault source 1 (pwm3fltsrc1), offset 0x138 .................................................. 1178 register 72: pwm0 minimum fault period (pwm0minfltper), offset 0x07c ................................... 1181 register 73: pwm1 minimum fault period (pwm1minfltper), offset 0x0bc ................................... 1181 register 74: pwm2 minimum fault period (pwm2minfltper), offset 0x0fc ................................... 1181 register 75: pwm3 minimum fault period (pwm3minfltper), offset 0x13c ................................... 1181 register 76: pwm0 fault pin logic sense (pwm0fltsen), offset 0x800 .......................................... 1182 register 77: pwm1 fault pin logic sense (pwm1fltsen), offset 0x880 .......................................... 1182 register 78: pwm2 fault pin logic sense (pwm2fltsen), offset 0x900 .......................................... 1182 register 79: pwm3 fault pin logic sense (pwm3fltsen), offset 0x980 .......................................... 1182 register 80: pwm0 fault status 0 (pwm0fltstat0), offset 0x804 ................................................... 1183 register 81: pwm1 fault status 0 (pwm1fltstat0), offset 0x884 ................................................... 1183 register 82: pwm2 fault status 0 (pwm2fltstat0), offset 0x904 ................................................... 1183 register 83: pwm3 fault status 0 (pwm3fltstat0), offset 0x984 ................................................... 1183 register 84: pwm0 fault status 1 (pwm0fltstat1), offset 0x808 ................................................... 1185 register 85: pwm1 fault status 1 (pwm1fltstat1), offset 0x888 ................................................... 1185 register 86: pwm2 fault status 1 (pwm2fltstat1), offset 0x908 ................................................... 1185 register 87: pwm3 fault status 1 (pwm3fltstat1), offset 0x988 ................................................... 1185 quadrature encoder interface (qei) ........................................................................................ 1188 register 1: qei control (qeictl), offset 0x000 .............................................................................. 1195 register 2: qei status (qeistat), offset 0x004 .............................................................................. 1198 register 3: qei position (qeipos), offset 0x008 ............................................................................ 1199 register 4: qei maximum position (qeimaxpos), offset 0x00c ..................................................... 1200 register 5: qei timer load (qeiload), offset 0x010 ..................................................................... 1201 register 6: qei timer (qeitime), offset 0x014 ............................................................................... 1202 register 7: qei velocity counter (qeicount), offset 0x018 ........................................................... 1203 register 8: qei velocity (qeispeed), offset 0x01c ........................................................................ 1204 register 9: qei interrupt enable (qeiinten), offset 0x020 ............................................................. 1205 register 10: qei raw interrupt status (qeiris), offset 0x024 ........................................................... 1207 register 11: qei interrupt status and clear (qeiisc), offset 0x028 ................................................... 1209 39 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller revision history the revision history table notes changes made between the indicated revisions of the lm3s9gn5 data sheet. table 1. revision history description revision date in jtag chapter, clarified jtag-to-swd switching and swd-to-jtag switching. in system control chapter, clarified behavior of reset cause (resc) register external reset bit. in internal memory chapter, noted that the boot configuration (bootcfg) register requires a por before committed changes to the flash-resident registers take effect. in gpio chapter, corrected values for gpiopctl in the table gpio pins with non-zero reset values. in uart chapter, clarified that the transmit interrupt is based on a transition through level. in ethernet chapter, corrected register type of ethernet phy management register 29 C interrupt status (mr29) to rc. in ordering and contact information appendix, moved orderable part numbers table to addendum. additional minor data sheet clarifications and corrections. 15852.2743 july 2014 marked lm3s9gn5 device as not recommended for new designs (nrnd). device is in production to support existing customers, but ti does not recommend using this part in a new design. in the udma chapter, in the "dma channel assignments" and "request type support" tables, corrected to show udma support for burst requests from the general-purpose timer, not single requests. in the watchdog timers chapter, added information on servicing the watchdog timer to the initialization and configuration section. in the general-purpose timers chapter, added note to the gptmtnv registers that in 16-bit mode, only the lower 16-bits of the register can be written with a new value. writes to the prescaler bits have no effect. corrected reset for the uart raw interrupt status (uartris) register. in the usb chapter, clarified that the usb phy has internal termination resistors, and thus there is no need for external resistors. in the electrical characteristics chapter, added clarifying footnote to the gpio module characteristics table. additional minor data sheet clarifications and corrections. 13440.2549 october 2012 11425 january 2012 in system control chapter: C clarified that an external ldo cannot be used. C clarified system clock requirements when the adc module is in operation. C added important note to write the rcc register before the rcc2 register. in internal memory chapter, clarified programming and use of the non-volatile registers. in gpio chapter, corrected "gpio pins with non-zero reset values" table and added note that if the same signal is assigned to two different gpio port pins, the signal is assigned to the port with the lowest letter. july 03, 2014 40 texas instruments-production data revision history table 1. revision history (continued) description revision date in epi chapter: C clarified table "capabilities of host bus 8 and host bus 16 modes". C corrected bit and register resets for freq (frequency range) in epi sdram configuration (episdramcfg) register. C corrected bit and register resets for maxwait (maximum wait) in epi host-bus 8 configuration (epihb8cfg) and epi host-bus 16 configuration (epihb16cfg) registers. also clarified bit descriptions in these registers. C corrected bit definitions for the epsz and ersz bits in the epi address map (epiaddrmap) register. C corrected size of count bit field in epi read fifo count (epirfifocnt) register. in timer chapter, clarified timer modes and interrupts. in adc chapter, added "adc input equivalency diagram". in uart chapter, clarified interrupt behavior. in ssi chapter, corrected ssiclk in the figure "synchronous serial frame format (single transfer)" and clarified behavior of transmit bits in interrupt registers. in i 2 c chapter, corrected bit and register reset values for idle bit in i 2 c master control/status (i2cmcs) register. in usb chapter: C clarified that when the usb module is in operation, mosc must be provided with a clock source, and the system clock must be at least 30 mhz. C removed multtran bit from usb transmit hub address endpoint n (usbtxhubaddrn) and usb receive hub address endpoint n (usbrxhubaddrn) registers. C corrected description for the usb device resume interrupt mask (usbdrim) register. in analog comparators chapter, clarified internal reference programming. in pwm chapter, clarified pwm interrupt enable (pwminten) register description. in signal tables chapter, clarified vddc and ldo pin descriptions. in electrical characteristics chapter: C in maximum ratings table, deleted parameter "input voltage for a gpio configured as an analog input". C in recommended dc operating conditions table, corrected values for i oh parameter. C in jtag characteristics, table, corrected values for parameters "tck clock low time" and "tck clock high time". C in ldo regulator characteristics table, added clarifying footnote to c ldo parameter. C in system clock characteristics with adc operation table, added clarifying footnote to f sysadc parameter. C added "system clock characteristics with usb operation" table. C in sleep modes ac characteristics table, split parameter "time to wake from interrupt" into sleep mode and deep-sleep mode parameters. 41 july 03, 2014 texas instruments-production data stellaris lm3s9gn5 microcontroller table 1. revision history (continued) description revision date C in ssi characteristics table, corrected value for parameter "ssiclk cycle time". C in analog comparator characteristics table, added parameter "input voltage range" and corrected values for parameter "input common mode voltage range". C in analog comparator voltage reference characteristics table, corrected values for absolute accuracy parameters. C deleted table "usb controller dc characteristics". C in nominal power consumption table, added parameter for sleep mode. C in maximum current consumption section, changed reference value for mosc and temperature in tables that follow. C deleted table "external vddc source current specifications". additional minor data sheet clarifications and corrections. corrected "reset sources" table. added important note that rcc register must be written before rcc2 register. added a note that all gpio signals are 5-v tolerant when configured as inputs except for pb0 and pb1 , which are limited to 3.6 v. corrected lin mode bit names in uart interrupt clear (uarticr) register. corrected pin number for rst in table "connections for unused signals" (other pin tables were correct). in the "operating characteristics" chapter: C in the "thermal characteristics" table, the thermal resistance value was changed. C in the "esd absolute maximum ratings" table, the v esdcdm parameter was changed and the v esdmm parameter was deleted. the "electrical characteristics" chapter was reorganized by module. in addition, some of the recommended dc operating conditions, ldo regulator, clock, gpio, epi, adc, and ssi characteristics were finalized. additional minor data sheet clarifications and corrections. 9970 july 2011 started tracking revision history. 9538 march 2011 july 03, 2014 42 texas instruments-production data revision history about this document this data sheet provides reference information for the lm3s9gn5 microcontroller, describing the functional blocks of the system-on-chip (soc) device designed around the arm? cortex?-m3 core. audience this manual is intended for system software developers, hardware designers, and application developers. about this manual this document is organized into sections that correspond to each major feature. related documents the following related documents are available on the stellaris ? web site at www.ti.com/stellaris : stellaris? errata arm? cortex?-m3 errata cortex?-m3/m4 instruction set technical user's manual stellaris? boot loader user's guide stellaris? graphics library user's guide stellaris? peripheral driver library user's guide stellaris? rom users guide stellaris? usb library user's guide the following related documents are also referenced: arm? debug interface v5 architecture specification arm? embedded trace macrocell architecture specification ieee standard 1149.1-test access port and boundary-scan architecture this documentation list was current as of publication date. please check the web site for additional documentation, including application notes and white papers. 43 july 03, 2014 texas instruments-production data stellaris lm3s9gn5 microcontroller documentation conventions this document uses the conventions shown in table 2 on page 44. table 2. documentation conventions meaning notation general register notation apb registers are indicated in uppercase bold. for example, pborctl is the power-on and brown-out reset control register. if a register name contains a lowercase n, it represents more than one register. for example, srcrn represents any (or all) of the three software reset control registers: srcr0, srcr1 , and srcr2 . register a single bit in a register. bit two or more consecutive and related bits. bit field a hexadecimal increment to a register's address, relative to that module's base address as specified in table 2-4 on page 88. offset 0x nnn registers are numbered consecutively throughout the document to aid in referencing them. the register number has no meaning to software. register n register bits marked reserved are reserved for future use. in most cases, reserved bits are set to 0; however, user software should not rely on the value of a reserved bit. to provide software compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. reserved the range of register bits inclusive from xx to yy. for example, 31:15 means bits 15 through 31 in that register. yy:xx this value in the register bit diagram indicates whether software running on the controller can change the value of the bit field. register bit/field types software can read this field. the bit or field is cleared by hardware after reading the bit/field. rc software can read this field. always write the chip reset value. ro software can read or write this field. r/w software can read or write this field. writing to it with any value clears the register. r/wc software can read or write this field. a write of a 0 to a w1c bit does not affect the bit value in the register. a write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. this register type is primarily used for clearing interrupt status bits where the read operation provides the interrupt status and the write of the read value clears only the interrupts being reported at the time the register was read. r/w1c software can read or write a 1 to this field. a write of a 0 to a r/w1s bit does not affect the bit value in the register. r/w1s software can write this field. a write of a 0 to a w1c bit does not affect the bit value in the register. a write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. a read of the register returns no meaningful data. this register is typically used to clear the corresponding bit in an interrupt register. w1c only a write by software is valid; a read of the register returns no meaningful data. wo this value in the register bit diagram shows the bit/field value after any reset, unless noted. register bit/field reset value bit cleared to 0 on chip reset. 0 bit set to 1 on chip reset. 1 nondeterministic. - pin/signal notation pin alternate function; a pin defaults to the signal without the brackets. [ ] refers to the physical connection on the package. pin refers to the electrical signal encoding of a pin. signal july 03, 2014 44 texas instruments-production data about this document table 2. documentation conventions (continued) meaning notation change the value of the signal from the logically false state to the logically true state. for active high signals, the asserted signal value is 1 (high); for active low signals, the asserted signal value is 0 (low). the active polarity (high or low) is defined by the signal name (see signal and signal below). assert a signal change the value of the signal from the logically true state to the logically false state. deassert a signal signal names are in uppercase and in the courier font. an overbar on a signal name indicates that it is active low. to assert signal is to drive it low; to deassert signal is to drive it high. signal signal names are in uppercase and in the courier font. an active high signal has no overbar. to assert signal is to drive it high; to deassert signal is to drive it low. signal numbers an uppercase x indicates any of several values is allowed, where x can be any legal pattern. for example, a binary value of 0x00 can be either 0100 or 0000, a hex value of 0xx is 0x0 or 0x1, and so on. x hexadecimal numbers have a prefix of 0x. for example, 0x00ff is the hexadecimal number ff. all other numbers within register tables are assumed to be binary. within conceptual information, binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written without a prefix or suffix. 0x 45 july 03, 2014 texas instruments-production data stellaris lm3s9gn5 microcontroller 1 architectural overview texas instruments is the industry leader in bringing 32-bit capabilities and the full benefits of arm ? cortex ? -m-based microcontrollers to the broadest reach of the microcontroller market. for current users of 8- and 16-bit mcus, stellaris ? with cortex-m offers a direct path to the strongest ecosystem of development tools, software and knowledge in the industry. designers who migrate to stellaris benefit from great tools, small code footprint and outstanding performance. even more important, designers can enter the arm ecosystem with full confidence in a compatible roadmap from $1 to 1 ghz. for users of current 32-bit mcus, the stellaris family offers the industrys first implementation of cortex-m3 and the thumb-2 instruction set. with blazingly-fast responsiveness, thumb-2 technology combines both 16-bit and 32-bit instructions to deliver the best balance of code density and performance. thumb-2 uses 26 percent less memory than pure 32-bit code to reduce system cost while delivering 25 percent better performance. the texas instruments stellaris family of microcontrollersthe first arm cortex-m3 based controllers brings high-performance 32-bit computing to cost-sensitive embedded microcontroller applications. 1.1 overview the stellaris lm3s9gn5 microcontroller combines complex integration and high performance with the following feature highlights: arm cortex-m3 processor core high performance: 80-mhz operation; 100 dmips performance 384 kb single-cycle flash memory 64 kb single-cycle sram internal rom loaded with stellarisware ? software external peripheral interface (epi) advanced communication interfaces: uart, ssi, i2c, i2s, can, ethernet macwith mii, usb system integration: general-purpose timers, watchdog timers, dma, general-purpose i/os advanced motion control using pwms, fault inputs, and quadrature encoder inputs analog support: analog and digital comparators, analog-to-digital converters (adc), on-chip voltage regulator jtag and arm serial wire debug (swd) 100-pin lqfp package 108-ball bga package industrial (-40c to 85c) temperature range figure 1-1 on page 47 depicts the features on the stellaris lm3s9gn5 microcontroller. note that there are two on-chip buses that connect the core to the peripherals. the advanced peripheral bus (apb) bus is the legacy bus. the advanced high-performance bus (ahb) bus provides better back-to-back access performance than the apb bus. july 03, 2014 46 texas instruments-production data architectural overview figure 1-1. stellaris lm3s9gn5 microcontroller high-level block diagram 47 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller arm? cortex?-m3 (80mhz) nvic mpu flash (384kb) boot loader driverlib aes & crc ethernet boot loader rom dcode?bus icode?bus jtag/swd system control?and clocks (w/ precis. osc.) bus matrix system bus sram (64kb) system peripherals watchdog timer (2) dma general- purpose timer (4) gpios (72) external peripheral interface serial peripherals uart (3) usb?otg (fs?phy) i2c (2) ssi (2) ethernet mac can controller (2) i2s analog peripherals 12- bit?adc channels (16) analog comparator (3) motion control peripherals qei (2) pwm (8) advanced peripheral bus (apb) advanced high-performance bus (ahb) lm3s9gn5 in addition, the lm3s9gn5 microcontroller offers the advantages of arm's widely available development tools, system-on-chip (soc) infrastructure ip applications, and a large user community. additionally, the microcontroller uses arm's thumb?-compatible thumb-2 instruction set to reduce memory requirements and, thereby, cost. finally, the lm3s9gn5 microcontroller is code-compatible to all members of the extensive stellaris family; providing flexibility to fit precise needs. texas instruments offers a complete solution to get to market quickly, with evaluation and development boards, white papers and application notes, an easy-to-use peripheral driver library, and a strong support, sales, and distributor network. 1.2 target applications the stellaris family is positioned for cost-conscious applications requiring significant control processing and connectivity capabilities such as: gaming equipment network appliances and switches home and commercial site monitoring and control electronic point-of-sale (pos) machines motion control medical instrumentation remote connectivity and monitoring test and measurement equipment factory automation fire and security lighting control transportation 1.3 features the lm3s9gn5 microcontroller component features and general function are discussed in more detail in the following section. 1.3.1 arm cortex-m3 processor core all members of the stellaris product family, including the lm3s9gn5 microcontroller, are designed around an arm cortex-m3 processor core. the arm cortex-m3 processor provides the core for a high-performance, low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. 1.3.1.1 processor core (see page 69) 32-bit arm cortex-m3 architecture optimized for small-footprint embedded applications 80-mhz operation; 100 dmips performance outstanding processing performance combined with fast interrupt handling thumb-2 mixed 16-/32-bit instruction set delivers the high performance expected of a 32-bit arm core in a compact memory size usually associated with 8- and 16-bit devices, typically in the range of a few kilobytes of memory for microcontroller-class applications C single-cycle multiply instruction and hardware divide july 03, 2014 48 texas instruments-production data architectural overview C atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined peripheral control C unaligned data access, enabling data to be efficiently packed into memory fast code execution permits slower processor clock or increases sleep mode time harvard architecture characterized by separate buses for instruction and data efficient processor core, system and memories hardware division and fast digital-signal-processing orientated multiply accumulate saturating arithmetic for signal processing deterministic, high-performance interrupt handling for time-critical applications memory protection unit (mpu) to provide a privileged mode for protected operating system functionality enhanced system debug with extensive breakpoint and trace capabilities serial wire debug and serial wire trace reduce the number of pins required for debugging and tracing migration from the arm7 processor family for better performance and power efficiency optimized for single-cycle flash memory usage ultra-low power consumption with integrated sleep modes 1.3.1.2 system timer (systick) (see page 112) arm cortex-m3 includes an integrated system timer, systick. systick provides a simple, 24-bit, clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. the counter can be used in several different ways, for example: an rtos tick timer that fires at a programmable rate (for example, 100 hz) and invokes a systick routine a high-speed alarm timer using the system clock a variable rate alarm or signal timerthe duration is range-dependent on the reference clock used and the dynamic range of the counter a simple counter used to measure time to completion and time used an internal clock-source control based on missing/meeting durations. 1.3.1.3 nested vectored interrupt controller (nvic) (see page 113) the lm3s9gn5 controller includes the arm nested vectored interrupt controller (nvic). the nvic and cortex-m3 prioritize and handle all exceptions in handler mode. the processor state is automatically stored to the stack on an exception and automatically restored from the stack at the end of the interrupt service routine (isr). the interrupt vector is fetched in parallel to the state saving, enabling efficient interrupt entry. the processor supports tail-chaining, meaning that 49 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller back-to-back interrupts can be performed without the overhead of state saving and restoration. software can set eight priority levels on 7 exceptions (system handlers) and 53 interrupts. deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining external non-maskable interrupt signal (nmi) available for immediate execution of nmi handler for safety critical applications dynamically reprioritizable interrupts exceptional interrupt handling via hardware implementation of required register manipulations 1.3.1.4 system control block (scb) (see page 115) the scb provides system implementation information and system control, including configuration, control, and reporting of system exceptions. 1.3.1.5 memory protection unit (mpu) (see page 115) the mpu supports the standard arm7 protected memory system architecture (pmsa) model. the mpu provides full support for protection regions, overlapping protection regions, access permissions, and exporting memory attributes to the system. 1.3.2 on-chip memory the lm3s9gn5 microcontroller is integrated with the following set of on-chip memory and features: 64 kb single-cycle sram 384 kb single-cycle flash memory up to 50 mhz; a prefetch buffer improves performance above 50 mhz internal rom loaded with stellarisware software: C stellaris peripheral driver library C stellaris boot loader C advanced encryption standard (aes) cryptography tables C cyclic redundancy check (crc) error detection functionality 1.3.2.1 sram (see page 299) the lm3s9gn5 microcontroller provides 64 kb of single-cycle on-chip sram. the internal sram of the stellaris devices is located at offset 0x2000.0000 of the device memory map. because read-modify-write (rmw) operations are very time consuming, arm has introduced bit-banding technology in the cortex-m3 processor. with a bit-band-enabled processor, certain regions in the memory map (sram and peripheral space) can use address aliases to access individual bits in a single, atomic operation. data can be transferred to and from the sram using the micro direct memory access controller (dma). 1.3.2.2 flash memory (see page 301) the lm3s9gn5 microcontroller provides 384 kb of single-cycle on-chip flash memory (above 50 mhz, the flash memory can be accessed in a single cycle as long as the code is linear; branches incur a one-cycle stall). the flash memory is organized as a set of 1-kb blocks that can be individually erased. erasing a block causes the entire contents of the block to be reset to all 1s. july 03, 2014 50 texas instruments-production data architectural overview these blocks are paired into a set of 2-kb blocks that can be individually protected. the blocks can be marked as read-only or execute-only, providing different levels of code protection. read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. execute-only blocks cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism, protecting the contents of those blocks from being read by either the controller or by a debugger. 1.3.2.3 rom (see page 299) the lm3s9gn5 rom is preprogrammed with the following software and programs: stellaris peripheral driver library stellaris boot loader advanced encryption standard (aes) cryptography tables cyclic redundancy check (crc) error-detection functionality the stellaris peripheral driver library is a royalty-free software library for controlling on-chip peripherals with a boot-loader capability. the library performs both peripheral initialization and control functions, with a choice of polled or interrupt-driven peripheral support. in addition, the library is designed to take full advantage of the stellar interrupt performance of the arm cortex-m3 core. no special pragmas or custom assembly code prologue/epilogue functions are required. for applications that require in-field programmability, the royalty-free stellaris boot loader can act as an application loader and support in-field firmware updates. the advanced encryption standard (aes) is a publicly defined encryption standard used by the u.s. government. aes is a strong encryption method with reasonable performance and size. in addition, it is fast in both hardware and software, is fairly easy to implement, and requires little memory. the texas instruments encryption package is available with full source code, and is based on lesser general public license (lgpl) source. an lgpl means that the code can be used within an application without any copyleft implications for the application (the code does not automatically become open source). modifications to the package source, however, must be open source. crc (cyclic redundancy check) is a technique to validate a span of data has the same contents as when previously checked. this technique can be used to validate correct receipt of messages (nothing lost or modified in transit), to validate data after decompression, to validate that flash memory contents have not been changed, and for other cases where the data needs to be validated. a crc is preferred over a simple checksum (e.g. xor all bits) because it catches changes more readily. 1.3.3 external peripheral interface (see page 461) the external peripheral interface (epi) provides access to external devices using a parallel path. unlike communications peripherals such as ssi, uart, and i 2 c, the epi is designed to act like a bus to external peripherals and memory. the epi has the following features: 8/16/32-bit dedicated parallel bus for external peripherals and memory memory interface supports contiguous memory access independent of data bus width, thus enabling code execution directly from sdram, sram and flash memory blocking and non-blocking reads 51 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller separates processor from timing details through use of an internal write fifo efficient transfers using micro direct memory access controller (dma) C separate channels for read and write C read channel request asserted by programmable levels on the internal non-blocking read fifo (nbrfifo) C write channel request asserted by empty on the internal write fifo (wfifo) the epi supports three primary functional modes: synchronous dynamic random access memory (sdram) mode, traditional host-bus mode, and general-purpose mode. the epi module also provides custom gpios; however, unlike regular gpios, the epi module uses a fifo in the same way as a communication mechanism and is speed-controlled using clocking. synchronous dynamic random access memory (sdram) mode C supports x16 (single data rate) sdram at up to 50 mhz C supports low-cost sdrams up to 64 mb (512 megabits) C includes automatic refresh and access to all banks/rows C includes a sleep/standby mode to keep contents active with minimal power draw C multiplexed address/data interface for reduced pin count host-bus mode C traditional x8 and x16 mcu bus interface capabilities C similar device compatibility options as pic, atmega, 8051, and others C access to sram, nor flash memory, and other devices, with up to 1 mb of addressing in unmultiplexed mode and 256 mb in multiplexed mode (512 mb in host-bus 16 mode with no byte selects) C support of both muxed and de-muxed address and data C access to a range of devices supporting the non-address fifo x8 and x16 interface variant, with support for external fifo (xfifo) empty and full signals C speed controlled, with read and write data wait-state counters C chip select modes include ale, csn, dual csn and ale with dual csn C manual chip-enable (or use extra address pins) general-purpose mode C wide parallel interfaces for fast communications with cplds and fpgas C data widths up to 32 bits C data rates up to 150 mb/second july 03, 2014 52 texas instruments-production data architectural overview C optional "address" sizes from 4 bits to 20 bits C optional clock output, read/write strobes, framing (with counter-based size), and clock-enable input general parallel gpio C 1 to 32 bits, fifoed with speed control C useful for custom peripherals or for digital data acquisition and actuator controls 1.3.4 serial communications peripherals the lm3s9gn5 controller supports both asynchronous and synchronous serial communications with: 10/100 ethernet mac with media independent interface (mii) and ieee 1588 ptp hardware support two can 2.0 a/b controllers usb 2.0 otg/host/device three uarts with irda and iso 7816 support (one uart with modem flow control and status) two i 2 c modules two synchronous serial interface modules (ssi) integrated interchip sound (i 2 s) module the following sections provide more detail on each of these communications functions. 1.3.4.1 ethernet controller (see page 921) ethernet is a frame-based computer networking technology for local area networks (lans). ethernet has been standardized as ieee 802.3. this specification defines a number of wiring and signaling standards for the physical layer, two means of network access at the media access control (mac)/data link layer, and a common addressing format. the stellaris ethernet controller consists of a fully integrated media access controller (mac) and network physical (phy) interface and has the following features: conforms to the ieee 802.3-2002 specification multiple operational modes C full- and half-duplex 100 mbps C full- and half-duplex 10 mbps highly configurable C programmable mac address C promiscuous mode support 53 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller C crc error-rejection control C user-configurable interrupts media independent interface (mii) for connection to external 10/100 mbps phy transceivers ieee 1588 precision time protocol: provides highly accurate time stamps for individual packets efficient transfers using micro direct memory access controller (dma) C separate channels for transmit and receive C receive channel request asserted on packet receipt C transmit channel request asserted on empty transmit fifo 1.3.4.2 controller area network (see page 870) controller area network (can) is a multicast shared serial-bus standard for connecting electronic control units (ecus). can was specifically designed to be robust in electromagnetically noisy environments and can utilize a differential balanced line like rs-485 or twisted-pair wire. originally created for automotive purposes, it is now used in many embedded control applications (for example, industrial or medical). bit rates up to 1 mbps are possible at network lengths below 40 meters. decreased bit rates allow longer network distances (for example, 125 kbps at 500m). a transmitter sends a message to all can nodes (broadcasting). each node decides on the basis of the identifier received whether it should process the message. the identifier also determines the priority that the message enjoys in competition for bus access. each can message can transmit from 0 to 8 bytes of user information. the lm3s9gn5 microcontroller includes two can units with the following features: can protocol version 2.0 part a/b bit rates up to 1 mbps 32 message objects with individual identifier masks maskable interrupt disable automatic retransmission mode for time-triggered can (ttcan) applications programmable loopback mode for self-test operation programmable fifo mode enables storage of multiple message objects gluelessly attaches to an external can transceiver through the canntx and cannrx signals 1.3.4.3 usb (see page 957) universal serial bus (usb) is a serial bus standard designed to allow peripherals to be connected and disconnected using a standardized interface without rebooting the system. the lm3s9gn5 microcontroller supports three configurations in usb 2.0 full and low speed: usb device, usb host, and usb on-the-go (negotiated on-the-go as host or device when connected to other usb-enabled systems). the usb module has the following features: july 03, 2014 54 texas instruments-production data architectural overview complies with usb-if certification standards usb 2.0 full-speed (12 mbps) and low-speed (1.5 mbps) operation with integrated phy 4 transfer types: control, interrupt, bulk, and isochronous 32 endpoints C 1 dedicated control in endpoint and 1 dedicated control out endpoint C 15 configurable in endpoints and 15 configurable out endpoints 4 kb dedicated endpoint memory: one endpoint may be defined for double-buffered 1023-byte isochronous packet size vbus droop and valid id detection and interrupt efficient transfers using micro direct memory access controller (dma) C separate channels for transmit and receive for up to three in endpoints and three out endpoints C channel requests asserted when fifo contains required amount of data 1.3.4.4 uart (see page 689) a universal asynchronous receiver/transmitter (uart) is an integrated circuit used for rs-232c serial communications, containing a transmitter (parallel-to-serial converter) and a receiver (serial-to-parallel converter), each clocked separately. the lm3s9gn5 microcontroller includes three fully programmable 16c550-type uarts. although the functionality is similar to a 16c550 uart, this uart design is not register compatible. the uart can generate individually masked interrupts from the rx, tx, modem flow control, modem status, and error conditions. the module generates a single combined interrupt when any of the interrupts are asserted and are unmasked. the three uarts have the following features: programmable baud-rate generator allowing speeds up to 5 mbps for regular speed (divide by 16) and 10 mbps for high speed (divide by 8) separate 16x8 transmit (tx) and receive (rx) fifos to reduce cpu interrupt service loading programmable fifo length, including 1-byte deep operation providing conventional double-buffered interface fifo trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8 standard asynchronous communication bits for start, stop, and parity line-break generation and detection fully programmable serial interface characteristics C 5, 6, 7, or 8 data bits C even, odd, stick, or no-parity bit generation/detection 55 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller C 1 or 2 stop bit generation irda serial-ir (sir) encoder/decoder providing C programmable use of irda serial infrared (sir) or uart input/output C support of irda sir encoder/decoder functions for data rates up to 115.2 kbps half-duplex C support of normal 3/16 and low-power (1.41-2.23 s) bit durations C programmable internal clock generator enabling division of reference clock by 1 to 256 for low-power mode bit duration support for communication with iso 7816 smart cards full modem handshake support (on uart1) lin protocol support standard fifo-level and end-of-transmission interrupts efficient transfers using micro direct memory access controller (dma) C separate channels for transmit and receive C receive single request asserted when data is in the fifo; burst request asserted at programmed fifo level C transmit single request asserted when there is space in the fifo; burst request asserted at programmed fifo level 1.3.4.5 i 2 c (see page 795) the inter-integrated circuit (i 2 c) bus provides bi-directional data transfer through a two-wire design (a serial data line sda and a serial clock line scl). the i 2 c bus interfaces to external i 2 c devices such as serial memory (rams and roms), networking devices, lcds, tone generators, and so on. the i 2 c bus may also be used for system testing and diagnostic purposes in product development and manufacture. each device on the i 2 c bus can be designated as either a master or a slave. each i 2 c module supports both sending and receiving data as either a master or a slave and can operate simultaneously as both a master and a slave. both the i 2 c master and slave can generate interrupts. the lm3s9gn5 microcontroller includes two i 2 c modules with the following features: devices on the i 2 c bus can be designated as either a master or a slave C supports both transmitting and receiving data as either a master or a slave C supports simultaneous master and slave operation four i 2 c modes C master transmit C master receive july 03, 2014 56 texas instruments-production data architectural overview C slave transmit C slave receive two transmission speeds: standard (100 kbps) and fast (400 kbps) master and slave interrupt generation C master generates interrupts when a transmit or receive operation completes (or aborts due to an error) C slave generates interrupts when data has been transferred or requested by a master or when a start or stop condition is detected master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode 1.3.4.6 ssi (see page 753) synchronous serial interface (ssi) is a four-wire bi-directional communications interface that converts data between parallel and serial. the ssi module performs serial-to-parallel conversion on data received from a peripheral device, and parallel-to-serial conversion on data transmitted to a peripheral device. the ssi module can be configured as either a master or slave device. as a slave device, the ssi module can also be configured to disable its output, which allows a master device to be coupled with multiple slave devices. the tx and rx paths are buffered with separate internal fifos. the ssi module also includes a programmable bit rate clock divider and prescaler to generate the output serial clock derived from the ssi module's input clock. bit rates are generated based on the input clock and the maximum bit rate is determined by the connected peripheral. the lm3s9gn5 microcontroller includes two ssi modules with the following features: programmable interface operation for freescale spi, microwire, or texas instruments synchronous serial interfaces master or slave operation programmable clock bit rate and prescaler separate transmit and receive fifos, each 16 bits wide and 8 locations deep programmable data frame size from 4 to 16 bits internal loopback test mode for diagnostic/debug testing standard fifo-based interrupts and end-of-transmission interrupt efficient transfers using micro direct memory access controller (dma) C separate channels for transmit and receive C receive single request asserted when data is in the fifo; burst request asserted when fifo contains 4 entries C transmit single request asserted when there is space in the fifo; burst request asserted when fifo contains 4 entries 57 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 1.3.4.7 inter-integrated circuit sound (i 2 s) interface (see page 833) the i 2 s interface is a configurable serial audio core that contains a transmit module and a receive module. the module is configurable for the i 2 s as well as left-justified and right-justified serial audio formats. data can be in one of four modes: stereo, mono, compact 16-bit stereo and compact 8-bit stereo. the transmit and receive modules each have an 8-entry audio-sample fifo. an audio sample can consist of a left and right stereo sample, a mono sample, or a left and right compact stereo sample. in compact 16-bit stereo, each fifo entry contains both the 16-bit left and 16-bit right samples, allowing efficient data transfers and requiring less memory space. in compact 8-bit stereo, each fifo entry contains an 8-bit left and an 8-bit right sample, reducing memory requirements further. both the transmitter and receiver are capable of being a master or a slave. the stellaris i 2 s interface has the following features: configurable audio format supporting i 2 s, left-justification, and right-justification configurable sample size from 8 to 32 bits mono and stereo support 8-, 16-, and 32-bit fifo interface for packing memory independent transmit and receive 8-entry fifos configurable fifo-level interrupt and dma requests independent transmit and receive mclk direction control transmit and receive internal mclk sources independent transmit and receive control for serial clock and word select mclk and sclk can be independently set to master or slave configurable transmit zero or last sample when fifo empty efficient transfers using micro direct memory access controller (dma) C separate channels for transmit and receive C burst requests C channel requests asserted when fifo contains required amount of data 1.3.5 system integration the lm3s9gn5 microcontroller provides a variety of standard system functions integrated into the device, including: direct memory access controller (dma) system control and clocks including on-chip precision 16-mhz oscillator july 03, 2014 58 texas instruments-production data architectural overview four 32-bit timers (up to eight 16-bit), with real-time clock capability eight capture compare pwm (ccp) pins two watchdog timers C one timer runs off the main oscillator C one timer runs off the precision internal oscillator up to 72 gpios, depending on configuration C highly flexible pin muxing allows use as gpio or one of several peripheral functions C independently configurable to 2, 4 or 8 ma drive capability C up to 4 gpios can have 18 ma drive capability the following sections provide more detail on each of these functions. 1.3.5.1 direct memory access (see page 344) the lm3s9gn5 microcontroller includes a direct memory access (dma) controller, known as micro-dma (dma). the dma controller provides a way to offload data transfer tasks from the cortex-m3 processor, allowing for more efficient use of the processor and the available bus bandwidth. the dma controller can perform transfers between memory and peripherals. it has dedicated channels for each supported on-chip module and can be programmed to automatically perform transfers between peripherals and memory as the peripheral is ready to transfer more data. the dma controller provides the following features: arm primecell ? 32-channel configurable dma controller support for memory-to-memory, memory-to-peripheral, and peripheral-to-memory in multiple transfer modes C basic for simple transfer scenarios C ping-pong for continuous data flow C scatter-gather for a programmable list of up to 256 arbitrary transfers initiated from a single request highly flexible and configurable channel operation C independently configured and operated channels C dedicated channels for supported on-chip modules C primary and secondary channel assignments C one channel each for receive and transmit path for bidirectional modules C dedicated channel for software-initiated transfers C per-channel configurable priority scheme C optional software-initiated requests for any channel two levels of priority 59 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller design optimizations for improved bus access performance between dma controller and the processor core C dma controller access is subordinate to core access C ram striping C peripheral bus segmentation data sizes of 8, 16, and 32 bits transfer size is programmable in binary steps from 1 to 1024 source and destination address increment size of byte, half-word, word, or no increment maskable peripheral requests interrupt on transfer completion, with a separate interrupt per channel 1.3.5.2 system control and clocks (see page 190) system control determines the overall operation of the device. it provides information about the device, controls power-saving features, controls the clocking of the device and individual peripherals, and handles reset detection and reporting. device identification information: version, part number, sram size, flash memory size, and so on power control C on-chip fixed low drop-out (ldo) voltage regulator C low-power options for microcontroller: sleep and deep-sleep modes with clock gating C low-power options for on-chip modules: software controls shutdown of individual peripherals and memory C 3.3-v supply brown-out detection and reporting via interrupt or reset multiple clock sources for microcontroller system clock C precision oscillator (piosc): on-chip resource providing a 16 mhz 1% frequency at room temperature ? 16 mhz 3% across temperature ? can be recalibrated with 7-bit trim resolution ? software power down control for low power modes C main oscillator (mosc): a frequency-accurate clock source by one of two means: an external single-ended clock source is connected to the osc0 input pin, or an external crystal is connected across the osc0 input and osc1 output pins. ? external crystal used with or without on-chip pll: select supported frequencies from 1 mhz to 16.384 mhz. ? external oscillator: from dc to maximum device speed C internal 30-khz oscillator: on chip resource providing a 30 khz 50% frequency, used during power-saving modes july 03, 2014 60 texas instruments-production data architectural overview flexible reset sources C power-on reset (por) C reset pin assertion C brown-out reset (bor) detector alerts to system power drops C software reset C watchdog timer reset C mosc failure 1.3.5.3 programmable timers (see page 536) programmable timers can be used to count or time external events that drive the timer input pins. each gptm block provides two 16-bit timers/counters that can be configured to operate independently as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit real-time clock (rtc). timers can also be used to trigger analog-to-digital (adc) conversions. the general-purpose timer module (gptm) contains four gptm blocks with the following functional options: operating modes: C 16- or 32-bit programmable one-shot timer C 16- or 32-bit programmable periodic timer C 16-bit general-purpose timer with an 8-bit prescaler C 32-bit real-time clock (rtc) when using an external 32.768-khz clock as the input C 16-bit input-edge count- or time-capture modes C 16-bit pwm mode with software-programmable output inversion of the pwm signal count up or down eight capture compare pwm pins (ccp) daisy chaining of timer modules to allow a single timer to initiate multiple timing events adc event trigger user-enabled stalling when the microcontroller asserts cpu halt flag during debug (excluding rtc mode) ability to determine the elapsed time between the assertion of the timer interrupt and entry into the interrupt service routine. efficient transfers using micro direct memory access controller (dma) C dedicated channel for each timer C burst request generated on timer interrupt 61 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 1.3.5.4 ccp pins (see page 544) capture compare pwm pins (ccp) can be used by the general-purpose timer module to time/count external events using the ccp pin as an input. alternatively, the gptm can generate a simple pwm output on the ccp pin. the lm3s9gn5 microcontroller includes eight capture compare pwm pins (ccp) that can be programmed to operate in the following modes: capture: the gp timer is incremented/decremented by programmed events on the ccp input. the gp timer captures and stores the current timer value when a programmed event occurs. compare: the gp timer is incremented/decremented by programmed events on the ccp input. the gp timer compares the current value with a stored value and generates an interrupt when a match occurs. pwm: the gp timer is incremented/decremented by the system clock. a pwm signal is generated based on a match between the counter value and a value stored in a match register and is output on the ccp pin. 1.3.5.5 watchdog timers (see page 583) a watchdog timer is used to regain control when a system has failed due to a software error or to the failure of an external device to respond in the expected way. the stellaris watchdog timer can generate an interrupt or a reset when a time-out value is reached. in addition, the watchdog timer is arm firm-compliant and can be configured to generate an interrupt to the microcontroller on its first time-out, and to generate a reset signal on its second time-out. once the watchdog timer has been configured, the lock register can be written to prevent the timer configuration from being inadvertently altered. the lm3s9gn5 microcontroller has two watchdog timer modules: watchdog timer 0 uses the system clock for its timer clock; watchdog timer 1 uses the piosc as its timer clock. the stellaris watchdog timer module has the following features: 32-bit down counter with a programmable load register separate watchdog clock with an enable programmable interrupt generation logic with interrupt masking lock register protection from runaway software reset generation logic with an enable/disable user-enabled stalling when the microcontroller asserts the cpu halt flag during debug 1.3.5.6 programmable gpios (see page 405) general-purpose input/output (gpio) pins offer flexibility for a variety of connections. the stellaris gpio module is comprised of nine physical gpio blocks, each corresponding to an individual gpio port. the gpio module is firm-compliant (compliant to the arm foundation ip for real-time microcontrollers specification) and supports 0-72 programmable input/output pins. the number of gpios available depends on the peripherals being used (see signal tables on page 1213 for the signals available to each gpio pin). up to 72 gpios, depending on configuration july 03, 2014 62 texas instruments-production data architectural overview highly flexible pin muxing allows use as gpio or one of several peripheral functions 5-v-tolerant in input configuration two means of port access: either advanced high-performance bus (ahb) with better back-to-back access performance, or the legacy advanced peripheral bus (apb) for backwards-compatibility with existing code fast toggle capable of a change every clock cycle for ports on ahb, every two clock cycles for ports on apb programmable control for gpio interrupts C interrupt generation masking C edge-triggered on rising, falling, or both C level-sensitive on high or low values bit masking in both read and write operations through address lines can be used to initiate an adc sample sequence pins configured as digital inputs are schmitt-triggered programmable control for gpio pad configuration C weak pull-up or pull-down resistors C 2-ma, 4-ma, and 8-ma pad drive for digital communication; up to four pads can sink 18-ma for high-current applications C slew rate control for the 8-ma drive C open drain enables C digital input enables 1.3.6 advanced motion control the lm3s9gn5 microcontroller provides motion control functions integrated into the device, including: eight advanced pwm outputs for motion and energy applications four fault inputs to promote low-latency shutdown two quadrature encoder inputs (qei) the following provides more detail on these motion control functions. 1.3.6.1 pwm (see page 1110) pulse width modulation (pwm) is a powerful technique for digitally encoding analog signal levels. high-resolution counters are used to generate a square wave, and the duty cycle of the square wave is modulated to encode an analog signal. typical applications include switching power supplies and motor control. the lm3s9gn5 pwm module consists of four pwm generator blocks and a control block. each pwm generator block contains one timer (16-bit down or up/down counter), two 63 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller comparators, a pwm signal generator, a dead-band generator, and an interrupt/adc-trigger selector. each pwm generator block produces two pwm signals that can either be independent signals or a single pair of complementary signals with dead-band delays inserted. each pwm generator has the following features: four fault-condition handling inputs to quickly provide low-latency shutdown and prevent damage to the motor being controlled one 16-bit counter C runs in down or up/down mode C output frequency controlled by a 16-bit load value C load value updates can be synchronized C produces output signals at zero and load value two pwm comparators C comparator value updates can be synchronized C produces output signals on match pwm signal generator C output pwm signal is constructed based on actions taken as a result of the counter and pwm comparator output signals C produces two independent pwm signals dead-band generator C produces two pwm signals with programmable dead-band delays suitable for driving a half-h bridge C can be bypassed, leaving input pwm signals unmodified can initiate an adc sample sequence the control block determines the polarity of the pwm signals and which signals are passed through to the pins. the output of the pwm generation blocks are managed by the output control block before being passed to the device pins. the pwm control block has the following options: pwm output enable of each pwm signal optional output inversion of each pwm signal (polarity control) optional fault handling for each pwm signal synchronization of timers in the pwm generator blocks synchronization of timer/comparator updates across the pwm generator blocks extended pwm synchronization of timer/comparator updates across the pwm generator blocks july 03, 2014 64 texas instruments-production data architectural overview interrupt status summary of the pwm generator blocks extended pwm fault handling, with multiple fault signals, programmable polarities, and filtering pwm generators can be operated independently or synchronized with other generators 1.3.6.2 qei (see page 1188) a quadrature encoder, also known as a 2-channel incremental encoder, converts linear displacement into a pulse signal. by monitoring both the number of pulses and the relative phase of the two signals, the position, direction of rotation, and speed can be tracked. in addition, a third channel, or index signal, can be used to reset the position counter. the stellaris quadrature encoder with index (qei) module interprets the code produced by a quadrature encoder wheel to integrate position over time and determine direction of rotation. in addition, it can capture a running estimate of the velocity of the encoder wheel. the input frequency of the qei inputs may be as high as 1/4 of the processor frequency (for example, 20 mhz for a 80-mhz system). the lm3s9gn5 microcontroller includes two qei modules providing control of two motors at the same time with the following features: position integrator that tracks the encoder position programmable noise filter on the inputs velocity capture using built-in timer the input frequency of the qei inputs may be as high as 1/4 of the processor frequency (for example, 12.5 mhz for a 50-mhz system) interrupt generation on: C index pulse C velocity-timer expiration C direction change C quadrature error detection 1.3.7 analog the lm3s9gn5 microcontroller provides analog functions integrated into the device, including: two 12-bit analog-to-digital converters (adc) with 16 analog input channels and a sample rate of one million samples/second three analog comparators 16 digital comparators on-chip voltage regulator the following provides more detail on these analog functions. 65 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 1.3.7.1 adc (see page 608) an analog-to-digital converter (adc) is a peripheral that converts a continuous analog voltage to a discrete digital number. the stellaris adc module features 12-bit conversion resolution and supports 16 input channels plus an internal temperature sensor. four buffered sample sequencers allow rapid sampling of up to 16 analog input sources without controller intervention. each sample sequencer provides flexible programming with fully configurable input source, trigger events, interrupt generation, and sequencer priority. each adc module has a digital comparator function that allows the conversion value to be diverted to a comparison unit that provides eight digital comparators. the lm3s9gn5 microcontroller provides two adc modules with the following features: 16 shared analog input channels 12-bit precision adc with an accurate 10-bit data compatibility mode single-ended and differential-input configurations on-chip internal temperature sensor maximum sample rate of one million samples/second optional phase shift in sample time programmable from 22.5o to 337.5o four programmable sample conversion sequencers from one to eight entries long, with corresponding conversion result fifos flexible trigger control C controller (software) C timers C analog comparators C pwm C gpio hardware averaging of up to 64 samples digital comparison unit providing eight digital comparators converter uses an internal 3-v reference or an external reference power and ground for the analog circuitry is separate from the digital power and ground efficient transfers using micro direct memory access controller (dma) C dedicated channel for each sample sequencer C adc module uses burst requests for dma 1.3.7.2 analog comparators (see page 1096) an analog comparator is a peripheral that compares two analog voltages and provides a logical output that signals the comparison result. the lm3s9gn5 microcontroller provides three independent july 03, 2014 66 texas instruments-production data architectural overview integrated analog comparators that can be configured to drive an output or generate an interrupt or adc event. the comparator can provide its output to a device pin, acting as a replacement for an analog comparator on the board, or it can be used to signal the application via interrupts or triggers to the adc to cause it to start capturing a sample sequence. the interrupt generation and adc triggering logic is separate. this means, for example, that an interrupt can be generated on a rising edge and the adc triggered on a falling edge. the lm3s9gn5 microcontroller provides three independent integrated analog comparators with the following functions: compare external pin input to external pin input or to internal programmable voltage reference compare a test voltage against any one of the following voltages: C an individual external reference voltage C a shared single external reference voltage C a shared internal reference voltage 1.3.8 jtag and arm serial wire debug (see page 178) the joint test action group (jtag) port is an ieee standard that defines a test access port and boundary scan architecture for digital integrated circuits and provides a standardized serial interface for controlling the associated test logic. the tap, instruction register (ir), and data registers (dr) can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing information on the components. the jtag port also provides a means of accessing and controlling design-for-test features such as i/o pin observation and control, scan testing, and debugging. texas instruments replaces the arm sw-dp and jtag-dp with the arm serial wire jtag debug port (swj-dp) interface. the swj-dp interface combines the swd and jtag debug ports into one module providing all the normal jtag debug and test functionality plus real-time access to system memory without halting the core or requiring any target resident code. the swj-dp interface has the following features: ieee 1149.1-1990 compatible test access port (tap) controller four-bit instruction register (ir) chain for storing jtag instructions ieee standard instructions: bypass, idcode, sample/preload, extest and intest arm additional instructions: apacc, dpacc and abort integrated arm serial wire debug (swd) C serial wire jtag debug port (swj-dp) C flash patch and breakpoint (fpb) unit for implementing breakpoints C data watchpoint and trace (dwt) unit for implementing watchpoints, trigger resources, and system profiling C instrumentation trace macrocell (itm) for support of printf style debugging C trace port interface unit (tpiu) for bridging to a trace port analyzer 67 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 1.3.9 packaging and temperature industrial-range (-40c to 85c) 100-pin rohs-compliant lqfp package industrial-range (-40c to 85c) 108-ball rohs-compliant bga package 1.4 hardware details details on the pins and package can be found in the following sections: pin diagram on page 1211 signal tables on page 1213 operating characteristics on page 1297 electrical characteristics on page 1298 package information on page 1380 july 03, 2014 68 texas instruments-production data architectural overview 2 the cortex-m3 processor the arm? cortex?-m3 processor provides a high-performance, low-cost platform that meets the system requirements of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. features include: 32-bit arm ? cortex ? -m3 architecture optimized for small-footprint embedded applications 80-mhz operation; 100 dmips performance outstanding processing performance combined with fast interrupt handling thumb-2 mixed 16-/32-bit instruction set delivers the high performance expected of a 32-bit arm core in a compact memory size usually associated with 8- and 16-bit devices, typically in the range of a few kilobytes of memory for microcontroller-class applications C single-cycle multiply instruction and hardware divide C atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined peripheral control C unaligned data access, enabling data to be efficiently packed into memory fast code execution permits slower processor clock or increases sleep mode time harvard architecture characterized by separate buses for instruction and data efficient processor core, system and memories hardware division and fast digital-signal-processing orientated multiply accumulate saturating arithmetic for signal processing deterministic, high-performance interrupt handling for time-critical applications memory protection unit (mpu) to provide a privileged mode for protected operating system functionality enhanced system debug with extensive breakpoint and trace capabilities serial wire debug and serial wire trace reduce the number of pins required for debugging and tracing migration from the arm7 processor family for better performance and power efficiency optimized for single-cycle flash memory usage ultra-low power consumption with integrated sleep modes the stellaris ? family of microcontrollers builds on this core to bring high-performance 32-bit computing to cost-sensitive embedded microcontroller applications, such as factory automation and control, industrial control power devices, building and home automation, and stepper motor control. 69 july 03, 2014 texas instruments-production data stellaris lm3s9gn5 microcontroller this chapter provides information on the stellaris implementation of the cortex-m3 processor, including the programming model, the memory model, the exception model, fault handling, and power management. for technical details on the instruction set, see the cortex?-m3/m4 instruction set technical user's manual. 2.1 block diagram the cortex-m3 processor is built on a high-performance processor core, with a 3-stage pipeline harvard architecture, making it ideal for demanding embedded applications. the processor delivers exceptional power efficiency through an efficient instruction set and extensively optimized design, providing high-end processing hardware including a range of single-cycle and simd multiplication and multiply-with-accumulate capabilities, saturating arithmetic and dedicated hardware division. to facilitate the design of cost-sensitive devices, the cortex-m3 processor implements tightly coupled system components that reduce processor area while significantly improving interrupt handling and system debug capabilities. the cortex-m3 processor implements a version of the thumb? instruction set based on thumb-2 technology, ensuring high code density and reduced program memory requirements. the cortex-m3 instruction set provides the exceptional performance expected of a modern 32-bit architecture, with the high code density of 8-bit and 16-bit microcontrollers. the cortex-m3 processor closely integrates a nested interrupt controller (nvic), to deliver industry-leading interrupt performance. the stellaris nvic includes a non-maskable interrupt (nmi) and provides eight interrupt priority levels. the tight integration of the processor core and nvic provides fast execution of interrupt service routines (isrs), dramatically reducing interrupt latency. the hardware stacking of registers and the ability to suspend load-multiple and store-multiple operations further reduce interrupt latency. interrupt handlers do not require any assembler stubs which removes code overhead from the isrs. tail-chaining optimization also significantly reduces the overhead when switching from one isr to another. to optimize low-power designs, the nvic integrates with the sleep modes, including deep-sleep mode, which enables the entire device to be rapidly powered down. july 03, 2014 70 texas instruments-production data the cortex-m3 processor figure 2-1. cpu block diagram 2.2 overview 2.2.1 system-level interface the cortex-m3 processor provides multiple interfaces using amba? technology to provide high-speed, low-latency memory accesses. the core supports unaligned data accesses and implements atomic bit manipulation that enables faster peripheral controls, system spinlocks, and thread-safe boolean data handling. the cortex-m3 processor has a memory protection unit (mpu) that provides fine-grain memory control, enabling applications to implement security privilege levels and separate code, data and stack on a task-by-task basis. 2.2.2 integrated configurable debug the cortex-m3 processor implements a complete hardware debug solution, providing high system visibility of the processor and memory through either a traditional jtag port or a 2-pin serial wire debug (swd) port that is ideal for microcontrollers and other small package devices. the stellaris implementation replaces the arm sw-dp and jtag-dp with the arm coresight?-compliant serial wire jtag debug port (swj-dp) interface. the swj-dp interface combines the swd and jtag debug ports into one module. see the arm? debug interface v5 architecture specification for details on swj-dp. for system trace, the processor integrates an instrumentation trace macrocell (itm) alongside data watchpoints and a profiling unit. to enable simple and cost-effective profiling of the system trace events, a serial wire viewer (swv) can export a stream of software-generated messages, data trace, and profiling information through a single pin. 71 july 03, 2014 texas instruments-production data stellaris ? 3 u l y d w h 3 h u l s k h u d o % x v l q w h u q d o ' d w d : d w f k s r l q w d q g 7 u d f h , q w h u u x s w v ' h e x j 6 o h h s , q v w u x p h q w d w l r q 7 u d f h 0 d f u r f h o o 7 u d f h 3 r u w , q w h u i d f h 8 q l w & 0 & r u h , q v w u x f w l r q v ' d w d ) o d v k 3 d w f k d q g % u h d n s r l q w 0 h p r u \ 3 u r w h f w l r q 8 q l w ' h e x j $ f f h v v 3 r u w 1 h v w h g 9 h f w r u h g , q w h u u x s w & r q w u r o o h u 6 h u l d o : l u h - 7 $ * ' h e x j 3 r u w % x v 0 d w u l [ $ g y 3 h u l s k h u d o % x v , f r g h e x v ' f r g h e x v 6 \ v w h p e x v 5 2 0 7 d e o h 6 h u l d o : l u h 2 x w s x w 7 u d f h 3 r u w 6 : 2 $ 5 0 & r u w h [ 0 the flash patch and breakpoint unit (fpb) provides up to eight hardware breakpoint comparators that debuggers can use. the comparators in the fpb also provide remap functions of up to eight words in the program code in the code memory region. this enables applications stored in a read-only area of flash memory to be patched in another area of on-chip sram or flash memory. if a patch is required, the application programs the fpb to remap a number of addresses. when those addresses are accessed, the accesses are redirected to a remap table specified in the fpb configuration. for more information on the cortex-m3 debug capabilities, see the arm? debug interface v5 architecture specification . 2.2.3 trace port interface unit (tpiu) the tpiu acts as a bridge between the cortex-m3 trace data from the itm, and an off-chip trace port analyzer, as shown in figure 2-2 on page 72. figure 2-2. tpiu block diagram 2.2.4 cortex-m3 system component details the cortex-m3 includes the following system components: systick a 24-bit count-down timer that can be used as a real-time operating system (rtos) tick timer or as a simple counter (see system timer (systick) on page 112). nested vectored interrupt controller (nvic) an embedded interrupt controller that supports low latency interrupt processing (see nested vectored interrupt controller (nvic) on page 113). system control block (scb) july 03, 2014 72 texas instruments-production data the cortex-m3 processor $ 7 % , q w h u i d f h $ v \ q f k u r q r x v ) , ) 2 $ 3 % , q w h u i d f h 7 u d f h 2 x w v h u l d o l ] h u ' h e x j $ 7 % 6 o d y h 3 r u w $ 3 % 6 o d y h 3 r u w 6 h u l d o : l u h 7 u d f h 3 r u w 6 : 2 the programming model interface to the processor. the scb provides system implementation information and system control, including configuration, control, and reporting of system exceptions (see system control block (scb) on page 115). memory protection unit (mpu) improves system reliability by defining the memory attributes for different memory regions. the mpu provides up to eight different regions and an optional predefined background region (see memory protection unit (mpu) on page 115). 2.3 programming model this section describes the cortex-m3 programming model. in addition to the individual core register descriptions, information about the processor modes and privilege levels for software execution and stacks is included. 2.3.1 processor mode and privilege levels for software execution the cortex-m3 has two modes of operation: thread mode used to execute application software. the processor enters thread mode when it comes out of reset. handler mode used to handle exceptions. when the processor has finished exception processing, it returns to thread mode. in addition, the cortex-m3 has two privilege levels: unprivileged in this mode, software has the following restrictions: C limited access to the msr and mrs instructions and no use of the cps instruction C no access to the system timer, nvic, or system control block C possibly restricted access to memory or peripherals privileged in this mode, software can use all the instructions and has access to all resources. in thread mode, the control register (see page 87) controls whether software execution is privileged or unprivileged. in handler mode, software execution is always privileged. only privileged software can write to the control register to change the privilege level for software execution in thread mode. unprivileged software can use the svc instruction to make a supervisor call to transfer control to privileged software. 2.3.2 stacks the processor uses a full descending stack, meaning that the stack pointer indicates the last stacked item on the memory. when the processor pushes a new item onto the stack, it decrements the stack pointer and then writes the item to the new memory location. the processor implements two stacks: 73 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller the main stack and the process stack, with a pointer for each held in independent registers (see the sp register on page 77). in thread mode, the control register (see page 87) controls whether the processor uses the main stack or the process stack. in handler mode, the processor always uses the main stack. the options for processor operations are shown in table 2-1 on page 74. table 2-1. summary of processor mode, privilege level, and stack use stack used privilege level use processor mode main stack or process stack a privileged or unprivileged a applications thread main stack always privileged exception handlers handler a. see control (page 87). 2.3.3 register map figure 2-3 on page 74 shows the cortex-m3 register set. table 2-2 on page 75 lists the core registers. the core registers are not memory mapped and are accessed by register name, so the base address is n/a (not applicable) and there is no offset. figure 2-3. cortex-m3 register set july 03, 2014 74 texas instruments-production data the cortex-m3 processor 6 3 5 / 5 5 3 & 5 5 5 5 5 5 5 5 5 5 5 5 5 5 / r z u h j l v w h u v + l j k u h j l v w h u v 0 6 3 3 6 3 3 6 5 3 5 , 0 $ 6 . ) $ 8 / 7 0 $ 6 . % $ 6 ( 3 5 , & 2 1 7 5 2 / * h q h u d o s x u s r v h u h j l v w h u v 6 w d f n 3 r l q w h u / l q n 5 h j l v w h u 3 u r j u d p & r x q w h u 3 u r j u d p v w d w x v u h j l v w h u ( [ f h s w l r q p d v n u h j l v w h u v & 2 1 7 5 2 / u h j l v w h u 6 s h f l d o u h j l v w h u v % d q n h g y h u v l r q r i 6 3 table 2-2. processor register map see page description reset type name offset 76 cortex general-purpose register 0 - r/w r0- 76 cortex general-purpose register 1 - r/w r1- 76 cortex general-purpose register 2 - r/w r2- 76 cortex general-purpose register 3 - r/w r3- 76 cortex general-purpose register 4 - r/w r4- 76 cortex general-purpose register 5 - r/w r5- 76 cortex general-purpose register 6 - r/w r6- 76 cortex general-purpose register 7 - r/w r7- 76 cortex general-purpose register 8 - r/w r8- 76 cortex general-purpose register 9 - r/w r9- 76 cortex general-purpose register 10 - r/w r10 - 76 cortex general-purpose register 11 - r/w r11 - 76 cortex general-purpose register 12 - r/w r12 - 77 stack pointer - r/w sp- 78 link register 0xffff.ffff r/w lr- 79 program counter - r/w pc- 80 program status register 0x0100.0000 r/w psr - 84 priority mask register 0x0000.0000 r/w primask - 85 fault mask register 0x0000.0000 r/w faultmask - 86 base priority mask register 0x0000.0000 r/w basepri - 87 control register 0x0000.0000 r/w control - 2.3.4 register descriptions this section lists and describes the cortex-m3 registers, in the order shown in figure 2-3 on page 74. the core registers are not memory mapped and are accessed by register name rather than offset. note: the register type shown in the register descriptions refers to type during program execution in thread mode and handler mode. debug access can differ. 75 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 1: cortex general-purpose register 0 (r0) register 2: cortex general-purpose register 1 (r1) register 3: cortex general-purpose register 2 (r2) register 4: cortex general-purpose register 3 (r3) register 5: cortex general-purpose register 4 (r4) register 6: cortex general-purpose register 5 (r5) register 7: cortex general-purpose register 6 (r6) register 8: cortex general-purpose register 7 (r7) register 9: cortex general-purpose register 8 (r8) register 10: cortex general-purpose register 9 (r9) register 11: cortex general-purpose register 10 (r10) register 12: cortex general-purpose register 11 (r11) register 13: cortex general-purpose register 12 (r12) the rn registers are 32-bit general-purpose registers for data operations and can be accessed from either privileged or unprivileged mode. cortex general-purpose register 0 (r0) type r/w, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 data r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type - - - - - - - - - - - - - - - - reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 data r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type - - - - - - - - - - - - - - - - reset description reset type name bit/field register data. - r/w data 31:0 july 03, 2014 76 texas instruments-production data the cortex-m3 processor register 14: stack pointer (sp) the stack pointer (sp) is register r13. in thread mode, the function of this register changes depending on the asp bit in the control register (control) register. when the asp bit is clear, this register is the main stack pointer (msp) . when the asp bit is set, this register is the process stack pointer (psp) . on reset, the asp bit is clear, and the processor loads the msp with the value from address 0x0000.0000. the msp can only be accessed in privileged mode; the psp can be accessed in either privileged or unprivileged mode. stack pointer (sp) type r/w, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 sp r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type - - - - - - - - - - - - - - - - reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 sp r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type - - - - - - - - - - - - - - - - reset description reset type name bit/field this field is the address of the stack pointer. - r/w sp 31:0 77 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 15: link register (lr) the link register (lr ) is register r14, and it stores the return information for subroutines, function calls, and exceptions. lr can be accessed from either privileged or unprivileged mode. exc_return is loaded into lr on exception entry. see table 2-10 on page 105 for the values and description. link register (lr) type r/w, reset 0xffff.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 link r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 link r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field this field is the return address. 0xffff.ffff r/w link 31:0 july 03, 2014 78 texas instruments-production data the cortex-m3 processor register 16: program counter (pc) the program counter (pc) is register r15, and it contains the current program address. on reset, the processor loads the pc with the value of the reset vector, which is at address 0x0000.0004. bit 0 of the reset vector is loaded into the thumb bit of the epsr at reset and must be 1. the pc register can be accessed in either privileged or unprivileged mode. program counter (pc) type r/w, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 pc r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type - - - - - - - - - - - - - - - - reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pc r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type - - - - - - - - - - - - - - - - reset description reset type name bit/field this field is the current program address. - r/w pc 31:0 79 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 17: program status register (psr) note: this register is also referred to as xpsr . the program status register (psr) has three functions, and the register bits are assigned to the different functions: application program status register (apsr) , bits 31:27, execution program status register (epsr) , bits 26:24, 15:10 interrupt program status register (ipsr) , bits 6:0 the psr , ipsr , and epsr registers can only be accessed in privileged mode; the apsr register can be accessed in either privileged or unprivileged mode. apsr contains the current state of the condition flags from previous instruction executions. epsr contains the thumb state bit and the execution state bits for the if-then ( it ) instruction or the interruptible-continuable instruction ( ici ) field for an interrupted load multiple or store multiple instruction. attempts to read the epsr directly through application software using the msr instruction always return zero. attempts to write the epsr using the msr instruction in application software are always ignored. fault handlers can examine the epsr value in the stacked psr to determine the operation that faulted (see exception entry and return on page 103). ipsr contains the exception type number of the current interrupt service routine (isr). these registers can be accessed individually or as a combination of any two or all three registers, using the register name as an argument to the msr or mrs instructions. for example, all of the registers can be read using psr with the mrs instruction, or apsr only can be written to using apsr with the msr instruction. page 80 shows the possible register combinations for the psr . see the mrs and msr instruction descriptions in the cortex?-m3/m4 instruction set technical user's manual for more information about how to access the program status registers. table 2-3. psr register combinations combination type register apsr , epsr , and ipsr r/w a , b psr epsr and ipsr ro iepsr apsr and ipsr r/w a iapsr apsr and epsr r/w b eapsr a. the processor ignores writes to the ipsr bits. b. reads of the epsr bits return zero, and the processor ignores writes to these bits. program status register (psr) type r/w, reset 0x0100.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved thumb ici / it q v c z n ro ro ro ro ro ro ro ro ro ro ro r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 isrnum reserved ici / it ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset july 03, 2014 80 texas instruments-production data the cortex-m3 processor description reset type name bit/field apsr negative or less flag description value the previous operation result was negative or less than. 1 the previous operation result was positive, zero, greater than, or equal. 0 the value of this bit is only meaningful when accessing psr or apsr . 0 r/w n 31 apsr zero flag description value the previous operation result was zero. 1 the previous operation result was non-zero. 0 the value of this bit is only meaningful when accessing psr or apsr . 0 r/w z 30 apsr carry or borrow flag description value the previous add operation resulted in a carry bit or the previous subtract operation did not result in a borrow bit. 1 the previous add operation did not result in a carry bit or the previous subtract operation resulted in a borrow bit. 0 the value of this bit is only meaningful when accessing psr or apsr . 0 r/w c 29 apsr overflow flag description value the previous operation resulted in an overflow. 1 the previous operation did not result in an overflow. 0 the value of this bit is only meaningful when accessing psr or apsr . 0 r/w v 28 apsr dsp overflow and saturation flag description value dsp overflow or saturation has occurred. 1 dsp overflow or saturation has not occurred since reset or since the bit was last cleared. 0 the value of this bit is only meaningful when accessing psr or apsr . this bit is cleared by software using an mrs instruction. 0 r/w q 27 81 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field epsr ici / it status these bits, along with bits 15:10, contain the interruptible-continuable instruction ( ici ) field for an interrupted load multiple or store multiple instruction or the execution state bits of the it instruction. when epsr holds the ici execution state, bits 26:25 are zero. the if-then block contains up to four instructions following an it instruction. each instruction in the block is conditional. the conditions for the instructions are either all the same, or some can be the inverse of others. see the cortex?-m3/m4 instruction set technical user's manual for more information. the value of this field is only meaningful when accessing psr or epsr . 0x0 ro ici / it 26:25 epsr thumb state this bit indicates the thumb state and should always be set. the following can clear the thumb bit: the blx, bx and pop{pc} instructions restoration from the stacked xpsr value on an exception return bit 0 of the vector value on an exception entry or reset attempting to execute instructions when this bit is clear results in a fault or lockup. see lockup on page 107 for more information. the value of this bit is only meaningful when accessing psr or epsr . 1 ro thumb 24 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 23:16 epsr ici / it status these bits, along with bits 26:25, contain the interruptible-continuable instruction ( ici ) field for an interrupted load multiple or store multiple instruction or the execution state bits of the it instruction. when an interrupt occurs during the execution of an ldm, stm, push or pop instruction, the processor stops the load multiple or store multiple instruction operation temporarily and stores the next register operand in the multiple operation to bits 15:12. after servicing the interrupt, the processor returns to the register pointed to by bits 15:12 and resumes execution of the multiple load or store instruction. when epsr holds the ici execution state, bits 11:10 are zero. the if-then block contains up to four instructions following a 16-bit it instruction. each instruction in the block is conditional. the conditions for the instructions are either all the same, or some can be the inverse of others. see the cortex?-m3/m4 instruction set technical user's manual for more information. the value of this field is only meaningful when accessing psr or epsr . 0x0 ro ici / it 15:10 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 9:7 july 03, 2014 82 texas instruments-production data the cortex-m3 processor description reset type name bit/field ipsr isr number this field contains the exception type number of the current interrupt service routine (isr). description value thread mode 0x00 reserved 0x01 nmi 0x02 hard fault 0x03 memory management fault 0x04 bus fault 0x05 usage fault 0x06 reserved 0x07-0x0a svcall 0x0b reserved for debug 0x0c reserved 0x0d pendsv 0x0e systick 0x0f interrupt vector 0 0x10 interrupt vector 1 0x11 ... ... interrupt vector 54 0x46 reserved 0x47-0x7f see exception types on page 98 for more information. the value of this field is only meaningful when accessing psr or ipsr . 0x00 ro isrnum 6:0 83 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 18: priority mask register (primask) the primask register prevents activation of all exceptions with programmable priority. reset, non-maskable interrupt (nmi), and hard fault are the only exceptions with fixed priority. exceptions should be disabled when they might impact the timing of critical tasks. this register is only accessible in privileged mode. the msr and mrs instructions are used to access the primask register, and the cps instruction may be used to change the value of the primask register. see the cortex?-m3/m4 instruction set technical user's manual for more information on these instructions. for more information on exception priority levels, see exception types on page 98. priority mask register (primask) type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 primask reserved r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:1 priority mask description value prevents the activation of all exceptions with configurable priority. 1 no effect. 0 0 r/w primask 0 july 03, 2014 84 texas instruments-production data the cortex-m3 processor register 19: fault mask register (faultmask) the faultmask register prevents activation of all exceptions except for the non-maskable interrupt (nmi). exceptions should be disabled when they might impact the timing of critical tasks. this register is only accessible in privileged mode. the msr and mrs instructions are used to access the faultmask register, and the cps instruction may be used to change the value of the faultmask register. see the cortex?-m3/m4 instruction set technical user's manual for more information on these instructions. for more information on exception priority levels, see exception types on page 98. fault mask register (faultmask) type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 faultmask reserved r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:1 fault mask description value prevents the activation of all exceptions except for nmi. 1 no effect. 0 the processor clears the faultmask bit on exit from any exception handler except the nmi handler. 0 r/w faultmask 0 85 july 03, 2014 texas instruments-production data stellaris ? register 20: base priority mask register (basepri) the basepri register defines the minimum priority for exception processing. when basepri is set to a nonzero value, it prevents the activation of all exceptions with the same or lower priority level as the basepri value. exceptions should be disabled when they might impact the timing of critical tasks. this register is only accessible in privileged mode. for more information on exception priority levels, see exception types on page 98. base priority mask register (basepri) type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved basepri reserved ro ro ro ro ro r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 base priority any exception that has a programmable priority level with the same or lower priority as the value of this field is masked. the primask register can be used to mask all exceptions with programmable priority levels. higher priority exceptions have lower priority levels. description value all exceptions are unmasked. 0x0 all exceptions with priority level 1-7 are masked. 0x1 all exceptions with priority level 2-7 are masked. 0x2 all exceptions with priority level 3-7 are masked. 0x3 all exceptions with priority level 4-7 are masked. 0x4 all exceptions with priority level 5-7 are masked. 0x5 all exceptions with priority level 6-7 are masked. 0x6 all exceptions with priority level 7 are masked. 0x7 0x0 r/w basepri 7:5 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 4:0 july 03, 2014 86 texas instruments-production data the cortex-m3 processor register 21: control register (control) the control register controls the stack used and the privilege level for software execution when the processor is in thread mode. this register is only accessible in privileged mode. handler mode always uses msp , so the processor ignores explicit writes to the asp bit of the control register when in handler mode. the exception entry and return mechanisms automatically update the control register based on the exc_return value (see table 2-10 on page 105). in an os environment, threads running in thread mode should use the process stack and the kernel and exception handlers should use the main stack. by default, thread mode uses msp . to switch the stack pointer used in thread mode to psp , either use the msr instruction to set the asp bit, as detailed in the cortex?-m3/m4 instruction set technical user's manual , or perform an exception return to thread mode with the appropriate exc_return value, as shown in table 2-10 on page 105. note: when changing the stack pointer, software must use an isb instruction immediately after the msr instruction, ensuring that instructions after the isb execute use the new stack pointer. see the cortex?-m3/m4 instruction set technical user's manual . control register (control) type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tmpl asp reserved r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:2 active stack pointer description value psp is the current stack pointer. 1 msp is the current stack pointer 0 in handler mode, this bit reads as zero and ignores writes. the cortex-m3 updates this bit automatically on exception return. 0 r/w asp 1 thread mode privilege level description value unprivileged software can be executed in thread mode. 1 only privileged software can be executed in thread mode. 0 0 r/w tmpl 0 87 july 03, 2014 texas instruments-production data stellaris ? 2.3.5 exceptions and interrupts the cortex-m3 processor supports interrupts and system exceptions. the processor and the nested vectored interrupt controller (nvic) prioritize and handle all exceptions. an exception changes the normal flow of software control. the processor uses handler mode to handle all exceptions except for reset. see exception entry and return on page 103 for more information. the nvic registers control interrupt handling. see nested vectored interrupt controller (nvic) on page 113 for more information. 2.3.6 data types the cortex-m3 supports 32-bit words, 16-bit halfwords, and 8-bit bytes. the processor also supports 64-bit data transfer instructions. all instruction and data memory accesses are little endian. see memory regions, types and attributes on page 90 for more information. 2.4 memory model this section describes the processor memory map, the behavior of memory accesses, and the bit-banding features. the processor has a fixed memory map that provides up to 4 gb of addressable memory. the memory map for the lm3s9gn5 controller is provided in table 2-4 on page 88. in this manual, register addresses are given as a hexadecimal increment, relative to the modules base address as shown in the memory map. the regions for sram and peripherals include bit-band regions. bit-banding provides atomic operations to bit data (see bit-banding on page 93). the processor reserves regions of the private peripheral bus (ppb) address range for core peripheral registers (see cortex-m3 peripherals on page 112). note: within the memory map, all reserved space returns a bus fault when read or written. table 2-4. memory map for details, see page ... description end start memory 308 on-chip flash 0x0005.ffff 0x0000.0000 - reserved 0x00ff.ffff 0x0006.0000 299 reserved for rom 0x1fff.ffff 0x0100.0000 299 bit-banded on-chip sram 0x2000.ffff 0x2000.0000 - reserved 0x21ff.ffff 0x2001.0000 299 bit-band alias of bit-banded on-chip sram starting at 0x2000.0000 0x221f.ffff 0x2200.0000 - reserved 0x3fff.ffff 0x2220.0000 firm peripherals 586 watchdog timer 0 0x4000.0fff 0x4000.0000 586 watchdog timer 1 0x4000.1fff 0x4000.1000 - reserved 0x4000.3fff 0x4000.2000 418 gpio port a 0x4000.4fff 0x4000.4000 418 gpio port b 0x4000.5fff 0x4000.5000 418 gpio port c 0x4000.6fff 0x4000.6000 july 03, 2014 88 texas instruments-production data the cortex-m3 processor table 2-4. memory map (continued) for details, see page ... description end start 418 gpio port d 0x4000.7fff 0x4000.7000 767 ssi0 0x4000.8fff 0x4000.8000 767 ssi1 0x4000.9fff 0x4000.9000 - reserved 0x4000.bfff 0x4000.a000 703 uart0 0x4000.cfff 0x4000.c000 703 uart1 0x4000.dfff 0x4000.d000 703 uart2 0x4000.efff 0x4000.e000 - reserved 0x4001.ffff 0x4000.f000 peripherals 811 i 2 c 0 0x4002.0fff 0x4002.0000 811 i 2 c 1 0x4002.1fff 0x4002.1000 - reserved 0x4002.3fff 0x4002.2000 418 gpio port e 0x4002.4fff 0x4002.4000 418 gpio port f 0x4002.5fff 0x4002.5000 418 gpio port g 0x4002.6fff 0x4002.6000 418 gpio port h 0x4002.7fff 0x4002.7000 1125 pwm 0x4002.8fff 0x4002.8000 - reserved 0x4002.bfff 0x4002.9000 1194 qei0 0x4002.cfff 0x4002.c000 1194 qei1 0x4002.dfff 0x4002.d000 - reserved 0x4002.ffff 0x4002.e000 552 timer 0 0x4003.0fff 0x4003.0000 552 timer 1 0x4003.1fff 0x4003.1000 552 timer 2 0x4003.2fff 0x4003.2000 552 timer 3 0x4003.3fff 0x4003.3000 - reserved 0x4003.7fff 0x4003.4000 630 adc0 0x4003.8fff 0x4003.8000 630 adc1 0x4003.9fff 0x4003.9000 - reserved 0x4003.bfff 0x4003.a000 1096 analog comparators 0x4003.cfff 0x4003.c000 418 gpio port j 0x4003.dfff 0x4003.d000 - reserved 0x4003.ffff 0x4003.e000 890 can0 controller 0x4004.0fff 0x4004.0000 890 can1 controller 0x4004.1fff 0x4004.1000 - reserved 0x4004.7fff 0x4004.2000 933 ethernet controller 0x4004.8fff 0x4004.8000 - reserved 0x4004.ffff 0x4004.9000 984 usb 0x4005.0fff 0x4005.0000 - reserved 0x4005.3fff 0x4005.1000 845 i 2 s0 0x4005.4fff 0x4005.4000 - reserved 0x4005.7fff 0x4005.5000 89 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 2-4. memory map (continued) for details, see page ... description end start 418 gpio port a (ahb aperture) 0x4005.8fff 0x4005.8000 418 gpio port b (ahb aperture) 0x4005.9fff 0x4005.9000 418 gpio port c (ahb aperture) 0x4005.afff 0x4005.a000 418 gpio port d (ahb aperture) 0x4005.bfff 0x4005.b000 418 gpio port e (ahb aperture) 0x4005.cfff 0x4005.c000 418 gpio port f (ahb aperture) 0x4005.dfff 0x4005.d000 418 gpio port g (ahb aperture) 0x4005.efff 0x4005.e000 418 gpio port h (ahb aperture) 0x4005.ffff 0x4005.f000 418 gpio port j (ahb aperture) 0x4006.0fff 0x4006.0000 - reserved 0x400c.ffff 0x4006.1000 492 epi 0 0x400d.0fff 0x400d.0000 - reserved 0x400f.cfff 0x400d.1000 308 flash memory control 0x400f.dfff 0x400f.d000 207 system control 0x400f.efff 0x400f.e000 366 dma 0x400f.ffff 0x400f.f000 - reserved 0x41ff.ffff 0x4010.0000 - bit-banded alias of 0x4000.0000 through 0x400f.ffff 0x43ff.ffff 0x4200.0000 - reserved 0x5fff.ffff 0x4400.0000 - epi0 mapped peripheral and ram 0xdfff.ffff 0x6000.0000 private peripheral bus 71 instrumentation trace macrocell (itm) 0xe000.0fff 0xe000.0000 71 data watchpoint and trace (dwt) 0xe000.1fff 0xe000.1000 71 flash patch and breakpoint (fpb) 0xe000.2fff 0xe000.2000 - reserved 0xe000.dfff 0xe000.3000 120 cortex-m3 peripherals (systick, nvic, mpu and scb) 0xe000.efff 0xe000.e000 - reserved 0xe003.ffff 0xe000.f000 72 trace port interface unit (tpiu) 0xe004.0fff 0xe004.0000 - reserved 0xffff.ffff 0xe004.1000 2.4.1 memory regions, types and attributes the memory map and the programming of the mpu split the memory map into regions. each region has a defined memory type, and some regions have additional memory attributes. the memory type and attributes determine the behavior of accesses to the region. the memory types are: normal: the processor can re-order transactions for efficiency and perform speculative reads. device: the processor preserves transaction order relative to other transactions to device or strongly ordered memory. strongly ordered: the processor preserves transaction order relative to all other transactions. july 03, 2014 90 texas instruments-production data the cortex-m3 processor the different ordering requirements for device and strongly ordered memory mean that the memory system can buffer a write to device memory but must not buffer a write to strongly ordered memory. an additional memory attribute is execute never (xn), which means the processor prevents instruction accesses. a fault exception is generated only on execution of an instruction executed from an xn region. 2.4.2 memory system ordering of memory accesses for most memory accesses caused by explicit memory access instructions, the memory system does not guarantee that the order in which the accesses complete matches the program order of the instructions, providing the order does not affect the behavior of the instruction sequence. normally, if correct program execution depends on two memory accesses completing in program order, software must insert a memory barrier instruction between the memory access instructions (see software ordering of memory accesses on page 92). however, the memory system does guarantee ordering of accesses to device and strongly ordered memory. for two memory access instructions a1 and a2, if both a1 and a2 are accesses to either device or strongly ordered memory, and if a1 occurs before a2 in program order, a1 is always observed before a2. 2.4.3 behavior of memory accesses table 2-5 on page 91 shows the behavior of accesses to each region in the memory map. see memory regions, types and attributes on page 90 for more information on memory types and the xn attribute. stellaris devices may have reserved memory areas within the address ranges shown below (refer to table 2-4 on page 88 for more information). table 2-5. memory access behavior description execute never (xn) memory type memory region address range this executable region is for program code. data can also be stored here. - normal code 0x0000.0000 - 0x1fff.ffff this executable region is for data. code can also be stored here. this region includes bit band and bit band alias areas (see table 2-6 on page 93). - normal sram 0x2000.0000 - 0x3fff.ffff this region includes bit band and bit band alias areas (see table 2-7 on page 93). xn device peripheral 0x4000.0000 - 0x5fff.ffff this executable region is for data. - normal external ram 0x6000.0000 - 0x9fff.ffff this region is for external device memory. xn device external device 0xa000.0000 - 0xdfff.ffff this region includes the nvic, system timer, and system control block. xn strongly ordered private peripheral bus 0xe000.0000- 0xe00f.ffff - - - reserved 0xe010.0000- 0xffff.ffff the code, sram, and external ram regions can hold programs. however, it is recommended that programs always use the code region because the cortex-m3 has separate buses that can perform instruction fetches and data accesses simultaneously. the mpu can override the default memory access behavior described in this section. for more information, see memory protection unit (mpu) on page 115. the cortex-m3 prefetches instructions ahead of execution and speculatively prefetches from branch target addresses. 91 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 2.4.4 software ordering of memory accesses the order of instructions in the program flow does not always guarantee the order of the corresponding memory transactions for the following reasons: the processor can reorder some memory accesses to improve efficiency, providing this does not affect the behavior of the instruction sequence. the processor has multiple bus interfaces. memory or devices in the memory map have different wait states. some memory accesses are buffered or speculative. memory system ordering of memory accesses on page 91 describes the cases where the memory system guarantees the order of memory accesses. otherwise, if the order of memory accesses is critical, software must include memory barrier instructions to force that ordering. the cortex-m3 has the following memory barrier instructions: the data memory barrier ( dmb ) instruction ensures that outstanding memory transactions complete before subsequent memory transactions. the data synchronization barrier ( dsb ) instruction ensures that outstanding memory transactions complete before subsequent instructions execute. the instruction synchronization barrier ( isb ) instruction ensures that the effect of all completed memory transactions is recognizable by subsequent instructions. memory barrier instructions can be used in the following situations: mpu programming C if the mpu settings are changed and the change must be effective on the very next instruction, use a dsb instruction to ensure the effect of the mpu takes place immediately at the end of context switching. C use an isb instruction to ensure the new mpu setting takes effect immediately after programming the mpu region or regions, if the mpu configuration code was accessed using a branch or call. if the mpu configuration code is entered using exception mechanisms, then an isb instruction is not required. vector table if the program changes an entry in the vector table and then enables the corresponding exception, use a dmb instruction between the operations. the dmb instruction ensures that if the exception is taken immediately after being enabled, the processor uses the new exception vector. self-modifying code if a program contains self-modifying code, use an isb instruction immediately after the code modification in the program. the isb instruction ensures subsequent instruction execution uses the updated program. memory map switching july 03, 2014 92 texas instruments-production data the cortex-m3 processor if the system contains a memory map switching mechanism, use a dsb instruction after switching the memory map in the program. the dsb instruction ensures subsequent instruction execution uses the updated memory map. dynamic exception priority change when an exception priority has to change when the exception is pending or active, use dsb instructions after the change. the change then takes effect on completion of the dsb instruction. memory accesses to strongly ordered memory, such as the system control block, do not require the use of dmb instructions. for more information on the memory barrier instructions, see the cortex?-m3/m4 instruction set technical user's manual . 2.4.5 bit-banding a bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region. the bit-band regions occupy the lowest 1 mb of the sram and peripheral memory regions. accesses to the 32-mb sram alias region map to the 1-mb sram bit-band region, as shown in table 2-6 on page 93. accesses to the 32-mb peripheral alias region map to the 1-mb peripheral bit-band region, as shown in table 2-7 on page 93. for the specific address range of the bit-band regions, see table 2-4 on page 88. note: a word access to the sram or the peripheral bit-band alias region maps to a single bit in the sram or peripheral bit-band region. a word access to a bit band address results in a word access to the underlying memory, and similarly for halfword and byte accesses. this allows bit band accesses to match the access requirements of the underlying peripheral. table 2-6. sram memory bit-banding regions instruction and data accesses memory region address range end start direct accesses to this memory range behave as sram memory accesses, but this region is also bit addressable through bit-band alias. sram bit-band region 0x2000.ffff 0x2000.0000 data accesses to this region are remapped to bit band region. a write operation is performed as read-modify-write. instruction accesses are not remapped. sram bit-band alias 0x221f.ffff 0x2200.0000 table 2-7. peripheral memory bit-banding regions instruction and data accesses memory region address range end start direct accesses to this memory range behave as peripheral memory accesses, but this region is also bit addressable through bit-band alias. peripheral bit-band region 0x400f.ffff 0x4000.0000 data accesses to this region are remapped to bit band region. a write operation is performed as read-modify-write. instruction accesses are not permitted. peripheral bit-band alias 0x43ff.ffff 0x4200.0000 the following formula shows how the alias region maps onto the bit-band region: bit_word_offset = (byte_offset x 32) + (bit_number x 4) -xo\ 7h[dv ,qvwuxphqwv3urgxfwlrq dwd 6whoodulv ? bit_word_addr = bit_band_base + bit_word_offset where: bit_word_offset the position of the target bit in the bit-band memory region. bit_word_addr the address of the word in the alias memory region that maps to the targeted bit. bit_band_base the starting address of the alias region. byte_offset the number of the byte in the bit-band region that contains the targeted bit. bit_number the bit position, 0-7, of the targeted bit. figure 2-4 on page 95 shows examples of bit-band mapping between the sram bit-band alias region and the sram bit-band region: the alias word at 0x23ff.ffe0 maps to bit 0 of the bit-band byte at 0x200f.ffff: 0x23ff.ffe0 = 0x2200.0000 + (0x000f.ffff*32) + (0*4) the alias word at 0x23ff.fffc maps to bit 7 of the bit-band byte at 0x200f.ffff: 0x23ff.fffc = 0x2200.0000 + (0x000f.ffff*32) + (7*4) the alias word at 0x2200.0000 maps to bit 0 of the bit-band byte at 0x2000.0000: 0x2200.0000 = 0x2200.0000 + (0*32) + (0*4) the alias word at 0x2200.001c maps to bit 7 of the bit-band byte at 0x2000.0000: 0x2200.001c = 0x2200.0000+ (0*32) + (7*4) july 03, 2014 94 texas instruments-production data the cortex-m3 processor figure 2-4. bit-band mapping 2.4.5.1 directly accessing an alias region writing to a word in the alias region updates a single bit in the bit-band region. bit 0 of the value written to a word in the alias region determines the value written to the targeted bit in the bit-band region. writing a value with bit 0 set writes a 1 to the bit-band bit, and writing a value with bit 0 clear writes a 0 to the bit-band bit. bits 31:1 of the alias word have no effect on the bit-band bit. writing 0x01 has the same effect as writing 0xff. writing 0x00 has the same effect as writing 0x0e. when reading a word in the alias region, 0x0000.0000 indicates that the targeted bit in the bit-band region is clear and 0x0000.0001 indicates that the targeted bit in the bit-band region is set. 2.4.5.2 directly accessing a bit-band region behavior of memory accesses on page 91 describes the behavior of direct byte, halfword, or word accesses to the bit-band regions. 2.4.6 data storage the processor views memory as a linear collection of bytes numbered in ascending order from zero. for example, bytes 0-3 hold the first stored word, and bytes 4-7 hold the second stored word. data is stored in little-endian format, with the least-significant byte (lsbyte) of a word stored at the lowest-numbered byte, and the most-significant byte (msbyte) stored at the highest-numbered byte. figure 2-5 on page 96 illustrates how data is stored. 95 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller [ ) ) ) ) ( [ [ ) ) ) ) ( [ ) ) ) ) ( [ ) ) ) ) ( & [ ) ) ) ) ) [ ) ) ) ) ) [ ) ) ) ) ) [ ) ) ) ) ) & [ [ [ [ & [ [ [ & 0 % $ o l d v 5 h j l r q [ [ [ [ [ ) ) ) ) & [ ) ) ) ) ' [ ) ) ) ) ( [ ) ) ) ) ) 0 % 6 5 $ 0 % l w % d q g 5 h j l r q figure 2-5. data storage 2.4.7 synchronization primitives the cortex-m3 instruction set includes pairs of synchronization primitives which provide a non-blocking mechanism that a thread or process can use to obtain exclusive access to a memory location. software can use these primitives to perform a guaranteed read-modify-write memory update sequence or for a semaphore mechanism. a pair of synchronization primitives consists of: a load-exclusive instruction, which is used to read the value of a memory location and requests exclusive access to that location. a store-exclusive instruction, which is used to attempt to write to the same memory location and returns a status bit to a register. if this status bit is clear, it indicates that the thread or process gained exclusive access to the memory and the write succeeds; if this status bit is set, it indicates that the thread or process did not gain exclusive access to the memory and no write was performed. the pairs of load-exclusive and store-exclusive instructions are: the word instructions ldrex and strex the halfword instructions ldrexh and strexh the byte instructions ldrexb and strexb software must use a load-exclusive instruction with the corresponding store-exclusive instruction. to perform an exclusive read-modify-write of a memory location, software must: 1. use a load-exclusive instruction to read the value of the location. 2. modify the value, as required. 3. use a store-exclusive instruction to attempt to write the new value back to the memory location. 4. test the returned status bit. if the status bit is clear, the read-modify-write completed successfully. if the status bit is set, no write was performed, which indicates that the value returned at step 1 might be out of date. the software must retry the entire read-modify-write sequence. software can use the synchronization primitives to implement a semaphore as follows: july 03, 2014 96 texas instruments-production data the cortex-m3 processor 0 h p r u \ 5 h j l v w h u $ g g u h v v $ $ o v e \ w h p v e \ w h $ $ % % % % % % % % 1. use a load-exclusive instruction to read from the semaphore address to check whether the semaphore is free. 2. if the semaphore is free, use a store-exclusive to write the claim value to the semaphore address. 3. if the returned status bit from step 2 indicates that the store-exclusive succeeded, then the software has claimed the semaphore. however, if the store-exclusive failed, another process might have claimed the semaphore after the software performed step 1. the cortex-m3 includes an exclusive access monitor that tags the fact that the processor has executed a load-exclusive instruction. the processor removes its exclusive access tag if: it executes a clrex instruction. it executes a store-exclusive instruction, regardless of whether the write succeeds. an exception occurs, which means the processor can resolve semaphore conflicts between different threads. for more information about the synchronization primitive instructions, see the cortex?-m3/m4 instruction set technical user's manual . 2.5 exception model the arm cortex-m3 processor and the nested vectored interrupt controller (nvic) prioritize and handle all exceptions in handler mode. the processor state is automatically stored to the stack on an exception and automatically restored from the stack at the end of the interrupt service routine (isr). the vector is fetched in parallel to the state saving, enabling efficient interrupt entry. the processor supports tail-chaining, which enables back-to-back interrupts to be performed without the overhead of state saving and restoration. table 2-8 on page 99 lists all exception types. software can set eight priority levels on seven of these exceptions (system handlers) as well as on 53 interrupts (listed in table 2-9 on page 100). priorities on the system handlers are set with the nvic system handler priority n (sysprin) registers. interrupts are enabled through the nvic interrupt set enable n (enn) register and prioritized with the nvic interrupt priority n (prin) registers. priorities can be grouped by splitting priority levels into preemption priorities and subpriorities. all the interrupt registers are described in nested vectored interrupt controller (nvic) on page 113. internally, the highest user-programmable priority (0) is treated as fourth priority, after a reset, non-maskable interrupt (nmi), and a hard fault, in that order. note that 0 is the default priority for all the programmable priorities. important: after a write to clear an interrupt source, it may take several processor cycles for the nvic to see the interrupt source de-assert. thus if the interrupt clear is done as the last action in an interrupt handler, it is possible for the interrupt handler to complete while the nvic sees the interrupt as still asserted, causing the interrupt handler to be re-entered errantly. this situation can be avoided by either clearing the interrupt source at the beginning of the interrupt handler or by performing a read or write after the write to clear the interrupt source (and flush the write buffer). see nested vectored interrupt controller (nvic) on page 113 for more information on exceptions and interrupts. 97 july 03, 2014 texas instruments-production data stellaris ? 2.5.1 exception states each exception is in one of the following states: inactive. the exception is not active and not pending. pending. the exception is waiting to be serviced by the processor. an interrupt request from a peripheral or from software can change the state of the corresponding interrupt to pending. active. an exception that is being serviced by the processor but has not completed. note: an exception handler can interrupt the execution of another exception handler. in this case, both exceptions are in the active state. active and pending. the exception is being serviced by the processor, and there is a pending exception from the same source. 2.5.2 exception types the exception types are: reset. reset is invoked on power up or a warm reset. the exception model treats reset as a special form of exception. when reset is asserted, the operation of the processor stops, potentially at any point in an instruction. when reset is deasserted, execution restarts from the address provided by the reset entry in the vector table. execution restarts as privileged execution in thread mode. nmi. a non-maskable interrupt (nmi) can be signaled using the nmi signal or triggered by software using the interrupt control and state (intctrl) register. this exception has the highest priority other than reset. nmi is permanently enabled and has a fixed priority of -2. nmis cannot be masked or prevented from activation by any other exception or preempted by any exception other than reset. hard fault. a hard fault is an exception that occurs because of an error during exception processing, or because an exception cannot be managed by any other exception mechanism. hard faults have a fixed priority of -1, meaning they have higher priority than any exception with configurable priority. memory management fault. a memory management fault is an exception that occurs because of a memory protection related fault, including access violation and no match. the mpu or the fixed memory protection constraints determine this fault, for both instruction and data memory transactions. this fault is used to abort instruction accesses to execute never (xn) memory regions, even if the mpu is disabled. bus fault. a bus fault is an exception that occurs because of a memory-related fault for an instruction or data memory transaction such as a prefetch fault or a memory access fault. this fault can be enabled or disabled. usage fault. a usage fault is an exception that occurs because of a fault related to instruction execution, such as: C an undefined instruction C an illegal unaligned access C invalid state on instruction execution july 03, 2014 98 texas instruments-production data the cortex-m3 processor C an error on exception return an unaligned address on a word or halfword memory access or division by zero can cause a usage fault when the core is properly configured. svcall. a supervisor call (svc) is an exception that is triggered by the svc instruction. in an os environment, applications can use svc instructions to access os kernel functions and device drivers. debug monitor. this exception is caused by the debug monitor (when not halting). this exception is only active when enabled. this exception does not activate if it is a lower priority than the current activation. pendsv. pendsv is a pendable, interrupt-driven request for system-level service. in an os environment, use pendsv for context switching when no other exception is active. pendsv is triggered using the interrupt control and state (intctrl) register. systick. a systick exception is an exception that the system timer generates when it reaches zero when it is enabled to generate an interrupt. software can also generate a systick exception using the interrupt control and state (intctrl) register. in an os environment, the processor can use this exception as system tick. interrupt (irq). an interrupt, or irq, is an exception signaled by a peripheral or generated by a software request and fed through the nvic (prioritized). all interrupts are asynchronous to instruction execution. in the system, peripherals use interrupts to communicate with the processor. table 2-9 on page 100 lists the interrupts on the lm3s9gn5 controller. for an asynchronous exception, other than reset, the processor can execute another instruction between when the exception is triggered and when the processor enters the exception handler. privileged software can disable the exceptions that table 2-8 on page 99 shows as having configurable priority (see the syshndctrl register on page 156 and the dis0 register on page 129). for more information about hard faults, memory management faults, bus faults, and usage faults, see fault handling on page 105. table 2-8. exception types activation vector address or offset b priority a vector number exception type stack top is loaded from the first entry of the vector table on reset. 0x0000.0000 - 0 - asynchronous 0x0000.0004 -3 (highest) 1 reset asynchronous 0x0000.0008 -2 2 non-maskable interrupt (nmi) - 0x0000.000c -1 3 hard fault synchronous 0x0000.0010 programmable c 4 memory management synchronous when precise and asynchronous when imprecise 0x0000.0014 programmable c 5 bus fault synchronous 0x0000.0018 programmable c 6 usage fault reserved - - 7-10 - synchronous 0x0000.002c programmable c 11 svcall synchronous 0x0000.0030 programmable c 12 debug monitor reserved - - 13 - 99 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 2-8. exception types (continued) activation vector address or offset b priority a vector number exception type asynchronous 0x0000.0038 programmable c 14 pendsv asynchronous 0x0000.003c programmable c 15 systick asynchronous 0x0000.0040 and above programmable d 16 and above interrupts a. 0 is the default priority for all the programmable priorities. b. see vector table on page 101. c. see syspri1 on page 153. d. see prin registers on page 137. table 2-9. interrupts description vector address or offset interrupt number (bit in interrupt registers) vector number processor exceptions 0x0000.0000 - 0x0000.003c - 0-15 gpio port a 0x0000.0040 0 16 gpio port b 0x0000.0044 1 17 gpio port c 0x0000.0048 2 18 gpio port d 0x0000.004c 3 19 gpio port e 0x0000.0050 4 20 uart0 0x0000.0054 5 21 uart1 0x0000.0058 6 22 ssi0 0x0000.005c 7 23 i 2 c0 0x0000.0060 8 24 pwm fault 0x0000.0064 9 25 pwm generator 0 0x0000.0068 10 26 pwm generator 1 0x0000.006c 11 27 pwm generator 2 0x0000.0070 12 28 qei0 0x0000.0074 13 29 adc0 sequence 0 0x0000.0078 14 30 adc0 sequence 1 0x0000.007c 15 31 adc0 sequence 2 0x0000.0080 16 32 adc0 sequence 3 0x0000.0084 17 33 watchdog timers 0 and 1 0x0000.0088 18 34 timer 0a 0x0000.008c 19 35 timer 0b 0x0000.0090 20 36 timer 1a 0x0000.0094 21 37 timer 1b 0x0000.0098 22 38 timer 2a 0x0000.009c 23 39 timer 2b 0x0000.00a0 24 40 analog comparator 0 0x0000.00a4 25 41 analog comparator 1 0x0000.00a8 26 42 analog comparator 2 0x0000.00ac 27 43 system control 0x0000.00b0 28 44 july 03, 2014 100 texas instruments-production data the cortex-m3 processor table 2-9. interrupts (continued) description vector address or offset interrupt number (bit in interrupt registers) vector number flash memory control 0x0000.00b4 29 45 gpio port f 0x0000.00b8 30 46 gpio port g 0x0000.00bc 31 47 gpio port h 0x0000.00c0 32 48 uart2 0x0000.00c4 33 49 ssi1 0x0000.00c8 34 50 timer 3a 0x0000.00cc 35 51 timer 3b 0x0000.00d0 36 52 i 2 c1 0x0000.00d4 37 53 qei1 0x0000.00d8 38 54 can0 0x0000.00dc 39 55 can1 0x0000.00e0 40 56 reserved - 41 57 ethernet controller 0x0000.00e8 42 58 reserved - 43 59 usb 0x0000.00f0 44 60 pwm generator 3 0x0000.00f4 45 61 dma software 0x0000.00f8 46 62 dma error 0x0000.00fc 47 63 adc1 sequence 0 0x0000.0100 48 64 adc1 sequence 1 0x0000.0104 49 65 adc1 sequence 2 0x0000.0108 50 66 adc1 sequence 3 0x0000.010c 51 67 i 2 s0 0x0000.0110 52 68 epi 0x0000.0114 53 69 gpio port j 0x0000.0118 54 70 2.5.3 exception handlers the processor handles exceptions using: interrupt service routines (isrs). interrupts (irqx) are the exceptions handled by isrs. fault handlers. hard fault, memory management fault, usage fault, and bus fault are fault exceptions handled by the fault handlers. system handlers. nmi, pendsv, svcall, systick, and the fault exceptions are all system exceptions that are handled by system handlers. 2.5.4 vector table the vector table contains the reset value of the stack pointer and the start addresses, also called exception vectors, for all exception handlers. the vector table is constructed using the vector address or offset shown in table 2-8 on page 99. figure 2-6 on page 102 shows the order of the exception 101 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller vectors in the vector table. the least-significant bit of each vector must be 1, indicating that the exception handler is thumb code figure 2-6. vector table on system reset, the vector table is fixed at address 0x0000.0000. privileged software can write to the vector table offset (vtable) register to relocate the vector table start address to a different memory location, in the range 0x0000.0200 to 0x3fff.fe00 (see vector table on page 101). note that when configuring the vtable register, the offset must be aligned on a 512-byte boundary. 2.5.5 exception priorities as table 2-8 on page 99 shows, all exceptions have an associated priority, with a lower priority value indicating a higher priority and configurable priorities for all exceptions except reset, hard fault, and nmi. if software does not configure any priorities, then all exceptions with a configurable priority have a priority of 0. for information about configuring exception priorities, see page 153 and page 137. note: configurable priority values for the stellaris implementation are in the range 0-7. this means that the reset, hard fault, and nmi exceptions, with fixed negative priority values, always have higher priority than any other exception. july 03, 2014 102 texas instruments-production data the cortex-m3 processor , q l w l d o 6 3 y d o x h 5 h v h w + d u g i d x o w 1 0 , 0 h p r u \ p d q d j h p h q w i d x o w 8 v d j h i d x o w % x v i d x o w [ [ [ [ & [ [ [ 5 h v h u y h g 6 9 & d o o 3 h q g 6 9 5 h v h u y h g i r u ' h e x j 6 \ v w l f n , 5 4 5 h v h u y h g [ & [ [ & [ 2 i i v h w ( [ f h s w l r q q x p e h u 9 h f w r u , 5 4 , 5 4 [ , 5 4 [ [ & [ , 5 4 q x p e h u for example, assigning a higher priority value to irq[0] and a lower priority value to irq[1] means that irq[1] has higher priority than irq[0]. if both irq[1] and irq[0] are asserted, irq[1] is processed before irq[0]. if multiple pending exceptions have the same priority, the pending exception with the lowest exception number takes precedence. for example, if both irq[0] and irq[1] are pending and have the same priority, then irq[0] is processed before irq[1]. when the processor is executing an exception handler, the exception handler is preempted if a higher priority exception occurs. if an exception occurs with the same priority as the exception being handled, the handler is not preempted, irrespective of the exception number. however, the status of the new interrupt changes to pending. 2.5.6 interrupt priority grouping to increase priority control in systems with interrupts, the nvic supports priority grouping. this grouping divides each interrupt priority register entry into two fields: an upper field that defines the group priority a lower field that defines a subpriority within the group only the group priority determines preemption of interrupt exceptions. when the processor is executing an interrupt exception handler, another interrupt with the same group priority as the interrupt being handled does not preempt the handler. if multiple pending interrupts have the same group priority, the subpriority field determines the order in which they are processed. if multiple pending interrupts have the same group priority and subpriority, the interrupt with the lowest irq number is processed first. for information about splitting the interrupt priority fields into group priority and subpriority, see page 147. 2.5.7 exception entry and return descriptions of exception handling use the following terms: preemption. when the processor is executing an exception handler, an exception can preempt the exception handler if its priority is higher than the priority of the exception being handled. see interrupt priority grouping on page 103 for more information about preemption by an interrupt. when one exception preempts another, the exceptions are called nested exceptions. see exception entry on page 104 more information. return. return occurs when the exception handler is completed, and there is no pending exception with sufficient priority to be serviced and the completed exception handler was not handling a late-arriving exception. the processor pops the stack and restores the processor state to the state it had before the interrupt occurred. see exception return on page 105 for more information. tail-chaining. this mechanism speeds up exception servicing. on completion of an exception handler, if there is a pending exception that meets the requirements for exception entry, the stack pop is skipped and control transfers to the new exception handler. late-arriving. this mechanism speeds up preemption. if a higher priority exception occurs during state saving for a previous exception, the processor switches to handle the higher priority exception and initiates the vector fetch for that exception. state saving is not affected by late 103 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller arrival because the state saved is the same for both exceptions. therefore, the state saving continues uninterrupted. the processor can accept a late arriving exception until the first instruction of the exception handler of the original exception enters the execute stage of the processor. on return from the exception handler of the late-arriving exception, the normal tail-chaining rules apply. 2.5.7.1 exception entry exception entry occurs when there is a pending exception with sufficient priority and either the processor is in thread mode or the new exception is of higher priority than the exception being handled, in which case the new exception preempts the original exception. when one exception preempts another, the exceptions are nested. sufficient priority means the exception has more priority than any limits set by the mask registers (see primask on page 84, faultmask on page 85, and basepri on page 86). an exception with less priority than this is pending but is not handled by the processor. when the processor takes an exception, unless the exception is a tail-chained or a late-arriving exception, the processor pushes information onto the current stack. this operation is referred to as stacking and the structure of eight data words is referred to as stack frame . figure 2-7. exception stack frame immediately after stacking, the stack pointer indicates the lowest address in the stack frame. the stack frame includes the return address, which is the address of the next instruction in the interrupted program. this value is restored to the pc at exception return so that the interrupted program resumes. in parallel to the stacking operation, the processor performs a vector fetch that reads the exception handler start address from the vector table. when stacking is complete, the processor starts executing the exception handler. at the same time, the processor writes an exc_return value to the lr , indicating which stack pointer corresponds to the stack frame and what operation mode the processor was in before the entry occurred. if no higher-priority exception occurs during exception entry, the processor starts executing the exception handler and automatically changes the status of the corresponding pending interrupt to active. if another higher-priority exception occurs during exception entry, known as late arrival, the processor starts executing the exception handler for this exception and does not change the pending status of the earlier exception. july 03, 2014 104 texas instruments-production data the cortex-m3 processor 3 u h , 5 4 w r s r i v w d f n [ 3 6 5 3 & / 5 5 5 5 5 5 ^ d o l j q h u ` , 5 4 w r s r i v w d f n 2.5.7.2 exception return exception return occurs when the processor is in handler mode and executes one of the following instructions to load the exc_return value into the pc : an ldm or pop instruction that loads the pc a bx instruction using any register an ldr instruction with the pc as the destination exc_return is the value loaded into the lr on exception entry. the exception mechanism relies on this value to detect when the processor has completed an exception handler. the lowest four bits of this value provide information on the return stack and processor mode. table 2-10 on page 105 shows the exc_return values with a description of the exception return behavior. exc_return bits 31:4 are all set. when this value is loaded into the pc , it indicates to the processor that the exception is complete, and the processor initiates the appropriate exception return sequence. table 2-10. exception return behavior description exc_return[31:0] reserved 0xffff.fff0 return to handler mode. exception return uses state from msp . execution uses msp after return. 0xffff.fff1 reserved 0xffff.fff2 - 0xffff.fff8 return to thread mode. exception return uses state from msp . execution uses msp after return. 0xffff.fff9 reserved 0xffff.fffa - 0xffff.fffc return to thread mode. exception return uses state from psp . execution uses psp after return. 0xffff.fffd reserved 0xffff.fffe - 0xffff.ffff 2.6 fault handling faults are a subset of the exceptions (see exception model on page 97). the following conditions generate a fault: a bus error on an instruction fetch or vector table load or a data access. an internally detected error such as an undefined instruction or an attempt to change state with a bx instruction. attempting to execute an instruction from a memory region marked as non-executable (xn). an mpu fault because of a privilege violation or an attempt to access an unmanaged region. 105 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 2.6.1 fault types table 2-11 on page 106 shows the types of fault, the handler used for the fault, the corresponding fault status register, and the register bit that indicates the fault has occurred. see page 160 for more information about the fault status registers. table 2-11. faults bit name fault status register handler fault vect hard fault status (hfaultstat) hard fault bus error on a vector read forced hard fault status (hfaultstat) hard fault fault escalated to a hard fault ierr a memory management fault status (mfaultstat) memory management fault mpu or default memory mismatch on instruction access derr memory management fault status (mfaultstat) memory management fault mpu or default memory mismatch on data access mstke memory management fault status (mfaultstat) memory management fault mpu or default memory mismatch on exception stacking mustke memory management fault status (mfaultstat) memory management fault mpu or default memory mismatch on exception unstacking bstke bus fault status (bfaultstat) bus fault bus error during exception stacking bustke bus fault status (bfaultstat) bus fault bus error during exception unstacking ibus bus fault status (bfaultstat) bus fault bus error during instruction prefetch precise bus fault status (bfaultstat) bus fault precise data bus error impre bus fault status (bfaultstat) bus fault imprecise data bus error nocp usage fault status (ufaultstat) usage fault attempt to access a coprocessor undef usage fault status (ufaultstat) usage fault undefined instruction invstat usage fault status (ufaultstat) usage fault attempt to enter an invalid instruction set state b invpc usage fault status (ufaultstat) usage fault invalid exc_return value unalign usage fault status (ufaultstat) usage fault illegal unaligned load or store div0 usage fault status (ufaultstat) usage fault divide by 0 a. occurs on an access to an xn region even if the mpu is disabled. b. attempting to use an instruction set other than the thumb instruction set, or returning to a non load-store-multiple instruction with ici continuation. 2.6.2 fault escalation and hard faults all fault exceptions except for hard fault have configurable exception priority (see syspri1 on page 153). software can disable execution of the handlers for these faults (see syshndctrl on page 156). usually, the exception priority, together with the values of the exception mask registers, determines whether the processor enters the fault handler, and whether a fault handler can preempt another fault handler as described in exception model on page 97. in some situations, a fault with configurable priority is treated as a hard fault. this process is called priority escalation, and the fault is described as escalated to hard fault . escalation to hard fault occurs when: a fault handler causes the same kind of fault as the one it is servicing. this escalation to hard fault occurs because a fault handler cannot preempt itself because it must have the same priority as the current priority level. july 03, 2014 106 texas instruments-production data the cortex-m3 processor a fault handler causes a fault with the same or lower priority as the fault it is servicing. this situation happens because the handler for the new fault cannot preempt the currently executing fault handler. an exception handler causes a fault for which the priority is the same as or lower than the currently executing exception. a fault occurs and the handler for that fault is not enabled. if a bus fault occurs during a stack push when entering a bus fault handler, the bus fault does not escalate to a hard fault. thus if a corrupted stack causes a fault, the fault handler executes even though the stack push for the handler failed. the fault handler operates but the stack contents are corrupted. note: only reset and nmi can preempt the fixed priority hard fault. a hard fault can preempt any exception other than reset, nmi, or another hard fault. 2.6.3 fault status registers and fault address registers the fault status registers indicate the cause of a fault. for bus faults and memory management faults, the fault address register indicates the address accessed by the operation that caused the fault, as shown in table 2-12 on page 107. table 2-12. fault status and fault address registers register description address register name status register name handler page 166 - hard fault status (hfaultstat) hard fault page 160 page 167 memory management fault address (mmaddr) memory management fault status (mfaultstat) memory management fault page 160 page 168 bus fault address (faultaddr) bus fault status (bfaultstat) bus fault page 160 - usage fault status (ufaultstat) usage fault 2.6.4 lockup the processor enters a lockup state if a hard fault occurs when executing the nmi or hard fault handlers. when the processor is in the lockup state, it does not execute any instructions. the processor remains in lockup state until it is reset, an nmi occurs, or it is halted by a debugger. note: if the lockup state occurs from the nmi handler, a subsequent nmi does not cause the processor to leave the lockup state. 2.7 power management the cortex-m3 processor sleep modes reduce power consumption: sleep mode stops the processor clock. deep-sleep mode stops the system clock and switches off the pll and flash memory. the sleepdeep bit of the system control (sysctrl) register selects which sleep mode is used (see page 149). for more information about the behavior of the sleep modes, see system control on page 203. 107 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller this section describes the mechanisms for entering sleep mode and the conditions for waking up from sleep mode, both of which apply to sleep mode and deep-sleep mode. 2.7.1 entering sleep modes this section describes the mechanisms software can use to put the processor into one of the sleep modes. the system can generate spurious wake-up events, for example a debug operation wakes up the processor. therefore, software must be able to put the processor back into sleep mode after such an event. a program might have an idle loop to put the processor back to sleep mode. 2.7.1.1 wait for interrupt the wait for interrupt instruction, wfi , causes immediate entry to sleep mode unless the wake-up condition is true (see wake up from wfi or sleep-on-exit on page 108). when the processor executes a wfi instruction, it stops executing instructions and enters sleep mode. see the cortex?-m3/m4 instruction set technical user's manual for more information. 2.7.1.2 wait for event the wait for event instruction, wfe , causes entry to sleep mode conditional on the value of a one-bit event register. when the processor executes a wfe instruction, it checks the event register. if the register is 0, the processor stops executing instructions and enters sleep mode. if the register is 1, the processor clears the register and continues executing instructions without entering sleep mode. if the event register is 1, the processor must not enter sleep mode on execution of a wfe instruction. typically, this situation occurs if an sev instruction has been executed. software cannot access this register directly. see the cortex?-m3/m4 instruction set technical user's manual for more information. 2.7.1.3 sleep-on-exit if the sleepexit bit of the sysctrl register is set, when the processor completes the execution of all exception handlers, it returns to thread mode and immediately enters sleep mode. this mechanism can be used in applications that only require the processor to run when an exception occurs. 2.7.2 wake up from sleep mode the conditions for the processor to wake up depend on the mechanism that cause it to enter sleep mode. 2.7.2.1 wake up from wfi or sleep-on-exit normally, the processor wakes up only when the nvic detects an exception with sufficient priority to cause exception entry. some embedded systems might have to execute system restore tasks after the processor wakes up and before executing an interrupt handler. entry to the interrupt handler can be delayed by setting the primask bit and clearing the faultmask bit. if an interrupt arrives that is enabled and has a higher priority than current exception priority, the processor wakes up but does not execute the interrupt handler until the processor clears primask . for more information about primask and faultmask , see page 84 and page 85. 2.7.2.2 wake up from wfe the processor wakes up if it detects an exception with sufficient priority to cause exception entry. july 03, 2014 108 texas instruments-production data the cortex-m3 processor in addition, if the sevonpend bit in the sysctrl register is set, any new pending interrupt triggers an event and wakes up the processor, even if the interrupt is disabled or has insufficient priority to cause exception entry. for more information about sysctrl , see page 149. 2.8 instruction set summary the processor implements a version of the thumb instruction set. table 2-13 on page 109 lists the supported instructions. note: in table 2-13 on page 109: angle brackets, <>, enclose alternative forms of the operand braces, {}, enclose optional operands the operands column is not exhaustive op2 is a flexible second operand that can be either a register or a constant most instructions can use an optional condition code suffix for more information on the instructions and operands, see the instruction descriptions in the cortex?-m3/m4 instruction set technical user's manual . table 2-13. cortex-m3 instruction summary flags brief description operands mnemonic n,z,c,v add with carry {rd,} rn, op2 adc, adcs n,z,c,v add {rd,} rn, op2 add, adds n,z,c,v add {rd,} rn , #imm12 add, addw - load pc-relative address rd, label adr n,z,c logical and {rd,} rn, op2 and, ands n,z,c arithmetic shift right rd, rm, table 2-13. cortex-m3 instruction summary (continued) flags brief description operands mnemonic n,z,c exclusive or {rd,} rn, op2 eor, eors - instruction synchronization barrier - isb - if-then condition block - it - load multiple registers, increment after rn{!}, reglist ldm - load multiple registers, decrement before rn{!}, reglist ldmdb, ldmea - load multiple registers, increment after rn{!}, reglist ldmfd, ldmia - load register with word rt, [rn, #offset] ldr - load register with byte rt, [rn, #offset] ldrb, ldrbt - load register with two bytes rt, rt2, [rn, #offset] ldrd - load register exclusive rt, [rn, #offset] ldrex - load register exclusive with byte rt, [rn] ldrexb - load register exclusive with halfword rt, [rn] ldrexh - load register with halfword rt, [rn, #offset] ldrh, ldrht - load register with signed byte rt, [rn, #offset] ldrsb, ldrsbt - load register with signed halfword rt, [rn, #offset] ldrsh, ldrsht - load register with word rt, [rn, #offset] ldrt n,z,c logical shift left rd, rm, table 2-13. cortex-m3 instruction summary (continued) flags brief description operands mnemonic n,z,c,v reverse subtract {rd,} rn, op2 rsb, rsbs n,z,c,v subtract with carry {rd,} rn, op2 sbc, sbcs - signed bit field extract rd, rn, #lsb, #width sbfx - signed divide {rd,} rn, rm sdiv - send event - sev - signed multiply with accumulate (32x32+64), 64-bit result rdlo, rdhi, rn, rm smlal - signed multiply (32x32), 64-bit result rdlo, rdhi, rn, rm smull q signed saturate rd, #n, rm {,shift #s} ssat - store multiple registers, increment after rn{!}, reglist stm - store multiple registers, decrement before rn{!}, reglist stmdb, stmea - store multiple registers, increment after rn{!}, reglist stmfd, stmia - store register word rt, [rn {, #offset}] str - store register byte rt, [rn {, #offset}] strb, strbt - store register two words rt, rt2, [rn {, #offset}] strd - store register exclusive rt, rt, [rn {, #offset}] strex - store register exclusive byte rd, rt, [rn] strexb - store register exclusive halfword rd, rt, [rn] strexh - store register halfword rt, [rn {, #offset}] strh, strht - store register signed byte rt, [rn {, #offset}] strsb, strsbt - store register signed halfword rt, [rn {, #offset}] strsh, strsht - store register word rt, [rn {, #offset}] strt n,z,c,v subtract {rd,} rn, op2 sub, subs n,z,c,v subtract 12-bit constant {rd,} rn, #imm12 sub, subw - supervisor call #imm svc - sign extend a byte {rd,} rm {,ror #n} sxtb - sign extend a halfword {rd,} rm {,ror #n} sxth - table branch byte [rn, rm] tbb - table branch halfword [rn, rm, lsl #1] tbh n,z,c test equivalence rn, op2 teq n,z,c test rn, op2 tst - unsigned bit field extract rd, rn, #lsb, #width ubfx - unsigned divide {rd,} rn, rm udiv - unsigned multiply with accumulate (32x32+32+32), 64-bit result rdlo, rdhi, rn, rm umlal - unsigned multiply (32x 2), 64-bit result rdlo, rdhi, rn, rm umull q unsigned saturate rd, #n, rm {,shift #s} usat - zero extend a byte {rd,} rm, {,ror #n} uxtb - zero extend a halfword {rd,} rm, {,ror #n} uxth - wait for event - wfe - wait for interrupt - wfi 111 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 3 cortex-m3 peripherals this chapter provides information on the stellaris ? implementation of the cortex-m3 processor peripherals, including: systick (see page 112) provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. nested vectored interrupt controller (nvic) (see page 113) C facilitates low-latency exception and interrupt handling C controls power management C implements system control registers system control block (scb) (see page 115) provides system implementation information and system control, including configuration, control, and reporting of system exceptions. memory protection unit (mpu) (see page 115) supports the standard armv7 protected memory system architecture (pmsa) model. the mpu provides full support for protection regions, overlapping protection regions, access permissions, and exporting memory attributes to the system. table 3-1 on page 112 shows the address map of the private peripheral bus (ppb). some peripheral register regions are split into two address regions, as indicated by two addresses listed. table 3-1. core peripheral register regions description (see page ...) core peripheral address 112 system timer 0xe000.e010-0xe000.e01f 113 nested vectored interrupt controller 0xe000.e100-0xe000.e4ef 0xe000.ef00-0xe000.ef03 115 system control block 0xe000.e008-0xe000.e00f 0xe000.ed00-0xe000.ed3f 115 memory protection unit 0xe000.ed90-0xe000.edb8 3.1 functional description this chapter provides information on the stellaris implementation of the cortex-m3 processor peripherals: systick, nvic, scb and mpu. 3.1.1 system timer (systick) cortex-m3 includes an integrated system timer, systick, which provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. the counter can be used in several different ways, for example as: an rtos tick timer that fires at a programmable rate (for example, 100 hz) and invokes a systick routine. a high-speed alarm timer using the system clock. july 03, 2014 112 texas instruments-production data cortex-m3 peripherals a variable rate alarm or signal timerthe duration is range-dependent on the reference clock used and the dynamic range of the counter. a simple counter used to measure time to completion and time used. an internal clock source control based on missing/meeting durations. the count bit in the stctrl control and status register can be used to determine if an action completed within a set duration, as part of a dynamic clock management control loop. the timer consists of three registers: systick control and status (stctrl) : a control and status counter to configure its clock, enable the counter, enable the systick interrupt, and determine counter status. systick reload value (streload) : the reload value for the counter, used to provide the counter's wrap value. systick current value (stcurrent) : the current value of the counter. when enabled, the timer counts down on each clock from the reload value to zero, reloads (wraps) to the value in the streload register on the next clock edge, then decrements on subsequent clocks. clearing the streload register disables the counter on the next wrap. when the counter reaches zero, the count status bit is set. the count bit clears on reads. writing to the stcurrent register clears the register and the count status bit. the write does not trigger the systick exception logic. on a read, the current value is the value of the register at the time the register is accessed. the systick counter runs on the system clock. if this clock signal is stopped for low power mode, the systick counter stops. ensure software uses aligned word accesses to access the systick registers. note: when the processor is halted for debugging, the counter does not decrement. 3.1.2 nested vectored interrupt controller (nvic) this section describes the nested vectored interrupt controller (nvic) and the registers it uses. the nvic supports: 53 interrupts. a programmable priority level of 0-7 for each interrupt. a higher level corresponds to a lower priority, so level 0 is the highest interrupt priority. low-latency exception and interrupt handling. level and pulse detection of interrupt signals. dynamic reprioritization of interrupts. grouping of priority values into group priority and subpriority fields. interrupt tail-chaining. an external non-maskable interrupt (nmi). 113 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller the processor automatically stacks its state on exception entry and unstacks this state on exception exit, with no instruction overhead, providing low latency exception handling. 3.1.2.1 level-sensitive and pulse interrupts the processor supports both level-sensitive and pulse interrupts. pulse interrupts are also described as edge-triggered interrupts. a level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal. typically this happens because the isr accesses the peripheral, causing it to clear the interrupt request. a pulse interrupt is an interrupt signal sampled synchronously on the rising edge of the processor clock. to ensure the nvic detects the interrupt, the peripheral must assert the interrupt signal for at least one clock cycle, during which the nvic detects the pulse and latches the interrupt. when the processor enters the isr, it automatically removes the pending state from the interrupt (see hardware and software control of interrupts on page 114 for more information). for a level-sensitive interrupt, if the signal is not deasserted before the processor returns from the isr, the interrupt becomes pending again, and the processor must execute its isr again. as a result, the peripheral can hold the interrupt signal asserted until it no longer needs servicing. 3.1.2.2 hardware and software control of interrupts the cortex-m3 latches all interrupts. a peripheral interrupt becomes pending for one of the following reasons: the nvic detects that the interrupt signal is high and the interrupt is not active. the nvic detects a rising edge on the interrupt signal. software writes to the corresponding interrupt set-pending register bit, or to the software trigger interrupt (swtrig) register to make a software-generated interrupt pending. see the int bit in the pend0 register on page 131 or swtrig on page 139. a pending interrupt remains pending until one of the following: the processor enters the isr for the interrupt, changing the state of the interrupt from pending to active. then: C for a level-sensitive interrupt, when the processor returns from the isr, the nvic samples the interrupt signal. if the signal is asserted, the state of the interrupt changes to pending, which might cause the processor to immediately re-enter the isr. otherwise, the state of the interrupt changes to inactive. C for a pulse interrupt, the nvic continues to monitor the interrupt signal, and if this is pulsed the state of the interrupt changes to pending and active. in this case, when the processor returns from the isr the state of the interrupt changes to pending, which might cause the processor to immediately re-enter the isr. if the interrupt signal is not pulsed while the processor is in the isr, when the processor returns from the isr the state of the interrupt changes to inactive. software writes to the corresponding interrupt clear-pending register bit C for a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt does not change. otherwise, the state of the interrupt changes to inactive. july 03, 2014 114 texas instruments-production data cortex-m3 peripherals C for a pulse interrupt, the state of the interrupt changes to inactive, if the state was pending or to active, if the state was active and pending. 3.1.3 system control block (scb) the system control block (scb) provides system implementation information and system control, including configuration, control, and reporting of the system exceptions. 3.1.4 memory protection unit (mpu) this section describes the memory protection unit (mpu). the mpu divides the memory map into a number of regions and defines the location, size, access permissions, and memory attributes of each region. the mpu supports independent attribute settings for each region, overlapping regions, and export of memory attributes to the system. the memory attributes affect the behavior of memory accesses to the region. the cortex-m3 mpu defines eight separate memory regions, 0-7, and a background region. when memory regions overlap, a memory access is affected by the attributes of the region with the highest number. for example, the attributes for region 7 take precedence over the attributes of any region that overlaps region 7. the background region has the same memory access attributes as the default memory map, but is accessible from privileged software only. the cortex-m3 mpu memory map is unified, meaning that instruction accesses and data accesses have the same region settings. if a program accesses a memory location that is prohibited by the mpu, the processor generates a memory management fault, causing a fault exception and possibly causing termination of the process in an os environment. in an os environment, the kernel can update the mpu region setting dynamically based on the process to be executed. typically, an embedded os uses the mpu for memory protection. configuration of mpu regions is based on memory types (see memory regions, types and attributes on page 90 for more information). table 3-2 on page 115 shows the possible mpu region attributes. see the section called mpu configuration for a stellaris microcontroller on page 119 for guidelines for programming a microcontroller implementation. table 3-2. memory attributes summary description memory type all accesses to strongly ordered memory occur in program order. strongly ordered memory-mapped peripherals device normal memory normal to avoid unexpected behavior, disable the interrupts before updating the attributes of a region that the interrupt handlers might access. ensure software uses aligned accesses of the correct size to access mpu registers: except for the mpu region attribute and size (mpuattr) register, all mpu registers must be accessed with aligned word accesses. the mpuattr register can be accessed with byte or aligned halfword or word accesses. 115 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller the processor does not support unaligned accesses to mpu registers. when setting up the mpu, and if the mpu has previously been programmed, disable unused regions to prevent any previous region settings from affecting the new mpu setup. 3.1.4.1 updating an mpu region to update the attributes for an mpu region, the mpu region number (mpunumber) , mpu region base address (mpubase) and mpuattr registers must be updated. each register can be programmed separately or with a multiple-word write to program all of these registers. you can use the mpubasex and mpuattrx aliases to program up to four regions simultaneously using an stm instruction. updating an mpu region using separate words this example simple code configures one region: ; r1 = region number ; r2 = size/enable ; r3 = attributes ; r4 = address ldr r0,=mpunumber ; 0xe000ed98, mpu region number register str r1, [r0, #0x0] ; region number str r4, [r0, #0x4] ; region base address strh r2, [r0, #0x8] ; region size and enable strh r3, [r0, #0xa] ; region attribute disable a region before writing new region settings to the mpu if you have previously enabled the region being changed. for example: ; r1 = region number ; r2 = size/enable ; r3 = attributes ; r4 = address ldr r0,=mpunumber ; 0xe000ed98, mpu region number register str r1, [r0, #0x0] ; region number bic r2, r2, #1 ; disable strh r2, [r0, #0x8] ; region size and enable str r4, [r0, #0x4] ; region base address strh r3, [r0, #0xa] ; region attribute orr r2, #1 ; enable strh r2, [r0, #0x8] ; region size and enable software must use memory barrier instructions: before mpu setup, if there might be outstanding memory transfers, such as buffered writes, that might be affected by the change in mpu settings. after mpu setup, if it includes memory transfers that must use the new mpu settings. however, memory barrier instructions are not required if the mpu setup process starts by entering an exception handler, or is followed by an exception return, because the exception entry and exception return mechanism cause memory barrier behavior. software does not need any memory barrier instructions during mpu setup, because it accesses the mpu through the private peripheral bus (ppb), which is a strongly ordered memory region. july 03, 2014 116 texas instruments-production data cortex-m3 peripherals for example, if all of the memory access behavior is intended to take effect immediately after the programming sequence, then a dsb instruction and an isb instruction should be used. a dsb is required after changing mpu settings, such as at the end of context switch. an isb is required if the code that programs the mpu region or regions is entered using a branch or call. if the programming sequence is entered using a return from exception, or by taking an exception, then an isb is not required. updating an mpu region using multi-word writes the mpu can be programmed directly using multi-word writes, depending how the information is divided. consider the following reprogramming: ; r1 = region number ; r2 = address ; r3 = size, attributes in one ldr r0, =mpunumber ; 0xe000ed98, mpu region number register str r1, [r0, #0x0] ; region number str r2, [r0, #0x4] ; region base address str r3, [r0, #0x8] ; region attribute, size and enable an stm instruction can be used to optimize this: ; r1 = region number ; r2 = address ; r3 = size, attributes in one ldr r0, =mpunumber ; 0xe000ed98, mpu region number register stm r0, {r1-r3} ; region number, address, attribute, size and enable this operation can be done in two words for pre-packed information, meaning that the mpu region base address (mpubase) register (see page 173) contains the required region number and has the valid bit set. this method can be used when the data is statically packed, for example in a boot loader: ; r1 = address and region number in one ; r2 = size and attributes in one ldr r0, =mpubase ; 0xe000ed9c, mpu region base register str r1, [r0, #0x0] ; region base address and region number combined ; with valid (bit 4) set str r2, [r0, #0x4] ; region attribute, size and enable subregions regions of 256 bytes or more are divided into eight equal-sized subregions. set the corresponding bit in the srd field of the mpu region attribute and size (mpuattr) register (see page 175) to disable a subregion. the least-significant bit of the srd field controls the first subregion, and the most-significant bit controls the last subregion. disabling a subregion means another region overlapping the disabled range matches instead. if no other enabled region overlaps the disabled subregion, the mpu issues a fault. regions of 32, 64, and 128 bytes do not support subregions. with regions of these sizes, the srd field must be configured to 0x00 , otherwise the mpu behavior is unpredictable. 117 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller example of srd use two regions with the same base address overlap. region one is 128 kb, and region two is 512 kb. to ensure the attributes from region one apply to the first 128 kb region, configure the srd field for region two to 0x03 to disable the first two subregions, as figure 3-1 on page 118 shows. figure 3-1. srd use example 3.1.4.2 mpu access permission attributes the access permission bits, tex, s, c, b, ap , and xn of the mpuattr register, control access to the corresponding memory region. if an access is made to an area of memory without the required permissions, then the mpu generates a permission fault. table 3-3 on page 118 shows the encodings for the tex, c, b , and s access permission bits. all encodings are shown for completeness, however the current implementation of the cortex-m3 does not support the concept of cacheability or shareability. refer to the section called mpu configuration for a stellaris microcontroller on page 119 for information on programming the mpu for stellaris implementations. table 3-3. tex, s, c, and b bit field encoding other attributes shareability memory type bc s tex - shareable strongly ordered 00 x a 000b - shareable device 10 x a 000 outer and inner write-through. no write allocate. not shareable normal 01 0 000 shareable normal 01 1 000 not shareable normal 11 0 000 shareable normal 11 1 000 outer and inner noncacheable. not shareable normal 00 0 001 shareable normal 00 1 001 - - reserved encoding 10 x a 001 - - reserved encoding 01 x a 001 outer and inner write-back. write and read allocate. not shareable normal 11 0 001 shareable normal 11 1 001 nonshared device. not shareable device 00 x a 010 - - reserved encoding 10 x a 010 - - reserved encoding x a 1 x a 010 july 03, 2014 118 texas instruments-production data cortex-m3 peripherals 5 h j l r q ' l v d e o h g v x e u h j l r q ' l v d e o h g v x e u h j l r q 5 h j l r q z l w k v x e u h j l r q v % d v h d g g u h v v r i e r w k u h j l r q v 2 i i v h w i u r p e d v h d g g u h v v . % . % . % . % . % . % . % . % table 3-3. tex, s, c, and b bit field encoding (continued) other attributes shareability memory type bc s tex cached memory (bb = outer policy, aa = inner policy). see table 3-4 for the encoding of the aa and bb bits. not shareable normal aa 0 1bb shareable normal aa 1 1bb a. the mpu ignores the value of this bit. table 3-4 on page 119 shows the cache policy for memory attribute encodings with a tex value in the range of 0x4-0x7. table 3-4. cache policy for memory attribute encoding corresponding cache policy encoding, aa or bb non-cacheable 00 write back, write and read allocate 01 write through, no write allocate 10 write back, no write allocate 11 table 3-5 on page 119 shows the ap encodings in the mpuattr register that define the access permissions for privileged and unprivileged software. table 3-5. ap bit field encoding description unprivileged permissions privileged permissions ap bit field all accesses generate a permission fault. no access no access 000 access from privileged software only. no access r/w 001 writes by unprivileged software generate a permission fault. ro r/w 010 full access. r/w r/w 011 reserved. unpredictable unpredictable 100 reads by privileged software only. no access ro 101 read-only, by privileged or unprivileged software. ro ro 110 read-only, by privileged or unprivileged software. ro ro 111 mpu configuration for a stellaris microcontroller stellaris microcontrollers have only a single processor and no caches. as a result, the mpu should be programmed as shown in table 3-6 on page 119. table 3-6. memory region attributes for stellaris microcontrollers memory type and attributes bcs tex memory region normal memory, non-shareable, write-through 010 000b flash memory normal memory, shareable, write-through 011 000b internal sram normal memory, shareable, write-back, write-allocate 111 000b external sram device memory, shareable 101 000b peripherals 119 july 03, 2014 texas instruments-production data stellaris lm3s9gn5 microcontroller in current stellaris microcontroller implementations, the shareability and cache policy attributes do not affect the system behavior. however, using these settings for the mpu regions can make the application code more portable. the values given are for typical situations. 3.1.4.3 mpu mismatch when an access violates the mpu permissions, the processor generates a memory management fault (see exceptions and interrupts on page 88 for more information). the mfaultstat register indicates the cause of the fault. see page 160 for more information. 3.2 register map table 3-7 on page 120 lists the cortex-m3 peripheral systick, nvic, mpu and scb registers. the offset listed is a hexadecimal increment to the register's address, relative to the core peripherals base address of 0xe000.e000. note: register spaces that are not used are reserved for future or internal use. software should not modify any reserved memory address. table 3-7. peripherals register map see page description reset type name offset system timer (systick) registers 123 systick control and status register 0x0000.0004 r/w stctrl 0x010 125 systick reload value register 0x0000.0000 r/w streload 0x014 126 systick current value register 0x0000.0000 r/wc stcurrent 0x018 nested vectored interrupt controller (nvic) registers 127 interrupt 0-31 set enable 0x0000.0000 r/w en0 0x100 128 interrupt 32-54 set enable 0x0000.0000 r/w en1 0x104 129 interrupt 0-31 clear enable 0x0000.0000 r/w dis0 0x180 130 interrupt 32-54 clear enable 0x0000.0000 r/w dis1 0x184 131 interrupt 0-31 set pending 0x0000.0000 r/w pend0 0x200 132 interrupt 32-54 set pending 0x0000.0000 r/w pend1 0x204 133 interrupt 0-31 clear pending 0x0000.0000 r/w unpend0 0x280 134 interrupt 32-54 clear pending 0x0000.0000 r/w unpend1 0x284 135 interrupt 0-31 active bit 0x0000.0000 ro active0 0x300 136 interrupt 32-54 active bit 0x0000.0000 ro active1 0x304 137 interrupt 0-3 priority 0x0000.0000 r/w pri0 0x400 137 interrupt 4-7 priority 0x0000.0000 r/w pri1 0x404 137 interrupt 8-11 priority 0x0000.0000 r/w pri2 0x408 137 interrupt 12-15 priority 0x0000.0000 r/w pri3 0x40c 137 interrupt 16-19 priority 0x0000.0000 r/w pri4 0x410 july 03, 2014 120 texas instruments-production data cortex-m3 peripherals table 3-7. peripherals register map (continued) see page description reset type name offset 137 interrupt 20-23 priority 0x0000.0000 r/w pri5 0x414 137 interrupt 24-27 priority 0x0000.0000 r/w pri6 0x418 137 interrupt 28-31 priority 0x0000.0000 r/w pri7 0x41c 137 interrupt 32-35 priority 0x0000.0000 r/w pri8 0x420 137 interrupt 36-39 priority 0x0000.0000 r/w pri9 0x424 137 interrupt 40-43 priority 0x0000.0000 r/w pri10 0x428 137 interrupt 44-47 priority 0x0000.0000 r/w pri11 0x42c 137 interrupt 48-51 priority 0x0000.0000 r/w pri12 0x430 137 interrupt 52-54 priority 0x0000.0000 r/w pri13 0x434 139 software trigger interrupt 0x0000.0000 wo swtrig 0xf00 system control block (scb) registers 140 auxiliary control 0x0000.0000 r/w actlr 0x008 142 cpu id base 0x412f.c230 ro cpuid 0xd00 143 interrupt control and state 0x0000.0000 r/w intctrl 0xd04 146 vector table offset 0x0000.0000 r/w vtable 0xd08 147 application interrupt and reset control 0xfa05.0000 r/w apint 0xd0c 149 system control 0x0000.0000 r/w sysctrl 0xd10 151 configuration and control 0x0000.0200 r/w cfgctrl 0xd14 153 system handler priority 1 0x0000.0000 r/w syspri1 0xd18 154 system handler priority 2 0x0000.0000 r/w syspri2 0xd1c 155 system handler priority 3 0x0000.0000 r/w syspri3 0xd20 156 system handler control and state 0x0000.0000 r/w syshndctrl 0xd24 160 configurable fault status 0x0000.0000 r/w1c faultstat 0xd28 166 hard fault status 0x0000.0000 r/w1c hfaultstat 0xd2c 167 memory management fault address - r/w mmaddr 0xd34 168 bus fault address - r/w faultaddr 0xd38 memory protection unit (mpu) registers 169 mpu type 0x0000.0800 ro mputype 0xd90 170 mpu control 0x0000.0000 r/w mpuctrl 0xd94 172 mpu region number 0x0000.0000 r/w mpunumber 0xd98 173 mpu region base address 0x0000.0000 r/w mpubase 0xd9c 175 mpu region attribute and size 0x0000.0000 r/w mpuattr 0xda0 121 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 3-7. peripherals register map (continued) see page description reset type name offset 173 mpu region base address alias 1 0x0000.0000 r/w mpubase1 0xda4 175 mpu region attribute and size alias 1 0x0000.0000 r/w mpuattr1 0xda8 173 mpu region base address alias 2 0x0000.0000 r/w mpubase2 0xdac 175 mpu region attribute and size alias 2 0x0000.0000 r/w mpuattr2 0xdb0 173 mpu region base address alias 3 0x0000.0000 r/w mpubase3 0xdb4 175 mpu region attribute and size alias 3 0x0000.0000 r/w mpuattr3 0xdb8 3.3 system timer (systick) register descriptions this section lists and describes the system timer registers, in numerical order by address offset. july 03, 2014 122 texas instruments-production data cortex-m3 peripherals register 1: systick control and status register (stctrl), offset 0x010 note: this register can only be accessed from privileged mode. the systick stctrl register enables the systick features. systick control and status register (stctrl) base 0xe000.e000 offset 0x010 type r/w, reset 0x0000.0004 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 count reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 enable inten clk_src reserved r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 31:17 count flag description value the systick timer has not counted to 0 since the last time this bit was read. 0 the systick timer has counted to 0 since the last time this bit was read. 1 this bit is cleared by a read of the register or if the stcurrent register is written with any value. if read by the debugger using the dap, this bit is cleared only if the mastertype bit in the ahb-ap control register is clear. otherwise, the count bit is not changed by the debugger read. see the arm? debug interface v5 architecture specification for more information on mastertype. 0 ro count 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 15:3 clock source description value external reference clock. (not implemented for most stellaris microcontrollers.) 0 system clock 1 because an external reference clock is not implemented, this bit must be set in order for systick to operate. 1 r/w clk_src 2 123 july 03, 2014 texas instruments-production data stellaris ? description reset type name bit/field interrupt enable description value interrupt generation is disabled. software can use the count bit to determine if the counter has ever reached 0. 0 an interrupt is generated to the nvic when systick counts to 0. 1 0 r/w inten 1 enable description value the counter is disabled. 0 enables systick to operate in a multi-shot way. that is, the counter loads the reload value and begins counting down. on reaching 0, the count bit is set and an interrupt is generated if enabled by inten . the counter then loads the reload value again and begins counting. 1 0 r/w enable 0 july 03, 2014 124 texas instruments-production data cortex-m3 peripherals register 2: systick reload value register (streload), offset 0x014 note: this register can only be accessed from privileged mode. the streload register specifies the start value to load into the systick current value (stcurrent) register when the counter reaches 0. the start value can be between 0x1 and 0x00ff.ffff. a start value of 0 is possible but has no effect because the systick interrupt and the count bit are activated when counting from 1 to 0. systick can be configured as a multi-shot timer, repeated over and over, firing every n+1 clock pulses, where n is any value from 1 to 0x00ff.ffff. for example, if a tick interrupt is required every 100 clock pulses, 99 must be written into the reload field. systick reload value register (streload) base 0xe000.e000 offset 0x014 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reload reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reload r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:24 reload value value to load into the systick current value (stcurrent) register when the counter reaches 0. 0x00.0000 r/w reload 23:0 125 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 3: systick current value register (stcurrent), offset 0x018 note: this register can only be accessed from privileged mode. the stcurrent register contains the current value of the systick counter. systick current value register (stcurrent) base 0xe000.e000 offset 0x018 type r/wc, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 current reserved r/wc r/wc r/wc r/wc r/wc r/wc r/wc r/wc ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 current r/wc r/wc r/wc r/wc r/wc r/wc r/wc r/wc r/wc r/wc r/wc r/wc r/wc r/wc r/wc r/wc type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:24 current value this field contains the current value at the time the register is accessed. no read-modify-write protection is provided, so change with care. this register is write-clear. writing to it with any value clears the register. clearing this register also clears the count bit of the stctrl register. 0x00.0000 r/wc current 23:0 3.4 nvic register descriptions this section lists and describes the nvic registers, in numerical order by address offset. the nvic registers can only be fully accessed from privileged mode, but interrupts can be pended while in unprivileged mode by enabling the configuration and control (cfgctrl) register. any other unprivileged mode access causes a bus fault. ensure software uses correctly aligned register accesses. the processor does not support unaligned accesses to nvic registers. an interrupt can enter the pending state even if it is disabled. before programming the vtable register to relocate the vector table, ensure the vector table entries of the new vector table are set up for fault handlers, nmi, and all enabled exceptions such as interrupts. for more information, see page 146. july 03, 2014 126 texas instruments-production data cortex-m3 peripherals register 4: interrupt 0-31 set enable (en0), offset 0x100 note: this register can only be accessed from privileged mode. see table 2-9 on page 100 for interrupt assignments. if a pending interrupt is enabled, the nvic activates the interrupt based on its priority. if an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the nvic never activates the interrupt, regardless of its priority. interrupt 0-31 set enable (en0) base 0xe000.e000 offset 0x100 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 int r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 int r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field interrupt enable description value on a read, indicates the interrupt is disabled. on a write, no effect. 0 on a read, indicates the interrupt is enabled. on a write, enables the interrupt. 1 a bit can only be cleared by setting the corresponding int[n] bit in the disn register. 0x0000.0000 r/w int 31:0 127 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 5: interrupt 32-54 set enable (en1), offset 0x104 note: this register can only be accessed from privileged mode. the en1 register enables interrupts and shows which interrupts are enabled. bit 0 corresponds to interrupt 32; bit 22 corresponds to interrupt 54. see table 2-9 on page 100 for interrupt assignments. if a pending interrupt is enabled, the nvic activates the interrupt based on its priority. if an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the nvic never activates the interrupt, regardless of its priority. interrupt 32-54 set enable (en1) base 0xe000.e000 offset 0x104 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 int reserved r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 int r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:23 interrupt enable description value on a read, indicates the interrupt is disabled. on a write, no effect. 0 on a read, indicates the interrupt is enabled. on a write, enables the interrupt. 1 a bit can only be cleared by setting the corresponding int[n] bit in the dis1 register. 0x00.0000 r/w int 22:0 july 03, 2014 128 texas instruments-production data cortex-m3 peripherals register 6: interrupt 0-31 clear enable (dis0), offset 0x180 note: this register can only be accessed from privileged mode. see table 2-9 on page 100 for interrupt assignments. interrupt 0-31 clear enable (dis0) base 0xe000.e000 offset 0x180 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 int r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 int r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field interrupt disable description value on a read, indicates the interrupt is disabled. on a write, no effect. 0 on a read, indicates the interrupt is enabled. on a write, clears the corresponding int[n] bit in the en0 register, disabling interrupt [n]. 1 0x0000.0000 r/w int 31:0 129 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 7: interrupt 32-54 clear enable (dis1), offset 0x184 note: this register can only be accessed from privileged mode. the dis1 register disables interrupts. bit 0 corresponds to interrupt 32; bit 22 corresponds to interrupt 54. see table 2-9 on page 100 for interrupt assignments. interrupt 32-54 clear enable (dis1) base 0xe000.e000 offset 0x184 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 int reserved r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 int r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:23 interrupt disable description value on a read, indicates the interrupt is disabled. on a write, no effect. 0 on a read, indicates the interrupt is enabled. on a write, clears the corresponding int[n] bit in the en1 register, disabling interrupt [n]. 1 0x00.0000 r/w int 22:0 july 03, 2014 130 texas instruments-production data cortex-m3 peripherals register 8: interrupt 0-31 set pending (pend0), offset 0x200 note: this register can only be accessed from privileged mode. see table 2-9 on page 100 for interrupt assignments. interrupt 0-31 set pending (pend0) base 0xe000.e000 offset 0x200 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 int r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 int r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field interrupt set pending description value on a read, indicates that the interrupt is not pending. on a write, no effect. 0 on a read, indicates that the interrupt is pending. on a write, the corresponding interrupt is set to pending even if it is disabled. 1 if the corresponding interrupt is already pending, setting a bit has no effect. a bit can only be cleared by setting the corresponding int[n] bit in the unpend0 register. 0x0000.0000 r/w int 31:0 131 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 9: interrupt 32-54 set pending (pend1), offset 0x204 note: this register can only be accessed from privileged mode. the pend1 register forces interrupts into the pending state and shows which interrupts are pending. bit 0 corresponds to interrupt 32; bit 22 corresponds to interrupt 54. see table 2-9 on page 100 for interrupt assignments. interrupt 32-54 set pending (pend1) base 0xe000.e000 offset 0x204 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 int reserved r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 int r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:23 interrupt set pending description value on a read, indicates that the interrupt is not pending. on a write, no effect. 0 on a read, indicates that the interrupt is pending. on a write, the corresponding interrupt is set to pending even if it is disabled. 1 if the corresponding interrupt is already pending, setting a bit has no effect. a bit can only be cleared by setting the corresponding int[n] bit in the unpend1 register. 0x00.0000 r/w int 22:0 july 03, 2014 132 texas instruments-production data cortex-m3 peripherals register 10: interrupt 0-31 clear pending (unpend0), offset 0x280 note: this register can only be accessed from privileged mode. see table 2-9 on page 100 for interrupt assignments. interrupt 0-31 clear pending (unpend0) base 0xe000.e000 offset 0x280 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 int r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 int r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field interrupt clear pending description value on a read, indicates that the interrupt is not pending. on a write, no effect. 0 on a read, indicates that the interrupt is pending. on a write, clears the corresponding int[n] bit in the pend0 register, so that interrupt [n] is no longer pending. setting a bit does not affect the active state of the corresponding interrupt. 1 0x0000.0000 r/w int 31:0 133 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 11: interrupt 32-54 clear pending (unpend1), offset 0x284 note: this register can only be accessed from privileged mode. the unpend1 register shows which interrupts are pending and removes the pending state from interrupts. bit 0 corresponds to interrupt 32; bit 22 corresponds to interrupt 54. see table 2-9 on page 100 for interrupt assignments. interrupt 32-54 clear pending (unpend1) base 0xe000.e000 offset 0x284 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 int reserved r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 int r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:23 interrupt clear pending description value on a read, indicates that the interrupt is not pending. on a write, no effect. 0 on a read, indicates that the interrupt is pending. on a write, clears the corresponding int[n] bit in the pend1 register, so that interrupt [n] is no longer pending. setting a bit does not affect the active state of the corresponding interrupt. 1 0x00.0000 r/w int 22:0 july 03, 2014 134 texas instruments-production data cortex-m3 peripherals register 12: interrupt 0-31 active bit (active0), offset 0x300 note: this register can only be accessed from privileged mode. see table 2-9 on page 100 for interrupt assignments. caution C do not manually set or clear the bits in this register. interrupt 0-31 active bit (active0) base 0xe000.e000 offset 0x300 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 int ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 int ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field interrupt active description value the corresponding interrupt is not active. 0 the corresponding interrupt is active, or active and pending. 1 0x0000.0000 ro int 31:0 135 july 03, 2014 texas instruments-production data stellaris ? register 13: interrupt 32-54 active bit (active1), offset 0x304 note: this register can only be accessed from privileged mode. the active1 register indicates which interrupts are active. bit 0 corresponds to interrupt 32; bit 22 corresponds to interrupt 54. see table 2-9 on page 100 for interrupt assignments. caution C do not manually set or clear the bits in this register. interrupt 32-54 active bit (active1) base 0xe000.e000 offset 0x304 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 int reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 int ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:23 interrupt active description value the corresponding interrupt is not active. 0 the corresponding interrupt is active, or active and pending. 1 0x00.0000 ro int 22:0 july 03, 2014 136 texas instruments-production data cortex-m3 peripherals register 14: interrupt 0-3 priority (pri0), offset 0x400 register 15: interrupt 4-7 priority (pri1), offset 0x404 register 16: interrupt 8-11 priority (pri2), offset 0x408 register 17: interrupt 12-15 priority (pri3), offset 0x40c register 18: interrupt 16-19 priority (pri4), offset 0x410 register 19: interrupt 20-23 priority (pri5), offset 0x414 register 20: interrupt 24-27 priority (pri6), offset 0x418 register 21: interrupt 28-31 priority (pri7), offset 0x41c register 22: interrupt 32-35 priority (pri8), offset 0x420 register 23: interrupt 36-39 priority (pri9), offset 0x424 register 24: interrupt 40-43 priority (pri10), offset 0x428 register 25: interrupt 44-47 priority (pri11), offset 0x42c register 26: interrupt 48-51 priority (pri12), offset 0x430 register 27: interrupt 52-54 priority (pri13), offset 0x434 note: this register can only be accessed from privileged mode. the prin registers provide 3-bit priority fields for each interrupt. these registers are byte accessible. each register holds four priority fields that are assigned to interrupts as follows: interrupt prin register bit field interrupt [4n+3] bits 31:29 interrupt [4n+2] bits 23:21 interrupt [4n+1] bits 15:13 interrupt [4n] bits 7:5 see table 2-9 on page 100 for interrupt assignments. each priority level can be split into separate group priority and subpriority fields. the prigroup field in the application interrupt and reset control (apint) register (see page 147) indicates the position of the binary point that splits the priority and subpriority fields. these registers can only be accessed from privileged mode. 137 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller interrupt 0-3 priority (pri0) base 0xe000.e000 offset 0x400 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved intc reserved intd ro ro ro ro ro r/w r/w r/w ro ro ro ro ro r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved inta reserved intb ro ro ro ro ro r/w r/w r/w ro ro ro ro ro r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field interrupt priority for interrupt [4n+3] this field holds a priority value, 0-7, for the interrupt with the number [4n+3], where n is the number of the interrupt priority register (n=0 for pri0 , and so on). the lower the value, the greater the priority of the corresponding interrupt. 0x0 r/w intd 31:29 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 28:24 interrupt priority for interrupt [4n+2] this field holds a priority value, 0-7, for the interrupt with the number [4n+2], where n is the number of the interrupt priority register (n=0 for pri0 , and so on). the lower the value, the greater the priority of the corresponding interrupt. 0x0 r/w intc 23:21 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 20:16 interrupt priority for interrupt [4n+1] this field holds a priority value, 0-7, for the interrupt with the number [4n+1], where n is the number of the interrupt priority register (n=0 for pri0 , and so on). the lower the value, the greater the priority of the corresponding interrupt. 0x0 r/w intb 15:13 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 12:8 interrupt priority for interrupt [4n] this field holds a priority value, 0-7, for the interrupt with the number [4n], where n is the number of the interrupt priority register (n=0 for pri0 , and so on). the lower the value, the greater the priority of the corresponding interrupt. 0x0 r/w inta 7:5 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 4:0 july 03, 2014 138 texas instruments-production data cortex-m3 peripherals register 28: software trigger interrupt (swtrig), offset 0xf00 note: only privileged software can enable unprivileged access to the swtrig register. writing an interrupt number to the swtrig register generates a software generated interrupt (sgi). see table 2-9 on page 100 for interrupt assignments. when the mainpend bit in the configuration and control (cfgctrl) register (see page 151) is set, unprivileged software can access the swtrig register. software trigger interrupt (swtrig) base 0xe000.e000 offset 0xf00 type wo, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 intid reserved wo wo wo wo wo wo ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:6 interrupt id this field holds the interrupt id of the required sgi. for example, a value of 0x3 generates an interrupt on irq3. 0x00 wo intid 5:0 3.5 system control block (scb) register descriptions this section lists and describes the system control block (scb) registers, in numerical order by address offset. the scb registers can only be accessed from privileged mode. all registers must be accessed with aligned word accesses except for the faultstat and syspri1 -syspri3 registers, which can be accessed with byte or aligned halfword or word accesses. the processor does not support unaligned accesses to system control block registers. 139 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 29: auxiliary control (actlr), offset 0x008 note: this register can only be accessed from privileged mode. the actlr register provides disable bits for it folding, write buffer use for accesses to the default memory map, and interruption of multi-cycle instructions. by default, this register is set to provide optimum performance from the cortex-m3 processor and does not normally require modification. auxiliary control (actlr) base 0xe000.e000 offset 0x008 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dismcyc diswbuf disfold reserved r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:3 disable it folding description value no effect. 0 disables it folding. 1 in some situations, the processor can start executing the first instruction in an it block while it is still executing the it instruction. this behavior is called it folding , and improves performance, however, it folding can cause jitter in looping. if a task must avoid jitter, set the disfold bit before executing the task, to disable it folding. 0 r/w disfold 2 disable write buffer description value no effect. 0 disables write buffer use during default memory map accesses. in this situation, all bus faults are precise bus faults but performance is decreased because any store to memory must complete before the processor can execute the next instruction. 1 note: this bit only affects write buffers implemented in the cortex-m3 processor. 0 r/w diswbuf 1 july 03, 2014 140 texas instruments-production data cortex-m3 peripherals description reset type name bit/field disable interrupts of multiple cycle instructions description value no effect. 0 disables interruption of load multiple and store multiple instructions. in this situation, the interrupt latency of the processor is increased because any ldm or stm must complete before the processor can stack the current state and enter the interrupt handler. 1 0 r/w dismcyc 0 141 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 30: cpu id base (cpuid), offset 0xd00 note: this register can only be accessed from privileged mode. the cpuid register contains the arm? cortex?-m3 processor part number, version, and implementation information. cpu id base (cpuid) base 0xe000.e000 offset 0xd00 type ro, reset 0x412f.c230 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 con var imp ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 1 1 0 1 0 0 1 0 0 0 0 0 1 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rev partno ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 1 reset description reset type name bit/field implementer code description value arm 0x41 0x41 ro imp 31:24 variant number description value the rn value in the rnpn product revision identifier, for example, the 2 in r2p0. 0x2 0x2 ro var 23:20 constant description value always reads as 0xf. 0xf 0xf ro con 19:16 part number description value cortex-m3 processor. 0xc23 0xc23 ro partno 15:4 revision number description value the pn value in the rnpn product revision identifier, for example, the 0 in r2p0. 0x0 0x0 ro rev 3:0 july 03, 2014 142 texas instruments-production data cortex-m3 peripherals register 31: interrupt control and state (intctrl), offset 0xd04 note: this register can only be accessed from privileged mode. the inctrl register provides a set-pending bit for the nmi exception, and set-pending and clear-pending bits for the pendsv and systick exceptions. in addition, bits in this register indicate the exception number of the exception being processed, whether there are preempted active exceptions, the exception number of the highest priority pending exception, and whether any interrupts are pending. when writing to inctrl , the effect is unpredictable when writing a 1 to both the pendsv and unpendsv bits, or writing a 1 to both the pendstset and pendstclr bits. interrupt control and state (intctrl) base 0xe000.e000 offset 0xd04 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 vecpend reserved isrpend isrpre reserved pendstclr pendstset unpendsv pendsv reserved nmiset ro ro ro ro ro ro ro ro ro wo r/w wo r/w ro ro r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 vecact reserved retbase vecpend ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field nmi set pending description value on a read, indicates an nmi exception is not pending. on a write, no effect. 0 on a read, indicates an nmi exception is pending. on a write, changes the nmi exception state to pending. 1 because nmi is the highest-priority exception, normally the processor enters the nmi exception handler as soon as it registers the setting of this bit, and clears this bit on entering the interrupt handler. a read of this bit by the nmi exception handler returns 1 only if the nmi signal is reasserted while the processor is executing that handler. 0 r/w nmiset 31 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 30:29 pendsv set pending description value on a read, indicates a pendsv exception is not pending. on a write, no effect. 0 on a read, indicates a pendsv exception is pending. on a write, changes the pendsv exception state to pending. 1 setting this bit is the only way to set the pendsv exception state to pending. this bit is cleared by writing a 1 to the unpendsv bit. 0 r/w pendsv 28 143 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field pendsv clear pending description value on a write, no effect. 0 on a write, removes the pending state from the pendsv exception. 1 this bit is write only; on a register read, its value is unknown. 0 wo unpendsv 27 systick set pending description value on a read, indicates a systick exception is not pending. on a write, no effect. 0 on a read, indicates a systick exception is pending. on a write, changes the systick exception state to pending. 1 this bit is cleared by writing a 1 to the pendstclr bit. 0 r/w pendstset 26 systick clear pending description value on a write, no effect. 0 on a write, removes the pending state from the systick exception. 1 this bit is write only; on a register read, its value is unknown. 0 wo pendstclr 25 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 24 debug interrupt handling description value the release from halt does not take an interrupt. 0 the release from halt takes an interrupt. 1 this bit is only meaningful in debug mode and reads as zero when the processor is not in debug mode. 0 ro isrpre 23 interrupt pending description value no interrupt is pending. 0 an interrupt is pending. 1 this bit provides status for all interrupts excluding nmi and faults. 0 ro isrpend 22 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 21:19 july 03, 2014 144 texas instruments-production data cortex-m3 peripherals description reset type name bit/field interrupt pending vector number this field contains the exception number of the highest priority pending enabled exception. the value indicated by this field includes the effect of the basepri and faultmask registers, but not any effect of the primask register. description value no exceptions are pending 0x00 reserved 0x01 nmi 0x02 hard fault 0x03 memory management fault 0x04 bus fault 0x05 usage fault 0x06 reserved 0x07-0x0a svcall 0x0b reserved for debug 0x0c reserved 0x0d pendsv 0x0e systick 0x0f interrupt vector 0 0x10 interrupt vector 1 0x11 ... ... interrupt vector 54 0x46 reserved 0x47-0x7f 0x00 ro vecpend 18:12 return to base description value there are preempted active exceptions to execute. 0 there are no active exceptions, or the currently executing exception is the only active exception. 1 this bit provides status for all interrupts excluding nmi and faults. this bit only has meaning if the processor is currently executing an isr (the interrupt program status (ipsr) register is non-zero). 0 ro retbase 11 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 10:7 interrupt pending vector number this field contains the active exception number. the exception numbers can be found in the description for the vecpend field. if this field is clear, the processor is in thread mode. this field contains the same value as the isrnum field in the ipsr register. subtract 16 from this value to obtain the irq number required to index into the interrupt set enable (enn) , interrupt clear enable (disn ), interrupt set pending (pendn) , interrupt clear pending (unpendn) , and interrupt priority (prin) registers (see page 80). 0x00 ro vecact 6:0 145 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 32: vector table offset (vtable), offset 0xd08 note: this register can only be accessed from privileged mode. the vtable register indicates the offset of the vector table base address from memory address 0x0000.0000. vector table offset (vtable) base 0xe000.e000 offset 0xd08 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 offset base reserved r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved offset ro ro ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 31:30 vector table base description value the vector table is in the code memory region. 0 the vector table is in the sram memory region. 1 0 r/w base 29 vector table offset when configuring the offset field, the offset must be aligned to the number of exception entries in the vector table. because there are 54 interrupts, the offset must be aligned on a 512-byte boundary. 0x000.00 r/w offset 28:9 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 8:0 july 03, 2014 146 texas instruments-production data cortex-m3 peripherals register 33: application interrupt and reset control (apint), offset 0xd0c note: this register can only be accessed from privileged mode. the apint register provides priority grouping control for the exception model, endian status for data accesses, and reset control of the system. to write to this register, 0x05fa must be written to the vectkey field, otherwise the write is ignored. the prigroup field indicates the position of the binary point that splits the intx fields in the interrupt priority (prix) registers into separate group priority and subpriority fields. table 3-8 on page 147 shows how the prigroup value controls this split. the bit numbers in the group priority field and subpriority field columns in the table refer to the bits in the inta field. for the intb field, the corresponding bits are 15:13; for intc , 23:21; and for intd , 31:29. note: determining preemption of an exception uses only the group priority field. table 3-8. interrupt priority levels subpriorities group priorities subpriority field group priority field binary point a prigroup bit field 1 8 none [7:5] bxxx. 0x0 - 0x4 2 4 [5] [7:6] bxx.y 0x5 4 2 [6:5] [7] bx.yy 0x6 8 1 [7:5] none b.yyy 0x7 a. intx field showing the binary point. an x denotes a group priority field bit, and a y denotes a subpriority field bit. application interrupt and reset control (apint) base 0xe000.e000 offset 0xd0c type r/w, reset 0xfa05.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 vectkey r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 0 1 0 0 0 0 0 0 1 0 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 vectreset vectclract sysresreq reserved prigroup reserved endianess wo wo wo ro ro ro ro ro r/w r/w r/w ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field register key this field is used to guard against accidental writes to this register. 0x05fa must be written to this field in order to change the bits in this register. on a read, 0xfa05 is returned. 0xfa05 r/w vectkey 31:16 data endianess the stellaris implementation uses only little-endian mode so this is cleared to 0. 0 ro endianess 15 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 14:11 147 july 03, 2014 texas instruments-production data stellaris lm3s9gn5 microcontroller description reset type name bit/field interrupt priority grouping this field determines the split of group priority from subpriority (see table 3-8 on page 147 for more information). 0x0 r/w prigroup 10:8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 7:3 system reset request description value no effect. 0 resets the core and all on-chip peripherals except the debug interface. 1 this bit is automatically cleared during the reset of the core and reads as 0. 0 wo sysresreq 2 clear active nmi / fault this bit is reserved for debug use and reads as 0. this bit must be written as a 0, otherwise behavior is unpredictable. 0 wo vectclract 1 system reset this bit is reserved for debug use and reads as 0. this bit must be written as a 0, otherwise behavior is unpredictable. 0 wo vectreset 0 july 03, 2014 148 texas instruments-production data cortex-m3 peripherals register 34: system control (sysctrl), offset 0xd10 note: this register can only be accessed from privileged mode. the sysctrl register controls features of entry to and exit from low-power state. system control (sysctrl) base 0xe000.e000 offset 0xd10 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved sleepexit sleepdeep reserved sevonpend reserved ro r/w r/w ro r/w ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:5 wake up on pending description value only enabled interrupts or events can wake up the processor; disabled interrupts are excluded. 0 enabled events and all interrupts, including disabled interrupts, can wake up the processor. 1 when an event or interrupt enters the pending state, the event signal wakes up the processor from wfe . if the processor is not waiting for an event, the event is registered and affects the next wfe. the processor also wakes up on execution of a sev instruction or an external event. 0 r/w sevonpend 4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 3 deep sleep enable description value use sleep mode as the low power mode. 0 use deep-sleep mode as the low power mode. 1 0 r/w sleepdeep 2 149 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field sleep on isr exit description value when returning from handler mode to thread mode, do not sleep when returning to thread mode. 0 when returning from handler mode to thread mode, enter sleep or deep sleep on return from an isr. 1 setting this bit enables an interrupt-driven application to avoid returning to an empty main application. 0 r/w sleepexit 1 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 0 july 03, 2014 150 texas instruments-production data cortex-m3 peripherals register 35: configuration and control (cfgctrl), offset 0xd14 note: this register can only be accessed from privileged mode. the cfgctrl register controls entry to thread mode and enables: the handlers for nmi, hard fault and faults escalated by the faultmask register to ignore bus faults; trapping of divide by zero and unaligned accesses; and access to the swtrig register by unprivileged software (see page 139). configuration and control (cfgctrl) base 0xe000.e000 offset 0xd14 type r/w, reset 0x0000.0200 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 basethr mainpend reserved unaligned div0 reserved bfhfnmign stkalign reserved r/w r/w ro r/w r/w ro ro ro r/w r/w ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:10 stack alignment on exception entry description value the stack is 4-byte aligned. 0 the stack is 8-byte aligned. 1 on exception entry, the processor uses bit 9 of the stacked psr to indicate the stack alignment. on return from the exception, it uses this stacked bit to restore the correct stack alignment. 1 r/w stkalign 9 ignore bus fault in nmi and fault this bit enables handlers with priority -1 or -2 to ignore data bus faults caused by load and store instructions. the setting of this bit applies to the hard fault, nmi, and faultmask escalated handlers. description value data bus faults caused by load and store instructions cause a lock-up. 0 handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions. 1 set this bit only when the handler and its data are in absolutely safe memory. the normal use of this bit is to probe system devices and bridges to detect control path problems and fix them. 0 r/w bfhfnmign 8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 7:5 151 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field trap on divide by 0 this bit enables faulting or halting when the processor executes an sdiv or udiv instruction with a divisor of 0. description value do not trap on divide by 0. a divide by zero returns a quotient of 0. 0 trap on divide by 0. 1 0 r/w div0 4 trap on unaligned access description value do not trap on unaligned halfword and word accesses. 0 trap on unaligned halfword and word accesses. an unaligned access generates a usage fault. 1 unaligned ldm, stm, ldrd , and strd instructions always fault regardless of whether unaligned is set. 0 r/w unaligned 3 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 2 allow main interrupt trigger description value disables unprivileged software access to the swtrig register. 0 enables unprivileged software access to the swtrig register (see page 139). 1 0 r/w mainpend 1 thread state control description value the processor can enter thread mode only when no exception is active. 0 the processor can enter thread mode from any level under the control of an exc_return value (see exception return on page 105 for more information). 1 0 r/w basethr 0 july 03, 2014 152 texas instruments-production data cortex-m3 peripherals register 36: system handler priority 1 (syspri1), offset 0xd18 note: this register can only be accessed from privileged mode. the syspri1 register configures the priority level, 0 to 7 of the usage fault, bus fault, and memory management fault exception handlers. this register is byte-accessible. system handler priority 1 (syspri1) base 0xe000.e000 offset 0xd18 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved usage reserved ro ro ro ro ro r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved mem reserved bus ro ro ro ro ro r/w r/w r/w ro ro ro ro ro r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:24 usage fault priority this field configures the priority level of the usage fault. configurable priority values are in the range 0-7, with lower values having higher priority. 0x0 r/w usage 23:21 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 20:16 bus fault priority this field configures the priority level of the bus fault. configurable priority values are in the range 0-7, with lower values having higher priority. 0x0 r/w bus 15:13 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 12:8 memory management fault priority this field configures the priority level of the memory management fault. configurable priority values are in the range 0-7, with lower values having higher priority. 0x0 r/w mem 7:5 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 4:0 153 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 37: system handler priority 2 (syspri2), offset 0xd1c note: this register can only be accessed from privileged mode. the syspri2 register configures the priority level, 0 to 7 of the svcall handler. this register is byte-accessible. system handler priority 2 (syspri2) base 0xe000.e000 offset 0xd1c type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved svc ro ro ro ro ro ro ro ro ro ro ro ro ro r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field svcall priority this field configures the priority level of svcall. configurable priority values are in the range 0-7, with lower values having higher priority. 0x0 r/w svc 31:29 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000.0000 ro reserved 28:0 july 03, 2014 154 texas instruments-production data cortex-m3 peripherals register 38: system handler priority 3 (syspri3), offset 0xd20 note: this register can only be accessed from privileged mode. the syspri3 register configures the priority level, 0 to 7 of the systick exception and pendsv handlers. this register is byte-accessible. system handler priority 3 (syspri3) base 0xe000.e000 offset 0xd20 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved pendsv reserved tick ro ro ro ro ro r/w r/w r/w ro ro ro ro ro r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved debug reserved ro ro ro ro ro r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field systick exception priority this field configures the priority level of the systick exception. configurable priority values are in the range 0-7, with lower values having higher priority. 0x0 r/w tick 31:29 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 28:24 pendsv priority this field configures the priority level of pendsv. configurable priority values are in the range 0-7, with lower values having higher priority. 0x0 r/w pendsv 23:21 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 20:8 debug priority this field configures the priority level of debug. configurable priority values are in the range 0-7, with lower values having higher priority. 0x0 r/w debug 7:5 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0.0000 ro reserved 4:0 155 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 39: system handler control and state (syshndctrl), offset 0xd24 note: this register can only be accessed from privileged mode. the syshndctrl register enables the system handlers, and indicates the pending status of the usage fault, bus fault, memory management fault, and svc exceptions as well as the active status of the system handlers. if a system handler is disabled and the corresponding fault occurs, the processor treats the fault as a hard fault. this register can be modified to change the pending or active status of system exceptions. an os kernel can write to the active bits to perform a context switch that changes the current exception type. caution C software that changes the value of an active bit in this register without correct adjustment to the stacked content can cause the processor to generate a fault exception. ensure software that writes to this register retains and subsequently restores the current active status. if the value of a bit in this register must be modifed after enabling the system handlers, a read-modify-write procedure must be used to ensure that only the required bit is modifed. system handler control and state (syshndctrl) base 0xe000.e000 offset 0xd24 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 mem bus usage reserved r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mema busa reserved usga reserved svca mon reserved pndsv tick usagep memp busp svc r/w r/w ro r/w ro ro ro r/w r/w ro r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 31:19 usage fault enable description value disables the usage fault exception. 0 enables the usage fault exception. 1 0 r/w usage 18 bus fault enable description value disables the bus fault exception. 0 enables the bus fault exception. 1 0 r/w bus 17 july 03, 2014 156 texas instruments-production data cortex-m3 peripherals description reset type name bit/field memory management fault enable description value disables the memory management fault exception. 0 enables the memory management fault exception. 1 0 r/w mem 16 svc call pending description value an svc call exception is not pending. 0 an svc call exception is pending. 1 this bit can be modified to change the pending status of the svc call exception. 0 r/w svc 15 bus fault pending description value a bus fault exception is not pending. 0 a bus fault exception is pending. 1 this bit can be modified to change the pending status of the bus fault exception. 0 r/w busp 14 memory management fault pending description value a memory management fault exception is not pending. 0 a memory management fault exception is pending. 1 this bit can be modified to change the pending status of the memory management fault exception. 0 r/w memp 13 usage fault pending description value a usage fault exception is not pending. 0 a usage fault exception is pending. 1 this bit can be modified to change the pending status of the usage fault exception. 0 r/w usagep 12 systick exception active description value a systick exception is not active. 0 a systick exception is active. 1 this bit can be modified to change the active status of the systick exception, however, see the caution above before setting this bit. 0 r/w tick 11 157 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field pendsv exception active description value a pendsv exception is not active. 0 a pendsv exception is active. 1 this bit can be modified to change the active status of the pendsv exception, however, see the caution above before setting this bit. 0 r/w pndsv 10 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 9 debug monitor active description value the debug monitor is not active. 0 the debug monitor is active. 1 0 r/w mon 8 svc call active description value svc call is not active. 0 svc call is active. 1 this bit can be modified to change the active status of the svc call exception, however, see the caution above before setting this bit. 0 r/w svca 7 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 6:4 usage fault active description value usage fault is not active. 0 usage fault is active. 1 this bit can be modified to change the active status of the usage fault exception, however, see the caution above before setting this bit. 0 r/w usga 3 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 2 bus fault active description value bus fault is not active. 0 bus fault is active. 1 this bit can be modified to change the active status of the bus fault exception, however, see the caution above before setting this bit. 0 r/w busa 1 july 03, 2014 158 texas instruments-production data cortex-m3 peripherals description reset type name bit/field memory management fault active description value memory management fault is not active. 0 memory management fault is active. 1 this bit can be modified to change the active status of the memory management fault exception, however, see the caution above before setting this bit. 0 r/w mema 0 159 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 40: configurable fault status (faultstat), offset 0xd28 note: this register can only be accessed from privileged mode. the faultstat register indicates the cause of a memory management fault, bus fault, or usage fault. each of these functions is assigned to a subregister as follows: usage fault status (ufaultstat) , bits 31:16 bus fault status (bfaultstat) , bits 15:8 memory management fault status (mfaultstat) , bits 7:0 faultstat is byte accessible. faultstat or its subregisters can be accessed as follows: the complete faultstat register, with a word access to offset 0xd28 the mfaultstat , with a byte access to offset 0xd28 the mfaultstat and bfaultstat , with a halfword access to offset 0xd28 the bfaultstat , with a byte access to offset 0xd29 the ufaultstat , with a halfword access to offset 0xd2a bits are cleared by writing a 1 to them. in a fault handler, the true faulting address can be determined by: 1. read and save the memory management fault address (mmaddr) or bus fault address (faultaddr) value. 2. read the mmarv bit in mfaultstat , or the bfarv bit in bfaultstat to determine if the mmaddr or faultaddr contents are valid. software must follow this sequence because another higher priority exception might change the mmaddr or faultaddr value. for example, if a higher priority handler preempts the current fault handler, the other fault might change the mmaddr or faultaddr value. configurable fault status (faultstat) base 0xe000.e000 offset 0xd28 type r/w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 undef invstat invpc nocp reserved unalign div0 reserved r/w1c r/w1c r/w1c r/w1c ro ro ro ro r/w1c r/w1c ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ierr derr reserved mustke mstke reserved mmarv ibus precise impre bustke bstke reserved bfarv r/w1c r/w1c ro r/w1c r/w1c ro ro r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c ro ro r/w1c type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:26 july 03, 2014 160 texas instruments-production data cortex-m3 peripherals description reset type name bit/field divide-by-zero usage fault description value no divide-by-zero fault has occurred, or divide-by-zero trapping is not enabled. 0 the processor has executed an sdiv or udiv instruction with a divisor of 0. 1 when this bit is set, the pc value stacked for the exception return points to the instruction that performed the divide by zero. trapping on divide-by-zero is enabled by setting the div0 bit in the configuration and control (cfgctrl) register (see page 151). this bit is cleared by writing a 1 to it. 0 r/w1c div0 25 unaligned access usage fault description value no unaligned access fault has occurred, or unaligned access trapping is not enabled. 0 the processor has made an unaligned memory access. 1 unaligned ldm, stm, ldrd , and strd instructions always fault regardless of the configuration of this bit. trapping on unaligned access is enabled by setting the unaligned bit in the cfgctrl register (see page 151). this bit is cleared by writing a 1 to it. 0 r/w1c unalign 24 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 23:20 no coprocessor usage fault description value a usage fault has not been caused by attempting to access a coprocessor. 0 the processor has attempted to access a coprocessor. 1 this bit is cleared by writing a 1 to it. 0 r/w1c nocp 19 invalid pc load usage fault description value a usage fault has not been caused by attempting to load an invalid pc value. 0 the processor has attempted an illegal load of exc_return to the pc as a result of an invalid context or an invalid exc_return value. 1 when this bit is set, the pc value stacked for the exception return points to the instruction that tried to perform the illegal load of the pc . this bit is cleared by writing a 1 to it. 0 r/w1c invpc 18 161 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field invalid state usage fault description value a usage fault has not been caused by an invalid state. 0 the processor has attempted to execute an instruction that makes illegal use of the epsr register. 1 when this bit is set, the pc value stacked for the exception return points to the instruction that attempted the illegal use of the execution program status register (epsr) register. this bit is not set if an undefined instruction uses the epsr register. this bit is cleared by writing a 1 to it. 0 r/w1c invstat 17 undefined instruction usage fault description value a usage fault has not been caused by an undefined instruction. 0 the processor has attempted to execute an undefined instruction. 1 when this bit is set, the pc value stacked for the exception return points to the undefined instruction. an undefined instruction is an instruction that the processor cannot decode. this bit is cleared by writing a 1 to it. 0 r/w1c undef 16 bus fault address register valid description value the value in the bus fault address (faultaddr) register is not a valid fault address. 0 the faultaddr register is holding a valid fault address. 1 this bit is set after a bus fault, where the address is known. other faults can clear this bit, such as a memory management fault occurring later. if a bus fault occurs and is escalated to a hard fault because of priority, the hard fault handler must clear this bit. this action prevents problems if returning to a stacked active bus fault handler whose faultaddr register value has been overwritten. this bit is cleared by writing a 1 to it. 0 r/w1c bfarv 15 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 14:13 july 03, 2014 162 texas instruments-production data cortex-m3 peripherals description reset type name bit/field stack bus fault description value no bus fault has occurred on stacking for exception entry. 0 stacking for an exception entry has caused one or more bus faults. 1 when this bit is set, the sp is still adjusted but the values in the context area on the stack might be incorrect. a fault address is not written to the faultaddr register. this bit is cleared by writing a 1 to it. 0 r/w1c bstke 12 unstack bus fault description value no bus fault has occurred on unstacking for a return from exception. 0 unstacking for a return from exception has caused one or more bus faults. 1 this fault is chained to the handler. thus, when this bit is set, the original return stack is still present. the sp is not adjusted from the failing return, a new save is not performed, and a fault address is not written to the faultaddr register. this bit is cleared by writing a 1 to it. 0 r/w1c bustke 11 imprecise data bus error description value an imprecise data bus error has not occurred. 0 a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error. 1 when this bit is set, a fault address is not written to the faultaddr register. this fault is asynchronous. therefore, if the fault is detected when the priority of the current process is higher than the bus fault priority, the bus fault becomes pending and becomes active only when the processor returns from all higher-priority processes. if a precise fault occurs before the processor enters the handler for the imprecise bus fault, the handler detects that both the impre bit is set and one of the precise fault status bits is set. this bit is cleared by writing a 1 to it. 0 r/w1c impre 10 precise data bus error description value a precise data bus error has not occurred. 0 a data bus error has occurred, and the pc value stacked for the exception return points to the instruction that caused the fault. 1 when this bit is set, the fault address is written to the faultaddr register. this bit is cleared by writing a 1 to it. 0 r/w1c precise 9 163 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field instruction bus error description value an instruction bus error has not occurred. 0 an instruction bus error has occurred. 1 the processor detects the instruction bus error on prefetching an instruction, but sets this bit only if it attempts to issue the faulting instruction. when this bit is set, a fault address is not written to the faultaddr register. this bit is cleared by writing a 1 to it. 0 r/w1c ibus 8 memory management fault address register valid description value the value in the memory management fault address (mmaddr) register is not a valid fault address. 0 the mmaddr register is holding a valid fault address. 1 if a memory management fault occurs and is escalated to a hard fault because of priority, the hard fault handler must clear this bit. this action prevents problems if returning to a stacked active memory management fault handler whose mmaddr register value has been overwritten. this bit is cleared by writing a 1 to it. 0 r/w1c mmarv 7 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 6:5 stack access violation description value no memory management fault has occurred on stacking for exception entry. 0 stacking for an exception entry has caused one or more access violations. 1 when this bit is set, the sp is still adjusted but the values in the context area on the stack might be incorrect. a fault address is not written to the mmaddr register. this bit is cleared by writing a 1 to it. 0 r/w1c mstke 4 july 03, 2014 164 texas instruments-production data cortex-m3 peripherals description reset type name bit/field unstack access violation description value no memory management fault has occurred on unstacking for a return from exception. 0 unstacking for a return from exception has caused one or more access violations. 1 this fault is chained to the handler. thus, when this bit is set, the original return stack is still present. the sp is not adjusted from the failing return, a new save is not performed, and a fault address is not written to the mmaddr register. this bit is cleared by writing a 1 to it. 0 r/w1c mustke 3 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 2 data access violation description value a data access violation has not occurred. 0 the processor attempted a load or store at a location that does not permit the operation. 1 when this bit is set, the pc value stacked for the exception return points to the faulting instruction and the address of the attempted access is written to the mmaddr register. this bit is cleared by writing a 1 to it. 0 r/w1c derr 1 instruction access violation description value an instruction access violation has not occurred. 0 the processor attempted an instruction fetch from a location that does not permit execution. 1 this fault occurs on any access to an xn region, even when the mpu is disabled or not present. when this bit is set, the pc value stacked for the exception return points to the faulting instruction and the address of the attempted access is not written to the mmaddr register. this bit is cleared by writing a 1 to it. 0 r/w1c ierr 0 165 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 41: hard fault status (hfaultstat), offset 0xd2c note: this register can only be accessed from privileged mode. the hfaultstat register gives information about events that activate the hard fault handler. bits are cleared by writing a 1 to them. hard fault status (hfaultstat) base 0xe000.e000 offset 0xd2c type r/w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved forced dbg ro ro ro ro ro ro ro ro ro ro ro ro ro ro r/w1c r/w1c type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved vect reserved ro r/w1c ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field debug event this bit is reserved for debug use. this bit must be written as a 0, otherwise behavior is unpredictable. 0 r/w1c dbg 31 forced hard fault description value no forced hard fault has occurred. 0 a forced hard fault has been generated by escalation of a fault with configurable priority that cannot be handled, either because of priority or because it is disabled. 1 when this bit is set, the hard fault handler must read the other fault status registers to find the cause of the fault. this bit is cleared by writing a 1 to it. 0 r/w1c forced 30 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 29:2 vector table read fault description value no bus fault has occurred on a vector table read. 0 a bus fault occurred on a vector table read. 1 this error is always handled by the hard fault handler. when this bit is set, the pc value stacked for the exception return points to the instruction that was preempted by the exception. this bit is cleared by writing a 1 to it. 0 r/w1c vect 1 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 0 july 03, 2014 166 texas instruments-production data cortex-m3 peripherals register 42: memory management fault address (mmaddr), offset 0xd34 note: this register can only be accessed from privileged mode. the mmaddr register contains the address of the location that generated a memory management fault. when an unaligned access faults, the address in the mmaddr register is the actual address that faulted. because a single read or write instruction can be split into multiple aligned accesses, the fault address can be any address in the range of the requested access size. bits in the memory management fault status (mfaultstat) register indicate the cause of the fault and whether the value in the mmaddr register is valid (see page 160). memory management fault address (mmaddr) base 0xe000.e000 offset 0xd34 type r/w, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 addr r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type - - - - - - - - - - - - - - - - reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 addr r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type - - - - - - - - - - - - - - - - reset description reset type name bit/field fault address when the mmarv bit of mfaultstat is set, this field holds the address of the location that generated the memory management fault. - r/w addr 31:0 167 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 43: bus fault address (faultaddr), offset 0xd38 note: this register can only be accessed from privileged mode. the faultaddr register contains the address of the location that generated a bus fault. when an unaligned access faults, the address in the faultaddr register is the one requested by the instruction, even if it is not the address of the fault. bits in the bus fault status (bfaultstat) register indicate the cause of the fault and whether the value in the faultaddr register is valid (see page 160). bus fault address (faultaddr) base 0xe000.e000 offset 0xd38 type r/w, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 addr r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type - - - - - - - - - - - - - - - - reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 addr r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type - - - - - - - - - - - - - - - - reset description reset type name bit/field fault address when the faultaddrv bit of bfaultstat is set, this field holds the address of the location that generated the bus fault. - r/w addr 31:0 3.6 memory protection unit (mpu) register descriptions this section lists and describes the memory protection unit (mpu) registers, in numerical order by address offset. the mpu registers can only be accessed from privileged mode. july 03, 2014 168 texas instruments-production data cortex-m3 peripherals register 44: mpu type (mputype), offset 0xd90 note: this register can only be accessed from privileged mode. the mputype register indicates whether the mpu is present, and if so, how many regions it supports. mpu type (mputype) base 0xe000.e000 offset 0xd90 type ro, reset 0x0000.0800 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 iregion reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 separate reserved dregion ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:24 number of i regions this field indicates the number of supported mpu instruction regions. this field always contains 0x00. the mpu memory map is unified and is described by the dregion field. 0x00 ro iregion 23:16 number of d regions description value indicates there are eight supported mpu data regions. 0x08 0x08 ro dregion 15:8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 7:1 separate or unified mpu description value indicates the mpu is unified. 0 0 ro separate 0 169 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 45: mpu control (mpuctrl), offset 0xd94 note: this register can only be accessed from privileged mode. the mpuctrl register enables the mpu, enables the default memory map background region, and enables use of the mpu when in the hard fault, non-maskable interrupt (nmi), and fault mask register (faultmask) escalated handlers. when the enable and privdefen bits are both set: for privileged accesses, the default memory map is as described in memory model on page 88. any access by privileged software that does not address an enabled memory region behaves as defined by the default memory map. any access by unprivileged software that does not address an enabled memory region causes a memory management fault. execute never (xn) and strongly ordered rules always apply to the system control space regardless of the value of the enable bit. when the enable bit is set, at least one region of the memory map must be enabled for the system to function unless the privdefen bit is set. if the privdefen bit is set and no regions are enabled, then only privileged software can operate. when the enable bit is clear, the system uses the default memory map, which has the same memory attributes as if the mpu is not implemented (see table 2-5 on page 91 for more information). the default memory map applies to accesses from both privileged and unprivileged software. when the mpu is enabled, accesses to the system control space and vector table are always permitted. other areas are accessible based on regions and whether privdefen is set. unless hfnmiena is set, the mpu is not enabled when the processor is executing the handler for an exception with priority C1 or C2. these priorities are only possible when handling a hard fault or nmi exception or when faultmask is enabled. setting the hfnmiena bit enables the mpu when operating with these two priorities. mpu control (mpuctrl) base 0xe000.e000 offset 0xd94 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 enable hfnmiena privdefen reserved r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:3 july 03, 2014 170 texas instruments-production data cortex-m3 peripherals description reset type name bit/field mpu default region this bit enables privileged software access to the default memory map. description value if the mpu is enabled, this bit disables use of the default memory map. any memory access to a location not covered by any enabled region causes a fault. 0 if the mpu is enabled, this bit enables use of the default memory map as a background region for privileged software accesses. 1 when this bit is set, the background region acts as if it is region number -1. any region that is defined and enabled has priority over this default map. if the mpu is disabled, the processor ignores this bit. 0 r/w privdefen 2 mpu enabled during faults this bit controls the operation of the mpu during hard fault, nmi, and faultmask handlers. description value the mpu is disabled during hard fault, nmi, and faultmask handlers, regardless of the value of the enable bit. 0 the mpu is enabled during hard fault, nmi, and faultmask handlers. 1 when the mpu is disabled and this bit is set, the resulting behavior is unpredictable. 0 r/w hfnmiena 1 mpu enable description value the mpu is disabled. 0 the mpu is enabled. 1 when the mpu is disabled and the hfnmiena bit is set, the resulting behavior is unpredictable. 0 r/w enable 0 171 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 46: mpu region number (mpunumber), offset 0xd98 note: this register can only be accessed from privileged mode. the mpunumber register selects which memory region is referenced by the mpu region base address (mpubase) and mpu region attribute and size (mpuattr) registers. normally, the required region number should be written to this register before accessing the mpubase or the mpuattr register. however, the region number can be changed by writing to the mpubase register with the valid bit set (see page 173). this write updates the value of the region field. mpu region number (mpunumber) base 0xe000.e000 offset 0xd98 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 number reserved r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:3 mpu region to access this field indicates the mpu region referenced by the mpubase and mpuattr registers. the mpu supports eight memory regions. 0x0 r/w number 2:0 july 03, 2014 172 texas instruments-production data cortex-m3 peripherals register 47: mpu region base address (mpubase), offset 0xd9c register 48: mpu region base address alias 1 (mpubase1), offset 0xda4 register 49: mpu region base address alias 2 (mpubase2), offset 0xdac register 50: mpu region base address alias 3 (mpubase3), offset 0xdb4 note: this register can only be accessed from privileged mode. the mpubase register defines the base address of the mpu region selected by the mpu region number (mpunumber) register and can update the value of the mpunumber register. to change the current region number and update the mpunumber register, write the mpubase register with the valid bit set. the addr field is bits 31: n of the mpubase register. bits ( n -1):5 are reserved. the region size, as specified by the size field in the mpu region attribute and size (mpuattr) register, defines the value of n where: n = log 2 (region size in bytes) if the region size is configured to 4 gb in the mpuattr register, there is no valid addr field. in this case, the region occupies the complete memory map, and the base address is 0x0000.0000. the base address is aligned to the size of the region. for example, a 64-kb region must be aligned on a multiple of 64 kb, for example, at 0x0001.0000 or 0x0002.0000. mpu region base address (mpubase) base 0xe000.e000 offset 0xd9c type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 addr r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 region reserved valid addr r/w r/w r/w ro wo r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field base address mask bits 31: n in this field contain the region base address. the value of n depends on the region size, as shown above. the remaining bits ( n-1):5 are reserved. software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 r/w addr 31:5 173 july 03, 2014 texas instruments-production data stellaris ? description reset type name bit/field region number valid description value the mpunumber register is not changed and the processor updates the base address for the region specified in the mpunumber register and ignores the value of the region field. 0 the mpunumber register is updated with the value of the region field and the base address is updated for the region specified in the region field. 1 this bit is always read as 0. 0 wo valid 4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 3 region number on a write, contains the value to be written to the mpunumber register. on a read, returns the current region number in the mpunumber register. 0x0 r/w region 2:0 july 03, 2014 174 texas instruments-production data cortex-m3 peripherals register 51: mpu region attribute and size (mpuattr), offset 0xda0 register 52: mpu region attribute and size alias 1 (mpuattr1), offset 0xda8 register 53: mpu region attribute and size alias 2 (mpuattr2), offset 0xdb0 register 54: mpu region attribute and size alias 3 (mpuattr3), offset 0xdb8 note: this register can only be accessed from privileged mode. the mpuattr register defines the region size and memory attributes of the mpu region specified by the mpu region number (mpunumber) register and enables that region and any subregions. the mpuattr register is accessible using word or halfword accesses with the most-significant halfword holding the region attributes and the least-significant halfword holds the region size and the region and subregion enable bits. the mpu access permission attribute bits, xn, ap, tex, s, c , and b , control access to the corresponding memory region. if an access is made to an area of memory without the required permissions, then the mpu generates a permission fault. the size field defines the size of the mpu memory region specified by the mpunumber register as follows: (region size in bytes) = 2 (size+1) the smallest permitted region size is 32 bytes, corresponding to a size value of 4. table 3-9 on page 175 gives example size values with the corresponding region size and value of n in the mpu region base address (mpubase) register. table 3-9. example size field values note value of n a region size size encoding minimum permitted size 5 32 b 00100b (0x4) - 10 1 kb 01001b (0x9) - 20 1 mb 10011b (0x13) - 30 1 gb 11101b (0x1d) maximum possible size no valid addr field in mpubase ; the region occupies the complete memory map. 4 gb 11111b (0x1f) a. refers to the n parameter in the mpubase register (see page 173). mpu region attribute and size (mpuattr) base 0xe000.e000 offset 0xda0 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 b c s tex reserved ap reserved xn reserved r/w r/w r/w r/w r/w r/w ro ro r/w r/w r/w ro r/w ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 enable size reserved srd r/w r/w r/w r/w r/w r/w ro ro r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 175 july 03, 2014 texas instruments-production data stellaris lm3s9gn5 microcontroller description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:29 instruction access disable description value instruction fetches are enabled. 0 instruction fetches are disabled. 1 0 r/w xn 28 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 27 access privilege for information on using this bit field, see table 3-5 on page 119. 0 r/w ap 26:24 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 23:22 type extension mask for information on using this bit field, see table 3-3 on page 118. 0x0 r/w tex 21:19 shareable for information on using this bit, see table 3-3 on page 118. 0 r/w s 18 cacheable for information on using this bit, see table 3-3 on page 118. 0 r/w c 17 bufferable for information on using this bit, see table 3-3 on page 118. 0 r/w b 16 subregion disable bits description value the corresponding subregion is enabled. 0 the corresponding subregion is disabled. 1 region sizes of 128 bytes and less do not support subregions. when writing the attributes for such a region, configure the srd field as 0x00. see the section called subregions on page 117 for more information. 0x00 r/w srd 15:8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 7:6 region size mask the size field defines the size of the mpu memory region specified by the mpunumber register. refer to table 3-9 on page 175 for more information. 0x0 r/w size 5:1 july 03, 2014 176 texas instruments-production data cortex-m3 peripherals description reset type name bit/field region enable description value the region is disabled. 0 the region is enabled. 1 0 r/w enable 0 177 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 4 jtag interface the joint test action group (jtag) port is an ieee standard that defines a test access port and boundary scan architecture for digital integrated circuits and provides a standardized serial interface for controlling the associated test logic. the tap, instruction register (ir), and data registers (dr) can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing information on the components. the jtag port also provides a means of accessing and controlling design-for-test features such as i/o pin observation and control, scan testing, and debugging. the jtag port is comprised of four pins: tck, tms, tdi , and tdo . data is transmitted serially into the controller on tdi and out of the controller on tdo . the interpretation of this data is dependent on the current state of the tap controller. for detailed information on the operation of the jtag port and tap controller, please refer to the ieee standard 1149.1-test access port and boundary-scan architecture . the stellaris ? jtag controller works with the arm jtag controller built into the cortex-m3 core by multiplexing the tdo outputs from both jtag controllers. arm jtag instructions select the arm tdo output while stellaris jtag instructions select the stellaris tdo output. the multiplexer is controlled by the stellaris jtag controller, which has comprehensive programming for the arm, stellaris, and unimplemented jtag instructions. the stellaris jtag module has the following features: ieee 1149.1-1990 compatible test access port (tap) controller four-bit instruction register (ir) chain for storing jtag instructions ieee standard instructions: bypass, idcode, sample/preload, extest and intest arm additional instructions: apacc, dpacc and abort integrated arm serial wire debug (swd) C serial wire jtag debug port (swj-dp) C flash patch and breakpoint (fpb) unit for implementing breakpoints C data watchpoint and trace (dwt) unit for implementing watchpoints, trigger resources, and system profiling C instrumentation trace macrocell (itm) for support of printf style debugging C trace port interface unit (tpiu) for bridging to a trace port analyzer see the arm? debug interface v5 architecture specification for more information on the arm jtag controller. july 03, 2014 178 texas instruments-production data jtag interface 4.1 block diagram figure 4-1. jtag module block diagram 4.2 signal description the following table lists the external signals of the jtag/swd controller and describes the function of each. the jtag/swd controller signals are alternate functions for some gpio signals, however note that the reset state of the pins is for the jtag/swd function. the jtag/swd controller signals are under commit protection and require a special process to be configured as gpios, see commit control on page 414. the column in the table below titled "pin mux/pin assignment" lists the gpio pin placement for the jtag/swd controller signals. the afsel bit in the gpio alternate function select (gpioafsel) register (page 429) is set to choose the jtag/swd function. the number in parentheses is the encoding that must be programmed into the pmcn field in the gpio port control (gpiopctl) register (page 447) to assign the jtag/swd controller signals to the specified gpio port pin. for more information on configuring gpios, see general-purpose input/outputs (gpios) on page 405. table 4-1. jtag_swd_swo signals (100lqfp) description buffer type a pin type pin mux / pin assignment pin number pin name jtag/swd clk. ttl i pc0 (3) 80 swclk jtag tms and swdio. ttl i/o pc1 (3) 79 swdio jtag tdo and swo. ttl o pc3 (3) 77 swo jtag/swd clk. ttl i pc0 (3) 80 tck jtag tdi. ttl i pc2 (3) 78 tdi jtag tdo and swo. ttl o pc3 (3) 77 tdo 179 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller , q v w u x f w l r q 5 h j l v w h u , 5 7 $ 3 & r q w u r o o h u % < 3 $ 6 6 ' d w d 5 h j l v w h u % r x q g d u \ 6 f d q ' d w d 5 h j l v w h u , ' & 2 ' ( ' d w d 5 h j l v w h u $ % 2 5 7 ' d w d 5 h j l v w h u ' 3 $ & & ' d w d 5 h j l v w h u $ 3 $ & & ' d w d 5 h j l v w h u 7 & . 7 0 6 7 ' , 7 ' 2 & r u w h [ 0 ' h e x j 3 r u w table 4-1. jtag_swd_swo signals (100lqfp) (continued) description buffer type a pin type pin mux / pin assignment pin number pin name jtag tms and swdio. ttl i pc1 (3) 79 tms a. the ttl designation indicates the pin has ttl-compatible voltage levels. table 4-2. jtag_swd_swo signals (108bga) description buffer type a pin type pin mux / pin assignment pin number pin name jtag/swd clk. ttl i pc0 (3) a9 swclk jtag tms and swdio. ttl i/o pc1 (3) b9 swdio jtag tdo and swo. ttl o pc3 (3) a10 swo jtag/swd clk. ttl i pc0 (3) a9 tck jtag tdi. ttl i pc2 (3) b8 tdi jtag tdo and swo. ttl o pc3 (3) a10 tdo jtag tms and swdio. ttl i pc1 (3) b9 tms a. the ttl designation indicates the pin has ttl-compatible voltage levels. 4.3 functional description a high-level conceptual drawing of the jtag module is shown in figure 4-1 on page 179. the jtag module is composed of the test access port (tap) controller and serial shift chains with parallel update registers. the tap controller is a simple state machine controlled by the tck and tms inputs. the current state of the tap controller depends on the sequence of values captured on tms at the rising edge of tck . the tap controller determines when the serial shift chains capture new data, shift data from tdi towards tdo , and update the parallel load registers. the current state of the tap controller also determines whether the instruction register (ir) chain or one of the data register (dr) chains is being accessed. the serial shift chains with parallel load registers are comprised of a single instruction register (ir) chain and multiple data register (dr) chains. the current instruction loaded in the parallel load register determines which dr chain is captured, shifted, or updated during the sequencing of the tap controller. some instructions, like extest and intest, operate on data currently in a dr chain and do not capture, shift, or update any of the chains. instructions that are not implemented decode to the bypass instruction to ensure that the serial path between tdi and tdo is always connected (see table 4-4 on page 186 for a list of implemented instructions). see jtag and boundary scan on page 1299 for jtag timing diagrams. note: of all the possible reset sources, only power-on reset (por) and the assertion of the rst input have any effect on the jtag module. the pin configurations are reset by both the rst input and por, whereas the internal jtag logic is only reset with por. see reset sources on page 191 for more information on reset. 4.3.1 jtag interface pins the jtag interface consists of four standard pins: tck, tms, tdi , and tdo . these pins and their associated state after a power-on reset or reset caused by the rst input are given in table 4-3. detailed information on each pin follows. refer to general-purpose input/outputs (gpios) on page 405 for information on how to reprogram the configuration of these pins. july 03, 2014 180 texas instruments-production data jtag interface table 4-3. jtag port pins state after power-on reset or rst assertion drive value drive strength internal pull-down internal pull-up data direction pin name n/a n/a disabled enabled input tck n/a n/a disabled enabled input tms n/a n/a disabled enabled input tdi high-z 2-ma driver disabled enabled output tdo 4.3.1.1 test clock input (tck) the tck pin is the clock for the jtag module. this clock is provided so the test logic can operate independently of any other system clocks and to ensure that multiple jtag tap controllers that are daisy-chained together can synchronously communicate serial test data between components. during normal operation, tck is driven by a free-running clock with a nominal 50% duty cycle. when necessary, tck can be stopped at 0 or 1 for extended periods of time. while tck is stopped at 0 or 1, the state of the tap controller does not change and data in the jtag instruction and data registers is not lost. by default, the internal pull-up resistor on the tck pin is enabled after reset, assuring that no clocking occurs if the pin is not driven from an external source. the internal pull-up and pull-down resistors can be turned off to save internal power as long as the tck pin is constantly being driven by an external source (see page 435 and page 437). 4.3.1.2 test mode select (tms) the tms pin selects the next state of the jtag tap controller. tms is sampled on the rising edge of tck . depending on the current tap state and the sampled value of tms , the next state may be entered. because the tms pin is sampled on the rising edge of tck , the ieee standard 1149.1 expects the value on tms to change on the falling edge of tck. holding tms high for five consecutive tck cycles drives the tap controller state machine to the test-logic-reset state. when the tap controller enters the test-logic-reset state, the jtag module and associated registers are reset to their default values. this procedure should be performed to initialize the jtag controller. the jtag test access port state machine can be seen in its entirety in figure 4-2 on page 182. by default, the internal pull-up resistor on the tms pin is enabled after reset. changes to the pull-up resistor settings on gpio port c should ensure that the internal pull-up resistor remains enabled on pc1/tms ; otherwise jtag communication could be lost (see page 435). 4.3.1.3 test data input (tdi) the tdi pin provides a stream of serial information to the ir chain and the dr chains. tdi is sampled on the rising edge of tck and, depending on the current tap state and the current instruction, may present this data to the proper shift register chain. because the tdi pin is sampled on the rising edge of tck , the ieee standard 1149.1 expects the value on tdi to change on the falling edge of tck. by default, the internal pull-up resistor on the tdi pin is enabled after reset. changes to the pull-up resistor settings on gpio port c should ensure that the internal pull-up resistor remains enabled on pc2/tdi ; otherwise jtag communication could be lost (see page 435). 4.3.1.4 test data output (tdo) the tdo pin provides an output stream of serial information from the ir chain or the dr chains. the value of tdo depends on the current tap state, the current instruction, and the data in the 181 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller chain being accessed. in order to save power when the jtag port is not being used, the tdo pin is placed in an inactive drive state when not actively shifting out data. because tdo can be connected to the tdi of another controller in a daisy-chain configuration, the ieee standard 1149.1 expects the value on tdo to change on the falling edge of tck. by default, the internal pull-up resistor on the tdo pin is enabled after reset, assuring that the pin remains at a constant logic level when the jtag port is not being used. the internal pull-up and pull-down resistors can be turned off to save internal power if a high-z output value is acceptable during certain tap controller states (see page 435 and page 437). 4.3.2 jtag tap controller the jtag tap controller state machine is shown in figure 4-2. the tap controller state machine is reset to the test-logic-reset state on the assertion of a power-on-reset (por). in order to reset the jtag module after the microcontroller has been powered on, the tms input must be held high for five tck clock cycles, resetting the tap controller and all associated jtag chains. asserting the correct sequence on the tms pin allows the jtag module to shift in new instructions, shift in data, or idle during extended testing sequences. for detailed information on the function of the tap controller and the operations that occur in each state, please refer to ieee standard 1149.1 . figure 4-2. test access port state machine 4.3.3 shift registers the shift registers consist of a serial shift register chain and a parallel load register. the serial shift register chain samples specific information during the tap controllers capture states and allows july 03, 2014 182 texas instruments-production data jtag interface 7 h v w / r j l f 5 h v h w 5 x q 7 h v w , g o h 6 h o h f w ' 5 6 f d q 6 h o h f w , 5 6 f d q & d s w x u h ' 5 & d s w x u h , 5 6 k l i w ' 5 6 k l i w , 5 ( [ l w ' 5 ( [ l w , 5 ( [ l w ' 5 ( [ l w , 5 3 d x v h ' 5 3 d x v h , 5 8 s g d w h ' 5 8 s g d w h , 5 this information to be shifted out on tdo during the tap controllers shift states. while the sampled data is being shifted out of the chain on tdo , new data is being shifted into the serial shift register on tdi . this new data is stored in the parallel load register during the tap controllers update states. each of the shift registers is discussed in detail in register descriptions on page 186. 4.3.4 operational considerations certain operational parameters must be considered when using the jtag module. because the jtag pins can be programmed to be gpios, board configuration and reset conditions on these pins must be considered. in addition, because the jtag module has integrated arm serial wire debug, the method for switching between these two operational modes is described below. 4.3.4.1 gpio functionality when the microcontroller is reset with either a por or rst , the jtag/swd port pins default to their jtag/swd configurations. the default configuration includes enabling digital functionality ( den[3:0] set in the port c gpio digital enable (gpioden) register), enabling the pull-up resistors ( pue[3:0] set in the port c gpio pull-up select (gpiopur) register), disabling the pull-down resistors (pde[3:0] cleared in the port c gpio pull-down select (gpiopdr) register) and enabling the alternate hardware function ( afsel[3:0] set in the port c gpio alternate function select (gpioafsel) register) on the jtag/swd pins. see page 429, page 435, page 437, and page 440. it is possible for software to configure these pins as gpios after reset by clearing afsel[3:0] in the port c gpioafsel register. if the user does not require the jtag/swd port for debugging or board-level testing, this provides four more gpios for use in the design. caution C it is possible to create a software sequence that prevents the debugger from connecting to the stellaris microcontroller. if the program code loaded into fash immediately changes the jtag pins to their gpio functionality, the debugger may not have enough time to connect and halt the controller before the jtag pin functionality switches. as a result, the debugger may be locked out of the part. this issue can be avoided with a software routine that restores jtag functionality based on an external or software trigger. the gpio commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. protection is provided for the nmi pin ( pb7 ) and the four jtag/swd pins ( pc[3:0] ). writes to protected bits of the gpio alternate function select (gpioafsel) register (see page 429), gpio pull up select (gpiopur) register (see page 435), gpio pull-down select (gpiopdr) register (see page 437), and gpio digital enable (gpioden) register (see page 440) are not committed to storage unless the gpio lock (gpiolock) register (see page 442) has been unlocked and the appropriate bits of the gpio commit (gpiocr) register (see page 443) have been set. 4.3.4.2 communication with jtag/swd because the debug clock and the system clock can be running at different frequencies, care must be taken to maintain reliable communication with the jtag/swd interface. in the capture-dr state, the result of the previous transaction, if any, is returned, together with a 3-bit ack response. software should check the ack response to see if the previous operation has completed before initiating a new transaction. alternatively, if the system clock is at least 8 times faster than the debug clock (tck or swclk ), the previous operation has enough time to complete and the ack bits do not have to be checked. 183 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 4.3.4.3 recovering a "locked" microcontroller note: performing the sequence below restores the non-volatile registers discussed in non-volatile register programming on page 305 to their factory default values. the mass erase of the flash memory caused by the sequence below occurs prior to the non-volatile registers being restored. if software configures any of the jtag/swd pins as gpio and loses the ability to communicate with the debugger, there is a debug port unlock sequence that can be used to recover the microcontroller. performing a total of ten jtag-to-swd and swd-to-jtag switch sequences while holding the microcontroller in reset mass erases the flash memory. the debug port unlock sequence is: 1. assert and hold the rst signal. 2. apply power to the device. 3. perform steps 1 and 2 of the jtag-to-swd switch sequence on the section called jtag-to-swd switching on page 185. 4. perform steps 1 and 2 of the swd-to-jtag switch sequence on the section called swd-to-jtag switching on page 185. 5. perform steps 1 and 2 of the jtag-to-swd switch sequence. 6. perform steps 1 and 2 of the swd-to-jtag switch sequence. 7. perform steps 1 and 2 of the jtag-to-swd switch sequence. 8. perform steps 1 and 2 of the swd-to-jtag switch sequence. 9. perform steps 1 and 2 of the jtag-to-swd switch sequence. 10. perform steps 1 and 2 of the swd-to-jtag switch sequence. 11. perform steps 1 and 2 of the jtag-to-swd switch sequence. 12. perform steps 1 and 2 of the swd-to-jtag switch sequence. 13. release the rst signal. 14. wait 400 ms. 15. power-cycle the microcontroller. 4.3.4.4 arm serial wire debug (swd) in order to seamlessly integrate the arm serial wire debug (swd) functionality, a serial-wire debugger must be able to connect to the cortex-m3 core without having to perform, or have any knowledge of, jtag cycles. this integration is accomplished with a swd preamble that is issued before the swd session begins. the switching preamble used to enable the swd interface of the swj-dp module starts with the tap controller in the test-logic-reset state. from here, the preamble sequences the tap controller through the following states: run test idle, select dr, select ir, test logic reset, test logic reset, run test idle, run test idle, select dr, select ir, test logic reset, test logic reset, run test idle, run test idle, select dr, select ir, and test logic reset states. july 03, 2014 184 texas instruments-production data jtag interface stepping through this sequence of the tap state machine enables the swd interface and disables the jtag interface. for more information on this operation and the swd interface, see the arm? debug interface v5 architecture specification . because this sequence is a valid series of jtag operations that could be issued, the arm jtag tap controller is not fully compliant to the ieee standard 1149.1 . this instance is the only one where the arm jtag tap controller does not meet full compliance with the specification. due to the low probability of this sequence occurring during normal operation of the tap controller, it should not affect normal performance of the jtag interface. jtag-to-swd switching to switch the operating mode of the debug access port (dap) from jtag to swd mode, the external debug hardware must send the switching preamble to the microcontroller. the 16-bit tms/swdio command for switching to swd mode is defined as b1110.0111.1001.1110, transmitted lsb first. this command can also be represented as 0xe79e when transmitted lsb first. the complete switch sequence should consist of the following transactions on the tck/ swclk and tms/ swdio signals: 1. send at least 50 tck/ swclk cycles with tms/ swdio high to ensure that both jtag and swd are in their reset states. 2. send the 16-bit jtag-to-swd switch command, 0xe79e, on tms/swdio. 3. send at least 50 tck/ swclk cycles with tms/ swdio high to ensure that if swj-dp was already in swd mode before sending the switch sequence, the swd goes into the line reset state. to verify that the debug access port (dap) has switched to the serial wire debug (swd) operating mode, perform a swd readid operation. the id value can be compared against the device's known id to verify the switch. swd-to-jtag switching to switch the operating mode of the debug access port (dap) from swd to jtag mode, the external debug hardware must send a switch command to the microcontroller. the 16-bit tms/swdio command for switching to jtag mode is defined as b1110.0111.0011.1100, transmitted lsb first. this command can also be represented as 0xe73c when transmitted lsb first. the complete switch sequence should consist of the following transactions on the tck/ swclk and tms/ swdio signals: 1. send at least 50 tck/ swclk cycles with tms/ swdio high to ensure that both jtag and swd are in their reset states. 2. send the 16-bit swd-to-jtag switch command, 0xe73c, on tms/swdio. 3. send at least 50 tck/ swclk cycles with tms/ swdio high to ensure that if swj-dp was already in jtag mode before sending the switch sequence, the jtag goes into the test logic reset state. to verify that the debug access port (dap) has switched to the jtag operating mode, set the jtag instruction register (ir) to the idcode instruction and shift out the data register (dr). the dr value can be compared against the device's known idcode to verify the switch. 4.4 initialization and configuration after a power-on-reset or an external reset ( rst ), the jtag pins are automatically configured for jtag communication. no user-defined initialization or configuration is needed. however, if the user 185 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller application changes these pins to their gpio function, they must be configured back to their jtag functionality before jtag communication can be restored. to return the pins to their jtag functions, enable the four jtag pins ( pc[3:0] ) for their alternate function using the gpioafsel register. in addition to enabling the alternate functions, any other changes to the gpio pad configurations on the four jtag pins ( pc[3:0] ) should be returned to their default settings. 4.5 register descriptions the registers in the jtag tap controller or shift register chains are not memory mapped and are not accessible through the on-chip advanced peripheral bus (apb). instead, the registers within the jtag controller are all accessed serially through the tap controller. these registers include the instruction register and the six data registers. 4.5.1 instruction register (ir) the jtag tap instruction register (ir) is a four-bit serial scan chain connected between the jtag tdi and tdo pins with a parallel load register. when the tap controller is placed in the correct states, bits can be shifted into the ir. once these bits have been shifted into the chain and updated, they are interpreted as the current instruction. the decode of the ir bits is shown in table 4-4. a detailed explanation of each instruction, along with its associated data register, follows. table 4-4. jtag instruction register commands description instruction ir[3:0] drives the values preloaded into the boundary scan chain by the sample/preload instruction onto the pads. extest 0x0 drives the values preloaded into the boundary scan chain by the sample/preload instruction into the controller. intest 0x1 captures the current i/o values and shifts the sampled values out of the boundary scan chain while new preload data is shifted in. sample / preload 0x2 shifts data into the arm debug port abort register. abort 0x8 shifts data into and out of the arm dp access register. dpacc 0xa shifts data into and out of the arm ac access register. apacc 0xb loads manufacturing information defined by the ieee standard 1149.1 into the idcode chain and shifts it out. idcode 0xe connects tdi to tdo through a single shift register chain. bypass 0xf defaults to the bypass instruction to ensure that tdi is always connected to tdo. reserved all others 4.5.1.1 extest instruction the extest instruction is not associated with its own data register chain. instead, the extest instruction uses the data that has been preloaded into the boundary scan data register using the sample/preload instruction. when the extest instruction is present in the instruction register, the preloaded data in the boundary scan data register associated with the outputs and output enables are used to drive the gpio pads rather than the signals coming from the core. with tests that drive known values out of the controller, this instruction can be used to verify connectivity. while the extest instruction is present in the instruction register, the boundary scan data register can be accessed to sample and shift out the current data and load new data into the boundary scan data register. july 03, 2014 186 texas instruments-production data jtag interface 4.5.1.2 intest instruction the intest instruction is not associated with its own data register chain. instead, the intest instruction uses the data that has been preloaded into the boundary scan data register using the sample/preload instruction. when the intest instruction is present in the instruction register, the preloaded data in the boundary scan data register associated with the inputs are used to drive the signals going into the core rather than the signals coming from the gpio pads. with tests that drive known values into the controller, this instruction can be used for testing. it is important to note that although the rst input pin is on the boundary scan data register chain, it is only observable. while the intest instruction is present in the instruction register, the boundary scan data register can be accessed to sample and shift out the current data and load new data into the boundary scan data register. 4.5.1.3 sample/preload instruction the sample/preload instruction connects the boundary scan data register chain between tdi and tdo . this instruction samples the current state of the pad pins for observation and preloads new test data. each gpio pad has an associated input, output, and output enable signal. when the tap controller enters the capture dr state during this instruction, the input, output, and output-enable signals to each of the gpio pads are captured. these samples are serially shifted out on tdo while the tap controller is in the shift dr state and can be used for observation or comparison in various tests. while these samples of the inputs, outputs, and output enables are being shifted out of the boundary scan data register, new data is being shifted into the boundary scan data register from tdi. once the new data has been shifted into the boundary scan data register, the data is saved in the parallel load registers when the tap controller enters the update dr state. this update of the parallel load register preloads data into the boundary scan data register that is associated with each input, output, and output enable. this preloaded data can be used with the extest and intest instructions to drive data into or out of the controller. see boundary scan data register on page 189 for more information. 4.5.1.4 abort instruction the abort instruction connects the associated abort data register chain between tdi and tdo . this instruction provides read and write access to the abort register of the arm debug access port (dap). shifting the proper data into this data register clears various error bits or initiates a dap abort of a previous request. see the abort data register on page 189 for more information. 4.5.1.5 dpacc instruction the dpacc instruction connects the associated dpacc data register chain between tdi and tdo . this instruction provides read and write access to the dpacc register of the arm debug access port (dap). shifting the proper data into this register and reading the data output from this register allows read and write access to the arm debug and status registers. see dpacc data register on page 189 for more information. 4.5.1.6 apacc instruction the apacc instruction connects the associated apacc data register chain between tdi and tdo . this instruction provides read and write access to the apacc register of the arm debug access port (dap). shifting the proper data into this register and reading the data output from this register allows read and write access to internal components and buses through the debug port. see apacc data register on page 189 for more information. 187 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 4.5.1.7 idcode instruction the idcode instruction connects the associated idcode data register chain between tdi and tdo . this instruction provides information on the manufacturer, part number, and version of the arm core. this information can be used by testing equipment and debuggers to automatically configure input and output data streams. idcode is the default instruction loaded into the jtag instruction register when a power-on-reset (por) is asserted, or the test-logic-reset state is entered. see idcode data register on page 188 for more information. 4.5.1.8 bypass instruction the bypass instruction connects the associated bypass data register chain between tdi and tdo . this instruction is used to create a minimum length serial path between the tdi and tdo ports. the bypass data register is a single-bit shift register. this instruction improves test efficiency by allowing components that are not needed for a specific test to be bypassed in the jtag scan chain by loading them with the bypass instruction. see bypass data register on page 188 for more information. 4.5.2 data registers the jtag module contains six data registers. these serial data register chains include: idcode, bypass, boundary scan, apacc, dpacc, and abort and are discussed in the following sections. 4.5.2.1 idcode data register the format for the 32-bit idcode data register defined by the ieee standard 1149.1 is shown in figure 4-3. the standard requires that every jtag-compliant microcontroller implement either the idcode instruction or the bypass instruction as the default instruction. the lsb of the idcode data register is defined to be a 1 to distinguish it from the bypass instruction, which has an lsb of 0. this definition allows auto-configuration test tools to determine which instruction is the default instruction. the major uses of the jtag port are for manufacturer testing of component assembly and program development and debug. to facilitate the use of auto-configuration debug tools, the idcode instruction outputs a value of 0x4ba0.0477. this value allows the debuggers to automatically configure themselves to work correctly with the cortex-m3 during debug. figure 4-3. idcode register format 4.5.2.2 bypass data register the format for the 1-bit bypass data register defined by the ieee standard 1149.1 is shown in figure 4-4. the standard requires that every jtag-compliant microcontroller implement either the bypass instruction or the idcode instruction as the default instruction. the lsb of the bypass data register is defined to be a 0 to distinguish it from the idcode instruction, which has an lsb of 1. this definition allows auto-configuration test tools to determine which instruction is the default instruction. july 03, 2014 188 texas instruments-production data jtag interface 9 h u v l r q 3 d u w 1 x p e h u 0 d q x i d f w x u h u , ' 7 ' 2 7 ' , figure 4-4. bypass register format 4.5.2.3 boundary scan data register the format of the boundary scan data register is shown in figure 4-5. each gpio pin, starting with a gpio pin next to the jtag port pins, is included in the boundary scan data register. each gpio pin has three associated digital signals that are included in the chain. these signals are input, output, and output enable, and are arranged in that order as shown in the figure. when the boundary scan data register is accessed with the sample/preload instruction, the input, output, and output enable from each digital pad are sampled and then shifted out of the chain to be verified. the sampling of these values occurs on the rising edge of tck in the capture dr state of the tap controller. while the sampled data is being shifted out of the boundary scan chain in the shift dr state of the tap controller, new data can be preloaded into the chain for use with the extest and intest instructions. the extest instruction forces data out of the controller, and the intest instruction forces data into the controller. figure 4-5. boundary scan register format 4.5.2.4 apacc data register the format for the 35-bit apacc data register defined by arm is described in the arm? debug interface v5 architecture specification . 4.5.2.5 dpacc data register the format for the 35-bit dpacc data register defined by arm is described in the arm? debug interface v5 architecture specification . 4.5.2.6 abort data register the format for the 35-bit abort data register defined by arm is described in the arm? debug interface v5 architecture specification . 189 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 7 ' 2 7 ' , , 1 7 ' , v w * 3 , 2 7 ' 2 2 8 7 2 ( , 1 p w k * 3 , 2 2 8 7 2 ( , 1 p w k * 3 , 2 2 8 7 2 ( , 1 * 3 , 2 q w k 2 8 7 2 ( 5 system control system control configures the overall operation of the device and provides information about the device. configurable features include reset control, nmi operation, power control, clock control, and low-power modes. 5.1 signal description the following table lists the external signals of the system control module and describes the function of each. the nmi signal is the alternate function for the gpio pb7 signal and functions as a gpio after reset. pb7 is under commit protection and requires a special process to be configured as any alternate function or to subsequently return to the gpio function, see commit control on page 414. the column in the table below titled "pin mux/pin assignment" lists the gpio pin placement for the nmi signal. the afsel bit in the gpio alternate function select (gpioafsel) register (page 429) should be set to choose the nmi function. the number in parentheses is the encoding that must be programmed into the pmcn field in the gpio port control (gpiopctl) register (page 447) to assign the nmi signal to the specified gpio port pin. for more information on configuring gpios, see general-purpose input/outputs (gpios) on page 405. the remaining signals (with the word "fixed" in the pin mux/pin assignment column) have a fixed pin assignment and function. table 5-1. system control & clocks signals (100lqfp) description buffer type a pin type pin mux / pin assignment pin number pin name non-maskable interrupt. ttl i pb7 (4) 89 nmi main oscillator crystal input or an external clock reference input. analog i fixed 48 osc0 main oscillator crystal output. leave unconnected when using a single-ended clock source. analog o fixed 49 osc1 system reset input. ttl i fixed 64 rst a. the ttl designation indicates the pin has ttl-compatible voltage levels. table 5-2. system control & clocks signals (108bga) description buffer type a pin type pin mux / pin assignment pin number pin name non-maskable interrupt. ttl i pb7 (4) a8 nmi main oscillator crystal input or an external clock reference input. analog i fixed l11 osc0 main oscillator crystal output. leave unconnected when using a single-ended clock source. analog o fixed m11 osc1 system reset input. ttl i fixed h11 rst a. the ttl designation indicates the pin has ttl-compatible voltage levels. 5.2 functional description the system control module provides the following capabilities: device identification, see device identification on page 191 local control, such as reset (see reset control on page 191), power (see power control on page 196) and clock control (see clock control on page 197) july 03, 2014 190 texas instruments-production data system control system control (run, sleep, and deep-sleep modes), see system control on page 203 5.2.1 device identification several read-only registers provide software with information on the microcontroller, such as version, part number, sram size, flash memory size, and other features. see the did0 (page 208), did1 (page 236), dc0-dc9 (page 238) and nvmstat (page 261) registers. 5.2.2 reset control this section discusses aspects of hardware functions during reset as well as system software requirements following the reset sequence. 5.2.2.1 reset sources the lm3s9gn5 microcontroller has six sources of reset: 1. power-on reset (por) (see page 192). 2. external reset input pin ( rst ) assertion (see page 192). 3. internal brown-out (bor) detector (see page 194). 4. software-initiated reset (with the software reset registers) (see page 194). 5. a watchdog timer reset condition violation (see page 195). 6. mosc failure (see page 196). table 5-3 provides a summary of results of the various reset operations. table 5-3. reset sources on-chip peripherals reset? jtag reset? core reset? reset source yes yes yes power-on reset yes yes yes rst yes yes yes brown-out reset yes yes yes software system request reset using the sysresreq bit in the apint register. no no yes software system request reset using the vectreset bit in the apint register. yes a yes no software peripheral reset yes yes yes watchdog reset yes yes yes mosc failure reset a. programmable on a module-by-module basis using the software reset control registers. after a reset, the reset cause (resc) register is set with the reset cause. the bits in this register are sticky and maintain their state across multiple reset sequences, except when an internal por or an external reset is the cause, and then all the other bits in the resc register are cleared except for the por or ext indicator. 191 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller at any reset that resets the core, the user has the opportunity to direct the core to execute the rom boot loader or the application in flash memory by using any gpio signal as configured in the boot configuration (bootcfg) register. at reset, the rom is mapped over the flash memory so that the rom boot sequence is always executed. the boot sequence executed from rom is as follows: 1. the ba bit (below) is cleared such that rom is mapped to 0x01xx.xxxx and flash memory is mapped to address 0x0. 2. the bootcfg register is read. if the en bit is clear, the status of the specified gpio pin is compared with the specified polarity. if the status matches the specified polarity, the rom is mapped to address 0x0000.0000 and execution continues out of the rom boot loader. 3. if the status doesn't match the specified polarity, the data at address 0x0000.0004 is read, and if the data at this address is 0xffff.ffff, the rom is mapped to address 0x0000.0000 and execution continues out of the rom boot loader. 4. if there is valid data at address 0x0000.0004, the stack pointer ( sp ) is loaded from flash memory at address 0x0000.0000 and the program counter ( pc ) is loaded from address 0x0000.0004. the user application begins executing. for example, if the bootcfg register is written and committed with the value of 0x0000.3c01, then pb7 is examined at reset to determine if the rom boot loader should be executed. if pb7 is low, the core unconditionally begins executing the rom boot loader. if pb7 is high, then the application in flash memory is executed if the reset vector at location 0x0000.0004 is not 0xffff.ffff. otherwise, the rom boot loader is executed. 5.2.2.2 power-on reset (por) the internal power-on reset (por) circuit monitors the power supply voltage (v dd ) and generates a reset signal to all of the internal logic including jtag when the power supply ramp reaches a threshold value (v th ). the microcontroller must be operating within the specified operating parameters when the on-chip power-on reset pulse is complete (see power and brown-out on page 1301). for applications that require the use of an external reset signal to hold the microcontroller in reset longer than the internal por, the rst input may be used as discussed in external rst pin on page 192. the power-on reset sequence is as follows: 1. the microcontroller waits for internal por to go inactive. 2. the internal reset is released and the core loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. the internal por is only active on the initial power-up of the microcontroller. the power-on reset timing is shown in figure 26-4 on page 1301. 5.2.2.3 external rst pin note: it is recommended that the trace for the rst signal must be kept as short as possible. be sure to place any components connected to the rst signal as close to the microcontroller as possible. if the application only uses the internal por circuit, the rst input must be connected to the power supply (v dd ) through an optional pull-up resistor (0 to 100k ?) as shown in figure 5-1 on page 193. july 03, 2014 192 texas instruments-production data system control figure 5-1. basic rst configuration r pu = 0 to 100 k the external reset pin ( rst ) resets the microcontroller including the core and all the on-chip peripherals except the jtag tap controller (see jtag interface on page 178). the external reset sequence is as follows: 1. the external reset pin ( rst ) is asserted for the duration specified by t min and then de-asserted (see reset on page 1302). 2. the internal reset is released and the core loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. to improve noise immunity and/or to delay reset at power up, the rst input may be connected to an rc network as shown in figure 5-2 on page 193. figure 5-2. external circuitry to extend power-on reset r pu = 1 k to 100 k c 1 = 1 nf to 10 f if the application requires the use of an external reset switch, figure 5-3 on page 194 shows the proper circuitry to use. 193 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 3 8 5 6 7 6 w h o o d u l v ? 5 9 ' ' 3 8 & 5 6 7 6 w h o o d u l v ? 5 9 ' ' figure 5-3. reset circuit controlled by switch typical r pu = 10 k typical r s = 470 c 1 = 10 nf the r pu and c 1 components define the power-on delay. the external reset timing is shown in figure 26-7 on page 1302. 5.2.2.4 brown-out reset (bor) the microcontroller provides a brown-out detection circuit that triggers if the power supply (v dd ) drops below a brown-out threshold voltage (v bth ). if a brown-out condition is detected, the system may generate an interrupt or a system reset. the default condition is to reset the microcontroller. brown-out resets are controlled with the power-on and brown-out reset control (pborctl) register. the borior bit in the pborctl register must be set for a brown-out condition to trigger a reset; if borior is clear, an interrupt is generated. when a brown-out condition occurs during a flash program or erase operation, a full system reset is always triggered without regard to the setting in the pborctl register. the brown-out reset sequence is as follows: 1. when v dd drops below v bth , an internal bor condition is set. 2. if the bor condition exists, an internal reset is asserted. 3. the internal reset is released and the microcontroller fetches and loads the initial stack pointer, the initial program counter, the first instruction designated by the program counter, and begins execution. 4. the internal bor condition is reset after 500 s to prevent another bor condition from being set before software has a chance to investigate the original cause. the result of a brown-out reset is equivalent to that of an assertion of the external rst input, and the reset is held active until the proper v dd level is restored. the resc register can be examined in the reset interrupt handler to determine if a brown-out condition was the cause of the reset, thus allowing software to determine what actions are required to recover. the internal brown-out reset timing is shown in figure 26-5 on page 1301. 5.2.2.5 software reset software can reset a specific peripheral or generate a reset to the entire microcontroller. july 03, 2014 194 texas instruments-production data system control 3 8 & 5 6 5 6 7 6 w h o o d u l v ? 5 9 ' ' peripherals can be individually reset by software via three registers that control reset signals to each on-chip peripheral (see the srcrn registers, page 291). if the bit position corresponding to a peripheral is set and subsequently cleared, the peripheral is reset. the encoding of the reset registers is consistent with the encoding of the clock gating control for peripherals and on-chip functions (see system control on page 203). the entire microcontroller, including the core, can be reset by software by setting the sysresreq bit in the application interrupt and reset control (apint) register. the software-initiated system reset sequence is as follows: 1. a software microcontroller reset is initiated by setting the sysresreq bit. 2. an internal reset is asserted. 3. the internal reset is deasserted and the microcontroller loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. the core only can be reset by software by setting the vectreset bit in the apint register. the software-initiated core reset sequence is as follows: 1. a core reset is initiated by setting the vectreset bit. 2. an internal reset is asserted. 3. the internal reset is deasserted and the microcontroller loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. the software-initiated system reset timing is shown in figure 26-8 on page 1302. 5.2.2.6 watchdog timer reset the watchdog timer module's function is to prevent system hangs. the lm3s9gn5 microcontroller has two watchdog timer modules in case one watchdog clock source fails. one watchdog is run off the system clock and the other is run off the precision internal oscillator (piosc). each module operates in the same manner except that because the piosc watchdog timer module is in a different clock domain, register accesses must have a time delay between them. the watchdog timer can be configured to generate an interrupt to the microcontroller on its first time-out and to generate a reset on its second time-out. after the watchdog's first time-out event, the 32-bit watchdog counter is reloaded with the value of the watchdog timer load (wdtload) register and resumes counting down from that value. if the timer counts down to zero again before the first time-out interrupt is cleared, and the reset signal has been enabled, the watchdog timer asserts its reset signal to the microcontroller. the watchdog timer reset sequence is as follows: 1. the watchdog timer times out for the second time without being serviced. 2. an internal reset is asserted. 3. the internal reset is released and the microcontroller loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. for more information on the watchdog timer module, see watchdog timers on page 583. 195 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller the watchdog reset timing is shown in figure 26-9 on page 1303. 5.2.3 non-maskable interrupt the microcontroller has three sources of non-maskable interrupt (nmi): the assertion of the nmi signal a main oscillator verification error the nmiset bit in the interrupt control and state (intctrl) register in the cortex ? -m3 (see page 143). software must check the cause of the interrupt in order to distinguish among the sources. 5.2.3.1 nmi pin the nmi signal is the alternate function for gpio port pin pb7 . the alternate function must be enabled in the gpio for the signal to be used as an interrupt, as described in general-purpose input/outputs (gpios) on page 405. note that enabling the nmi alternate function requires the use of the gpio lock and commit function just like the gpio port pins associated with jtag/swd functionality, see page 443. the active sense of the nmi signal is high; asserting the enabled nmi signal above v ih initiates the nmi interrupt sequence. 5.2.3.2 main oscillator verification failure the lm3s9gn5 microcontroller provides a main oscillator verification circuit that generates an error condition if the oscillator is running too fast or too slow. if the main oscillator verification circuit is enabled and a failure occurs, a power-on reset is generated and control is transferred to the nmi handler. the nmi handler is used to address the main oscillator verification failure because the necessary code can be removed from the general reset handler, speeding up reset processing. the detection circuit is enabled by setting the cval bit in the main oscillator control (moscctl) register. the main oscillator verification error is indicated in the main oscillator fail status ( moscfail) bit in the reset cause (resc) register. the main oscillator verification circuit action is described in more detail in main oscillator verification circuit on page 203. 5.2.4 power control the stellaris microcontroller provides an integrated ldo regulator that is used to provide power to the majority of the microcontroller's internal logic. figure 5-4 shows the power architecture. an external ldo may not be used. note: vdda must be supplied with a voltage that meets the specification in table 26-2 on page 1298, or the microcontroller does not function properly. vdda is the supply for all of the analog circuitry on the device, including the clock circuitry. july 03, 2014 196 texas instruments-production data system control figure 5-4. power architecture 5.2.5 clock control system control determines the control of clocks in this part. 5.2.5.1 fundamental clock sources there are multiple clock sources for use in the microcontroller: precision internal oscillator (piosc). the precision internal oscillator is an on-chip clock source that is the clock source the microcontroller uses during and following por. it does not require the use of any external components and provides a clock that is 16 mhz 1% at room temperature and 3% across temperature. the piosc allows for a reduced system cost in applications that require an accurate clock source. if the main oscillator is required, software must enable the main oscillator following reset and allow the main oscillator to stabilize before changing the clock reference. main oscillator (mosc). the main oscillator provides a frequency-accurate clock source by one of two means: an external single-ended clock source is connected to the osc0 input pin, or an external crystal is connected across the osc0 input and osc1 output pins. if the pll is being used, the crystal value must be one of the supported frequencies between 3.579545 mhz to 16.384 mhz (inclusive). if the pll is not being used, the crystal may be any one of the supported frequencies between 1 mhz to 16.384 mhz. the single-ended clock source range is from dc 197 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller $ q d o r j & l u f x l w v , 2 % x i i h u v / r z 1 r l v h / ' 2 , q w h u q d o / r j l f d q g 3 / / * 1 ' * 1 ' $ * 1 ' $ 9 ' ' $ 9 ' ' $ 9 ' ' & 9 ' ' & / ' 2 9 * 1 ' * 1 ' * 1 ' 9 ' ' 9 ' ' through the specified speed of the microcontroller. the supported crystals are listed in the xtal bit field in the rcc register (see page 219). note that the mosc provides the clock source for the usb pll and must be connected to a crystal or an oscillator. internal 30-khz oscillator. the internal 30-khz oscillator provides an operational frequency of 30 khz 50%. it is intended for use during deep-sleep power-saving modes. this power-savings mode benefits from reduced internal switching and also allows the mosc to be powered down. the internal system clock (sysclk), is derived from any of the above sources plus two others: the output of the main internal pll and the precision internal oscillator divided by four (4 mhz 1%). the frequency of the pll clock reference must be in the range of 3.579545 mhz to 16.384 mhz (inclusive). table 5-4 on page 198 shows how the various clock sources can be used in a system. table 5-4. clock source options used as sysclk? drive pll? clock source bypass = 1, oscsrc = 0x1 yes bypass = 0, oscsrc = 0x1 yes precision internal oscillator bypass = 1, oscsrc = 0x2 yes - no precision internal oscillator divide by 4 (4 mhz 1%) bypass = 1, oscsrc = 0x0 yes bypass = 0, oscsrc = 0x0 yes main oscillator bypass = 1, oscsrc = 0x3 yes - no internal 30-khz oscillator 5.2.5.2 clock configuration the run-mode clock configuration (rcc) and run-mode clock configuration 2 (rcc2) registers provide control for the system clock. the rcc2 register is provided to extend fields that offer additional encodings over the rcc register. when used, the rcc2 register field values are used by the logic over the corresponding field in the rcc register. in particular, rcc2 provides for a larger assortment of clock configuration options. these registers control the following clock functionality: source of clocks in sleep and deep-sleep modes system clock derived from pll or other clock source enabling/disabling of oscillators and pll clock divisors crystal input selection important: write the rcc register prior to writing the rcc2 register. if a subsequent write to the rcc register is required, include another register access after writing the rcc register and before writing the rcc2 register. figure 5-5 shows the logic for the main clock tree. the peripheral blocks are driven by the system clock signal and can be individually enabled/disabled. when the pll is enabled, the adc clock signal is automatically divided down to 16 mhz from the pll output for proper adc operation. the pwm clock signal is a synchronous divide of the system clock to provide the pwm circuit with more range (set with pwmdiv in rcc). july 03, 2014 198 texas instruments-production data system control note: when the adc module is in operation, the system clock must be at least 16 mhz. when the usb module is in operation, mosc must be the clock source, either with or without using the pll, and the system clock must be at least 30 mhz. figure 5-5. main clock tree note: the figure above shows all features available on all stellaris? firestorm-class microcontrollers. not all peripherals may be available on this device. 199 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 0 d l q 2 6 & 3 u h f l v l r q , q w h u q d o 2 6 & 0 + ] , q w h u q d o 2 6 & n + ] 3 : 5 ' 1 $ ' & & o r f n 6 \ v w h p & o r f n 0 2 6 & ' , 6 d , 2 6 & ' , 6 d 6 < 6 ' , 9 h 8 6 ( 6 < 6 ' , 9 d g 3 : 0 ' : d 8 6 ( 3 : 0 ' , 9 d 3 : 0 & o r f n + l e h u q d w l r q 2 6 & n + ] 2 6 & 6 5 & e g % < 3 $ 6 6 e g ; 7 $ / d 3 : 5 ' 1 e 8 6 % 3 / / 0 + ] 8 6 % & o r f n ; 7 $ / d 8 6 % 3 : 5 ' 1 f 5 ; , 1 7 5 ; ) 5 $ & , 6 5 h f h l y h 0 & / . , 6 7 u d q v p l w 0 & / . 3 / / 0 + ] 7 ; , 1 7 7 ; ) 5 $ & d & r q w u r o s u r y l g h g e \ 5 & & u h j l v w h u e l w i l h o g e & r q w u r o s u r y l g h g e \ 5 & & u h j l v w h u e l w i l h o g r u 5 & & u h j l v w h u e l w i l h o g l i r y h u u l g g h q z l w k 5 & & u h j l v w h u e l w usercc 2 f & r q w u r o s u r y l g h g e \ 5 & & u h j l v w h u e l w i l h o g g $ o v r p d \ e h f r q w u r o o h g e \ ' 6 / 3 & / . & ) * z k h q l q g h h s v o h h s p r g h h & r q w u r o s u r y l g h g e \ 5 & & u h j l v w h u sysdiv i l h o g 5 & & u h j l v w h u sysdiv 2 i l h o g l i r y h u u l g g h q z l w k usercc 2 e l w r u > sysdiv 2 sysdiv 2 lsb @ l i e r w k usercc 2 d q g div 400 e l w v d u h v h w ' , 9 f using the sysdiv and sysdiv2 fields in the rcc register, the sysdiv field specifies which divisor is used to generate the system clock from either the pll output or the oscillator source (depending on how the bypass bit in this register is configured). when using the pll, the vco frequency of 400 mhz is predivided by 2 before the divisor is applied. table 5-5 shows how the sysdiv encoding affects the system clock frequency, depending on whether the pll is used ( bypass =0) or another clock source is used (bypass=1). the divisor is equivalent to the sysdiv encoding plus 1. for a list of possible clock sources, see table 5-4 on page 198. table 5-5. possible system clock frequencies using the sysdiv field stellarisware ? parameter a frequency ( =1) frequency ( =0) divisor sysctl_sysdiv_1 clock source frequency/1 reserved /1 0x0 sysctl_sysdiv_2 clock source frequency/2 reserved /2 0x1 sysctl_sysdiv_3 clock source frequency/3 66.67 mhz /3 0x2 sysctl_sysdiv_4 clock source frequency/4 50 mhz /4 0x3 sysctl_sysdiv_5 clock source frequency/5 40 mhz /5 0x4 sysctl_sysdiv_6 clock source frequency/6 33.33 mhz /6 0x5 sysctl_sysdiv_7 clock source frequency/7 28.57 mhz /7 0x6 sysctl_sysdiv_8 clock source frequency/8 25 mhz /8 0x7 sysctl_sysdiv_9 clock source frequency/9 22.22 mhz /9 0x8 sysctl_sysdiv_10 clock source frequency/10 20 mhz /10 0x9 sysctl_sysdiv_11 clock source frequency/11 18.18 mhz /11 0xa sysctl_sysdiv_12 clock source frequency/12 16.67 mhz /12 0xb sysctl_sysdiv_13 clock source frequency/13 15.38 mhz /13 0xc sysctl_sysdiv_14 clock source frequency/14 14.29 mhz /14 0xd sysctl_sysdiv_15 clock source frequency/15 13.33 mhz /15 0xe sysctl_sysdiv_16 clock source frequency/16 12.5 mhz (default) /16 0xf a. this parameter is used in functions such as sysctlclockset() in the stellaris peripheral driver library. the sysdiv2 field in the rcc2 register is 2 bits wider than the sysdiv field in the rcc register so that additional larger divisors up to /64 are possible, allowing a lower system clock frequency for improved deep sleep power consumption. when using the pll, the vco frequency of 400 mhz is predivided by 2 before the divisor is applied. the divisor is equivalent to the sysdiv2 encoding plus 1. table 5-6 shows how the sysdiv2 encoding affects the system clock frequency, depending on whether the pll is used ( bypass2 =0) or another clock source is used (bypass2 =1). for a list of possible clock sources, see table 5-4 on page 198. table 5-6. examples of possible system clock frequencies using the sysdiv2 field stellarisware parameter a frequency ( =1) frequency (=0) divisor sysctl_sysdiv_1 clock source frequency/1 reserved /1 0x00 sysctl_sysdiv_2 clock source frequency/2 reserved /2 0x01 sysctl_sysdiv_3 clock source frequency/3 66.67 mhz /3 0x02 sysctl_sysdiv_4 clock source frequency/4 50 mhz /4 0x03 sysctl_sysdiv_5 clock source frequency/5 40 mhz /5 0x04 ... ... ...... ... july 03, 2014 200 texas instruments-production data system control table 5-6. examples of possible system clock frequencies using the sysdiv2 field (continued) stellarisware parameter a frequency ( bypass2=1) frequency (bypass2=0) divisor sysdiv2 sysctl_sysdiv_10 clock source frequency/10 20 mhz /10 0x09 ... ... ...... ... sysctl_sysdiv_64 clock source frequency/64 3.125 mhz /64 0x3f a. this parameter is used in functions such as sysctlclockset() in the stellaris peripheral driver library. to allow for additional frequency choices when using the pll, the div400 bit is provided along with the sysdiv2lsb bit. when the div400 bit is set, bit 22 becomes the lsb for sysdiv2 . in this situation, the divisor is equivalent to the ( sysdiv2 encoding with sysdiv2lsb appended) plus one. table 5-7 shows the frequency choices when div400 is set. when the div400 bit is clear, sysdiv2lsb is ignored, and the system clock frequency is determined as shown in table 5-6 on page 200. table 5-7. examples of possible system clock frequencies with div400=1 stellarisware parameter b frequency ( bypass2=0) a divisor sysdiv2lsb sysdiv2 - reserved /2 reserved 0x00 - reserved /3 0 0x01 - reserved /4 1 sysctl_sysdiv_2_5 80 mhz /5 0 0x02 sysctl_sysdiv_3 66.67 mhz /6 1 - reserved /7 0 0x03 sysctl_sysdiv_4 50 mhz /8 1 sysctl_sysdiv_4_5 44.44 mhz /9 0 0x04 sysctl_sysdiv_5 40 mhz /10 1 ... ... ... ... ... sysctl_sysdiv_63_5 3.15 mhz /127 0 0x3f sysctl_sysdiv_64 3.125 mhz /128 1 a. note that div400 and sysdiv2lsb are only valid when bypass2=0. b. this parameter is used in functions such as sysctlclockset() in the stellaris peripheral driver library. 5.2.5.3 precision internal oscillator operation (piosc) the microcontroller powers up with the piosc running. if another clock source is desired, the piosc must remain enabled as it is used for internal functions. the piosc can only be disabled during deep-sleep mode. it can be powered down by setting the ioscdis bit in the rcc register. the piosc generates a 16-mhz clock with a 1% accuracy at room temperatures. across the extended temperature range, the accuracy is 3%. at the factory, the piosc is set to 16 mhz at room temperature, however, the frequency can be trimmed for other voltage or temperature conditions using software in one of two ways: default calibration: clear the uten bit and set the update bit in the precision internal oscillator calibration (piosccal) register. user-defined calibration: the user can program the ut value to adjust the piosc frequency. as the ut value increases, the generated period increases. to commit a new ut value, first set the 201 july 03, 2014 texas instruments-production data stellaris lm3s9gn5 microcontroller uten bit, then program the ut field, and then set the update bit. the adjustment finishes within a few clock periods and is glitch free. 5.2.5.4 crystal configuration for the main oscillator (mosc) the main oscillator supports the use of a select number of crystals. if the main oscillator is used by the pll as a reference clock, the supported range of crystals is 3.579545 to 16.384 mhz, otherwise, the range of supported crystals is 1 to 16.384 mhz. the xtal bit in the rcc register (see page 219) describes the available crystal choices and default programming values. software configures the rcc register xtal field with the crystal number. if the pll is used in the design, the xtal field value is internally translated to the pll settings. 5.2.5.5 main pll frequency configuration the main pll is disabled by default during power-on reset and is enabled later by software if required. software specifies the output divisor to set the system clock frequency and enables the main pll to drive the output. the pll operates at 400 mhz, but is divided by two prior to the application of the output divisor, unless the div400 bit in the rcc2 register is set. to configure the piosc to be the clock source for the main pll, program the oscrc2 field in the run-mode clock configuration 2 (rcc2) register to be 0x1. if the main oscillator provides the clock reference to the main pll, the translation provided by hardware and used to program the pll is available for software in the xtal to pll translation (pllcfg) register (see page 224). the internal translation provides a translation within 1% of the targeted pll vco frequency. table 26-8 on page 1304 shows the actual pll frequency and error for a given crystal choice. the crystal value field ( xtal ) in the run-mode clock configuration (rcc) register (see page 219) describes the available crystal choices and default programming of the pllcfg register. any time the xtal field changes, the new settings are translated and the internal pll settings are updated. 5.2.5.6 usb pll frequency configuration the usb pll is disabled by default during power-on reset and is enabled later by software. the usb pll must be enabled and running for proper usb function. the main oscillator is the only clock reference for the usb pll. the usb pll is enabled by clearing the usbpwrdn bit of the rcc2 register. the xtal bit field (crystal value) of the rcc register describes the available crystal choices. the main oscillator must be connected to one of the following crystal values in order to correctly generate the usb clock: 4, 5, 6, 8, 10, 12, or 16 mhz. only these crystals provide the necessary usb pll vco frequency to conform with the usb timing specifications. 5.2.5.7 pll modes both plls have two modes of operation: normal and power-down normal: the pll multiplies the input clock reference and drives the output. power-down: most of the pll internal circuitry is disabled and the pll does not drive the output. the modes are programmed using the rcc/ rcc2 register fields (see page 219 and page 227). july 03, 2014 202 texas instruments-production data system control 5.2.5.8 pll operation if a pll configuration is changed, the pll output frequency is unstable until it reconverges (relocks) to the new setting. the time between the configuration change and relock is t ready (see table 26-7 on page 1303). during the relock time, the affected pll is not usable as a clock reference. either pll is changed by one of the following: change to the xtal value in the rcc registerwrites of the same value do not cause a relock. change in the pll from power-down to normal mode. a counter clocked by the system clock is used to measure the t ready requirement. if the system clock is the main oscillator and it is running off an 8.192 mhz or slower external oscillator clock, the down counter is set to 0x1200 (that is, ~600 s at an 8.192 mhz). if the system clock is running off the piosc or an external oscillator clock that is faster than 8.192 mhz, the down counter is set to 0x2400. hardware is provided to keep the pll from being used as a system clock until the t ready condition is met after one of the two changes above. it is the user's responsibility to have a stable clock source (like the main oscillator) before the rcc/ rcc2 register is switched to use the pll. if the main pll is enabled and the system clock is switched to use the pll in one step, the system control hardware continues to clock the microcontroller from the oscillator selected by the rcc/ rcc2 register until the main pll is stable (t ready time met), after which it changes to the pll. software can use many methods to ensure that the system is clocked from the main pll, including periodically polling the plllris bit in the raw interrupt status (ris) register, and enabling the pll lock interrupt. the usb pll is not protected during the lock time (t ready ), and software should ensure that the usb pll has locked before using the interface. software can use many methods to ensure the t ready period has passed, including periodically polling the usbplllris bit in the raw interrupt status (ris) register, and enabling the usb pll lock interrupt. 5.2.5.9 main oscillator verification circuit the clock control includes circuitry to ensure that the main oscillator is running at the appropriate frequency. the circuit monitors the main oscillator frequency and signals if the frequency is outside of the allowable band of attached crystals. the detection circuit is enabled using the cval bit in the main oscillator control (moscctl) register. if this circuit is enabled and detects an error, the following sequence is performed by the hardware: 1. the moscfail bit in the reset cause (resc) register is set. 2. if the internal oscillator (piosc) is disabled, it is enabled. 3. the system clock is switched from the main oscillator to the piosc. 4. an internal power-on reset is initiated that lasts for 32 piosc periods. 5. reset is de-asserted and the processor is directed to the nmi handler during the reset sequence. 5.2.6 system control for power-savings purposes, the rcgcn , scgcn , and dcgcn registers control the clock gating logic for each peripheral or block in the system while the microcontroller is in run, sleep, and deep-sleep mode, respectively. these registers are located in the system control register map 203 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller starting at offsets 0x600, 0x700, and 0x800, respectively. there must be a delay of 3 system clocks after a peripheral module clock is enabled in the rcgc register before any module registers are accessed. there are three levels of operation for the microcontroller defined as: run mode sleep mode deep-sleep mode the following sections describe the different modes in detail. caution C if the cortex-m3 debug access port (dap) has been enabled, and the device wakes from a low power sleep or deep-sleep mode, the core may start executing code before all clocks to peripherals have been restored to their run mode confguration. the dap is usually enabled by software tools accessing the jtag or swd interface when debugging or fash programming. if this condition occurs, a hard fault is triggered when software accesses a peripheral with an invalid clock. a software delay loop can be used at the beginning of the interrupt routine that is used to wake up a system from a wfi (wait for interrupt) instruction. this stalls the execution of any code that accesses a peripheral register that might cause a fault. this loop can be removed for production software as the dap is most likely not enabled during normal execution. because the dap is disabled by default (power on reset), the user can also power cycle the device. the dap is not enabled unless it is enabled through the jtag or swd interface. 5.2.6.1 run mode in run mode, the microcontroller actively executes code. run mode provides normal operation of the processor and all of the peripherals that are currently enabled by the rcgcn registers. the system clock can be any of the available clock sources including the pll. 5.2.6.2 sleep mode in sleep mode, the clock frequency of the active peripherals is unchanged, but the processor and the memory subsystem are not clocked and therefore no longer execute code. sleep mode is entered by the cortex-m3 core executing a wfi (wait for interrupt) instruction. any properly configured interrupt event in the system brings the processor back into run mode. see power management on page 107 for more details. peripherals are clocked that are enabled in the scgcn registers when auto-clock gating is enabled (see the rcc register) or the rcgcn registers when the auto-clock gating is disabled. the system clock has the same source and frequency as that during run mode. 5.2.6.3 deep-sleep mode in deep-sleep mode, the clock frequency of the active peripherals may change (depending on the run mode clock configuration) in addition to the processor clock being stopped. an interrupt returns the microcontroller to run mode from one of the sleep modes; the sleep modes are entered on request from the code. deep-sleep mode is entered by first setting the sleepdeep bit in the system control (sysctrl) register (see page 149) and then executing a wfi instruction. any properly configured interrupt event in the system brings the processor back into run mode. see power management on page 107 for more details. july 03, 2014 204 texas instruments-production data system control the cortex-m3 processor core and the memory subsystem are not clocked in deep-sleep mode. peripherals are clocked that are enabled in the dcgcn registers when auto-clock gating is enabled (see the rcc register) or the rcgcn registers when auto-clock gating is disabled. the system clock source is specified in the dslpclkcfg register. when the dslpclkcfg register is used, the internal oscillator source is powered up, if necessary, and other clocks are powered down. if the pll is running at the time of the wfi instruction, hardware powers the pll down and overrides the sysdiv field of the active rcc/ rcc2 register, to be determined by the dsdivoride setting in the dslpclkcfg register, up to /16 or /64 respectively. when the deep-sleep exit event occurs, hardware brings the system clock back to the source and frequency it had at the onset of deep-sleep mode before enabling the clocks that had been stopped during the deep-sleep duration. if the piosc is used as the pll reference clock source, it may continue to provide the clock during deep-sleep. see page 231. 5.3 initialization and configuration the pll is configured using direct register writes to the rcc/ rcc2 register. if the rcc2 register is being used, the usercc2 bit must be set and the appropriate rcc2 bit/field is used. the steps required to successfully change the pll-based system clock are: 1. bypass the pll and system clock divider by setting the bypass bit and clearing the usesys bit in the rcc register, thereby configuring the microcontroller to run off a "raw" clock source and allowing for the new pll configuration to be validated before switching the system clock to the pll. 2. select the crystal value ( xtal ) and oscillator source (oscsrc ), and clear the pwrdn bit in rcc/ rcc2 . setting the xtal field automatically pulls valid pll configuration data for the appropriate crystal, and clearing the pwrdn bit powers and enables the pll and its output. 3. select the desired system divider ( sysdiv ) in rcc/ rcc2 and set the usesys bit in rcc . the sysdiv field determines the system frequency for the microcontroller. 4. wait for the pll to lock by polling the plllris bit in the raw interrupt status (ris ) register. 5. enable use of the pll by clearing the bypass bit in rcc/ rcc2. 5.4 register map table 5-8 on page 205 lists the system control registers, grouped by function. the offset listed is a hexadecimal increment to the register's address, relative to the system control base address of 0x400f.e000. note: spaces in the system control register space that are not used are reserved for future or internal use. software should not modify any reserved memory address. additional flash and rom registers defined in the system control register space are described in the internal memory on page 298. table 5-8. system control register map see page description reset type name offset 208 device identification 0 - ro did0 0x000 236 device identification 1 - ro did1 0x004 205 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 5-8. system control register map (continued) see page description reset type name offset 238 device capabilities 0 0x00ff.00bf ro dc0 0x008 239 device capabilities 1 - ro dc1 0x010 242 device capabilities 2 0x570f.5337 ro dc2 0x014 244 device capabilities 3 0xbfff.ffff ro dc3 0x018 247 device capabilities 4 0x1104.f1ff ro dc4 0x01c 249 device capabilities 5 0x0f30.00ff ro dc5 0x020 251 device capabilities 6 0x0000.0013 ro dc6 0x024 252 device capabilities 7 0xffff.ffff ro dc7 0x028 256 device capabilities 8 adc channels 0xffff.ffff ro dc8 0x02c 210 brown-out reset control 0x0000.0002 r/w pborctl 0x030 291 software reset control 0 0x00000000 r/w srcr0 0x040 293 software reset control 1 0x00000000 r/w srcr1 0x044 296 software reset control 2 0x00000000 r/w srcr2 0x048 211 raw interrupt status 0x0000.0000 ro ris 0x050 213 interrupt mask control 0x0000.0000 r/w imc 0x054 215 masked interrupt status and clear 0x0000.0000 r/w1c misc 0x058 217 reset cause - r/w resc 0x05c 219 run-mode clock configuration 0x078e.3ad1 r/w rcc 0x060 224 xtal to pll translation - ro pllcfg 0x064 225 gpio high-performance bus control 0x0000.0000 r/w gpiohbctl 0x06c 227 run-mode clock configuration 2 0x07c0.6810 r/w rcc2 0x070 230 main oscillator control 0x0000.0000 r/w moscctl 0x07c 262 run mode clock gating control register 0 0x00000040 r/w rcgc0 0x100 270 run mode clock gating control register 1 0x00000000 r/w rcgc1 0x104 282 run mode clock gating control register 2 0x00000000 r/w rcgc2 0x108 265 sleep mode clock gating control register 0 0x00000040 r/w scgc0 0x110 274 sleep mode clock gating control register 1 0x00000000 r/w scgc1 0x114 285 sleep mode clock gating control register 2 0x00000000 r/w scgc2 0x118 268 deep sleep mode clock gating control register 0 0x00000040 r/w dcgc0 0x120 278 deep-sleep mode clock gating control register 1 0x00000000 r/w dcgc1 0x124 288 deep sleep mode clock gating control register 2 0x00000000 r/w dcgc2 0x128 231 deep sleep clock configuration 0x0780.0000 r/w dslpclkcfg 0x144 july 03, 2014 206 texas instruments-production data system control table 5-8. system control register map (continued) see page description reset type name offset 233 precision internal oscillator calibration 0x0000.0000 r/w piosccal 0x150 234 i2s mclk configuration 0x0000.0000 r/w i2smclkcfg 0x170 259 device capabilities 9 adc digital comparators 0x00ff.00ff ro dc9 0x190 261 non-volatile memory information 0x0000.0001 ro nvmstat 0x1a0 5.5 register descriptions all addresses given are relative to the system control base address of 0x400f.e000. 207 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 1: device identification 0 (did0), offset 0x000 this register identifies the version of the microcontroller. each microcontroller is uniquely identified by the combined values of the class field in the did0 register and the partno field in the did1 register. device identification 0 (did0) base 0x400f.e000 offset 0x000 type ro, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 class reserved ver reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 minor major ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type - - - - - - - - - - - - - - - - reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31 did0 version this field defines the did0 register format version. the version number is numeric. the value of the ver field is encoded as follows (all other encodings are reserved): description value second version of the did0 register format. 0x1 0x1 ro ver 30:28 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 27:24 device class the class field value identifies the internal design from which all mask sets are generated for all microcontrollers in a particular product line. the class field value is changed for new product lines, for changes in fab process (for example, a remap or shrink), or any case where the major or minor fields require differentiation from prior microcontrollers. the value of the class field is encoded as follows (all other encodings are reserved): description value stellaris? firestorm-class microcontrollers 0x06 0x06 ro class 23:16 july 03, 2014 208 texas instruments-production data system control description reset type name bit/field major revision this field specifies the major revision number of the microcontroller. the major revision reflects changes to base layers of the design. the major revision number is indicated in the part number as a letter (a for first revision, b for second, and so on). this field is encoded as follows: description value revision a (initial device) 0x0 revision b (first base layer revision) 0x1 revision c (second base layer revision) 0x2 and so on. - ro major 15:8 minor revision this field specifies the minor revision number of the microcontroller. the minor revision reflects changes to the metal layers of the design. the minor field value is reset when the major field is changed. this field is numeric and is encoded as follows: description value initial device, or a major revision update. 0x0 first metal layer change. 0x1 second metal layer change. 0x2 and so on. - ro minor 7:0 209 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 2: brown-out reset control (pborctl), offset 0x030 this register is responsible for controlling reset conditions after initial power-on reset. brown-out reset control (pborctl) base 0x400f.e000 offset 0x030 type r/w, reset 0x0000.0002 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved borior reserved ro r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:2 bor interrupt or reset description value a brown out event causes an interrupt to be generated to the interrupt controller. 0 a brown out event causes a reset of the microcontroller. 1 1 r/w borior 1 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 0 july 03, 2014 210 texas instruments-production data system control register 3: raw interrupt status (ris), offset 0x050 this register indicates the status for system control raw interrupts. an interrupt is sent to the interrupt controller if the corresponding bit in the interrupt mask control (imc) register is set. writing a 1 to the corresponding bit in the masked interrupt status and clear (misc) register clears an interrupt status bit. raw interrupt status (ris) base 0x400f.e000 offset 0x050 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved borris reserved plllris usbplllris moscpupris reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:9 mosc power up raw interrupt status description value sufficient time has passed for the mosc to reach the expected frequency. the value for this power-up time is indicated by t mosc_start . 1 sufficient time has not passed for the mosc to reach the expected frequency. 0 this bit is cleared by writing a 1 to the moscpupmis bit in the misc register. 0 ro moscpupris 8 usb pll lock raw interrupt status description value the usb pll timer has reached t ready indicating that sufficient time has passed for the usb pll to lock. 1 the usb pll timer has not reached t ready . 0 this bit is cleared by writing a 1 to the usbplllmis bit in the misc register. 0 ro usbplllris 7 pll lock raw interrupt status description value the pll timer has reached t ready indicating that sufficient time has passed for the pll to lock. 1 the pll timer has not reached t ready . 0 this bit is cleared by writing a 1 to the plllmis bit in the misc register. 0 ro plllris 6 211 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 5:2 brown-out reset raw interrupt status description value a brown-out condition is currently active. 1 a brown-out condition is not currently active. 0 note the borior bit in the pborctl register must be cleared to cause an interrupt due to a brown out event. this bit is cleared by writing a 1 to the bormis bit in the misc register. 0 ro borris 1 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 0 july 03, 2014 212 texas instruments-production data system control register 4: interrupt mask control (imc), offset 0x054 this register contains the mask bits for system control raw interrupts. a raw interrupt, indicated by a bit being set in the raw interrupt status (ris) register, is sent to the interrupt controller if the corresponding bit in this register is set. interrupt mask control (imc) base 0x400f.e000 offset 0x054 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved borim reserved plllim usbplllim moscpupim reserved ro r/w ro ro ro ro r/w r/w r/w ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:9 mosc power up interrupt mask description value an interrupt is sent to the interrupt controller when the moscpupris bit in the ris register is set. 1 the moscpupris interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w moscpupim 8 usb pll lock interrupt mask description value an interrupt is sent to the interrupt controller when the usbplllris bit in the ris register is set. 1 the usbplllris interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w usbplllim 7 pll lock interrupt mask description value an interrupt is sent to the interrupt controller when the plllris bit in the ris register is set. 1 the plllris interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w plllim 6 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 5:2 213 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field brown-out reset interrupt mask description value an interrupt is sent to the interrupt controller when the borris bit in the ris register is set. 1 the borris interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w borim 1 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 0 july 03, 2014 214 texas instruments-production data system control register 5: masked interrupt status and clear (misc), offset 0x058 on a read, this register gives the current masked status value of the corresponding interrupt in the raw interrupt status (ris) register. all of the bits are r/w1c, thus writing a 1 to a bit clears the corresponding raw interrupt bit in the ris register (see page 211). masked interrupt status and clear (misc) base 0x400f.e000 offset 0x058 type r/w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved bormis reserved plllmis usbplllmis moscpupmis reserved ro r/w1c ro ro ro ro r/w1c r/w1c r/w1c ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:9 mosc power up masked interrupt status description value when read, a 1 indicates that an unmasked interrupt was signaled because sufficient time has passed for the mosc pll to lock. writing a 1 to this bit clears it and also the moscpupris bit in the ris register. 1 when read, a 0 indicates that sufficient time has not passed for the mosc pll to lock. a write of 0 has no effect on the state of this bit. 0 0 r/w1c moscpupmis 8 usb pll lock masked interrupt status description value when read, a 1 indicates that an unmasked interrupt was signaled because sufficient time has passed for the usb pll to lock. writing a 1 to this bit clears it and also the usbplllris bit in the ris register. 1 when read, a 0 indicates that sufficient time has not passed for the usb pll to lock. a write of 0 has no effect on the state of this bit. 0 0 r/w1c usbplllmis 7 215 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field pll lock masked interrupt status description value when read, a 1 indicates that an unmasked interrupt was signaled because sufficient time has passed for the pll to lock. writing a 1 to this bit clears it and also the plllris bit in the ris register. 1 when read, a 0 indicates that sufficient time has not passed for the pll to lock. a write of 0 has no effect on the state of this bit. 0 0 r/w1c plllmis 6 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 5:2 bor masked interrupt status description value when read, a 1 indicates that an unmasked interrupt was signaled because of a brown-out condition. writing a 1 to this bit clears it and also the borris bit in the ris register. 1 when read, a 0 indicates that a brown-out condition has not occurred. a write of 0 has no effect on the state of this bit. 0 0 r/w1c bormis 1 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 0 july 03, 2014 216 texas instruments-production data system control register 6: reset cause (resc), offset 0x05c this register is set with the reset cause after reset. the bits in this register are sticky and maintain their state across multiple reset sequences, except when a power- on reset or an external reset is the cause, in which case, all bits other than por or ext in the resc register are cleared. reset cause (resc) base 0x400f.e000 offset 0x05c type r/w, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 moscfail reserved r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ext por bor wdt0 sw wdt1 reserved r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro type - - - - - - 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 31:17 mosc failure reset description value when read, this bit indicates that the mosc circuit was enabled for clock validation and failed, generating a reset event. 1 when read, this bit indicates that a mosc failure has not generated a reset since the previous power-on reset. writing a 0 to this bit clears it. 0 - r/w moscfail 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 15:6 watchdog timer 1 reset description value when read, this bit indicates that watchdog timer 1 timed out and generated a reset. 1 when read, this bit indicates that watchdog timer 1 has not generated a reset since the previous power-on reset. writing a 0 to this bit clears it. 0 - r/w wdt1 5 217 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field software reset description value when read, this bit indicates that a software reset has caused a reset event. 1 when read, this bit indicates that a software reset has not generated a reset since the previous power-on reset. writing a 0 to this bit clears it. 0 - r/w sw 4 watchdog timer 0 reset description value when read, this bit indicates that watchdog timer 0 timed out and generated a reset. 1 when read, this bit indicates that watchdog timer 0 has not generated a reset since the previous power-on reset. writing a 0 to this bit clears it. 0 - r/w wdt0 3 brown-out reset description value when read, this bit indicates that a brown-out reset has caused a reset event. 1 when read, this bit indicates that a brown-out reset has not generated a reset since the previous power-on reset. writing a 0 to this bit clears it. 0 - r/w bor 2 power-on reset description value when read, this bit indicates that a power-on reset has caused a reset event. 1 when read, this bit indicates that a power-on reset has not generated a reset. writing a 0 to this bit clears it. 0 - r/w por 1 external reset description value when read, this bit indicates that an external reset ( rst assertion) has caused a reset event. 1 when read, this bit indicates that an external reset ( rst assertion) has not caused a reset event since the previous power-on reset. writing a 0 to this bit clears it. 0 - r/w ext 0 july 03, 2014 218 texas instruments-production data system control register 7: run-mode clock configuration (rcc), offset 0x060 the bits in this register configure the system clock and oscillators. important: write the rcc register prior to writing the rcc2 register. if a subsequent write to the rcc register is required, include another register access after writing the rcc register and before writing the rcc2 register. run-mode clock configuration (rcc) base 0x400f.e000 offset 0x060 type r/w, reset 0x078e.3ad1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved pwmdiv usepwmdiv reserved usesysdiv sysdiv acg reserved ro r/w r/w r/w r/w ro r/w r/w r/w r/w r/w r/w ro ro ro ro type 0 1 1 1 0 0 0 1 1 1 1 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 moscdis ioscdis reserved oscsrc xtal bypass reserved pwrdn reserved r/w r/w ro ro r/w r/w r/w r/w r/w r/w r/w r/w ro r/w ro ro type 1 0 0 0 1 0 1 1 0 1 0 1 1 1 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 31:28 auto clock gating this bit specifies whether the system uses the sleep-mode clock gating control (scgcn) registers and deep-sleep-mode clock gating control (dcgcn) registers if the microcontroller enters a sleep or deep-sleep mode (respectively). description value the scgcn or dcgcn registers are used to control the clocks distributed to the peripherals when the microcontroller is in a sleep mode. the scgcn and dcgcn registers allow unused peripherals to consume less power when the microcontroller is in a sleep mode. 1 the run-mode clock gating control (rcgcn) registers are used when the microcontroller enters a sleep mode. 0 the rcgcn registers are always used to control the clocks in run mode. 0 r/w acg 27 system clock divisor specifies which divisor is used to generate the system clock from either the pll output or the oscillator source (depending on how the bypass bit in this register is configured). see table 5-5 on page 200 for bit encodings. if the sysdiv value is less than minsysdiv (see page 239), and the pll is being used, then the minsysdiv value is used as the divisor. if the pll is not being used, the sysdiv value can be less than minsysdiv. 0xf r/w sysdiv 26:23 219 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field enable system clock divider description value the system clock divider is the source for the system clock. the system clock divider is forced to be used when the pll is selected as the source. if the usercc2 bit in the rcc2 register is set, then the sysdiv2 field in the rcc2 register is used as the system clock divider rather than the sysdiv field in this register. 1 the system clock is used undivided. 0 0 r/w usesysdiv 22 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 21 enable pwm clock divisor description value the pwm clock divider is the source for the pwm clock. 1 the system clock is the source for the pwm clock. 0 note that when the pwm divisor is used, it is applied to the clock for both pwm modules. 0 r/w usepwmdiv 20 pwm unit clock divisor this field specifies the binary divisor used to predivide the system clock down for use as the timing reference for the pwm module. the rising edge of this clock is synchronous with the system clock. divisor value /20x0 /40x1 /80x2 /160x3 /320x4 /640x5 /640x6 /64 (default) 0x7 0x7 r/w pwmdiv 19:17 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 16:14 pll power down description value the pll is powered down. care must be taken to ensure that another clock source is functioning and that the bypass bit is set before setting this bit. 1 the pll is operating normally. 0 1 r/w pwrdn 13 july 03, 2014 220 texas instruments-production data system control description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 ro reserved 12 pll bypass description value the system clock is derived from the osc source and divided by the divisor specified by sysdiv. 1 the system clock is the pll output clock divided by the divisor specified by sysdiv. 0 see table 5-5 on page 200 for programming guidelines. note: the adc must be clocked from the pll or directly from a 16-mhz clock source to operate properly. 1 r/w bypass 11 221 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field crystal value this field specifies the crystal value attached to the main oscillator. the encoding for this field is provided below. depending on the crystal used, the pll frequency may not be exactly 400 mhz, see table 26-8 on page 1304 for more information. frequencies that may be used with the usb interface are indicated in the table. to function within the clocking requirements of the usb specification, a crystal of 4, 5, 6, 8, 10, 12, or 16 mhz must be used. crystal frequency (mhz) using the pll crystal frequency (mhz) not using the pll value reserved 1.000 mhz 0x00 reserved 1.8432 mhz 0x01 reserved 2.000 mhz 0x02 reserved 2.4576 mhz 0x03 3.579545 mhz 0x04 3.6864 mhz 0x05 4 mhz (usb) 0x06 4.096 mhz 0x07 4.9152 mhz 0x08 5 mhz (usb) 0x09 5.12 mhz 0x0a 6 mhz (reset value)(usb) 0x0b 6.144 mhz 0x0c 7.3728 mhz 0x0d 8 mhz (usb) 0x0e 8.192 mhz 0x0f 10.0 mhz (usb) 0x10 12.0 mhz (usb) 0x11 12.288 mhz 0x12 13.56 mhz 0x13 14.31818 mhz 0x14 16.0 mhz (usb) 0x15 16.384 mhz 0x16 0x0b r/w xtal 10:6 july 03, 2014 222 texas instruments-production data system control description reset type name bit/field oscillator source selects the input source for the osc. the values are: input source value mosc main oscillator 0x0 piosc precision internal oscillator (default) 0x1 piosc/4 precision internal oscillator / 4 0x2 30 khz 30-khz internal oscillator 0x3 for additional oscillator sources, see the rcc2 register. 0x1 r/w oscsrc 5:4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 3:2 precision internal oscillator disable description value the precision internal oscillator (piosc) is disabled. 1 the precision internal oscillator is enabled. 0 0 r/w ioscdis 1 main oscillator disable description value the main oscillator is disabled (default). 1 the main oscillator is enabled. 0 1 r/w moscdis 0 223 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 8: xtal to pll translation (pllcfg), offset 0x064 this register provides a means of translating external crystal frequencies into the appropriate pll settings. this register is initialized during the reset sequence and updated anytime that the xtal field changes in the run-mode clock configuration (rcc) register (see page 219). the pll frequency is calculated using the pllcfg field values, as follows: pllfreq = oscfreq * f / (r + 1) xtal to pll translation (pllcfg) base 0x400f.e000 offset 0x064 type ro, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r f reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type - - - - - - - - - - - - - - 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0 ro reserved 31:14 pll f value this field specifies the value supplied to the plls f input. - ro f 13:5 pll r value this field specifies the value supplied to the plls r input. - ro r 4:0 july 03, 2014 224 texas instruments-production data system control register 9: gpio high-performance bus control (gpiohbctl), offset 0x06c this register controls which internal bus is used to access each gpio port. when a bit is clear, the corresponding gpio port is accessed across the legacy advanced peripheral bus (apb) bus and through the apb memory aperture. when a bit is set, the corresponding port is accessed across the advanced high-performance bus (ahb) bus and through the ahb memory aperture. each gpio port can be individually configured to use ahb or apb, but may be accessed only through one aperture. the ahb bus provides better back-to-back access performance than the apb bus. the address aperture in the memory map changes for the ports that are enabled for ahb access (see table 8-7 on page 417). gpio high-performance bus control (gpiohbctl) base 0x400f.e000 offset 0x06c type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 porta portb portc portd porte portf portg porth portj reserved r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0 ro reserved 31:9 port j advanced high-performance bus this bit defines the memory aperture for port j. description value advanced high-performance bus (ahb) 1 advanced peripheral bus (apb). this bus is the legacy bus. 0 0 r/w portj 8 port h advanced high-performance bus this bit defines the memory aperture for port h. description value advanced high-performance bus (ahb) 1 advanced peripheral bus (apb). this bus is the legacy bus. 0 0 r/w porth 7 port g advanced high-performance bus this bit defines the memory aperture for port g. description value advanced high-performance bus (ahb) 1 advanced peripheral bus (apb). this bus is the legacy bus. 0 0 r/w portg 6 225 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field port f advanced high-performance bus this bit defines the memory aperture for port f. description value advanced high-performance bus (ahb) 1 advanced peripheral bus (apb). this bus is the legacy bus. 0 0 r/w portf 5 port e advanced high-performance bus this bit defines the memory aperture for port e. description value advanced high-performance bus (ahb) 1 advanced peripheral bus (apb). this bus is the legacy bus. 0 0 r/w porte 4 port d advanced high-performance bus this bit defines the memory aperture for port d. description value advanced high-performance bus (ahb) 1 advanced peripheral bus (apb). this bus is the legacy bus. 0 0 r/w portd 3 port c advanced high-performance bus this bit defines the memory aperture for port c. description value advanced high-performance bus (ahb) 1 advanced peripheral bus (apb). this bus is the legacy bus. 0 0 r/w portc 2 port b advanced high-performance bus this bit defines the memory aperture for port b. description value advanced high-performance bus (ahb) 1 advanced peripheral bus (apb). this bus is the legacy bus. 0 0 r/w portb 1 port a advanced high-performance bus this bit defines the memory aperture for port a. description value advanced high-performance bus (ahb) 1 advanced peripheral bus (apb). this bus is the legacy bus. 0 0 r/w porta 0 july 03, 2014 226 texas instruments-production data system control register 10: run-mode clock configuration 2 (rcc2), offset 0x070 this register overrides the rcc equivalent register fields, as shown in table 5-9, when the usercc2 bit is set, allowing the extended capabilities of the rcc2 register to be used while also providing a means to be backward-compatible to previous parts. each rcc2 field that supersedes an rcc field is located at the same lsb bit position; however, some rcc2 fields are larger than the corresponding rcc field. table 5-9. rcc2 fields that override rcc fields overrides rcc field rcc2 field... sysdiv , bits[26:23] sysdiv2 , bits[28:23] pwrdn , bit[13] pwrdn2 , bit[13] bypass , bit[11] bypass2 , bit[11] oscsrc , bits[5:4] oscsrc2 , bits[6:4] important: write the rcc register prior to writing the rcc2 register. if a subsequent write to the rcc register is required, include another register access after writing the rcc register and before writing the rcc2 register. run-mode clock configuration 2 (rcc2) base 0x400f.e000 offset 0x070 type r/w, reset 0x07c0.6810 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved sysdiv2lsb sysdiv2 reserved div400 usercc2 ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w ro r/w r/w type 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved oscsrc2 reserved bypass2 reserved pwrdn2 usbpwrdn reserved ro ro ro ro r/w r/w r/w ro ro ro ro r/w ro r/w r/w ro type 0 0 0 0 1 0 0 0 0 0 0 1 0 1 1 0 reset description reset type name bit/field use rcc2 description value the rcc2 register fields override the rcc register fields. 1 the rcc register fields are used, and the fields in rcc2 are ignored. 0 0 r/w usercc2 31 divide pll as 400 mhz vs. 200 mhz this bit, along with the sysdiv2lsb bit, allows additional frequency choices. description value append the sysdiv2lsb bit to the sysdiv2 field to create a 7 bit divisor using the 400 mhz pll output, see table 5-7 on page 201. 1 use sysdiv2 as is and apply to 200 mhz predivided pll output. see table 5-6 on page 200 for programming guidelines. 0 0 r/w div400 30 227 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 29 system clock divisor 2 specifies which divisor is used to generate the system clock from either the pll output or the oscillator source (depending on how the bypass2 bit is configured). sysdiv2 is used for the divisor when both the usesysdiv bit in the rcc register and the usercc2 bit in this register are set. see table 5-6 on page 200 for programming guidelines. 0x0f r/w sysdiv2 28:23 additional lsb for sysdiv2 when div400 is set, this bit becomes the lsb of sysdiv2 . if div400 is clear, this bit is not used. see table 5-6 on page 200 for programming guidelines. this bit can only be set or cleared when div400 is set. 1 r/w sysdiv2lsb 22 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 21:15 power-down usb pll description value the usb pll is powered down. 1 the usb pll operates normally. 0 1 r/w usbpwrdn 14 power-down pll 2 description value the pll is powered down. 1 the pll operates normally. 0 1 r/w pwrdn2 13 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 12 pll bypass 2 description value the system clock is derived from the osc source and divided by the divisor specified by sysdiv2. 1 the system clock is the pll output clock divided by the divisor specified by sysdiv2. 0 see table 5-6 on page 200 for programming guidelines. note: the adc must be clocked from the pll or directly from a 16-mhz clock source to operate properly. 1 r/w bypass2 11 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 10:7 july 03, 2014 228 texas instruments-production data system control description reset type name bit/field oscillator source 2 selects the input source for the osc. the values are: description value mosc main oscillator 0x0 piosc precision internal oscillator 0x1 piosc/4 precision internal oscillator / 4 0x2 30 khz 30-khz internal oscillator 0x3 reserved 0x4-0x7 0x1 r/w oscsrc2 6:4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 3:0 229 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 11: main oscillator control (moscctl), offset 0x07c this register provides the ability to enable the mosc clock verification circuit. when enabled, this circuit monitors the frequency of the mosc to verify that the oscillator is operating within specified limits. if the clock goes invalid after being enabled, the microcontroller issues a power-on reset and reboots to the nmi handler. main oscillator control (moscctl) base 0x400f.e000 offset 0x07c type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cval reserved r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:1 clock validation for mosc description value the mosc monitor circuit is enabled. 1 the mosc monitor circuit is disabled. 0 0 r/w cval 0 july 03, 2014 230 texas instruments-production data system control register 12: deep sleep clock configuration (dslpclkcfg), offset 0x144 this register provides configuration information for the hardware control of deep sleep mode. deep sleep clock configuration (dslpclkcfg) base 0x400f.e000 offset 0x144 type r/w, reset 0x0780.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved dsdivoride reserved ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w ro ro ro type 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved dsoscsrc reserved ro ro ro ro r/w r/w r/w ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 31:29 divider field override if deep-sleep mode is enabled when the pll is running, the pll is disabled. this 6-bit field contains a system divider field that overrides the sysdiv field in the rcc register or the sysdiv2 field in the rcc2 register during deep sleep. this divider is applied to the source selected by the dsoscsrc field. description value /10x0 /20x1 /30x2 /40x3 ...... /640x3f 0x0f r/w dsdivoride 28:23 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 22:7 231 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field clock source specifies the clock source during deep-sleep mode. description value mosc use the main oscillator as the source. 0x0 note: if the piosc is being used as the clock reference for the pll, the piosc is the clock source instead of mosc in deep-sleep mode. piosc use the precision internal 16-mhz oscillator as the source. 0x1 reserved 0x2 30 khz use the 30-khz internal oscillator as the source. 0x3 reserved 0x4-0x7 0x0 r/w dsoscsrc 6:4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 3:0 july 03, 2014 232 texas instruments-production data system control register 13: precision internal oscillator calibration (piosccal), offset 0x150 this register provides the ability to update or recalibrate the precision internal oscillator. precision internal oscillator calibration (piosccal) base 0x400f.e000 offset 0x150 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved uten ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ut reserved update reserved r/w r/w r/w r/w r/w r/w r/w ro r/w ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field use user trim value description value the trim value in bits[6:0] of this register are used for any update trim operation. 1 the factory calibration value is used for an update trim operation. 0 0 r/w uten 31 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 30:9 update trim description value updates the piosc trim value with the ut bit. used with uten. 1 no action. 0 this bit is auto-cleared after the update. 0 r/w update 8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7 user trim value user trim value that can be loaded into the piosc. refer to main pll frequency configuration on page 202 for more information on calibrating the piosc. 0x0 r/w ut 6:0 233 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 14: i 2 s mclk configuration (i2smclkcfg), offset 0x170 this register configures the receive and transmit fractional clock dividers for the for the i 2 s master transmit and receive clocks (i2s0txmclk and i2s0rxmclk). varying the integer and fractional inputs for the clocks allows greater accuracy in hitting the target i 2 s clock frequencies. refer to clock control on page 838 for combinations of the txi and txf bits and the rxi and rxf bits that provide mclk frequencies within acceptable error limits. i2s mclk configuration (i2smclkcfg) base 0x400f.e000 offset 0x170 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rxf rxi reserved rxen r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 txf txi reserved txen r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field rx clock enable description value the i 2 s receive clock generator is enabled. 1 the i 2 s receive clock generator is disabled. if the rxslv bit in the i 2 s module configuration (i2scfg) register is set, then the i2s0rxmclk must be externally generated. 0 0 r/w rxen 31 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 30 rx clock integer input this field contains the integer input for the receive clock generator. 0x0 r/w rxi 29:20 rx clock fractional input this field contains the fractional input for the receive clock generator. 0x0 r/w rxf 19:16 tx clock enable description value the i 2 s transmit clock generator is enabled. 1 the i 2 s transmit clock generator is disabled. if the txslv bit in the i 2 s module configuration (i2scfg) register is set, then the i2s0txmclk must be externally generated. 0 0 r/w txen 15 july 03, 2014 234 texas instruments-production data system control description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 14 tx clock integer input this field contains the integer input for the transmit clock generator. 0x00 r/w txi 13:4 tx clock fractional input this field contains the fractional input for the transmit clock generator. 0x0 r/w txf 3:0 235 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 15: device identification 1 (did1), offset 0x004 this register identifies the device family, part number, temperature range, pin count, and package type. each microcontroller is uniquely identified by the combined values of the class field in the did0 register and the partno field in the did1 register. device identification 1 (did1) base 0x400f.e000 offset 0x004 type ro, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 partno fam ver ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 0 0 1 1 1 1 0 0 0 0 0 1 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 qual rohs pkg temp reserved pincount ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type - - 1 - - - - - 0 0 0 0 0 0 1 0 reset description reset type name bit/field did1 version this field defines the did1 register format version. the version number is numeric. the value of the ver field is encoded as follows (all other encodings are reserved): description value second version of the did1 register format. 0x1 0x1 ro ver 31:28 family this field provides the family identification of the device within the luminary micro product portfolio. the value is encoded as follows (all other encodings are reserved): description value stellaris family of microcontollers, that is, all devices with external part numbers starting with lm3s. 0x0 0x0 ro fam 27:24 part number this field provides the part number of the device within the family. the value is encoded as follows (all other encodings are reserved): description value lm3s9gn5 0x79 0x79 ro partno 23:16 package pin count this field specifies the number of pins on the device package. the value is encoded as follows (all other encodings are reserved): description value 100-pin package 0x2 0x2 ro pincount 15:13 july 03, 2014 236 texas instruments-production data system control description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 12:8 temperature range this field specifies the temperature rating of the device. the value is encoded as follows (all other encodings are reserved): description value commercial temperature range (0c to 70c) 0x0 industrial temperature range (-40c to 85c) 0x1 extended temperature range (-40c to 105c) 0x2 - ro temp 7:5 package type this field specifies the package type. the value is encoded as follows (all other encodings are reserved): description value soic package 0x0 lqfp package 0x1 bga package 0x2 - ro pkg 4:3 rohs-compliance this bit specifies whether the device is rohs-compliant. a 1 indicates the part is rohs-compliant. 1 ro rohs 2 qualification status this field specifies the qualification status of the device. the value is encoded as follows (all other encodings are reserved): description value engineering sample (unqualified) 0x0 pilot production (unqualified) 0x1 fully qualified 0x2 - ro qual 1:0 237 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 16: device capabilities 0 (dc0), offset 0x008 this register is predefined by the part and can be used to verify features. device capabilities 0 (dc0) base 0x400f.e000 offset 0x008 type ro, reset 0x00ff.00bf 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 sramsz ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 flashsz ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 reset description reset type name bit/field sram size indicates the size of the on-chip sram memory. description value 64 kb of sram 0x00ff 0x00ff ro sramsz 31:16 flash size indicates the size of the on-chip flash memory. description value 384 kb of flash 0x00bf 0x00bf ro flashsz 15:0 july 03, 2014 238 texas instruments-production data system control register 17: device capabilities 1 (dc1), offset 0x010 this register is predefined by the part and can be used to verify features. if any bit is clear in this register, the module is not present. the corresponding bit in the rcgc0, scgc0, and dcgc0 registers cannot be set. device capabilities 1 (dc1) base 0x400f.e000 offset 0x010 type ro, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 adc0 adc1 reserved pwm reserved can0 can1 reserved wdt1 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 0 0 1 0 0 0 1 1 0 0 1 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 jtag swd swo wdt0 pll tempsns reserved mpu maxadc0spd maxadc1spd minsysdiv ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 1 1 1 1 0 1 1 1 1 1 - - - - reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:29 watchdog timer 1 present when set, indicates that watchdog timer 1 is present. 1 ro wdt1 28 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 27:26 can module 1 present when set, indicates that can unit 1 is present. 1 ro can1 25 can module 0 present when set, indicates that can unit 0 is present. 1 ro can0 24 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 23:21 pwm module present when set, indicates that the pwm module is present. 1 ro pwm 20 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 19:18 adc module 1 present when set, indicates that adc module 1 is present. 1 ro adc1 17 adc module 0 present when set, indicates that adc module 0 is present 1 ro adc0 16 239 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field system clock divider minimum 4-bit divider value for system clock. the reset value is hardware-dependent. see the rcc register for how to change the system clock divisor using the sysdiv bit. description value specifies an 80-mhz cpu clock with a pll divider of 2.5. 0x1 specifies a 66.67-mhz cpu clock with a pll divider of 3. 0x2 specifies a 50-mhz cpu clock with a pll divider of 4. 0x3 specifies a 25-mhz clock with a pll divider of 8. 0x7 specifies a 20-mhz clock with a pll divider of 10. 0x9 - ro minsysdiv 15:12 max adc1 speed this field indicates the maximum rate at which the adc samples data. description value 1m samples/second 0x3 0x3 ro maxadc1spd 11:10 max adc0 speed this field indicates the maximum rate at which the adc samples data. description value 1m samples/second 0x3 0x3 ro maxadc0spd 9:8 mpu present when set, indicates that the cortex-m3 memory protection unit (mpu) module is present. see the "cortex-m3 peripherals" chapter for details on the mpu. 1 ro mpu 7 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 6 temp sensor present when set, indicates that the on-chip temperature sensor is present. 1 ro tempsns 5 pll present when set, indicates that the on-chip phase locked loop (pll) is present. 1 ro pll 4 watchdog timer 0 present when set, indicates that watchdog timer 0 is present. 1 ro wdt0 3 swo trace port present when set, indicates that the serial wire output (swo) trace port is present. 1 ro swo 2 swd present when set, indicates that the serial wire debugger (swd) is present. 1 ro swd 1 july 03, 2014 240 texas instruments-production data system control description reset type name bit/field jtag present when set, indicates that the jtag debugger interface is present. 1 ro jtag 0 241 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 18: device capabilities 2 (dc2), offset 0x014 this register is predefined by the part and can be used to verify features. if any bit is clear in this register, the module is not present. the corresponding bit in the rcgc0, scgc0, and dcgc0 registers cannot be set. device capabilities 2 (dc2) base 0x400f.e000 offset 0x014 type ro, reset 0x570f.5337 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 timer0 timer1 timer2 timer3 reserved comp0 comp1 comp2 reserved i2s0 reserved epi0 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 1 1 0 0 0 0 1 1 1 0 1 0 1 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 uart0 uart1 uart2 reserved ssi0 ssi1 reserved qei0 qei1 reserved i2c0 reserved i2c1 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 1 0 1 1 0 0 1 1 0 0 1 0 1 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31 epi module 0 present when set, indicates that epi module 0 is present. 1 ro epi0 30 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 29 i2s module 0 present when set, indicates that i2s module 0 is present. 1 ro i2s0 28 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 27 analog comparator 2 present when set, indicates that analog comparator 2 is present. 1 ro comp2 26 analog comparator 1 present when set, indicates that analog comparator 1 is present. 1 ro comp1 25 analog comparator 0 present when set, indicates that analog comparator 0 is present. 1 ro comp0 24 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 23:20 timer module 3 present when set, indicates that general-purpose timer module 3 is present. 1 ro timer3 19 timer module 2 present when set, indicates that general-purpose timer module 2 is present. 1 ro timer2 18 july 03, 2014 242 texas instruments-production data system control description reset type name bit/field timer module 1 present when set, indicates that general-purpose timer module 1 is present. 1 ro timer1 17 timer module 0 present when set, indicates that general-purpose timer module 0 is present. 1 ro timer0 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 15 i2c module 1 present when set, indicates that i2c module 1 is present. 1 ro i2c1 14 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 13 i2c module 0 present when set, indicates that i2c module 0 is present. 1 ro i2c0 12 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 11:10 qei module 1 present when set, indicates that qei module 1 is present. 1 ro qei1 9 qei module 0 present when set, indicates that qei module 0 is present. 1 ro qei0 8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7:6 ssi module 1 present when set, indicates that ssi module 1 is present. 1 ro ssi1 5 ssi module 0 present when set, indicates that ssi module 0 is present. 1 ro ssi0 4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 3 uart module 2 present when set, indicates that uart module 2 is present. 1 ro uart2 2 uart module 1 present when set, indicates that uart module 1 is present. 1 ro uart1 1 uart module 0 present when set, indicates that uart module 0 is present. 1 ro uart0 0 243 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 19: device capabilities 3 (dc3), offset 0x018 this register is predefined by the part and can be used to verify features. if any bit is clear in this register, the module is not present. the corresponding bit in the rcgc0, scgc0, and dcgc0 registers cannot be set. device capabilities 3 (dc3) base 0x400f.e000 offset 0x018 type ro, reset 0xbfff.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 adc0ain0 adc0ain1 adc0ain2 adc0ain3 adc0ain4 adc0ain5 adc0ain6 adc0ain7 ccp0 ccp1 ccp2 ccp3 ccp4 ccp5 reserved 32khz ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pwm0 pwm1 pwm2 pwm3 pwm4 pwm5 c0minus c0plus c0o c1minus c1plus c1o c2minus c2plus c2o pwmfault ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field 32khz input clock available when set, indicates an even ccp pin is present and can be used as a 32-khz input clock. 1 ro 32khz 31 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 30 ccp5 pin present when set, indicates that capture/compare/pwm pin 5 is present. 1 ro ccp5 29 ccp4 pin present when set, indicates that capture/compare/pwm pin 4 is present. 1 ro ccp4 28 ccp3 pin present when set, indicates that capture/compare/pwm pin 3 is present. 1 ro ccp3 27 ccp2 pin present when set, indicates that capture/compare/pwm pin 2 is present. 1 ro ccp2 26 ccp1 pin present when set, indicates that capture/compare/pwm pin 1 is present. 1 ro ccp1 25 ccp0 pin present when set, indicates that capture/compare/pwm pin 0 is present. 1 ro ccp0 24 adc module 0 ain7 pin present when set, indicates that adc module 0 input pin 7 is present. 1 ro adc0ain7 23 adc module 0 ain6 pin present when set, indicates that adc module 0 input pin 6 is present. 1 ro adc0ain6 22 adc module 0 ain5 pin present when set, indicates that adc module 0 input pin 5 is present. 1 ro adc0ain5 21 july 03, 2014 244 texas instruments-production data system control description reset type name bit/field adc module 0 ain4 pin present when set, indicates that adc module 0 input pin 4 is present. 1 ro adc0ain4 20 adc module 0 ain3 pin present when set, indicates that adc module 0 input pin 3 is present. 1 ro adc0ain3 19 adc module 0 ain2 pin present when set, indicates that adc module 0 input pin 2 is present. 1 ro adc0ain2 18 adc module 0 ain1 pin present when set, indicates that adc module 0 input pin 1 is present. 1 ro adc0ain1 17 adc module 0 ain0 pin present when set, indicates that adc module 0 input pin 0 is present. 1 ro adc0ain0 16 pwm fault pin present when set, indicates that a pwm fault pin is present. see dc5 for specific fault pins on this device. 1 ro pwmfault 15 c2o pin present when set, indicates that the analog comparator 2 output pin is present. 1 ro c2o 14 c2+ pin present when set, indicates that the analog comparator 2 (+) input pin is present. 1 ro c2plus 13 c2- pin present when set, indicates that the analog comparator 2 (-) input pin is present. 1 ro c2minus 12 c1o pin present when set, indicates that the analog comparator 1 output pin is present. 1 ro c1o 11 c1+ pin present when set, indicates that the analog comparator 1 (+) input pin is present. 1 ro c1plus 10 c1- pin present when set, indicates that the analog comparator 1 (-) input pin is present. 1 ro c1minus 9 c0o pin present when set, indicates that the analog comparator 0 output pin is present. 1 ro c0o 8 c0+ pin present when set, indicates that the analog comparator 0 (+) input pin is present. 1 ro c0plus 7 c0- pin present when set, indicates that the analog comparator 0 (-) input pin is present. 1 ro c0minus 6 pwm5 pin present when set, indicates that the pwm pin 5 is present. 1 ro pwm5 5 pwm4 pin present when set, indicates that the pwm pin 4 is present. 1 ro pwm4 4 pwm3 pin present when set, indicates that the pwm pin 3 is present. 1 ro pwm3 3 245 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field pwm2 pin present when set, indicates that the pwm pin 2 is present. 1 ro pwm2 2 pwm1 pin present when set, indicates that the pwm pin 1 is present. 1 ro pwm1 1 pwm0 pin present when set, indicates that the pwm pin 0 is present. 1 ro pwm0 0 july 03, 2014 246 texas instruments-production data system control register 20: device capabilities 4 (dc4), offset 0x01c this register is predefined by the part and can be used to verify features. if any bit is clear in this register, the module is not present. the corresponding bit in the rcgc0, scgc0, and dcgc0 registers cannot be set. device capabilities 4 (dc4) base 0x400f.e000 offset 0x01c type ro, reset 0x1104.f1ff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved pical reserved e1588 reserved emac0 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 gpioa gpiob gpioc gpiod gpioe gpiof gpiog gpioh gpioj reserved rom udma ccp6 ccp7 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:29 ethernet mac layer 0 present when set, indicates that ethernet mac layer 0 is present. 1 ro emac0 28 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 27:25 1588 capable when set, indicates that that ethernet mac layer 0 is 1588 capable. 1 ro e1588 24 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 23:19 piosc calibrate when set, indicates that the piosc can be calibrated. 1 ro pical 18 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 17:16 ccp7 pin present when set, indicates that capture/compare/pwm pin 7 is present. 1 ro ccp7 15 ccp6 pin present when set, indicates that capture/compare/pwm pin 6 is present. 1 ro ccp6 14 micro-dma module present when set, indicates that the micro-dma module present. 1 ro udma 13 internal code rom present when set, indicates that internal code rom is present. 1 ro rom 12 247 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 11:9 gpio port j present when set, indicates that gpio port j is present. 1 ro gpioj 8 gpio port h present when set, indicates that gpio port h is present. 1 ro gpioh 7 gpio port g present when set, indicates that gpio port g is present. 1 ro gpiog 6 gpio port f present when set, indicates that gpio port f is present. 1 ro gpiof 5 gpio port e present when set, indicates that gpio port e is present. 1 ro gpioe 4 gpio port d present when set, indicates that gpio port d is present. 1 ro gpiod 3 gpio port c present when set, indicates that gpio port c is present. 1 ro gpioc 2 gpio port b present when set, indicates that gpio port b is present. 1 ro gpiob 1 gpio port a present when set, indicates that gpio port a is present. 1 ro gpioa 0 july 03, 2014 248 texas instruments-production data system control register 21: device capabilities 5 (dc5), offset 0x020 this register is predefined by the part and can be used to verify features. if any bit is clear in this register, the module is not present. the corresponding bit in the rcgc0, scgc0, and dcgc0 registers cannot be set. device capabilities 5 (dc5) base 0x400f.e000 offset 0x020 type ro, reset 0x0f30.00ff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved pwmesync pwmeflt reserved pwmfault0 pwmfault1 pwmfault2 pwmfault3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 1 1 0 0 1 1 1 1 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pwm0 pwm1 pwm2 pwm3 pwm4 pwm5 pwm6 pwm7 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:28 pwm fault 3 pin present when set, indicates that the pwm fault 3 pin is present. 1 ro pwmfault3 27 pwm fault 2 pin present when set, indicates that the pwm fault 2 pin is present. 1 ro pwmfault2 26 pwm fault 1 pin present when set, indicates that the pwm fault 1 pin is present. 1 ro pwmfault1 25 pwm fault 0 pin present when set, indicates that the pwm fault 0 pin is present. 1 ro pwmfault0 24 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 23:22 pwm extended fault active when set, indicates that the pwm extended fault feature is active. 1 ro pwmeflt 21 pwm extended sync active when set, indicates that the pwm extended sync feature is active. 1 ro pwmesync 20 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 19:8 pwm7 pin present when set, indicates that the pwm pin 7 is present. 1 ro pwm7 7 pwm6 pin present when set, indicates that the pwm pin 6 is present. 1 ro pwm6 6 249 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field pwm5 pin present when set, indicates that the pwm pin 5 is present. 1 ro pwm5 5 pwm4 pin present when set, indicates that the pwm pin 4 is present. 1 ro pwm4 4 pwm3 pin present when set, indicates that the pwm pin 3 is present. 1 ro pwm3 3 pwm2 pin present when set, indicates that the pwm pin 2 is present. 1 ro pwm2 2 pwm1 pin present when set, indicates that the pwm pin 1 is present. 1 ro pwm1 1 pwm0 pin present when set, indicates that the pwm pin 0 is present. 1 ro pwm0 0 july 03, 2014 250 texas instruments-production data system control register 22: device capabilities 6 (dc6), offset 0x024 this register is predefined by the part and can be used to verify features. if any bit is clear in this register, the module is not present. the corresponding bit in the rcgc0, scgc0, and dcgc0 registers cannot be set. device capabilities 6 (dc6) base 0x400f.e000 offset 0x024 type ro, reset 0x0000.0013 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 usb0 reserved usb0phy reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:5 usb module 0 phy present when set, indicates that the usb module 0 phy is present. 1 ro usb0phy 4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 3:2 usb module 0 present thie field indicates that usb module 0 is present and specifies its capability. description value usb0 is otg. 0x3 0x3 ro usb0 1:0 251 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 23: device capabilities 7 (dc7), offset 0x028 this register is predefined by the part and can be used to verify udma channel features. a 1 indicates the channel is available on this device; a 0 that the channel is only available on other devices in the family. most channels have primary and secondary assignments. if the primary function is not available on this microcontroller, the secondary function becomes the primary function. if the secondary function is not available, the primary function is the only option. device capabilities 7 (dc7) base 0x400f.e000 offset 0x028 type ro, reset 0xffff.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 dmach16 dmach17 dmach18 dmach19 dmach20 dmach21 dmach22 dmach23 dmach24 dmach25 dmach26 dmach27 dmach28 dmach29 dmach30 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dmach0 dmach1 dmach2 dmach3 dmach4 dmach5 dmach6 dmach7 dmach8 dmach9 dmach10 dmach11 dmach12 dmach13 dmach14 dmach15 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field reserved reserved for udma channel 31. 1 ro reserved 31 sw when set, indicates udma channel 30 is available for software transfers. 1 ro dmach30 30 i2s0_tx / can1_tx when set, indicates udma channel 29 is available and connected to the transmit path of i2s module 0. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of can module 1 transmit. 1 ro dmach29 29 i2s0_rx / can1_rx when set, indicates udma channel 28 is available and connected to the receive path of i2s module 0. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of can module 1 receive. 1 ro dmach28 28 can1_tx / adc1_ss3 when set, indicates udma channel 27 is available and connected to the transmit path of can module 1. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of adc module 1 sample sequencer 3. 1 ro dmach27 27 can1_rx / adc1_ss2 when set, indicates udma channel 26 is available and connected to the receive path of can module 1. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of adc module 1 sample sequencer 2. 1 ro dmach26 26 july 03, 2014 252 texas instruments-production data system control description reset type name bit/field ssi1_tx / adc1_ss1 when set, indicates udma channel 25 is available and connected to the transmit path of ssi module 1. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of adc module 1 sample sequencer 1. 1 ro dmach25 25 ssi1_rx / adc1_ss0 when set, indicates udma channel 24 is available and connected to the receive path of ssi module 1. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of adc module 1 sample sequencer 0. 1 ro dmach24 24 uart1_tx / can2_tx when set, indicates udma channel 23 is available and connected to the transmit path of uart module 1. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of can module 2 transmit. 1 ro dmach23 23 uart1_rx / can2_rx when set, indicates udma channel 22 is available and connected to the receive path of uart module 1. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of can module 2 receive. 1 ro dmach22 22 timer1b / epi0_wfifo when set, indicates udma channel 21 is available and connected to timer 1b. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of epi module 0 write fifo (wrifo). 1 ro dmach21 21 timer1a / epi0_nbrfifo when set, indicates udma channel 20 is available and connected to timer 1a. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of epi module 0 non-blocking read fifo (nbrfifo). 1 ro dmach20 20 timer0b / timer1b when set, indicates udma channel 19 is available and connected to timer 0b. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of timer 1b. 1 ro dmach19 19 timer0a / timer1a when set, indicates udma channel 18 is available and connected to timer 0a. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of timer 1a. 1 ro dmach18 18 adc0_ss3 when set, indicates udma channel 17 is available and connected to adc module 0 sample sequencer 3. 1 ro dmach17 17 adc0_ss2 when set, indicates udma channel 16 is available and connected to adc module 0 sample sequencer 2. 1 ro dmach16 16 253 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field adc0_ss1 / timer2b when set, indicates udma channel 15 is available and connected to adc module 0 sample sequencer 1. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of timer 2b. 1 ro dmach15 15 adc0_ss0 / timer2a when set, indicates udma channel 14 is available and connected to adc module 0 sample sequencer 0. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of timer 2a. 1 ro dmach14 14 can0_tx / uart2_tx when set, indicates udma channel 13 is available and connected to the transmit path of can module 0. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of uart module 2 transmit. 1 ro dmach13 13 can0_rx / uart2_rx when set, indicates udma channel 12 is available and connected to the receive path of can module 0. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of uart module 2 receive. 1 ro dmach12 12 ssi0_tx / ssi1_tx when set, indicates udma channel 11 is available and connected to the transmit path of ssi module 0. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of ssi module 1 transmit. 1 ro dmach11 11 ssi0_rx / ssi1_rx when set, indicates udma channel 10 is available and connected to the receive path of ssi module 0. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of ssi module 1 receive. 1 ro dmach10 10 uart0_tx / uart1_tx when set, indicates udma channel 9 is available and connected to the transmit path of uart module 0. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of uart module 1 transmit. 1 ro dmach9 9 uart0_rx / uart1_rx when set, indicates udma channel 8 is available and connected to the receive path of uart module 0. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of uart module 1 receive. 1 ro dmach8 8 eth_tx / timer2b when set, indicates udma channel 7 is available and connected to the transmit path of the ethernet module. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of timer 2b. 1 ro dmach7 7 july 03, 2014 254 texas instruments-production data system control description reset type name bit/field eth_rx / timer2a when set, indicates udma channel 6 is available and connected to the receive path of the ethernet module. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of timer 2a. 1 ro dmach6 6 usb_ep3_tx / timer2b when set, indicates udma channel 5 is available and connected to the transmit path of usb endpoint 3. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of timer 2b. 1 ro dmach5 5 usb_ep3_rx / timer2a when set, indicates udma channel 4 is available and connected to the receive path of usb endpoint 3. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of timer 2a. 1 ro dmach4 4 usb_ep2_tx / timer3b when set, indicates udma channel 3 is available and connected to the transmit path of usb endpoint 2. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of timer 3b. 1 ro dmach3 3 usb_ep2_rx / timer3a when set, indicates udma channel 2 is available and connected to the receive path of usb endpoint 2. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of timer 3a. 1 ro dmach2 2 usb_ep1_tx / uart2_tx when set, indicates udma channel 1 is available and connected to the transmit path of usb endpoint 1. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of uart module 2 transmit. 1 ro dmach1 1 usb_ep1_rx / uart2_rx when set, indicates udma channel 0 is available and connected to the receive path of usb endpoint 1. if the corresponding bit in the dmachasgn register is set, the channel is connected instead to the secondary channel assignment of uart module 2 receive. 1 ro dmach0 0 255 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 24: device capabilities 8 adc channels (dc8), offset 0x02c this register is predefined by the part and can be used to verify features. device capabilities 8 adc channels (dc8) base 0x400f.e000 offset 0x02c type ro, reset 0xffff.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 adc1ain0 adc1ain1 adc1ain2 adc1ain3 adc1ain4 adc1ain5 adc1ain6 adc1ain7 adc1ain8 adc1ain9 adc1ain10 adc1ain11 adc1ain12 adc1ain13 adc1ain14 adc1ain15 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 adc0ain0 adc0ain1 adc0ain2 adc0ain3 adc0ain4 adc0ain5 adc0ain6 adc0ain7 adc0ain8 adc0ain9 adc0ain10 adc0ain11 adc0ain12 adc0ain13 adc0ain14 adc0ain15 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field adc module 1 ain15 pin present when set, indicates that adc module 1 input pin 15 is present. 1 ro adc1ain15 31 adc module 1 ain14 pin present when set, indicates that adc module 1 input pin 14 is present. 1 ro adc1ain14 30 adc module 1 ain13 pin present when set, indicates that adc module 1 input pin 13 is present. 1 ro adc1ain13 29 adc module 1 ain12 pin present when set, indicates that adc module 1 input pin 12 is present. 1 ro adc1ain12 28 adc module 1 ain11 pin present when set, indicates that adc module 1 input pin 11 is present. 1 ro adc1ain11 27 adc module 1 ain10 pin present when set, indicates that adc module 1 input pin 10 is present. 1 ro adc1ain10 26 adc module 1 ain9 pin present when set, indicates that adc module 1 input pin 9 is present. 1 ro adc1ain9 25 adc module 1 ain8 pin present when set, indicates that adc module 1 input pin 8 is present. 1 ro adc1ain8 24 adc module 1 ain7 pin present when set, indicates that adc module 1 input pin 7 is present. 1 ro adc1ain7 23 adc module 1 ain6 pin present when set, indicates that adc module 1 input pin 6 is present. 1 ro adc1ain6 22 adc module 1 ain5 pin present when set, indicates that adc module 1 input pin 5 is present. 1 ro adc1ain5 21 adc module 1 ain4 pin present when set, indicates that adc module 1 input pin 4 is present. 1 ro adc1ain4 20 july 03, 2014 256 texas instruments-production data system control description reset type name bit/field adc module 1 ain3 pin present when set, indicates that adc module 1 input pin 3 is present. 1 ro adc1ain3 19 adc module 1 ain2 pin present when set, indicates that adc module 1 input pin 2 is present. 1 ro adc1ain2 18 adc module 1 ain1 pin present when set, indicates that adc module 1 input pin 1 is present. 1 ro adc1ain1 17 adc module 1 ain0 pin present when set, indicates that adc module 1 input pin 0 is present. 1 ro adc1ain0 16 adc module 0 ain15 pin present when set, indicates that adc module 0 input pin 15 is present. 1 ro adc0ain15 15 adc module 0 ain14 pin present when set, indicates that adc module 0 input pin 14 is present. 1 ro adc0ain14 14 adc module 0 ain13 pin present when set, indicates that adc module 0 input pin 13 is present. 1 ro adc0ain13 13 adc module 0 ain12 pin present when set, indicates that adc module 0 input pin 12 is present. 1 ro adc0ain12 12 adc module 0 ain11 pin present when set, indicates that adc module 0 input pin 11 is present. 1 ro adc0ain11 11 adc module 0 ain10 pin present when set, indicates that adc module 0 input pin 10 is present. 1 ro adc0ain10 10 adc module 0 ain9 pin present when set, indicates that adc module 0 input pin 9 is present. 1 ro adc0ain9 9 adc module 0 ain8 pin present when set, indicates that adc module 0 input pin 8 is present. 1 ro adc0ain8 8 adc module 0 ain7 pin present when set, indicates that adc module 0 input pin 7 is present. 1 ro adc0ain7 7 adc module 0 ain6 pin present when set, indicates that adc module 0 input pin 6 is present. 1 ro adc0ain6 6 adc module 0 ain5 pin present when set, indicates that adc module 0 input pin 5 is present. 1 ro adc0ain5 5 adc module 0 ain4 pin present when set, indicates that adc module 0 input pin 4 is present. 1 ro adc0ain4 4 adc module 0 ain3 pin present when set, indicates that adc module 0 input pin 3 is present. 1 ro adc0ain3 3 adc module 0 ain2 pin present when set, indicates that adc module 0 input pin 2 is present. 1 ro adc0ain2 2 257 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field adc module 0 ain1 pin present when set, indicates that adc module 0 input pin 1 is present. 1 ro adc0ain1 1 adc module 0 ain0 pin present when set, indicates that adc module 0 input pin 0 is present. 1 ro adc0ain0 0 july 03, 2014 258 texas instruments-production data system control register 25: device capabilities 9 adc digital comparators (dc9), offset 0x190 this register is predefined by the part and can be used to verify features. device capabilities 9 adc digital comparators (dc9) base 0x400f.e000 offset 0x190 type ro, reset 0x00ff.00ff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 adc1dc0 adc1dc1 adc1dc2 adc1dc3 adc1dc4 adc1dc5 adc1dc6 adc1dc7 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 adc0dc0 adc0dc1 adc0dc2 adc0dc3 adc0dc4 adc0dc5 adc0dc6 adc0dc7 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:24 adc1 dc7 present when set, indicates that adc module 1 digital comparator 7 is present. 1 ro adc1dc7 23 adc1 dc6 present when set, indicates that adc module 1 digital comparator 6 is present. 1 ro adc1dc6 22 adc1 dc5 present when set, indicates that adc module 1 digital comparator 5 is present. 1 ro adc1dc5 21 adc1 dc4 present when set, indicates that adc module 1 digital comparator 4 is present. 1 ro adc1dc4 20 adc1 dc3 present when set, indicates that adc module 1 digital comparator 3 is present. 1 ro adc1dc3 19 adc1 dc2 present when set, indicates that adc module 1 digital comparator 2 is present. 1 ro adc1dc2 18 adc1 dc1 present when set, indicates that adc module 1 digital comparator 1 is present. 1 ro adc1dc1 17 adc1 dc0 present when set, indicates that adc module 1 digital comparator 0 is present. 1 ro adc1dc0 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 15:8 adc0 dc7 present when set, indicates that adc module 0 digital comparator 7 is present. 1 ro adc0dc7 7 259 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field adc0 dc6 present when set, indicates that adc module 0 digital comparator 6 is present. 1 ro adc0dc6 6 adc0 dc5 present when set, indicates that adc module 0 digital comparator 5 is present. 1 ro adc0dc5 5 adc0 dc4 present when set, indicates that adc module 0 digital comparator 4 is present. 1 ro adc0dc4 4 adc0 dc3 present when set, indicates that adc module 0 digital comparator 3 is present. 1 ro adc0dc3 3 adc0 dc2 present when set, indicates that adc module 0 digital comparator 2 is present. 1 ro adc0dc2 2 adc0 dc1 present when set, indicates that adc module 0 digital comparator 1 is present. 1 ro adc0dc1 1 adc0 dc0 present when set, indicates that adc module 0 digital comparator 0 is present. 1 ro adc0dc0 0 july 03, 2014 260 texas instruments-production data system control register 26: non-volatile memory information (nvmstat), offset 0x1a0 this register is predefined by the part and can be used to verify features. non-volatile memory information (nvmstat) base 0x400f.e000 offset 0x1a0 type ro, reset 0x0000.0001 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 fwb reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:1 32 word flash write buffer active when set, indicates that the 32 word flash memory write buffer feature is active. 1 ro fwb 0 261 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 27: run mode clock gating control register 0 (rcgc0), offset 0x100 this register controls the clock gating logic in normal run mode. each bit controls a clock enable for a given interface, function, or module. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled (saving power). if the module is unclocked, reads or writes to the module generate a bus fault. the reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. it is the responsibility of software to enable the ports necessary for the application. note that these registers may contain more bits than there are interfaces, functions, or modules to control. this configuration is implemented to assure reasonable code compatibility with other family and future parts. rcgc0 is the clock configuration register for running operation, scgc0 for sleep operation, and dcgc0 for deep-sleep operation. setting the acg bit in the run-mode clock configuration (rcc) register specifies that the system uses sleep modes. run mode clock gating control register 0 (rcgc0) base 0x400f.e000 offset 0x100 type r/w, reset 0x00000040 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 adc0 adc1 reserved pwm reserved can0 can1 reserved wdt1 reserved r/w r/w ro ro r/w ro ro ro r/w r/w ro ro r/w ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved wdt0 reserved reserved reserved maxadc0spd maxadc1spd reserved ro ro ro r/w ro ro ro ro r/w r/w r/w r/w ro ro ro ro type 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:29 wdt1 clock gating control this bit controls the clock gating for the watchdog timer module 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w wdt1 28 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 27:26 can1 clock gating control this bit controls the clock gating for can module 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w can1 25 can0 clock gating control this bit controls the clock gating for can module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w can0 24 july 03, 2014 262 texas instruments-production data system control description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 23:21 pwm clock gating control this bit controls the clock gating for the pwm module. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w pwm 20 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 19:18 adc1 clock gating control this bit controls the clock gating for sar adc module 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w adc1 17 adc0 clock gating control this bit controls the clock gating for adc module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w adc0 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 15:12 adc1 sample speed this field sets the rate at which adc module 1 samples data. you cannot set the rate higher than the maximum rate. you can set the sample rate by setting the maxadc1spd bit as follows (all other encodings are reserved): description value 1m samples/second 0x3 500k samples/second 0x2 250k samples/second 0x1 125k samples/second 0x0 0 r/w maxadc1spd 11:10 adc0 sample speed this field sets the rate at which adc0 samples data. you cannot set the rate higher than the maximum rate. you can set the sample rate by setting the maxadc0spd bit as follows (all other encodings are reserved): description value 1m samples/second 0x3 500k samples/second 0x2 250k samples/second 0x1 125k samples/second 0x0 0 r/w maxadc0spd 9:8 263 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 ro reserved 6 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 5:4 wdt0 clock gating control this bit controls the clock gating for the watchdog timer module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w wdt0 3 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 2:0 july 03, 2014 264 texas instruments-production data system control register 28: sleep mode clock gating control register 0 (scgc0), offset 0x110 this register controls the clock gating logic in sleep mode. each bit controls a clock enable for a given interface, function, or module. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled (saving power). if the module is unclocked, reads or writes to the module generate a bus fault. the reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. it is the responsibility of software to enable the ports necessary for the application. note that these registers may contain more bits than there are interfaces, functions, or modules to control. this configuration is implemented to assure reasonable code compatibility with other family and future parts. rcgc0 is the clock configuration register for running operation, scgc0 for sleep operation, and dcgc0 for deep-sleep operation. setting the acg bit in the run-mode clock configuration (rcc) register specifies that the system uses sleep modes. sleep mode clock gating control register 0 (scgc0) base 0x400f.e000 offset 0x110 type r/w, reset 0x00000040 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 adc0 adc1 reserved pwm reserved can0 can1 reserved wdt1 reserved r/w r/w ro ro r/w ro ro ro r/w r/w ro ro r/w ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved wdt0 reserved reserved reserved maxadc0spd maxadc1spd reserved ro ro ro r/w ro ro ro ro r/w r/w r/w r/w ro ro ro ro type 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:29 wdt1 clock gating control this bit controls the clock gating for watchdog timer module 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w wdt1 28 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 27:26 can1 clock gating control this bit controls the clock gating for can module 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w can1 25 can0 clock gating control this bit controls the clock gating for can module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w can0 24 265 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 23:21 pwm clock gating control this bit controls the clock gating for the pwm module. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w pwm 20 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 19:18 adc1 clock gating control this bit controls the clock gating for adc module 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w adc1 17 adc0 clock gating control this bit controls the clock gating for adc module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w adc0 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 15:12 adc1 sample speed this field sets the rate at which adc module 1 samples data. you cannot set the rate higher than the maximum rate. you can set the sample rate by setting the maxadc1spd bit as follows (all other encodings are reserved): description value 1m samples/second 0x3 500k samples/second 0x2 250k samples/second 0x1 125k samples/second 0x0 0 r/w maxadc1spd 11:10 adc0 sample speed this field sets the rate at which adc module 0 samples data. you cannot set the rate higher than the maximum rate. you can set the sample rate by setting the maxadc0spd bit as follows (all other encodings are reserved): description value 1m samples/second 0x3 500k samples/second 0x2 250k samples/second 0x1 125k samples/second 0x0 0 r/w maxadc0spd 9:8 july 03, 2014 266 texas instruments-production data system control description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 ro reserved 6 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 5:4 wdt0 clock gating control this bit controls the clock gating for the watchdog timer module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w wdt0 3 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 2:0 267 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 29: deep sleep mode clock gating control register 0 (dcgc0), offset 0x120 this register controls the clock gating logic in deep-sleep mode. each bit controls a clock enable for a given interface, function, or module. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled (saving power). if the module is unclocked, reads or writes to the module generate a bus fault. the reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. it is the responsibility of software to enable the ports necessary for the application. note that these registers may contain more bits than there are interfaces, functions, or modules to control. this configuration is implemented to assure reasonable code compatibility with other family and future parts. rcgc0 is the clock configuration register for running operation, scgc0 for sleep operation, and dcgc0 for deep-sleep operation. setting the acg bit in the run-mode clock configuration (rcc) register specifies that the system uses sleep modes. deep sleep mode clock gating control register 0 (dcgc0) base 0x400f.e000 offset 0x120 type r/w, reset 0x00000040 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 adc0 adc1 reserved pwm reserved can0 can1 reserved wdt1 reserved r/w r/w ro ro r/w ro ro ro r/w r/w ro ro r/w ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved wdt0 reserved reserved reserved ro ro ro r/w ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:29 wdt1 clock gating control this bit controls the clock gating for the watchdog timer module 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w wdt1 28 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 27:26 can1 clock gating control this bit controls the clock gating for can module 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w can1 25 can0 clock gating control this bit controls the clock gating for can module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w can0 24 july 03, 2014 268 texas instruments-production data system control description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 23:21 pwm clock gating control this bit controls the clock gating for the pwm module. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w pwm 20 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 19:18 adc1 clock gating control this bit controls the clock gating for adc module 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w adc1 17 adc0 clock gating control this bit controls the clock gating for adc module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w adc0 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 15:7 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 ro reserved 6 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 5:4 wdt0 clock gating control this bit controls the clock gating for the watchdog timer module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w wdt0 3 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 2:0 269 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 30: run mode clock gating control register 1 (rcgc1), offset 0x104 this register controls the clock gating logic in normal run mode. each bit controls a clock enable for a given interface, function, or module. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled (saving power). if the module is unclocked, reads or writes to the module generate a bus fault. the reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. it is the responsibility of software to enable the ports necessary for the application. note that these registers may contain more bits than there are interfaces, functions, or modules to control. this configuration is implemented to assure reasonable code compatibility with other family and future parts. rcgc1 is the clock configuration register for running operation, scgc1 for sleep operation, and dcgc1 for deep-sleep operation. setting the acg bit in the run-mode clock configuration (rcc) register specifies that the system uses sleep modes. run mode clock gating control register 1 (rcgc1) base 0x400f.e000 offset 0x104 type r/w, reset 0x00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 timer0 timer1 timer2 timer3 reserved comp0 comp1 comp2 reserved i2s0 reserved epi0 reserved r/w r/w r/w r/w ro ro ro ro r/w r/w r/w ro r/w ro r/w ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 uart0 uart1 uart2 reserved ssi0 ssi1 reserved qei0 qei1 reserved i2c0 reserved i2c1 reserved r/w r/w r/w ro r/w r/w ro ro r/w r/w ro ro r/w ro r/w ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31 epi0 clock gating this bit controls the clock gating for epi module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w epi0 30 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 29 i2s0 clock gating this bit controls the clock gating for i2s module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w i2s0 28 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 27 july 03, 2014 270 texas instruments-production data system control description reset type name bit/field analog comparator 2 clock gating this bit controls the clock gating for analog comparator 2. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w comp2 26 analog comparator 1 clock gating this bit controls the clock gating for analog comparator 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w comp1 25 analog comparator 0 clock gating this bit controls the clock gating for analog comparator 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w comp0 24 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 23:20 timer 3 clock gating control this bit controls the clock gating for general-purpose timer module 3. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w timer3 19 timer 2 clock gating control this bit controls the clock gating for general-purpose timer module 2. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w timer2 18 timer 1 clock gating control this bit controls the clock gating for general-purpose timer module 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w timer1 17 timer 0 clock gating control this bit controls the clock gating for general-purpose timer module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w timer0 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 15 i2c1 clock gating control this bit controls the clock gating for i2c module 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w i2c1 14 271 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 13 i2c0 clock gating control this bit controls the clock gating for i2c module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w i2c0 12 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 11:10 qei1 clock gating control this bit controls the clock gating for qei module 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w qei1 9 qei0 clock gating control this bit controls the clock gating for qei module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w qei0 8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7:6 ssi1 clock gating control this bit controls the clock gating for ssi module 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w ssi1 5 ssi0 clock gating control this bit controls the clock gating for ssi module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w ssi0 4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 3 uart2 clock gating control this bit controls the clock gating for uart module 2. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w uart2 2 uart1 clock gating control this bit controls the clock gating for uart module 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w uart1 1 july 03, 2014 272 texas instruments-production data system control description reset type name bit/field uart0 clock gating control this bit controls the clock gating for uart module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w uart0 0 273 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 31: sleep mode clock gating control register 1 (scgc1), offset 0x114 this register controls the clock gating logic in sleep mode. each bit controls a clock enable for a given interface, function, or module. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled (saving power). if the module is unclocked, reads or writes to the module generate a bus fault. the reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. it is the responsibility of software to enable the ports necessary for the application. note that these registers may contain more bits than there are interfaces, functions, or modules to control. this configuration is implemented to assure reasonable code compatibility with other family and future parts. rcgc1 is the clock configuration register for running operation, scgc1 for sleep operation, and dcgc1 for deep-sleep operation. setting the acg bit in the run-mode clock configuration (rcc) register specifies that the system uses sleep modes. sleep mode clock gating control register 1 (scgc1) base 0x400f.e000 offset 0x114 type r/w, reset 0x00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 timer0 timer1 timer2 timer3 reserved comp0 comp1 comp2 reserved i2s0 reserved epi0 reserved r/w r/w r/w r/w ro ro ro ro r/w r/w r/w ro r/w ro r/w ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 uart0 uart1 uart2 reserved ssi0 ssi1 reserved qei0 qei1 reserved i2c0 reserved i2c1 reserved r/w r/w r/w ro r/w r/w ro ro r/w r/w ro ro r/w ro r/w ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31 epi0 clock gating this bit controls the clock gating for epi module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w epi0 30 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 29 i2s0 clock gating this bit controls the clock gating for i2s module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w i2s0 28 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 27 july 03, 2014 274 texas instruments-production data system control description reset type name bit/field analog comparator 2 clock gating this bit controls the clock gating for analog comparator 2. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w comp2 26 analog comparator 1 clock gating this bit controls the clock gating for analog comparator 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w comp1 25 analog comparator 0 clock gating this bit controls the clock gating for analog comparator 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w comp0 24 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 23:20 timer 3 clock gating control this bit controls the clock gating for general-purpose timer module 3. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w timer3 19 timer 2 clock gating control this bit controls the clock gating for general-purpose timer module 2. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w timer2 18 timer 1 clock gating control this bit controls the clock gating for general-purpose timer module 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w timer1 17 timer 0 clock gating control this bit controls the clock gating for general-purpose timer module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w timer0 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 15 i2c1 clock gating control this bit controls the clock gating for i2c module 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w i2c1 14 275 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 13 i2c0 clock gating control this bit controls the clock gating for i2c module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w i2c0 12 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 11:10 qei1 clock gating control this bit controls the clock gating for qei module 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w qei1 9 qei0 clock gating control this bit controls the clock gating for qei module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w qei0 8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7:6 ssi1 clock gating control this bit controls the clock gating for ssi module 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w ssi1 5 ssi0 clock gating control this bit controls the clock gating for ssi module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w ssi0 4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 3 uart2 clock gating control this bit controls the clock gating for uart module 2. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w uart2 2 uart1 clock gating control this bit controls the clock gating for uart module 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w uart1 1 july 03, 2014 276 texas instruments-production data system control description reset type name bit/field uart0 clock gating control this bit controls the clock gating for uart module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w uart0 0 277 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 32: deep-sleep mode clock gating control register 1 (dcgc1), offset 0x124 this register controls the clock gating logic in deep-sleep mode. each bit controls a clock enable for a given interface, function, or module. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled (saving power). if the module is unclocked, reads or writes to the module generate a bus fault. the reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. it is the responsibility of software to enable the ports necessary for the application. note that these registers may contain more bits than there are interfaces, functions, or modules to control. this configuration is implemented to assure reasonable code compatibility with other family and future parts. rcgc1 is the clock configuration register for running operation, scgc1 for sleep operation, and dcgc1 for deep-sleep operation. setting the acg bit in the run-mode clock configuration (rcc) register specifies that the system uses sleep modes. deep-sleep mode clock gating control register 1 (dcgc1) base 0x400f.e000 offset 0x124 type r/w, reset 0x00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 timer0 timer1 timer2 timer3 reserved comp0 comp1 comp2 reserved i2s0 reserved epi0 reserved r/w r/w r/w r/w ro ro ro ro r/w r/w r/w ro r/w ro r/w ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 uart0 uart1 uart2 reserved ssi0 ssi1 reserved qei0 qei1 reserved i2c0 reserved i2c1 reserved r/w r/w r/w ro r/w r/w ro ro r/w r/w ro ro r/w ro r/w ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31 epi0 clock gating this bit controls the clock gating for epi module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w epi0 30 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 29 i2s0 clock gating this bit controls the clock gating for i2s module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w i2s0 28 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 27 july 03, 2014 278 texas instruments-production data system control description reset type name bit/field analog comparator 2 clock gating this bit controls the clock gating for analog comparator 2. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w comp2 26 analog comparator 1 clock gating this bit controls the clock gating for analog comparator 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w comp1 25 analog comparator 0 clock gating this bit controls the clock gating for analog comparator 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w comp0 24 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 23:20 timer 3 clock gating control this bit controls the clock gating for general-purpose timer module 3. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w timer3 19 timer 2 clock gating control this bit controls the clock gating for general-purpose timer module 2. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w timer2 18 timer 1 clock gating control this bit controls the clock gating for general-purpose timer module 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w timer1 17 timer 0 clock gating control this bit controls the clock gating for general-purpose timer module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w timer0 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 15 i2c1 clock gating control this bit controls the clock gating for i2c module 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w i2c1 14 279 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 13 i2c0 clock gating control this bit controls the clock gating for i2c module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w i2c0 12 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 11:10 qei1 clock gating control this bit controls the clock gating for qei module 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w qei1 9 qei0 clock gating control this bit controls the clock gating for qei module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w qei0 8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7:6 ssi1 clock gating control this bit controls the clock gating for ssi module 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w ssi1 5 ssi0 clock gating control this bit controls the clock gating for ssi module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w ssi0 4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 3 uart2 clock gating control this bit controls the clock gating for uart module 2. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w uart2 2 uart1 clock gating control this bit controls the clock gating for uart module 1. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w uart1 1 july 03, 2014 280 texas instruments-production data system control description reset type name bit/field uart0 clock gating control this bit controls the clock gating for uart module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w uart0 0 281 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 33: run mode clock gating control register 2 (rcgc2), offset 0x108 this register controls the clock gating logic in normal run mode. each bit controls a clock enable for a given interface, function, or module. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled (saving power). if the module is unclocked, reads or writes to the module generate a bus fault. the reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. it is the responsibility of software to enable the ports necessary for the application. note that these registers may contain more bits than there are interfaces, functions, or modules to control. this configuration is implemented to assure reasonable code compatibility with other family and future parts. rcgc2 is the clock configuration register for running operation, scgc2 for sleep operation, and dcgc2 for deep-sleep operation. setting the acg bit in the run-mode clock configuration (rcc) register specifies that the system uses sleep modes. run mode clock gating control register 2 (rcgc2) base 0x400f.e000 offset 0x108 type r/w, reset 0x00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 usb0 reserved emac0 reserved r/w ro ro ro ro ro ro ro ro ro ro ro r/w ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 gpioa gpiob gpioc gpiod gpioe gpiof gpiog gpioh gpioj reserved udma reserved r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro r/w ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:29 mac0 clock gating control this bit controls the clock gating for ethernet mac layer 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w emac0 28 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 27:17 usb0 clock gating control this bit controls the clock gating for usb module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w usb0 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 15:14 july 03, 2014 282 texas instruments-production data system control description reset type name bit/field micro-dma clock gating control this bit controls the clock gating for micro-dma. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w udma 13 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 12:9 port j clock gating control this bit controls the clock gating for port j. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpioj 8 port h clock gating control this bit controls the clock gating for port h. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpioh 7 port g clock gating control this bit controls the clock gating for port g. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpiog 6 port f clock gating control this bit controls the clock gating for port f. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpiof 5 port e clock gating control port e clock gating control. this bit controls the clock gating for port e. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpioe 4 port d clock gating control port d clock gating control. this bit controls the clock gating for port d. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpiod 3 port c clock gating control this bit controls the clock gating for port c. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpioc 2 port b clock gating control this bit controls the clock gating for port b. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpiob 1 283 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field port a clock gating control this bit controls the clock gating for port a. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpioa 0 july 03, 2014 284 texas instruments-production data system control register 34: sleep mode clock gating control register 2 (scgc2), offset 0x118 this register controls the clock gating logic in sleep mode. each bit controls a clock enable for a given interface, function, or module. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled (saving power). if the module is unclocked, reads or writes to the module generate a bus fault. the reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. it is the responsibility of software to enable the ports necessary for the application. note that these registers may contain more bits than there are interfaces, functions, or modules to control. this configuration is implemented to assure reasonable code compatibility with other family and future parts. rcgc2 is the clock configuration register for running operation, scgc2 for sleep operation, and dcgc2 for deep-sleep operation. setting the acg bit in the run-mode clock configuration (rcc) register specifies that the system uses sleep modes. sleep mode clock gating control register 2 (scgc2) base 0x400f.e000 offset 0x118 type r/w, reset 0x00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 usb0 reserved emac0 reserved r/w ro ro ro ro ro ro ro ro ro ro ro r/w ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 gpioa gpiob gpioc gpiod gpioe gpiof gpiog gpioh gpioj reserved udma reserved r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro r/w ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:29 mac0 clock gating control this bit controls the clock gating for ethernet mac layer 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w emac0 28 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 27:17 usb0 clock gating control this bit controls the clock gating for usb module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w usb0 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 15:14 285 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field micro-dma clock gating control this bit controls the clock gating for micro-dma. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w udma 13 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 12:9 port j clock gating control this bit controls the clock gating for port j. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpioj 8 port h clock gating control this bit controls the clock gating for port h. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpioh 7 port g clock gating control this bit controls the clock gating for port g. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpiog 6 port f clock gating control this bit controls the clock gating for port f. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpiof 5 port e clock gating control port e clock gating control. this bit controls the clock gating for port e. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpioe 4 port d clock gating control port d clock gating control. this bit controls the clock gating for port d. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpiod 3 port c clock gating control this bit controls the clock gating for port c. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpioc 2 port b clock gating control this bit controls the clock gating for port b. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpiob 1 july 03, 2014 286 texas instruments-production data system control description reset type name bit/field port a clock gating control this bit controls the clock gating for port a. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpioa 0 287 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 35: deep sleep mode clock gating control register 2 (dcgc2), offset 0x128 this register controls the clock gating logic in deep-sleep mode. each bit controls a clock enable for a given interface, function, or module. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled (saving power). if the module is unclocked, reads or writes to the module generate a bus fault. the reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. it is the responsibility of software to enable the ports necessary for the application. note that these registers may contain more bits than there are interfaces, functions, or modules to control. this configuration is implemented to assure reasonable code compatibility with other family and future parts. rcgc2 is the clock configuration register for running operation, scgc2 for sleep operation, and dcgc2 for deep-sleep operation. setting the acg bit in the run-mode clock configuration (rcc) register specifies that the system uses sleep modes. deep sleep mode clock gating control register 2 (dcgc2) base 0x400f.e000 offset 0x128 type r/w, reset 0x00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 usb0 reserved emac0 reserved r/w ro ro ro ro ro ro ro ro ro ro ro r/w ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 gpioa gpiob gpioc gpiod gpioe gpiof gpiog gpioh gpioj reserved udma reserved r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro r/w ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:29 mac0 clock gating control this bit controls the clock gating for ethernet mac layer 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w emac0 28 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 27:17 usb0 clock gating control this bit controls the clock gating for usb module 0. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w usb0 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 15:14 july 03, 2014 288 texas instruments-production data system control description reset type name bit/field micro-dma clock gating control this bit controls the clock gating for micro-dma. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w udma 13 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 12:9 port j clock gating control this bit controls the clock gating for port j. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpioj 8 port h clock gating control this bit controls the clock gating for port h. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpioh 7 port g clock gating control this bit controls the clock gating for port g. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpiog 6 port f clock gating control this bit controls the clock gating for port f. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpiof 5 port e clock gating control port e clock gating control. this bit controls the clock gating for port e. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpioe 4 port d clock gating control port d clock gating control. this bit controls the clock gating for port d. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpiod 3 port c clock gating control this bit controls the clock gating for port c. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpioc 2 port b clock gating control this bit controls the clock gating for port b. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpiob 1 289 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field port a clock gating control this bit controls the clock gating for port a. if set, the module receives a clock and functions. otherwise, the module is unclocked and disabled. if the module is unclocked, a read or write to the module generates a bus fault. 0 r/w gpioa 0 july 03, 2014 290 texas instruments-production data system control register 36: software reset control 0 (srcr0), offset 0x040 this register allows individual modules to be reset. writes to this register are masked by the bits in the device capabilities 1 (dc1) register. software reset control 0 (srcr0) base 0x400f.e000 offset 0x040 type r/w, reset 0x00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 adc0 adc1 reserved pwm reserved can0 can1 reserved wdt1 reserved r/w r/w ro ro r/w ro ro ro r/w r/w ro ro r/w ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved wdt0 reserved ro ro ro r/w ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:29 wdt1 reset control when this bit is set, watchdog timer module 1 is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w wdt1 28 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 27:26 can1 reset control when this bit is set, can module 1 is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w can1 25 can0 reset control when this bit is set, can module 0 is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w can0 24 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 23:21 pwm reset control when this bit is set, pwm module 0 is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w pwm 20 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 19:18 291 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field adc1 reset control when this bit is set, adc module 1 is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w adc1 17 adc0 reset control when this bit is set, adc module 0 is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w adc0 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 15:4 wdt0 reset control when this bit is set, watchdog timer module 0 is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w wdt0 3 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 2:0 july 03, 2014 292 texas instruments-production data system control register 37: software reset control 1 (srcr1), offset 0x044 this register allows individual modules to be reset. writes to this register are masked by the bits in the device capabilities 2 (dc2) register. software reset control 1 (srcr1) base 0x400f.e000 offset 0x044 type r/w, reset 0x00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 timer0 timer1 timer2 timer3 reserved comp0 comp1 comp2 reserved i2s0 reserved epi0 reserved r/w r/w r/w r/w ro ro ro ro r/w r/w r/w ro r/w ro r/w ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 uart0 uart1 uart2 reserved ssi0 ssi1 reserved qei0 qei1 reserved i2c0 reserved i2c1 reserved r/w r/w r/w ro r/w r/w ro ro r/w r/w ro ro r/w ro r/w ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31 epi0 reset control when this bit is set, epi module 0 is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w epi0 30 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 29 i2s0 reset control when this bit is set, i2s module 0 is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w i2s0 28 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 27 analog comp 2 reset control when this bit is set, analog comparator module 2 is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w comp2 26 analog comp 1 reset control when this bit is set, analog comparator module 1 is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w comp1 25 analog comp 0 reset control when this bit is set, analog comparator module 0 is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w comp0 24 293 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 23:20 timer 3 reset control timer 3 reset control. when this bit is set, general-purpose timer module 3 is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w timer3 19 timer 2 reset control when this bit is set, general-purpose timer module 2 is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w timer2 18 timer 1 reset control when this bit is set, general-purpose timer module 1 is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w timer1 17 timer 0 reset control when this bit is set, general-purpose timer module 0 is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w timer0 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 15 i2c1 reset control when this bit is set, i2c module 1 is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w i2c1 14 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 13 i2c0 reset control when this bit is set, i2c module 0 is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w i2c0 12 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 11:10 qei1 reset control when this bit is set, qei module 1 is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w qei1 9 qei0 reset control when this bit is set, qei module 0 is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w qei0 8 july 03, 2014 294 texas instruments-production data system control description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7:6 ssi1 reset control when this bit is set, ssi module 1 is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w ssi1 5 ssi0 reset control when this bit is set, ssi module 0 is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w ssi0 4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 3 uart2 reset control when this bit is set, uart module 2 is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w uart2 2 uart1 reset control when this bit is set, uart module 1 is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w uart1 1 uart0 reset control when this bit is set, uart module 0 is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w uart0 0 295 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 38: software reset control 2 (srcr2), offset 0x048 this register allows individual modules to be reset. writes to this register are masked by the bits in the device capabilities 4 (dc4) register. software reset control 2 (srcr2) base 0x400f.e000 offset 0x048 type r/w, reset 0x00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 usb0 reserved emac0 reserved r/w ro ro ro ro ro ro ro ro ro ro ro r/w ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 gpioa gpiob gpioc gpiod gpioe gpiof gpiog gpioh gpioj reserved udma reserved r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro r/w ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:29 mac0 reset control when this bit is set, ethernet mac layer 0 is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w emac0 28 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 27:17 usb0 reset control when this bit is set, usb module 0 is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w usb0 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 15:14 micro-dma reset control when this bit is set, udma module is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w udma 13 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 12:9 port j reset control when this bit is set, port j module is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w gpioj 8 july 03, 2014 296 texas instruments-production data system control description reset type name bit/field port h reset control when this bit is set, port h module is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w gpioh 7 port g reset control when this bit is set, port g module is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w gpiog 6 port f reset control when this bit is set, port f module is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w gpiof 5 port e reset control when this bit is set, port e module is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w gpioe 4 port d reset control when this bit is set, port d module is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w gpiod 3 port c reset control when this bit is set, port c module is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w gpioc 2 port b reset control when this bit is set, port b module is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w gpiob 1 port a reset control when this bit is set, port a module is reset. all internal data is lost and the registers are returned to their reset states. this bit must be manually cleared after being set. 0 r/w gpioa 0 297 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 6 internal memory the lm3s9gn5 microcontroller comes with 64 kb of bit-banded sram, internal rom,and 384 kb of flash memory. the flash memory controller provides a user-friendly interface, making flash memory programming a simple task. flash memory protection can be applied to the flash memory on a 2-kb block basis. 6.1 block diagram figure 6-1 on page 298 illustrates the internal memory blocks and control logic. the dashed boxes in the figure indicate registers residing in the system control module. figure 6-1. internal memory block diagram 6.2 functional description this section describes the functionality of the sram, rom, and flash memories. note: the dma controller can transfer data to and from the on-chip sram. however, because the flash memory and rom are located on a separate internal bus, it is not possible to transfer data from the flash memory or rom with the dma controller. july 03, 2014 298 texas instruments-production data internal memory 5 2 0 & r q w u r o 5 0 & 7 / 5 2 0 $ u u d \ ) o d v k & r q w u r o ) o d v k : u l w h % x i i h u ) 0 $ ) 0 ' ) & , 0 ) & 0 , 6 & ) o d v k $ u u d \ & r u w h [ 0 % u l g j h 6 5 $ 0 $ u u d \ 6 \ v w h p % x v , f r g h % x v ' f r g h % x v ) o d v k 3 u r w h f w l r q ) 0 3 5 ( ) 0 3 3 ( ) o d v k 7 l p l q j 8 6 ( & 5 / ) o d v k 3 u r w h f w l r q ) 0 3 5 ( q ) 0 3 3 ( q 8 v h u 5 h j l v w h u v % 2 2 7 & ) * 8 6 ( 5 b 5 ( * 8 6 ( 5 b 5 ( * 8 6 ( 5 b 5 ( * 8 6 ( 5 b 5 ( * ) 0 & ) & 5 , 6 ) 0 & ) : % 9 $ / ) : % q z r u g v 6.2.1 sram the internal sram of the stellaris ? devices is located at address 0x2000.0000 of the device memory map. to reduce the number of time consuming read-modify-write (rmw) operations, arm provides bit-banding technology in the processor. with a bit-band-enabled processor, certain regions in the memory map (sram and peripheral space) can use address aliases to access individual bits in a single, atomic operation. the bit-band base is located at address 0x2200.0000. the bit-band alias is calculated by using the formula: bit-band alias = bit-band base + (byte offset * 32) + (bit number * 4) for example, if bit 3 at address 0x2000.1000 is to be modified, the bit-band alias is calculated as: 0x2200.0000 + (0x1000 * 32) + (3 * 4) = 0x2202.000c with the alias address calculated, an instruction performing a read/write to address 0x2202.000c allows direct access to only bit 3 of the byte at address 0x2000.1000. for details about bit-banding, see bit-banding on page 93. note: the sram is implemented using two 32-bit wide sram banks (separate sram arrays). the banks are partitioned such that one bank contains all even words (the even bank) and the other contains all odd words (the odd bank). a write access that is followed immediately by a read access to the same bank incurs a stall of a single clock cycle. however, a write to one bank followed by a read of the other bank can occur in successive clock cycles without incurring any delay. 6.2.2 rom the internal rom of the stellaris device is located at address 0x0100.0000 of the device memory map. detailed information on the rom contents can be found in the stellaris? rom users guide . the rom contains the following components: stellaris boot loader and vector table stellaris peripheral driver library (driverlib) release for product-specific peripherals and interfaces advanced encryption standard (aes) cryptography tables cyclic redundancy check (crc) error detection functionality the boot loader is used as an initial program loader (when the flash memory is empty) as well as an application-initiated firmware upgrade mechanism (by calling back to the boot loader). the peripheral driver library apis in rom can be called by applications, reducing flash memory requirements and freeing the flash memory to be used for other purposes (such as additional features in the application). advance encryption standard (aes) is a publicly defined encryption standard used by the u.s. government and cyclic redundancy check (crc) is a technique to validate a span of data has the same contents as when previously checked. 6.2.2.1 boot loader overview the stellaris boot loader is used to download code to the flash memory of a device without the use of a debug interface. when the core is reset, the user has the opportunity to direct the core to execute the rom boot loader or the application in flash memory by using any gpio signal in ports a-h as configured in the boot configuration (bootcfg) register. 299 july 03, 2014 texas instruments-production data stellaris ? at reset, the rom is mapped over the flash memory so that the rom boot sequence is always executed. the boot sequence executed from rom is as follows: 1. the ba bit (below) is cleared such that rom is mapped to 0x01xx.xxxx and flash memory is mapped to address 0x0. 2. the bootcfg register is read. if the en bit is clear, the status of the specified gpio pin is compared with the specified polarity. if the status matches the specified polarity, the rom is mapped to address 0x0000.0000 and execution continues out of the rom boot loader. 3. if the status doesn't match the specified polarity, the data at address 0x0000.0004 is read, and if the data at this address is 0xffff.ffff, the rom is mapped to address 0x0000.0000 and execution continues out of the rom boot loader. 4. if there is data at address 0x0000.0004 that is not 0xffff.ffff, the stack pointer ( sp ) is loaded from flash memory at address 0x0000.0000 and the program counter ( pc ) is loaded from address 0x0000.0004. the user application begins executing. the boot loader uses a simple packet interface to provide synchronous communication with the device. the speed of the boot loader is determined by the internal oscillator (piosc) frequency as it does not enable the pll. the following serial interfaces can be used: uart0 ssi0 i 2 c0 ethernet for simplicity, both the data format and communication protocol are identical for all serial interfaces. note: the flash-memory-resident version of the boot loader also supports can and usb. see the stellaris? boot loader user's guide for information on the boot loader software. 6.2.2.2 stellaris peripheral driver library the stellaris peripheral driver library contains a file called driverlib/rom.h that assists with calling the peripheral driver library functions in the rom. the detailed description of each function is available in the stellaris? rom users guide . see the "using the rom" chapter of the stellaris? peripheral driver library user's guide for more details on calling the rom functions and using driverlib/rom.h. a table at the beginning of the rom points to the entry points for the apis that are provided in the rom. accessing the api through these tables provides scalability; while the api locations may change in future versions of the rom, the api tables will not. the tables are split into two levels; the main table contains one pointer per peripheral which points to a secondary table that contains one pointer per api that is associated with that peripheral. the main table is located at 0x0100.0010, right after the cortex-m3 vector table in the rom. driverlib functions are described in detail in the stellaris? peripheral driver library user's guide . additional apis are available for graphics and usb functions, but are not preloaded into rom. the stellaris graphics library provides a set of graphics primitives and a widget set for creating graphical user interfaces on stellaris microcontroller-based boards that have a graphical display (for more information, see the stellaris? graphics library user's guide ). the stellaris usb library is a set july 03, 2014 300 texas instruments-production data internal memory of data types and functions for creating usb device, host or on-the-go (otg) applications on stellaris microcontroller-based boards (for more information, see the stellaris? usb library user's guide ). 6.2.2.3 advanced encryption standard (aes) cryptography tables aes is a strong encryption method with reasonable performance and size. aes is fast in both hardware and software, is fairly easy to implement, and requires little memory. aes is ideal for applications that can use pre-arranged keys, such as setup during manufacturing or configuration. four data tables used by the xyssl aes implementation are provided in the rom. the first is the forward s-box substitution table, the second is the reverse s-box substitution table, the third is the forward polynomial table, and the final is the reverse polynomial table. see the stellaris? rom users guide for more information on aes. 6.2.2.4 cyclic redundancy check (crc) error detection the crc technique can be used to validate correct receipt of messages (nothing lost or modified in transit), to validate data after decompression, to validate that flash memory contents have not been changed, and for other cases where the data needs to be validated. a crc is preferred over a simple checksum (e.g. xor all bits) because it catches changes more readily. see the stellaris? rom users guide for more information on crc. 6.2.3 flash memory at system clock speeds of 50 mhz and below, the flash memory is read in a single cycle. the flash memory is organized as a set of 1-kb blocks that can be individually erased. an individual 32-bit word can be programmed to change bits from 1 to 0. in addition, a write buffer provides the ability to concurrently program 32 continuous words in flash memory. erasing a block causes the entire contents of the block to be reset to all 1s. the 1-kb blocks are paired into sets of 2-kb blocks that can be individually protected. the protection allows blocks to be marked as read-only or execute-only, providing different levels of code protection. read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. execute-only blocks cannot be erased or programmed and can only be read by the controller instruction fetch mechanism, protecting the contents of those blocks from being read by either the controller or by a debugger. caution C the stellaris flash memory array has ecc which uses a test port into the flash memory to continually scan the array for ecc errors and to correct any that are detected. this operation is transparent to the microcontroller. the bist must scan the entire memory array occasionally to ensure integrity, taking about fve minutes to do so. in systems where the microcontroller is frequently powered for less than fve minutes, power should be removed from the microcontroller in a controlled manner to ensure proper operation. software can request permission to power down the part using the usdreq bit in the flash control (fctl) register and wait to receive an acknowledge from the usdack bit prior to removing power. if the microcontroller is powered down using this controlled method, the bist engine keeps track of where it was in the memory array and it always scans the complete array after any aggregate of fve minutes powered-on, regardless of the number of intervening power cycles. if the microcontroller is powered down before fve minutes of being powered up, bist starts again from wherever it left off before the last controlled power-down or from 0 if there never was a controlled power down. an occasional short power down is not a concern, but the microcontroller should not always be powered down frequently in an uncontrolled manner. the microcontroller can be power-cycled as frequently as necessary if it is powered-down in a controlled manner. 301 july 03, 2014 texas instruments-production data stellaris ? 6.2.3.1 prefetch buffer the flash memory controller has a prefetch buffer that is automatically used when the cpu frequency is greater than 50 mhz. in this mode, the flash memory operates at half of the system clock. the prefetch buffer fetches two 32-bit words per clock allowing instructions to be fetched with no wait states while code is executing linearly. the fetch buffer includes a branch speculation mechanism that recognizes a branch and avoids extra wait states by not reading the next word pair. also, short loop branches often stay in the buffer. as a result, some branches can be executed with no wait states. other branches incur a single wait state. 6.2.3.2 flash memory protection the user is provided two forms of flash memory protection per 2-kb flash memory block in six pairs of 32-bit wide registers. the policy for each protection form is controlled by individual bits (per policy per block) in the fmppen and fmpren registers. flash memory protection program enable (fmppen) : if a bit is set, the corresponding block may be programmed (written) or erased. if a bit is cleared, the corresponding block may not be changed. flash memory protection read enable (fmpren) : if a bit is set, the corresponding block may be executed or read by software or debuggers. if a bit is cleared, the corresponding block may only be executed, and contents of the memory block are prohibited from being read as data. the policies may be combined as shown in table 6-1 on page 302. table 6-1. flash memory protection policy combinations protection fmpren fmppen execute-only protection. the block may only be executed and may not be written or erased. this mode is used to protect code. 0 0 the block may be written, erased or executed, but not read. this combination is unlikely to be used. 0 1 read-only protection. the block may be read or executed but may not be written or erased. this mode is used to lock the block from further modification while allowing any read or execute access. 1 0 no protection. the block may be written, erased, executed or read. 1 1 a flash memory access that attempts to read a read-protected block ( fmpren bit is set) is prohibited and generates a bus fault. a flash memory access that attempts to program or erase a program-protected block ( fmppen bit is set) is prohibited and can optionally generate an interrupt (by setting the amask bit in the flash controller interrupt mask (fcim) register) to alert software developers of poorly behaving software during the development and debug phases. note that if a fmpren bit is cleared, all read accesses to the flash memory block are disallowed, including any data accesses. care must be taken not to store required data in a flash memory block that has the associated fmpren bit cleared. the factory settings for the fmpren and fmppen registers are a value of 1 for all implemented banks. these settings create a policy of open access and programmability. the register bits may be changed by clearing the specific register bit. the changes are effective immediately, but are not permanent until the register is committed (saved), at which point the bit change is permanent. if a bit is changed from a 1 to a 0 and not committed, it may be restored by executing any type of reset sequence. the changes are committed using the flash memory control (fmc) register. details on programming these bits are discussed in non-volatile register programming on page 305. july 03, 2014 302 texas instruments-production data internal memory 6.2.3.3 interrupts the flash memory controller can generate interrupts when the following conditions are observed: programming interrupt - signals when a program or erase action is complete. access interrupt - signals when a program or erase action has been attempted on a 2-kb block of memory that is protected by its corresponding fmppen bit. the interrupt events that can trigger a controller-level interrupt are defined in the flash controller masked interrupt status (fcmis) register (see page 315) by setting the corresponding mask bits. if interrupts are not used, the raw interrupt status is always visible via the flash controller raw interrupt status (fcris) register (see page 314). interrupts are always cleared (for both the fcmis and fcris registers) by writing a 1 to the corresponding bit in the flash controller masked interrupt status and clear (fcmisc) register (see page 316). 6.2.3.4 flash memory programming the stellaris devices provide a user-friendly interface for flash memory programming. all erase/program operations are handled via three registers: flash memory address (fma) , flash memory data (fmd) , and flash memory control (fmc) . note that if the debug capabilities of the microcontroller have been deactivated, resulting in a "locked" state, a recovery sequence must be performed in order to reactivate the debug module. see recovering a "locked" microcontroller on page 184. during a flash memory operation (write, page erase, or mass erase) access to the flash memory is inhibited. as a result, instruction and literal fetches are held off until the flash memory operation is complete. if instruction execution is required during a flash memory operation, the code that is executing must be placed in sram and executed from there while the flash operation is in progress. caution C the flash memory is divided into sectors of electrically separated address ranges of 4 kb each, aligned on 4 kb boundaries. erase/program operations on a 1-kb page have an electrical effect on the other three 1-kb pages within the sector. a specifc 1-kb page must be erased after 6 total erase/program cycles occur to the other pages within its 4-kb sector. the following sequence of operations on a 4-kb sector of flash memory (page 0..3) provides an example: page 3 is erase and programmed with values. page 0, page 1, and page 2 are erased and then programmed with values. at this point page 3 has been affected by 3 erase/program cycles. page 0, page 1, and page 2 are again erased and then programmed with values. at this point page 3 has been affected by 6 erase/program cycles. if the contents of page 3 must continue to be valid, page 3 must be erased and reprogrammed before any other page in this sector has another erase or program operation. to program a 32-bit word 1. write source data to the fmd register. 2. write the target address to the fma register. 303 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 3. write the flash memory write key and the write bit (a value of 0xa442.0001) to the fmc register. 4. poll the fmc register until the write bit is cleared. important: to ensure proper operation, two writes to the same word must be separated by an erase. the following two sequences are allowed: erase -> program value -> program 0x0000.0000 erase -> program value -> erase the following sequence is not allowed: erase -> program value -> program value to perform an erase of a 1-kb page 1. write the page address to the fma register. 2. write the flash memory write key and the erase bit (a value of 0xa442.0002) to the fmc register. 3. poll the fmc register until the erase bit is cleared or, alternatively, enable the programming interrupt using the pmask bit in the fcim register. to perform a mass erase of the flash memory 1. write the flash memory write key and the merase bit (a value of 0xa442.0004) to the fmc register. 2. poll the fmc register until the merase bit is cleared or, alternatively, enable the programming interrupt using the pmask bit in the fcim register. 6.2.3.5 32-word flash memory write buffer a 32-word write buffer provides the capability to perform faster write accesses to the flash memory by concurrently programing 32 words with a single buffered flash memory write operation. the buffered flash memory write operation takes the same amount of time as the single word write operation controlled by bit 0 in the fmc register. the data for the buffered write is written to the flash write buffer (fwbn) registers. the registers are 32-word aligned with flash memory, and therefore the register fwb0 corresponds with the address in fma where bits [6:0] of fma are all 0. fwb1 corresponds with the address in fma + 0x4 and so on. only the fwbn registers that have been updated since the previous buffered flash memory write operation are written. the flash write buffer valid (fwbval) register shows which registers have been written since the last buffered flash memory write operation. this register contains a bit for each of the 32 fwbn registers, where bit[n] of fwbval corresponds to fwbn . the fwbn register has been updated if the corresponding bit in the fwbval register is set. to program 32 words with a single buffered flash memory write operation 1. write the source data to the fwbn registers. july 03, 2014 304 texas instruments-production data internal memory 2. write the target address to the fma register. this must be a 32-word aligned address (that is, bits [6:0] in fma must be 0s). 3. write the flash memory write key and the wrbuf bit (a value of 0xa442.0001) to the fmc2 register. 4. poll the fmc2 register until the wrbuf bit is cleared or wait for the pmis interrupt to be signaled. 6.2.3.6 non-volatile register programming note: the boot configuration (bootcfg) register requires a por before the committed changes take effect. this section discusses how to update the registers shown in table 6-2 on page 306 that are resident within the flash memory itself. these registers exist in a separate space from the main flash memory array and are not affected by an erase or mass erase operation. with the exception of the boot configuration (bootcfg) register, the settings in these registers can be written, their functions verified, and their values read back before they are committed, at which point they become non-volatile. if a value in one of these registers has not been committed, any type of reset restores the last committed value or the default value if the register has never been committed. once the register contents are committed, the only way to restore the factory default values is to perform the sequence described in recovering a "locked" microcontroller on page 184. to write to a non-volatile register: bits can only be changed from 1 to 0. for all registers except the bootcfg register, write the data to the register address provided in the register description. for the bootcfg register, write the data to the fmd register. the registers can be read to verify their contents. to verify what is to be stored in the bootcfg register, read the fmd register. reading the bootcfg register returns the previously committed value or the default value if the register has never been committed. the new values are effectively immediately for all registers except bootcfg , as the new value for the register is not stored in the register until it has been committed. prior to committing the register value, any type of reset restores the last committed value or the default value if the register has never been committed. to commit a new value to a non-volatile register: write the data as described above. write to the fma register the value shown in table 6-2 on page 306. write the flash memory write key and set the comt bit in the fmc register. these values must be written to the fmc register at the same time. committing a non-volatile register has the same timing as a write to regular flash memory, defined by t prog , as shown in table 26-16 on page 1306. software can poll the comt bit in the fmc register to determine when the operation is complete, or an interrupt can be enabled by setting the pmask bit in the fcim register. when committing the bootcfg register, the invdris bit in the fcris register is set if a bit that has already been committed as a 0 is attempted to be committed as a 1. 305 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller once the value has been committed, any type of reset has no effect on the register contents. changes to the bootcfg register are effective after the next reset. the nw bit in the user_reg0 , user_reg1 , user_reg2 , user_reg3 , and bootcfg registers is cleared when the register is committed. once this bit is cleared, additional changes to the register are not allowed. important: after being committed, these registers can only be restored to their factory default values by performing the sequence described in recovering a "locked" microcontroller on page 184. the mass erase of the main flash memory array caused by the sequence is performed prior to restoring these registers. table 6-2. user-programmable flash memory resident registers data source fma value register to be committed fmpre0 0x0000.0000 fmpre0 fmpre1 0x0000.0002 fmpre1 fmpre2 0x0000.0004 fmpre2 fmpre3 0x0000.0006 fmpre3 fmpre4 0x0000.0008 fmpre4 fmpre5 0x0000.000a fmpre5 fmppe0 0x0000.0001 fmppe0 fmppe1 0x0000.0003 fmppe1 fmppe2 0x0000.0005 fmppe2 fmppe3 0x0000.0007 fmppe3 fmpre4 0x0000.0009 fmpre4 fmpre5 0x0000.000b fmpre5 user_reg0 0x8000.0000 user_reg0 user_reg1 0x8000.0001 user_reg1 user_reg2 0x8000.0002 user_reg2 user_reg3 0x8000.0003 user_reg3 fmd 0x7510.0000 bootcfg 6.3 register map table 6-3 on page 306 lists the rom controller register and the flash memory and control registers. the offset listed is a hexadecimal increment to the register's address. the flash memory register offsets are relative to the flash memory control base address of 0x400f.d000. the rom and flash memory protection register offsets are relative to the system control base address of 0x400f.e000. table 6-3. flash register map see page description reset type name offset flash memory registers (flash control offset) 309 flash memory address 0x0000.0000 r/w fma 0x000 310 flash memory data 0x0000.0000 r/w fmd 0x004 july 03, 2014 306 texas instruments-production data internal memory table 6-3. flash register map (continued) see page description reset type name offset 311 flash memory control 0x0000.0000 r/w fmc 0x008 314 flash controller raw interrupt status 0x0000.0000 ro fcris 0x00c 315 flash controller interrupt mask 0x0000.0000 r/w fcim 0x010 316 flash controller masked interrupt status and clear 0x0000.0000 r/w1c fcmisc 0x014 317 flash memory control 2 0x0000.0000 r/w fmc2 0x020 318 flash write buffer valid 0x0000.0000 r/w fwbval 0x030 319 flash control 0x0000.0000 r/w fctl 0x0f8 320 flash write buffer n 0x0000.0000 r/w fwbn 0x100 - 0x17c memory registers (system control offset) 321 rom control - r/w1c rmctl 0x0f0 322 flash memory protection read enable 0 0xffff.ffff r/w fmpre0 0x130 322 flash memory protection read enable 0 0xffff.ffff r/w fmpre0 0x200 323 flash memory protection program enable 0 0xffff.ffff r/w fmppe0 0x134 323 flash memory protection program enable 0 0xffff.ffff r/w fmppe0 0x400 324 boot configuration 0xffff.fffe r/w bootcfg 0x1d0 326 user register 0 0xffff.ffff r/w user_reg0 0x1e0 327 user register 1 0xffff.ffff r/w user_reg1 0x1e4 328 user register 2 0xffff.ffff r/w user_reg2 0x1e8 329 user register 3 0xffff.ffff r/w user_reg3 0x1ec 330 flash memory protection read enable 1 0xffff.ffff r/w fmpre1 0x204 331 flash memory protection read enable 2 0xffff.ffff r/w fmpre2 0x208 332 flash memory protection read enable 3 0xffff.ffff r/w fmpre3 0x20c 333 flash memory protection read enable 4 0xffff.ffff r/w fmpre4 0x210 334 flash memory protection read enable 5 0xffff.ffff r/w fmpre5 0x214 335 flash memory protection read enable 6 0x0000.0000 r/w fmpre6 0x218 336 flash memory protection read enable 7 0x0000.0000 r/w fmpre7 0x21c 337 flash memory protection program enable 1 0xffff.ffff r/w fmppe1 0x404 338 flash memory protection program enable 2 0xffff.ffff r/w fmppe2 0x408 339 flash memory protection program enable 3 0xffff.ffff r/w fmppe3 0x40c 340 flash memory protection program enable 4 0xffff.ffff r/w fmppe4 0x410 341 flash memory protection program enable 5 0xffff.ffff r/w fmppe5 0x414 307 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 6-3. flash register map (continued) see page description reset type name offset 342 flash memory protection program enable 6 0x0000.0000 r/w fmppe6 0x418 343 flash memory protection program enable 7 0x0000.0000 r/w fmppe7 0x41c 6.4 flash memory register descriptions (flash control offset) this section lists and describes the flash memory registers, in numerical order by address offset. registers in this section are relative to the flash control base address of 0x400f.d000. july 03, 2014 308 texas instruments-production data internal memory register 1: flash memory address (fma), offset 0x000 during a write operation, this register contains a 4-byte-aligned address and specifies where the data is written. during erase operations, this register contains a 1 kb-aligned cpu byte address and specifies which block is erased. note that the alignment requirements must be met by software or the results of the operation are unpredictable. flash memory address (fma) base 0x400f.d000 offset 0x000 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 offset reserved r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 31:19 address offset address offset in flash memory where operation is performed, except for non-volatile registers (see non-volatile register programming on page 305 for details on values for this field). 0x0 r/w offset 18:0 309 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 2: flash memory data (fmd), offset 0x004 this register contains the data to be written during the programming cycle or read during the read cycle. note that the contents of this register are undefined for a read access of an execute-only block. this register is not used during erase cycles. flash memory data (fmd) base 0x400f.d000 offset 0x004 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 data r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 data r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field data value data value for write operation. 0x0000.0000 r/w data 31:0 july 03, 2014 310 texas instruments-production data internal memory register 3: flash memory control (fmc), offset 0x008 when this register is written, the flash memory controller initiates the appropriate access cycle for the location specified by the flash memory address (fma) register (see page 309). if the access is a write access, the data contained in the flash memory data (fmd) register (see page 310) is written to the specified address. this register must be the final register written and initiates the memory operation. the four control bits in the lower byte of this register are used to initiate memory operations. care must be taken not to set multiple control bits as the results of such an operation are unpredictable. caution C if any of bits [15:4] are written to 1, the device may become inoperable. these bits should always be written to 0. in all registers, the value of a reserved bit should be preserved across a read-modify-write operation. flash memory control (fmc) base 0x400f.d000 offset 0x008 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 wrkey wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 write erase merase comt reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field flash memory write key this field contains a write key, which is used to minimize the incidence of accidental flash memory writes. the value 0xa442 must be written into this field for a flash memory write to occur. writes to the fmc register without this wrkey value are ignored. a read of this field returns the value 0. 0x0000 wo wrkey 31:16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 15:4 311 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field commit register value this bit is used to commit writes to flash-memory-resident registers and to monitor the progress of that process. description value set this bit to commit (write) the register value to a flash-memory-resident register. when read, a 1 indicates that the previous commit access is not complete. 1 a write of 0 has no effect on the state of this bit. when read, a 0 indicates that the previous commit access is complete. 0 see non-volatile register programming on page 305 for more information on programming flash-memory-resident registers. 0 r/w comt 3 mass erase flash memory this bit is used to mass erase the flash main memory and to monitor the progress of that process. description value set this bit to erase the flash main memory. when read, a 1 indicates that the previous mass erase access is not complete. 1 a write of 0 has no effect on the state of this bit. when read, a 0 indicates that the previous mass erase access is complete. 0 for information on erase time, see flash memory on page 1306. 0 r/w merase 2 erase a page of flash memory this bit is used to erase a page of flash memory and to monitor the progress of that process. description value set this bit to erase the flash memory page specified by the contents of the fma register. when read, a 1 indicates that the previous page erase access is not complete. 1 a write of 0 has no effect on the state of this bit. when read, a 0 indicates that the previous page erase access is complete. 0 for information on erase time, see flash memory on page 1306. 0 r/w erase 1 july 03, 2014 312 texas instruments-production data internal memory description reset type name bit/field write a word into flash memory this bit is used to write a word into flash memory and to monitor the progress of that process. description value set this bit to write the data stored in the fmd register into the flash memory location specified by the contents of the fma register. when read, a 1 indicates that the write update access is not complete. 1 a write of 0 has no effect on the state of this bit. when read, a 0 indicates that the previous write update access is complete. 0 for information on programming time, see flash memory on page 1306. 0 r/w write 0 313 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 4: flash controller raw interrupt status (fcris), offset 0x00c this register indicates that the flash memory controller has an interrupt condition. an interrupt is sent to the interrupt controller only if the corresponding fcim register bit is set. flash controller raw interrupt status (fcris) base 0x400f.d000 offset 0x00c type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 aris pris reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:2 programming raw interrupt status this bit provides status on programming cycles which are write or erase actions generated through the fmc or fmc2 register bits (see page 311 and page 317). description value the programming or erase cycle has completed. 1 the programming or erase cycle has not completed. 0 this status is sent to the interrupt controller when the pmask bit in the fcim register is set. this bit is cleared by writing a 1 to the pmisc bit in the fcmisc register. 0 ro pris 1 access raw interrupt status description value a program or erase action was attempted on a block of flash memory that contradicts the protection policy for that block as set in the fmppen registers. 1 no access has tried to improperly program or erase the flash memory. 0 this status is sent to the interrupt controller when the amask bit in the fcim register is set. this bit is cleared by writing a 1 to the amisc bit in the fcmisc register. 0 ro aris 0 july 03, 2014 314 texas instruments-production data internal memory register 5: flash controller interrupt mask (fcim), offset 0x010 this register controls whether the flash memory controller generates interrupts to the controller. flash controller interrupt mask (fcim) base 0x400f.d000 offset 0x010 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 amask pmask reserved r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:2 programming interrupt mask this bit controls the reporting of the programming raw interrupt status to the interrupt controller. description value an interrupt is sent to the interrupt controller when the pris bit is set. 1 the pris interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w pmask 1 access interrupt mask this bit controls the reporting of the access raw interrupt status to the interrupt controller. description value an interrupt is sent to the interrupt controller when the aris bit is set. 1 the aris interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w amask 0 315 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 6: flash controller masked interrupt status and clear (fcmisc), offset 0x014 this register provides two functions. first, it reports the cause of an interrupt by indicating which interrupt source or sources are signalling the interrupt. second, it serves as the method to clear the interrupt reporting. flash controller masked interrupt status and clear (fcmisc) base 0x400f.d000 offset 0x014 type r/w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 amisc pmisc reserved r/w1c r/w1c ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:2 programming masked interrupt status and clear description value when read, a 1 indicates that an unmasked interrupt was signaled because a programming cycle completed. writing a 1 to this bit clears pmisc and also the pris bit in the fcris register (see page 314). 1 when read, a 0 indicates that a programming cycle complete interrupt has not occurred. a write of 0 has no effect on the state of this bit. 0 0 r/w1c pmisc 1 access masked interrupt status and clear description value when read, a 1 indicates that an unmasked interrupt was signaled because a program or erase action was attempted on a block of flash memory that contradicts the protection policy for that block as set in the fmppen registers. writing a 1 to this bit clears amisc and also the aris bit in the fcris register (see page 314). 1 when read, a 0 indicates that no improper accesses have occurred. a write of 0 has no effect on the state of this bit. 0 0 r/w1c amisc 0 july 03, 2014 316 texas instruments-production data internal memory register 7: flash memory control 2 (fmc2), offset 0x020 when this register is written, the flash memory controller initiates the appropriate access cycle for the location specified by the flash memory address (fma) register (see page 309). if the access is a write access, the data contained in the flash write buffer (fwb) registers is written. this register must be the final register written as it initiates the memory operation. flash memory control 2 (fmc2) base 0x400f.d000 offset 0x020 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 wrkey wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 wrbuf reserved r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field flash memory write key this field contains a write key, which is used to minimize the incidence of accidental flash memory writes. the value 0xa442 must be written into this field for a write to occur. writes to the fmc2 register without this wrkey value are ignored. a read of this field returns the value 0. 0x0000 wo wrkey 31:16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 15:1 buffered flash memory write this bit is used to start a buffered write to flash memory. description value set this bit to write the data stored in the fwbn registers to the location specified by the contents of the fma register. when read, a 1 indicates that the previous buffered flash memory write access is not complete. 1 a write of 0 has no effect on the state of this bit. when read, a 0 indicates that the previous buffered flash memory write access is complete. 0 for information on programming time, see flash memory on page 1306. 0 r/w wrbuf 0 317 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 8: flash write buffer valid (fwbval), offset 0x030 this register provides a bitwise status of which fwbn registers have been written by the processor since the last write of the flash memory write buffer. the entries with a 1 are written on the next write of the flash memory write buffer. this register is cleared after the write operation by hardware. a protection violation on the write operation also clears this status. software can program the same 32 words to various flash memory locations by setting the fwb[n] bits after they are cleared by the write operation. the next write operation then uses the same data as the previous one. in addition, if a fwbn register change should not be written to flash memory, software can clear the corresponding fwb[n] bit to preserve the existing data when the next write operation occurs. flash write buffer valid (fwbval) base 0x400f.d000 offset 0x030 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 fwb[n] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 fwb[n] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field flash memory write buffer description value the corresponding fwbn register has been updated since the last buffer write operation and is ready to be written to flash memory. 1 the corresponding fwbn register has no new data to be written. 0 bit 0 corresponds to fwb0 , offset 0x100, and bit 31 corresponds to fwb31 , offset 0x13c. 0x0 r/w fwb[n] 31:0 july 03, 2014 318 texas instruments-production data internal memory register 9: flash control (fctl), offset 0x0f8 this register is used to ensure that the microcontroller is powered down in a controlled fashion in systems where power is cycled more frequently than once every five minutes. the usdreq bit should be set to indicate that power is going to be turned off. software should poll the usdack bit to determine when it is acceptable to power down. flash control (fctl) base 0x400f.d000 offset 0x0f8 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 usdreq usdack reserved r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:2 user shut down acknowledge description value the microcontroller can be powered down. 1 the microcontroller cannot yet be powered down. 0 this bit should be set within 50 ms of setting the usdreq bit. 0 ro usdack 1 user shut down request description value requests permission to power down the microcontroller. 1 no effect. 0 0 r/w usdreq 0 319 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 10: flash write buffer n (fwbn), offset 0x100 - 0x17c these 32 registers hold the contents of the data to be written into the flash memory on a buffered flash memory write operation. the offset selects one of the 32-bit registers. only fwbn registers that have been updated since the preceding buffered flash memory write operation are written into the flash memory, so it is not necessary to write the entire bank of registers in order to write 1 or 2 words. the fwbn registers are written into the flash memory with the fwb0 register corresponding to the address contained in fma . fwb1 is written to the address fma +0x4 etc. note that only data bits that are 0 result in the flash memory being modified. a data bit that is 1 leaves the content of the flash memory bit at its previous value. flash write buffer n (fwbn) base 0x400f.d000 offset 0x100 - 0x17c type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 data r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 data r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field data data to be written into the flash memory. 0x0000.0000 r/w data 31:0 6.5 memory register descriptions (system control offset) the remainder of this section lists and describes the registers that reside in the system control address space, in numerical order by address offset. registers in this section are relative to the system control base address of 0x400f.e000. july 03, 2014 320 texas instruments-production data internal memory register 11: rom control (rmctl), offset 0x0f0 this register provides control of the rom controller state. this register offset is relative to the system control base address of 0x400f.e000. at reset, the rom is mapped over the flash memory so that the rom boot sequence is always executed. the boot sequence executed from rom is as follows: 1. the ba bit (below) is cleared such that rom is mapped to 0x01xx.xxxx and flash memory is mapped to address 0x0. 2. the bootcfg register is read. if the en bit is clear, the status of the specified gpio pin is compared with the specified polarity. if the status matches the specified polarity, the rom is mapped to address 0x0000.0000 and execution continues out of the rom boot loader. 3. if the status doesn't match the specified polarity, the data at address 0x0000.0004 is read, and if the data at this address is 0xffff.ffff, the rom is mapped to address 0x0000.0000 and execution continues out of the rom boot loader. 4. if there is data at address 0x0000.0004 that is not 0xffff.ffff, the stack pointer ( sp ) is loaded from flash memory at address 0x0000.0000 and the program counter ( pc ) is loaded from address 0x0000.0004. the user application begins executing. rom control (rmctl) base 0x400f.e000 offset 0x0f0 type r/w1c, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ba reserved r/w1c ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:1 boot alias description value the microcontroller's rom appears at address 0x0. 1 the flash memory is at address 0x0. 0 this bit is cleared by writing a 1 to this bit position. 1 r/w1c ba 0 321 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 12: flash memory protection read enable 0 (fmpre0), offset 0x130 and 0x200 note: this register is aliased for backwards compatability. note: offset is relative to system control base address of 0x400fe000. this register stores the read-only protection bits for each 2-kb flash block ( fmppen stores the execute-only bits). flash memory up to a total of 64 kb is controlled by this register. other fmpren registers (if any) provide protection for other 64k blocks. this register is loaded during the power-on reset sequence. the factory settings for the fmpren and fmppen registers are a value of 1 for all implemented banks. this achieves a policy of open access and programmability. the register bits may be changed by writing the specific register bit. however, this register is r/w0; the user can only change the protection bit from a 1 to a 0 (and may not change a 0 to a 1). the changes are not permanent until the register is committed (saved), at which point the bit change is permanent. if a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. the reset value shown only applies to power-on reset; any other type of reset does not affect this register. once committed, the only way to restore the factory default value of this register is to perform the sequence detailed in recovering a "locked" microcontroller on page 184. for additional information, see flash memory protection on page 302. flash memory protection read enable 0 (fmpre0) base 0x400f.e000 offset 0x130 and 0x200 type r/w, reset 0xffff.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 read_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 read_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field flash read enable configures 2-kb flash blocks to be read or executed only. the policies may be combined as shown in table 6-1 on page 302. description value bits [31:0] each enable protection on a 2-kb block of flash memory up to the total of 64 kb. 0xffffffff 0xffffffff r/w read_enable 31:0 july 03, 2014 322 texas instruments-production data internal memory register 13: flash memory protection program enable 0 (fmppe0), offset 0x134 and 0x400 note: this register is aliased for backwards compatability. note: offset is relative to system control base address of 0x400fe000. this register stores the execute-only protection bits for each 2-kb flash block ( fmpren stores the execute-only bits). flash memory up to a total of 64 kb is controlled by this register. other fmppen registers (if any) provide protection for other 64k blocks. this register is loaded during the power-on reset sequence. the factory settings for the fmpren and fmppen registers are a value of 1 for all implemented banks. this achieves a policy of open access and programmability. the register bits may be changed by writing the specific register bit. however, this register is r/w0; the user can only change the protection bit from a 1 to a 0 (and may not change a 0 to a 1). the changes are not permanent until the register is committed (saved), at which point the bit change is permanent. if a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. the reset value shown only applies to power-on reset; any other type of reset does not affect this register. once committed, the only way to restore the factory default value of this register is to perform the sequence detailed in recovering a "locked" microcontroller on page 184. for additional information, see flash memory protection on page 302. flash memory protection program enable 0 (fmppe0) base 0x400f.e000 offset 0x134 and 0x400 type r/w, reset 0xffff.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 prog_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 prog_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field flash programming enable configures 2-kb flash blocks to be execute only. the policies may be combined as shown in table 6-1 on page 302. description value bits [31:0] each enable protection on a 2-kb block of flash memory up to the total of 64 kb. 0xffffffff 0xffffffff r/w prog_enable 31:0 323 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 14: boot configuration (bootcfg), offset 0x1d0 note: offset is relative to system control base address of 0x400fe000. this register provides configuration of a gpio pin to enable the rom boot loader as well as a write-once mechanism to disable external debugger access to the device. upon reset, the user has the opportunity to direct the core to execute the rom boot loader or the application in flash memory by using any gpio signal from ports a-h as configured by the bits in this register. if the en bit is set or the specified pin does not have the required polarity, the system control module checks address 0x000.0004 to see if the flash memory has a valid reset vector. if the data at address 0x0000.0004 is 0xffff.ffff, then it is assumed that the flash memory has not yet been programmed, and the core executes the rom boot loader. the dbg0 bit (bit 0) is set to 0 from the factory and the dbg1 bit (bit 1) is set to 1, which enables external debuggers. clearing the dbg1 bit disables any external debugger access to the device permanently, starting with the next power-up cycle of the device. the nw bit (bit 31) indicates that the register has not yet been committed and is controlled through hardware to ensure that the register is only committed once. prior to being committed, bits can only be changed from 1 to 0. the reset value shown only applies to power-on reset; any other type of reset does not affect this register. once committed, the only way to restore the factory default value of this register is to perform the sequence detailed in recovering a "locked" microcontroller on page 184. boot configuration (bootcfg) base 0x400f.e000 offset 0x1d0 type r/w, reset 0xffff.fffe 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved nw ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dbg0 dbg1 reserved en pol pin port r/w r/w ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w type 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field not written when set, this bit indicates that this 32-bit register has not been committed. when clear, this bit specifies that this register has been committed and may not be committed again. 1 r/w nw 31 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x7fff ro reserved 30:16 july 03, 2014 324 texas instruments-production data internal memory description reset type name bit/field boot gpio port this field selects the port of the gpio port pin that enables the rom boot loader at reset. description value port a 0x0 port b 0x1 port c 0x2 port d 0x3 port e 0x4 port f 0x5 port g 0x6 port h 0x7 0x7 r/w port 15:13 boot gpio pin this field selects the pin number of the gpio port pin that enables the rom boot loader at reset. description value pin 0 0x0 pin 1 0x1 pin 2 0x2 pin 3 0x3 pin 4 0x4 pin 5 0x5 pin 6 0x6 pin 7 0x7 0x7 r/w pin 12:10 boot gpio polarity when set, this bit selects a high level for the gpio port pin to enable the rom boot loader at reset. when clear, this bit selects a low level for the gpio port pin. 0x1 r/w pol 9 boot gpio enable clearing this bit enables the use of a gpio pin to enable the rom boot loader at reset. when this bit is set, the contents of address 0x0000.0004 are checked to see if the flash memory has been programmed. if the contents are not 0xffff.ffff, the core executes out of flash memory. if the flash has not been programmed, the core executes out of rom. 0x1 r/w en 8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x3f ro reserved 7:2 debug control 1 the dbg1 bit must be 1 and dbg0 must be 0 for debug to be available. 1 r/w dbg1 1 debug control 0 the dbg1 bit must be 1 and dbg0 must be 0 for debug to be available. 0x0 r/w dbg0 0 325 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 15: user register 0 (user_reg0), offset 0x1e0 note: offset is relative to system control base address of 0x400fe000. this register provides 31 bits of user-defined data that is non-volatile and can only be committed once. bit 31 indicates that the register is available to be committed and is controlled through hardware to ensure that the register is only committed once. prior to being committed, bits can only be changed from 1 to 0. the reset value shown only applies to power-on reset; any other type of reset does not affect this register. the write-once characteristics of this register are useful for keeping static information like communication addresses that need to be unique per part and would otherwise require an external eeprom or other non-volatile device. once committed, the only way to restore the factory default value of this register is to perform the sequence detailed in recovering a "locked" microcontroller on page 184. user register 0 (user_reg0) base 0x400f.e000 offset 0x1e0 type r/w, reset 0xffff.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 data nw r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 data r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field not written when set, this bit indicates that this 32-bit register has not been committed. when clear, this bit specifies that this register has been committed and may not be committed again. 1 r/w nw 31 user data contains the user data value. this field is initialized to all 1s and can only be committed once. 0x7fffffff r/w data 30:0 july 03, 2014 326 texas instruments-production data internal memory register 16: user register 1 (user_reg1), offset 0x1e4 note: offset is relative to system control base address of 0x400fe000. this register provides 31 bits of user-defined data that is non-volatile and can only be written once. bit 31 indicates that the register is available to be written and is controlled through hardware to ensure that the register is only written once. the write-once characteristics of this register are useful for keeping static information like communication addresses that need to be unique per part and would otherwise require an external eeprom or other non-volatile device. user register 1 (user_reg1) base 0x400f.e000 offset 0x1e4 type r/w, reset 0xffff.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 data nw r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 data r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field not written when set, this bit indicates that this 32-bit register has not been committed. when clear, this bit specifies that this register has been committed and may not be committed again. 1 r/w nw 31 user data contains the user data value. this field is initialized to all 1s and can only be committed once. 0x7fffffff r/w data 30:0 327 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 17: user register 2 (user_reg2), offset 0x1e8 note: offset is relative to system control base address of 0x400fe000. this register provides 31 bits of user-defined data that is non-volatile and can only be written once. bit 31 indicates that the register is available to be written and is controlled through hardware to ensure that the register is only written once. the write-once characteristics of this register are useful for keeping static information like communication addresses that need to be unique per part and would otherwise require an external eeprom or other non-volatile device. user register 2 (user_reg2) base 0x400f.e000 offset 0x1e8 type r/w, reset 0xffff.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 data nw r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 data r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field not written when set, this bit indicates that this 32-bit register has not been committed. when clear, this bit specifies that this register has been committed and may not be committed again. 1 r/w nw 31 user data contains the user data value. this field is initialized to all 1s and can only be committed once. 0x7fffffff r/w data 30:0 july 03, 2014 328 texas instruments-production data internal memory register 18: user register 3 (user_reg3), offset 0x1ec note: offset is relative to system control base address of 0x400fe000. this register provides 31 bits of user-defined data that is non-volatile and can only be written once. bit 31 indicates that the register is available to be written and is controlled through hardware to ensure that the register is only written once. the write-once characteristics of this register are useful for keeping static information like communication addresses that need to be unique per part and would otherwise require an external eeprom or other non-volatile device. user register 3 (user_reg3) base 0x400f.e000 offset 0x1ec type r/w, reset 0xffff.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 data nw r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 data r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field not written when set, this bit indicates that this 32-bit register has not been committed. when clear, this bit specifies that this register has been committed and may not be committed again. 1 r/w nw 31 user data contains the user data value. this field is initialized to all 1s and can only be committed once. 0x7fffffff r/w data 30:0 329 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 19: flash memory protection read enable 1 (fmpre1), offset 0x204 note: offset is relative to system control base address of 0x400fe000. this register stores the read-only protection bits for each 2-kb flash block ( fmppen stores the execute-only bits). flash memory up to a total of 64 kb is controlled by this register. other fmpren registers (if any) provide protection for other 64k blocks. this register is loaded during the power-on reset sequence. the factory settings for the fmpren and fmppen registers are a value of 1 for all implemented banks. this achieves a policy of open access and programmability. the register bits may be changed by writing the specific register bit. however, this register is r/w0; the user can only change the protection bit from a 1 to a 0 (and may not change a 0 to a 1). the changes are not permanent until the register is committed (saved), at which point the bit change is permanent. if a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. the reset value shown only applies to power-on reset; any other type of reset does not affect this register. once committed, the only way to restore the factory default value of this register is to perform the sequence detailed in recovering a "locked" microcontroller on page 184. if the flash memory size on the device is less than 64 kb, this register usually reads as zeroes, but software should not rely on these bits to be zero. for additional information, see flash memory protection on page 302. flash memory protection read enable 1 (fmpre1) base 0x400f.e000 offset 0x204 type r/w, reset 0xffff.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 read_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 read_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field flash read enable configures 2-kb flash blocks to be read or executed only. the policies may be combined as shown in table 6-1 on page 302. description value bits [31:0] each enable protection on a 2-kb block of flash memory in memory range from 65 to 128 kb. 0xffffffff 0xffffffff r/w read_enable 31:0 july 03, 2014 330 texas instruments-production data internal memory register 20: flash memory protection read enable 2 (fmpre2), offset 0x208 note: offset is relative to system control base address of 0x400fe000. this register stores the read-only protection bits for each 2-kb flash block ( fmppen stores the execute-only bits). flash memory up to a total of 64 kb is controlled by this register. other fmpren registers (if any) provide protection for other 64k blocks. this register is loaded during the power-on reset sequence. the factory settings for the fmpren and fmppen registers are a value of 1 for all implemented banks. this achieves a policy of open access and programmability. the register bits may be changed by writing the specific register bit. however, this register is r/w0; the user can only change the protection bit from a 1 to a 0 (and may not change a 0 to a 1). the changes are not permanent until the register is committed (saved), at which point the bit change is permanent. if a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. the reset value shown only applies to power-on reset; any other type of reset does not affect this register. once committed, the only way to restore the factory default value of this register is to perform the sequence detailed in recovering a "locked" microcontroller on page 184. if the flash memory size on the device is less than 128 kb, this register usually reads as zeroes, but software should not rely on these bits to be zero. for additional information, see flash memory protection on page 302. flash memory protection read enable 2 (fmpre2) base 0x400f.e000 offset 0x208 type r/w, reset 0xffff.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 read_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 read_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field flash read enable configures 2-kb flash blocks to be read or executed only. the policies may be combined as shown in table 6-1 on page 302. description value bits [31:0] each enable protection on a 2-kb block of flash memory in the range from 129 to 192 kb. 0xffffffff 0xffffffff r/w read_enable 31:0 331 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 21: flash memory protection read enable 3 (fmpre3), offset 0x20c note: offset is relative to system control base address of 0x400fe000. this register stores the read-only protection bits for each 2-kb flash block ( fmppen stores the execute-only bits). flash memory up to a total of 64 kb is controlled by this register. other fmpren registers (if any) provide protection for other 64k blocks. this register is loaded during the power-on reset sequence. the factory settings for the fmpren and fmppen registers are a value of 1 for all implemented banks. this achieves a policy of open access and programmability. the register bits may be changed by writing the specific register bit. however, this register is r/w0; the user can only change the protection bit from a 1 to a 0 (and may not change a 0 to a 1). the changes are not permanent until the register is committed (saved), at which point the bit change is permanent. if a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. the reset value shown only applies to power-on reset; any other type of reset does not affect this register. once committed, the only way to restore the factory default value of this register is to perform the sequence detailed in recovering a "locked" microcontroller on page 184. if the flash memory size on the device is less than 192 kb, this register usually reads as zeroes, but software should not rely on these bits to be zero. for additional information, see flash memory protection on page 302. flash memory protection read enable 3 (fmpre3) base 0x400f.e000 offset 0x20c type r/w, reset 0xffff.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 read_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 read_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field flash read enable configures 2-kb flash blocks to be read or executed only. the policies may be combined as shown in table 6-1 on page 302. description value bits [31:0] each enable protection on a 2-kb block of flash memory in the range from 193 to 256 kb. 0xffffffff 0xffffffff r/w read_enable 31:0 july 03, 2014 332 texas instruments-production data internal memory register 22: flash memory protection read enable 4 (fmpre4), offset 0x210 note: offset is relative to system control base address of 0x400fe000. this register stores the read-only protection bits for each 2-kb flash block ( fmppen stores the execute-only bits). flash memory up to a total of 64 kb is controlled by this register. other fmpren registers (if any) provide protection for other 64k blocks. this register is loaded during the power-on reset sequence. the factory settings for the fmpren and fmppen registers are a value of 1 for all implemented banks. this achieves a policy of open access and programmability. the register bits may be changed by writing the specific register bit. however, this register is r/w0; the user can only change the protection bit from a 1 to a 0 (and may not change a 0 to a 1). the changes are not permanent until the register is committed (saved), at which point the bit change is permanent. if a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. the reset value shown only applies to power-on reset; any other type of reset does not affect this register. once committed, the only way to restore the factory default value of this register is to perform the sequence detailed in recovering a "locked" microcontroller on page 184. if the flash memory size on the device is less than 192 kb, this register usually reads as zeroes, but software should not rely on these bits to be zero. for additional information, see flash memory protection on page 302. flash memory protection read enable 4 (fmpre4) base 0x400f.e000 offset 0x210 type r/w, reset 0xffff.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 read_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 read_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field flash read enable configures 2-kb flash blocks to be read or executed only. the policies may be combined as shown in table 6-1 on page 302. description value bits [31:0] each enable protection on a 2-kb block of flash memory in the range from 257 to 320 kb. 0xffffffff 0xffffffff r/w read_enable 31:0 333 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 23: flash memory protection read enable 5 (fmpre5), offset 0x214 note: offset is relative to system control base address of 0x400fe000. this register stores the read-only protection bits for each 2-kb flash block ( fmppen stores the execute-only bits). flash memory up to a total of 64 kb is controlled by this register. other fmpren registers (if any) provide protection for other 64k blocks. this register is loaded during the power-on reset sequence. the factory settings for the fmpren and fmppen registers are a value of 1 for all implemented banks. this achieves a policy of open access and programmability. the register bits may be changed by writing the specific register bit. however, this register is r/w0; the user can only change the protection bit from a 1 to a 0 (and may not change a 0 to a 1). the changes are not permanent until the register is committed (saved), at which point the bit change is permanent. if a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. the reset value shown only applies to power-on reset; any other type of reset does not affect this register. once committed, the only way to restore the factory default value of this register is to perform the sequence detailed in recovering a "locked" microcontroller on page 184. if the flash memory size on the device is less than 192 kb, this register usually reads as zeroes, but software should not rely on these bits to be zero. for additional information, see flash memory protection on page 302. flash memory protection read enable 5 (fmpre5) base 0x400f.e000 offset 0x214 type r/w, reset 0xffff.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 read_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 read_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field flash read enable configures 2-kb flash blocks to be read or executed only. the policies may be combined as shown in table 6-1 on page 302. description value bits [31:0] each enable protection on a 2-kb block of flash memory in the range from 321 to 384 kb. 0xffffffff 0xffffffff r/w read_enable 31:0 july 03, 2014 334 texas instruments-production data internal memory register 24: flash memory protection read enable 6 (fmpre6), offset 0x218 note: offset is relative to system control base address of 0x400fe000. this register stores the read-only protection bits for each 2-kb flash block ( fmppen stores the execute-only bits). flash memory up to a total of 64 kb is controlled by this register. other fmpren registers (if any) provide protection for other 64k blocks. this register is loaded during the power-on reset sequence. the factory settings for the fmpren and fmppen registers are a value of 1 for all implemented banks. this achieves a policy of open access and programmability. the register bits may be changed by writing the specific register bit. however, this register is r/w0; the user can only change the protection bit from a 1 to a 0 (and may not change a 0 to a 1). the changes are not permanent until the register is committed (saved), at which point the bit change is permanent. if a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. the reset value shown only applies to power-on reset; any other type of reset does not affect this register. once committed, the only way to restore the factory default value of this register is to perform the sequence detailed in recovering a "locked" microcontroller on page 184. if the flash memory size on the device is less than 192 kb, this register usually reads as zeroes, but software should not rely on these bits to be zero. for additional information, see flash memory protection on page 302. flash memory protection read enable 6 (fmpre6) base 0x400f.e000 offset 0x218 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 read_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 read_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field flash read enable configures 2-kb flash blocks to be read or executed only. the policies may be combined as shown in table 6-1 on page 302. description value bits [31:0] each enable protection on a 2-kb block of flash memory in the range from 385 to 448 kb. 0x00000000 0x00000000 r/w read_enable 31:0 335 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 25: flash memory protection read enable 7 (fmpre7), offset 0x21c note: offset is relative to system control base address of 0x400fe000. this register stores the read-only protection bits for each 2-kb flash block ( fmppen stores the execute-only bits). flash memory up to a total of 64 kb is controlled by this register. other fmpren registers (if any) provide protection for other 64k blocks. this register is loaded during the power-on reset sequence. the factory settings for the fmpren and fmppen registers are a value of 1 for all implemented banks. this achieves a policy of open access and programmability. the register bits may be changed by writing the specific register bit. however, this register is r/w0; the user can only change the protection bit from a 1 to a 0 (and may not change a 0 to a 1). the changes are not permanent until the register is committed (saved), at which point the bit change is permanent. if a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. the reset value shown only applies to power-on reset; any other type of reset does not affect this register. once committed, the only way to restore the factory default value of this register is to perform the sequence detailed in recovering a "locked" microcontroller on page 184. if the flash memory size on the device is less than 192 kb, this register usually reads as zeroes, but software should not rely on these bits to be zero. for additional information, see flash memory protection on page 302. flash memory protection read enable 7 (fmpre7) base 0x400f.e000 offset 0x21c type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 read_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 read_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field flash read enable configures 2-kb flash blocks to be read or executed only. the policies may be combined as shown in table 6-1 on page 302. description value bits [31:0] each enable protection on a 2-kb block of flash memory in the range from 449 to 512 kb. 0x00000000 0x00000000 r/w read_enable 31:0 july 03, 2014 336 texas instruments-production data internal memory register 26: flash memory protection program enable 1 (fmppe1), offset 0x404 note: offset is relative to system control base address of 0x400fe000. this register stores the execute-only protection bits for each 2-kb flash block ( fmpren stores the execute-only bits). flash memory up to a total of 64 kb is controlled by this register. other fmppen registers (if any) provide protection for other 64k blocks. this register is loaded during the power-on reset sequence. the factory settings for the fmpren and fmppen registers are a value of 1 for all implemented banks. this achieves a policy of open access and programmability. the register bits may be changed by writing the specific register bit. however, this register is r/w0; the user can only change the protection bit from a 1 to a 0 (and may not change a 0 to a 1). the changes are not permanent until the register is committed (saved), at which point the bit change is permanent. if a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. the reset value shown only applies to power-on reset; any other type of reset does not affect this register. once committed, the only way to restore the factory default value of this register is to perform the sequence detailed in recovering a "locked" microcontroller on page 184. if the flash memory size on the device is less than 64 kb, this register usually reads as zeroes, but software should not rely on these bits to be zero. for additional information, see flash memory protection on page 302. flash memory protection program enable 1 (fmppe1) base 0x400f.e000 offset 0x404 type r/w, reset 0xffff.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 prog_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 prog_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field flash programming enable configures 2-kb flash blocks to be execute only. the policies may be combined as shown in table 6-1 on page 302. description value bits [31:0] each enable protection on a 2-kb block of flash memory in memory range from 65 to 128 kb. 0xffffffff 0xffffffff r/w prog_enable 31:0 337 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 27: flash memory protection program enable 2 (fmppe2), offset 0x408 note: offset is relative to system control base address of 0x400fe000. this register stores the execute-only protection bits for each 2-kb flash block ( fmpren stores the execute-only bits). flash memory up to a total of 64 kb is controlled by this register. other fmppen registers (if any) provide protection for other 64k blocks. this register is loaded during the power-on reset sequence. the factory settings for the fmpren and fmppen registers are a value of 1 for all implemented banks. this achieves a policy of open access and programmability. the register bits may be changed by writing the specific register bit. however, this register is r/w0; the user can only change the protection bit from a 1 to a 0 (and may not change a 0 to a 1). the changes are not permanent until the register is committed (saved), at which point the bit change is permanent. if a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. the reset value shown only applies to power-on reset; any other type of reset does not affect this register. once committed, the only way to restore the factory default value of this register is to perform the sequence detailed in recovering a "locked" microcontroller on page 184. if the flash memory size on the device is less than 128 kb, this register usually reads as zeroes, but software should not rely on these bits to be zero. for additional information, see flash memory protection on page 302. flash memory protection program enable 2 (fmppe2) base 0x400f.e000 offset 0x408 type r/w, reset 0xffff.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 prog_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 prog_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field flash programming enable configures 2-kb flash blocks to be execute only. the policies may be combined as shown in table 6-1 on page 302. description value bits [31:0] each enable protection on a 2-kb block of flash memory in the range from 129 to 192 kb. 0xffffffff 0xffffffff r/w prog_enable 31:0 july 03, 2014 338 texas instruments-production data internal memory register 28: flash memory protection program enable 3 (fmppe3), offset 0x40c note: offset is relative to system control base address of 0x400fe000. this register stores the execute-only protection bits for each 2-kb flash block ( fmpren stores the execute-only bits). flash memory up to a total of 64 kb is controlled by this register. other fmppen registers (if any) provide protection for other 64k blocks. this register is loaded during the power-on reset sequence. the factory settings for the fmpren and fmppen registers are a value of 1 for all implemented banks. this achieves a policy of open access and programmability. the register bits may be changed by writing the specific register bit. however, this register is r/w0; the user can only change the protection bit from a 1 to a 0 (and may not change a 0 to a 1). the changes are not permanent until the register is committed (saved), at which point the bit change is permanent. if a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. the reset value shown only applies to power-on reset; any other type of reset does not affect this register. once committed, the only way to restore the factory default value of this register is to perform the sequence detailed in recovering a "locked" microcontroller on page 184. if the flash memory size on the device is less than 192 kb, this register usually reads as zeroes, but software should not rely on these bits to be zero. for additional information, see flash memory protection on page 302. flash memory protection program enable 3 (fmppe3) base 0x400f.e000 offset 0x40c type r/w, reset 0xffff.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 prog_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 prog_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field flash programming enable configures 2-kb flash blocks to be execute only. the policies may be combined as shown in table 6-1 on page 302. description value bits [31:0] each enable protection on a 2-kb block of flash memory in the range from 193 to 256 kb. 0xffffffff 0xffffffff r/w prog_enable 31:0 339 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 29: flash memory protection program enable 4 (fmppe4), offset 0x410 note: offset is relative to system control base address of 0x400fe000. this register stores the execute-only protection bits for each 2-kb flash block ( fmpren stores the execute-only bits). flash memory up to a total of 64 kb is controlled by this register. other fmppen registers (if any) provide protection for other 64k blocks. this register is loaded during the power-on reset sequence. the factory settings for the fmpren and fmppen registers are a value of 1 for all implemented banks. this achieves a policy of open access and programmability. the register bits may be changed by writing the specific register bit. however, this register is r/w0; the user can only change the protection bit from a 1 to a 0 (and may not change a 0 to a 1). the changes are not permanent until the register is committed (saved), at which point the bit change is permanent. if a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. the reset value shown only applies to power-on reset; any other type of reset does not affect this register. once committed, the only way to restore the factory default value of this register is to perform the sequence detailed in recovering a "locked" microcontroller on page 184. if the flash memory size on the device is less than 192 kb, this register usually reads as zeroes, but software should not rely on these bits to be zero. for additional information, see flash memory protection on page 302. flash memory protection program enable 4 (fmppe4) base 0x400f.e000 offset 0x410 type r/w, reset 0xffff.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 prog_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 prog_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field flash programming enable configures 2-kb flash blocks to be execute only. the policies may be combined as shown in table 6-1 on page 302. description value bits [31:0] each enable protection on a 2-kb block of flash memory in the range from 257 to 320 kb. 0xffffffff 0xffffffff r/w prog_enable 31:0 july 03, 2014 340 texas instruments-production data internal memory register 30: flash memory protection program enable 5 (fmppe5), offset 0x414 note: offset is relative to system control base address of 0x400fe000. this register stores the execute-only protection bits for each 2-kb flash block ( fmpren stores the execute-only bits). flash memory up to a total of 64 kb is controlled by this register. other fmppen registers (if any) provide protection for other 64k blocks. this register is loaded during the power-on reset sequence. the factory settings for the fmpren and fmppen registers are a value of 1 for all implemented banks. this achieves a policy of open access and programmability. the register bits may be changed by writing the specific register bit. however, this register is r/w0; the user can only change the protection bit from a 1 to a 0 (and may not change a 0 to a 1). the changes are not permanent until the register is committed (saved), at which point the bit change is permanent. if a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. the reset value shown only applies to power-on reset; any other type of reset does not affect this register. once committed, the only way to restore the factory default value of this register is to perform the sequence detailed in recovering a "locked" microcontroller on page 184. if the flash memory size on the device is less than 192 kb, this register usually reads as zeroes, but software should not rely on these bits to be zero. for additional information, see flash memory protection on page 302. flash memory protection program enable 5 (fmppe5) base 0x400f.e000 offset 0x414 type r/w, reset 0xffff.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 prog_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 prog_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field flash programming enable configures 2-kb flash blocks to be execute only. the policies may be combined as shown in table 6-1 on page 302. description value bits [31:0] each enable protection on a 2-kb block of flash memory in the range from 321 to 384 kb. 0xffffffff 0xffffffff r/w prog_enable 31:0 341 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 31: flash memory protection program enable 6 (fmppe6), offset 0x418 note: offset is relative to system control base address of 0x400fe000. this register stores the execute-only protection bits for each 2-kb flash block ( fmpren stores the execute-only bits). flash memory up to a total of 64 kb is controlled by this register. other fmppen registers (if any) provide protection for other 64k blocks. this register is loaded during the power-on reset sequence. the factory settings for the fmpren and fmppen registers are a value of 1 for all implemented banks. this achieves a policy of open access and programmability. the register bits may be changed by writing the specific register bit. however, this register is r/w0; the user can only change the protection bit from a 1 to a 0 (and may not change a 0 to a 1). the changes are not permanent until the register is committed (saved), at which point the bit change is permanent. if a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. the reset value shown only applies to power-on reset; any other type of reset does not affect this register. once committed, the only way to restore the factory default value of this register is to perform the sequence detailed in recovering a "locked" microcontroller on page 184. if the flash memory size on the device is less than 192 kb, this register usually reads as zeroes, but software should not rely on these bits to be zero. for additional information, see flash memory protection on page 302. flash memory protection program enable 6 (fmppe6) base 0x400f.e000 offset 0x418 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 prog_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 prog_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field flash programming enable configures 2-kb flash blocks to be execute only. the policies may be combined as shown in table 6-1 on page 302. description value bits [31:0] each enable protection on a 2-kb block of flash memory in the range from 385 to 448 kb. 0x00000000 0x00000000 r/w prog_enable 31:0 july 03, 2014 342 texas instruments-production data internal memory register 32: flash memory protection program enable 7 (fmppe7), offset 0x41c note: offset is relative to system control base address of 0x400fe000. this register stores the execute-only protection bits for each 2-kb flash block ( fmpren stores the execute-only bits). flash memory up to a total of 64 kb is controlled by this register. other fmppen registers (if any) provide protection for other 64k blocks. this register is loaded during the power-on reset sequence. the factory settings for the fmpren and fmppen registers are a value of 1 for all implemented banks. this achieves a policy of open access and programmability. the register bits may be changed by writing the specific register bit. however, this register is r/w0; the user can only change the protection bit from a 1 to a 0 (and may not change a 0 to a 1). the changes are not permanent until the register is committed (saved), at which point the bit change is permanent. if a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. the reset value shown only applies to power-on reset; any other type of reset does not affect this register. once committed, the only way to restore the factory default value of this register is to perform the sequence detailed in recovering a "locked" microcontroller on page 184. if the flash memory size on the device is less than 192 kb, this register usually reads as zeroes, but software should not rely on these bits to be zero. for additional information, see flash memory protection on page 302. flash memory protection program enable 7 (fmppe7) base 0x400f.e000 offset 0x41c type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 prog_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 prog_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field flash programming enable configures 2-kb flash blocks to be execute only. the policies may be combined as shown in table 6-1 on page 302. description value bits [31:0] each enable protection on a 2-kb block of flash memory in the range from 449 to 512 kb. 0x00000000 0x00000000 r/w prog_enable 31:0 343 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 7 micro direct memory access (dma) the lm3s9gn5 microcontroller includes a direct memory access (dma) controller, known as micro-dma (dma). the dma controller provides a way to offload data transfer tasks from the cortex ? -m3 processor, allowing for more efficient use of the processor and the available bus bandwidth. the dma controller can perform transfers between memory and peripherals. it has dedicated channels for each supported on-chip module and can be programmed to automatically perform transfers between peripherals and memory as the peripheral is ready to transfer more data. the dma controller provides the following features: arm ? primecell ? 32-channel configurable dma controller support for memory-to-memory, memory-to-peripheral, and peripheral-to-memory in multiple transfer modes C basic for simple transfer scenarios C ping-pong for continuous data flow C scatter-gather for a programmable list of up to 256 arbitrary transfers initiated from a single request highly flexible and configurable channel operation C independently configured and operated channels C dedicated channels for supported on-chip modules C primary and secondary channel assignments C one channel each for receive and transmit path for bidirectional modules C dedicated channel for software-initiated transfers C per-channel configurable priority scheme C optional software-initiated requests for any channel two levels of priority design optimizations for improved bus access performance between dma controller and the processor core C dma controller access is subordinate to core access C ram striping C peripheral bus segmentation data sizes of 8, 16, and 32 bits transfer size is programmable in binary steps from 1 to 1024 source and destination address increment size of byte, half-word, word, or no increment july 03, 2014 344 texas instruments-production data micro direct memory access (dma) maskable peripheral requests interrupt on transfer completion, with a separate interrupt per channel 7.1 block diagram figure 7-1. dma block diagram 7.2 functional description the dma controller is a flexible and highly configurable dma controller designed to work efficiently with the microcontroller's cortex-m3 processor core. it supports multiple data sizes and address increment schemes, multiple levels of priority among dma channels, and several transfer modes to allow for sophisticated programmed data transfers. the dma controller's usage of the bus is always subordinate to the processor core, so it never holds up a bus transaction by the processor. because the dma controller is only using otherwise-idle bus cycles, the data transfer bandwidth it provides is essentially free, with no impact on the rest of the system. the bus architecture has been optimized to greatly enhance the ability of the processor core and the dma controller to efficiently share the on-chip bus, thus improving performance. the optimizations include ram striping and peripheral bus segmentation, which in many cases allow both the processor core and the dma controller to access the bus and perform simultaneous data transfers. the dma controller can transfer data to and from the on-chip sram. however, because the flash memory and rom are located on a separate internal bus, it is not possible to transfer data from the flash memory or rom with the dma controller. each peripheral function that is supported has a dedicated channel on the dma controller that can be configured independently. the dma controller implements a unique configuration method using channel control structures that are maintained in system memory by the processor. while simple transfer modes are supported, it is also possible to build up sophisticated "task" lists in memory that allow the dma controller to perform arbitrary-sized transfers to and from arbitrary locations as part of a single transfer request. the dma controller also supports the use of ping-pong buffering to accommodate constant streaming of data to or from a peripheral. 345 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 6 \ v w h p 0 h p r u \ & + & r q w u r o 7 d e o h 7 u d q v i h u % x i i h u v 8 v h g e \ ? ' 0 $ x ' 0 $ & r q w u r o o h u ? ? ? ' 0 $ 6 5 & ( 1 ' 3 ' 0 $ ' 6 7 ( 1 ' 3 ' 0 $ & + & 7 5 / ' 0 $ 6 5 & ( 1 ' 3 ' 0 $ ' 6 7 ( 1 ' 3 ' 0 $ & + & 7 5 / ' 0 $ h u u r u 3 h u l s k h u d o ' 0 $ & k d q q h o 3 h u l s k h u d o ' 0 $ & k d q q h o 1 ? ? ? ' 0 $ 6 7 $ 7 ' 0 $ & ) * ' 0 $ & 7 / % $ 6 ( ' 0 $ $ / 7 % $ 6 ( ' 0 $ : $ , 7 6 7 $ 7 ' 0 $ 6 : 5 ( 4 ' 0 $ 8 6 ( % 8 5 6 7 6 ( 7 ' 0 $ 8 6 ( % 8 5 6 7 & / 5 ' 0 $ 5 ( 4 0 $ 6 . 6 ( 7 ' 0 $ 5 ( 4 0 $ 6 . & / 5 ' 0 $ ( 1 $ 6 ( 7 ' 0 $ ( 1 $ & / 5 ' 0 $ $ / 7 6 ( 7 ' 0 $ $ / 7 & / 5 ' 0 $ 3 5 , 2 6 ( 7 ' 0 $ 3 5 , 2 & / 5 ' 0 $ ( 5 5 & / 5 u h t x h v w g r q h u h t x h v w g r q h * h q h u d o 3 h u l s k h u d o 1 5 h j l v w h u v 1 h v w h g 9 h f w r u h g , q w h u u x s w & r q w u r o o h u 1 9 , & $ 5 0 & r u w h [ 0 , 5 4 u h t x h v w g r q h ' 0 $ & + $ 6 * 1 ' 0 $ & + , 6 each channel also has a configurable arbitration size. the arbitration size is the number of items that are transferred in a burst before the dma controller rearbitrates for channel priority. using the arbitration size, it is possible to control exactly how many items are transferred to or from a peripheral each time it makes a dma service request. 7.2.1 channel assignments dma channels 0-31 are assigned to peripherals according to the following table. the dma channel assignment (dmachasgn) register (see page 394) can be used to specify the primary or secondary assignment. if the primary function is not available on this microcontroller, the secondary function becomes the primary function. if the secondary function is not available, the primary function is the only option. note: channels noted in the table as "available for software" may be assigned to peripherals in the future. however, they are currently available for software use. channel 30 is dedicated for software use. the usb endpoints mapped to dma channels 0-3 can be changed with the usbdmasel register (see page 1094). because of the way the dma controller interacts with peripherals, the dma channel for the peripheral must be enabled in order for the dma controller to be able to read and write the peripheral registers, even if a different dma channel is used to perform the dma transfer. to minimize confusion and chance of software errors, it is best practice to use a peripheral's dma channel for performing all dma transfers for that peripheral, even if it is processor-triggered and using auto mode, which could be considered a software transfer. note that if the software channel is used, interrupts occur on the dedicated dma interrupt vector. if the peripheral channel is used, then the interrupt occurs on the interrupt vector for the peripheral. table 7-1. dma channel assignments secondary assignment primary assignment dma channel uart2 receive usb endpoint 1 receive 0 uart2 transmit usb endpoint 1 transmit 1 general-purpose timer 3a usb endpoint 2 receive 2 general-purpose timer 3b usb endpoint 2 transmit 3 general-purpose timer 2a usb endpoint 3 receive 4 general-purpose timer 2b usb endpoint 3 transmit 5 general-purpose timer 2a ethernet receive 6 general-purpose timer 2b ethernet transmit 7 uart1 receive uart0 receive 8 uart1 transmit uart0 transmit 9 ssi1 receive ssi0 receive 10 ssi1 transmit ssi0 transmit 11 uart2 receive available for software 12 uart2 transmit available for software 13 general-purpose timer 2a adc0 sample sequencer 0 14 general-purpose timer 2b adc0 sample sequencer 1 15 available for software adc0 sample sequencer 2 16 available for software adc0 sample sequencer 3 17 july 03, 2014 346 texas instruments-production data micro direct memory access (dma) table 7-1. dma channel assignments (continued) secondary assignment primary assignment dma channel general-purpose timer 1a general-purpose timer 0a 18 general-purpose timer 1b general-purpose timer 0b 19 epi0 nbrfifo general-purpose timer 1a 20 epi0 wfifo general-purpose timer 1b 21 available for software uart1 receive 22 available for software uart1 transmit 23 adc1 sample sequencer 0 ssi1 receive 24 adc1 sample sequencer 1 ssi1 transmit 25 adc1 sample sequencer 2 available for software 26 adc1 sample sequencer 3 available for software 27 available for software i 2 s0 receive 28 available for software i 2 s0 transmit 29 dedicated for software use 30 reserved 31 7.2.2 priority the dma controller assigns priority to each channel based on the channel number and the priority level bit for the channel. channel number 0 has the highest priority and as the channel number increases, the priority of a channel decreases. each channel has a priority level bit to provide two levels of priority: default priority and high priority. if the priority level bit is set, then that channel has higher priority than all other channels at default priority. if multiple channels are set for high priority, then the channel number is used to determine relative priority among all the high priority channels. the priority bit for a channel can be set using the dma channel priority set (dmaprioset) register and cleared with the dma channel priority clear (dmaprioclr) register. 7.2.3 arbitration size when a dma channel requests a transfer, the dma controller arbitrates among all the channels making a request and services the dma channel with the highest priority. once a transfer begins, it continues for a selectable number of transfers before rearbitrating among the requesting channels again. the arbitration size can be configured for each channel, ranging from 1 to 1024 item transfers. after the dma controller transfers the number of items specified by the arbitration size, it then checks among all the channels making a request and services the channel with the highest priority. if a lower priority dma channel uses a large arbitration size, the latency for higher priority channels is increased because the dma controller completes the lower priority burst before checking for higher priority requests. therefore, lower priority channels should not use a large arbitration size for best response on high priority channels. the arbitration size can also be thought of as a burst size. it is the maximum number of items that are transferred at any one time in a burst. here, the term arbitration refers to determination of dma channel priority, not arbitration for the bus. when the dma controller arbitrates for the bus, the processor always takes priority. furthermore, the dma controller is held off whenever the processor must perform a bus transaction on the same bus, even in the middle of a burst transfer. 347 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 7.2.4 request types the dma controller responds to two types of requests from a peripheral: single or burst. each peripheral may support either or both types of requests. a single request means that the peripheral is ready to transfer one item, while a burst request means that the peripheral is ready to transfer multiple items. the dma controller responds differently depending on whether the peripheral is making a single request or a burst request. if both are asserted, and the dma channel has been set up for a burst transfer, then the burst request takes precedence. see table 7-2 on page 348, which shows how each peripheral supports the two request types. table 7-2. request type support burst request signal single request signal peripheral sequencer ie bit none adc wfifo level (configurable) none epi wfifo nbrfifo level (configurable) none epi nbrfifo none tx fifo empty ethernet tx none rx packet received ethernet rx trigger event none general-purpose timer fifo service request none i 2 s tx fifo service request none i 2 s rx tx fifo level (fixed at 4) tx fifo not full ssi tx rx fifo level (fixed at 4) rx fifo not empty ssi rx tx fifo level (configurable) tx fifo not full uart tx rx fifo level (configurable) rx fifo not empty uart rx fifo txrdy none usb tx fifo rxrdy none usb rx 7.2.4.1 single request when a single request is detected, and not a burst request, the dma controller transfers one item and then stops to wait for another request. 7.2.4.2 burst request when a burst request is detected, the dma controller transfers the number of items that is the lesser of the arbitration size or the number of items remaining in the transfer. therefore, the arbitration size should be the same as the number of data items that the peripheral can accommodate when making a burst request. for example, the uart generates a burst request based on the fifo trigger level. in this case, the arbitration size should be set to the amount of data that the fifo can transfer when the trigger level is reached. a burst transfer runs to completion once it is started, and cannot be interrupted, even by a higher priority channel. burst transfers complete in a shorter time than the same number of non-burst transfers. it may be desirable to use only burst transfers and not allow single transfers. for example, perhaps the nature of the data is such that it only makes sense when transferred together as a single unit rather than one piece at a time. the single request can be disabled by using the dma channel useburst set (dmauseburstset) register. by setting the bit for a channel in this register, the dma controller only responds to burst requests for that channel. july 03, 2014 348 texas instruments-production data micro direct memory access (dma) 7.2.5 channel configuration the dma controller uses an area of system memory to store a set of channel control structures in a table. the control table may have one or two entries for each dma channel. each entry in the table structure contains source and destination pointers, transfer size, and transfer mode. the control table can be located anywhere in system memory, but it must be contiguous and aligned on a 1024-byte boundary. table 7-3 on page 349 shows the layout in memory of the channel control table. each channel may have one or two control structures in the control table: a primary control structure and an optional alternate control structure. the table is organized so that all of the primary entries are in the first half of the table, and all the alternate structures are in the second half of the table. the primary entry is used for simple transfer modes where transfers can be reconfigured and restarted after each transfer is complete. in this case, the alternate control structures are not used and therefore only the first half of the table must be allocated in memory; the second half of the control table is not necessary, and that memory can be used for something else. if a more complex transfer mode is used such as ping-pong or scatter-gather, then the alternate control structure is also used and memory space should be allocated for the entire table. any unused memory in the control table may be used by the application. this includes the control structures for any channels that are unused by the application as well as the unused control word for each channel. table 7-3. control structure memory map channel offset 0, primary 0x0 1, primary 0x10 ... ... 31, primary 0x1f0 0, alternate 0x200 1, alternate 0x210 ... ... 31, alternate 0x3f0 table 7-4 shows an individual control structure entry in the control table. each entry is aligned on a 16-byte boundary. the entry contains four long words: the source end pointer, the destination end pointer, the control word, and an unused entry. the end pointers point to the ending address of the transfer and are inclusive. if the source or destination is non-incrementing (as for a peripheral register), then the pointer should point to the transfer address. table 7-4. channel control structure description offset source end pointer 0x000 destination end pointer 0x004 control word 0x008 unused 0x00c the control word contains the following fields: source and destination data sizes 349 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller source and destination address increment size number of transfers before bus arbitration total number of items to transfer useburst flag transfer mode the control word and each field are described in detail in dma channel control structure on page 368. the dma controller updates the transfer size and transfer mode fields as the transfer is performed. at the end of a transfer, the transfer size indicates 0, and the transfer mode indicates "stopped." because the control word is modified by the dma controller, it must be reconfigured before each new transfer. the source and destination end pointers are not modified, so they can be left unchanged if the source or destination addresses remain the same. prior to starting a transfer, a dma channel must be enabled by setting the appropriate bit in the dma channel enable set (dmaenaset) register. a channel can be disabled by setting the channel bit in the dma channel enable clear (dmaenaclr) register. at the end of a complete dma transfer, the controller automatically disables the channel. 7.2.6 transfer modes the dma controller supports several transfer modes. two of the modes support simple one-time transfers. several complex modes support a continuous flow of data. 7.2.6.1 stop mode while stop is not actually a transfer mode, it is a valid value for the mode field of the control word. when the mode field has this value, the dma controller does not perform any transfers and disables the channel if it is enabled. at the end of a transfer, the dma controller updates the control word to set the mode to stop. 7.2.6.2 basic mode in basic mode, the dma controller performs transfers as long as there are more items to transfer, and a transfer request is present. this mode is used with peripherals that assert a dma request signal whenever the peripheral is ready for a data transfer. basic mode should not be used in any situation where the request is momentary even though the entire transfer should be completed. for example, a software-initiated transfer creates a momentary request, and in basic mode, only the number of transfers specified by the arbsize field in the dma channel control word (dmachctl) register is transferred on a software request, even if there is more data to transfer. when all of the items have been transferred using basic mode, the dma controller sets the mode for that channel to stop. 7.2.6.3 auto mode auto mode is similar to basic mode, except that once a transfer request is received, the transfer runs to completion, even if the dma request is removed. this mode is suitable for software-triggered transfers. generally, auto mode is not used with a peripheral. when all the items have been transferred using auto mode, the dma controller sets the mode for that channel to stop. july 03, 2014 350 texas instruments-production data micro direct memory access (dma) 7.2.6.4 ping-pong ping-pong mode is used to support a continuous data flow to or from a peripheral. to use ping-pong mode, both the primary and alternate data structures must be implemented. both structures are set up by the processor for data transfer between memory and a peripheral. the transfer is started using the primary control structure. when the transfer using the primary control structure is complete, the dma controller reads the alternate control structure for that channel to continue the transfer. each time this happens, an interrupt is generated, and the processor can reload the control structure for the just-completed transfer. data flow can continue indefinitely this way, using the primary and alternate control structures to switch back and forth between buffers as the data flows to or from the peripheral. refer to figure 7-2 on page 352 for an example showing operation in ping-pong mode. 351 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller figure 7-2. example of ping-pong dma transaction 7.2.6.5 memory scatter-gather memory scatter-gather mode is a complex mode used when data must be transferred to or from varied locations in memory instead of a set of contiguous locations in a memory buffer. for example, a gather dma operation could be used to selectively read the payload of several stored packets of a communication protocol and store them together in sequence in a memory buffer. july 03, 2014 352 texas instruments-production data micro direct memory access (dma) $ o w h u q d w h 6 w u x f w x u h 3 u l p d u \ 6 w u x f w x u h 3 u l p d u \ 6 w u x f w x u h $ o w h u q d w h 6 w u x f w x u h w u d q v i h u f r q w l q x h v x v l q j d o w h u q d w h % 8 ) ) ( 5 % % 8 ) ) ( 5 $ process data in buffer a reload primary structure transfers using buffer a buffer a transfers using buffer a transfers using buffer b transfer continues using alternate transfer continues using primary buffer b transfers using buffer b peripheral/ dma interrupt process data in buffer b reload alternate structure process data in buffer b reload alternate structure dma controller cortex-m3 processor t ime peripheral/ dma interrupt peripheral/ dma interrupt source dest control unused source dest control unused source dest control unused source dest control unused in memory scatter-gather mode, the primary control structure is used to program the alternate control structure from a table in memory. the table is set up by the processor software and contains a list of control structures, each containing the source and destination end pointers, and the control word for a specific transfer. the mode of each control word must be set to scatter-gather mode. each entry in the table is copied in turn to the alternate structure where it is then executed. the dma controller alternates between using the primary control structure to copy the next transfer instruction from the list and then executing the new transfer instruction. the end of the list is marked by programming the control word for the last entry to use auto transfer mode. once the last transfer is performed using auto mode, the dma controller stops. a completion interrupt is generated only after the last transfer. it is possible to loop the list by having the last entry copy the primary control structure to point back to the beginning of the list (or to a new list). it is also possible to trigger a set of other channels to perform a transfer, either directly, by programming a write to the software trigger for another channel, or indirectly, by causing a peripheral action that results in a dma request. by programming the dma controller using this method, a set of up to 256 arbitrary transfers can be performed based on a single dma request. refer to figure 7-3 on page 354 and figure 7-4 on page 355, which show an example of operation in memory scatter-gather mode. this example shows a gather operation, where data in three separate buffers in memory is copied together into one buffer. figure 7-3 on page 354 shows how the application sets up a dma task list in memory that is used by the controller to perform three sets of copy operations from different locations in memory. the primary control structure for the channel that is used for the operation is configured to copy from the task list to the alternate control structure. figure 7-4 on page 355 shows the sequence as the dma controller performs the three sets of copy operations. first, using the primary control structure, the dma controller loads the alternate control structure with task a. it then performs the copy operation specified by task a, copying the data from the source buffer a to the destination buffer. next, the dma controller again uses the primary control structure to load task b into the alternate control structure, and then performs the b operation with the alternate control structure. the process is repeated for task c. 353 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller figure 7-3. memory scatter-gather, setup and configuration july 03, 2014 354 texas instruments-production data micro direct memory access (dma) 1 2 7 ( 6 $ s s o l f d w l r q k d v d q h h g w r f r s \ g d w d l w h p v i u r p w k u h h v h s d u d w h o r f d w l r q v l q p h p r u \ l q w r r q h f r p e l q h g e x i i h u $ s s o l f d w l r q v h w v x s ? ' 0 $ 3 w d v n o l v w l q p h p r u \ z k l f k f r q w d l q v w k h s r l q w h u v d q g f r q w u r o f r q i l j x u d w l r q i r u w k u h h ? ' 0 $ f r s \ 3 w d v n v $ s s o l f d w l r q v h w v x s w k h f k d q q h o s u l p d u \ f r q w u r o v w u x f w x u h w r f r s \ h d f k w d v n f r q i l j x u d w l r q r q h d w d w l p h w r w k h d o w h u q d w h f r q w u r o v w u x f w x u h z k h u h l w l v h [ h f x w h g e \ w k h ? ' 0 $ f r q w u r o o h u 7 k h 6 5 & d q g ' 6 7 s r l q w h u v l q w k h w d v n o l v w p x v w s r l q w w r w k h o d v w o r f d w l r q l q w k h f r u u h v s r q g l q j e x i i h u & : 2 5 ' 6 6 5 & $ : 2 5 ' 6 6 5 & % 6 5 & ' 6 7 , 7 ( 0 6 8 q x v h g 6 5 & ' 6 7 , 7 ( 0 6 : 2 5 ' 6 5 & & ' ( 6 7 $ ' ( 6 7 % ' ( 6 7 & ' 6 7 $ % 3 7 $ 6 . $ 3 7 $ 6 . % 3 7 $ 6 . & 6 5 & ' 6 7 , 7 ( 0 6 6 5 & ' 6 7 , 7 ( 0 6 q 7 d v n / l v w l q 0 h p r u \ 6 r x u f h d q g ' h v w l q d w l r q % x i i h u l q 0 h p r u \ & k d q q h o & r q w u r o 7 d e o h l q 0 h p r u \ & k d q q h o 3 u l p d u \ & r q w u r o 6 w u x f w x u h & k d q q h o $ o w h u q d w h & r q w u r o 6 w u x f w x u h 8 q x v h g , 7 ( 0 6 6 5 & 8 q x v h g figure 7-4. memory scatter-gather, dma copy sequence 355 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 6 5 & ' 6 7 & 2 3 , ( ' 6 5 & ' 6 7 & 2 3 , ( ' 3 5 , $ / 7 6 5 & ' 6 7 & 2 3 , ( ' 6 5 & ' 6 7 & 2 3 , ( ' 6 5 & ' 6 7 & 2 3 , ( ' 6 5 & ' 6 7 & 2 3 , ( ' 7 d v n / l v w l q 0 h p r u \ ? ' 0 $ & r q w u r o 7 d e o h l q 0 h p r u \ % x i i h u v l q 0 h p r u \ 7 $ 6 . % 7 $ 6 . & 3 5 , $ / 7 6 5 & % 6 5 & & ' ( 6 7 % ' ( 6 7 & 8 v l q j w k h f k d q q h o ? v s u l p d u \ f r q w u r o v w u x f w x u h w k h ? ' 0 $ f r q w u r o o h u f r s l h v w d v n $ f r q i l j x u d w l r q w r w k h f k d q q h o ? v d o w h u q d w h f r q w u r o v w u x f w x u h 7 k h q x v l q j w k h f k d q q h o ? v d o w h u q d w h f r q w u r o v w u x f w x u h w k h ? ' 0 $ f r q w u r o o h u f r s l h v g d w d i u r p w k h v r x u f h e x i i h u $ w r w k h g h v w l q d w l r q e x i i h u 7 d v n / l v w l q 0 h p r u \ ? ' 0 $ & r q w u r o 7 d e o h l q 0 h p r u \ % x i i h u v l q 0 h p r u \ 8 v l q j w k h f k d q q h o ? v s u l p d u \ f r q w u r o v w u x f w x u h w k h ? ' 0 $ f r q w u r o o h u f r s l h v w d v n % f r q i l j x u d w l r q w r w k h f k d q q h o ? v d o w h u q d w h f r q w u r o v w u x f w x u h 7 k h q x v l q j w k h f k d q q h o ? v d o w h u q d w h f r q w u r o v w u x f w x u h w k h ? ' 0 $ f r q w u r o o h u f r s l h v g d w d i u r p w k h v r x u f h e x i i h u % w r w k h g h v w l q d w l r q e x i i h u ? ' 0 $ & r q w u r o 7 d e o h l q 0 h p r u \ % x i i h u v l q 0 h p r u \ 8 v l q j w k h f k d q q h o ? v s u l p d u \ f r q w u r o v w u x f w x u h w k h ? ' 0 $ f r q w u r o o h u f r s l h v w d v n & f r q i l j x u d w l r q w r w k h f k d q q h o ? v d o w h u q d w h f r q w u r o v w u x f w x u h 7 k h q x v l q j w k h f k d q q h o ? v d o w h u q d w h f r q w u r o v w u x f w x u h w k h ? ' 0 $ f r q w u r o o h u f r s l h v g d w d i u r p w k h v r x u f h e x i i h u & w r w k h g h v w l q d w l r q e x i i h u 3 5 , $ / 7 7 d v n / l v w l q 0 h p r u \ 7 $ 6 . $ 7 $ 6 . % 7 $ 6 . $ 7 $ 6 . & 6 5 & $ 6 5 & & ' ( 6 7 $ ' ( 6 7 & 6 5 & $ 6 5 & % ' ( 6 7 $ ' ( 6 7 % 7 $ 6 . $ 7 $ 6 . % 6 5 & $ 7 $ 6 . & 6 5 & & ' ( 6 7 & 6 5 & % ' ( 6 7 % ' ( 6 7 $ 7.2.6.6 peripheral scatter-gather peripheral scatter-gather mode is very similar to memory scatter-gather, except that the transfers are controlled by a peripheral making a dma request. upon detecting a request from the peripheral, the dma controller uses the primary control structure to copy one entry from the list to the alternate control structure and then performs the transfer. at the end of this transfer, the next transfer is started only if the peripheral again asserts a dma request. the dma controller continues to perform transfers from the list only when the peripheral is making a request, until the last transfer is complete. a completion interrupt is generated only after the last transfer. by using this method, the dma controller can transfer data to or from a peripheral from a set of arbitrary locations whenever the peripheral is ready to transfer data. refer to figure 7-5 on page 357 and figure 7-6 on page 358, which show an example of operation in peripheral scatter-gather mode. this example shows a gather operation, where data from three separate buffers in memory is copied to a single peripheral data register. figure 7-5 on page 357 shows how the application sets up a dma task list in memory that is used by the controller to perform three sets of copy operations from different locations in memory. the primary control structure for the channel that is used for the operation is configured to copy from the task list to the alternate control structure. figure 7-6 on page 358 shows the sequence as the dma controller performs the three sets of copy operations. first, using the primary control structure, the dma controller loads the alternate control structure with task a. it then performs the copy operation specified by task a, copying the data from the source buffer a to the peripheral data register. next, the dma controller again uses the primary control structure to load task b into the alternate control structure, and then performs the b operation with the alternate control structure. the process is repeated for task c. july 03, 2014 356 texas instruments-production data micro direct memory access (dma) figure 7-5. peripheral scatter-gather, setup and configuration 357 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller & : 2 5 ' 6 6 5 & $ : 2 5 ' 6 6 5 & % : 2 5 ' 6 5 & & $ % 6 5 & ' 6 7 , 7 ( 0 6 6 5 & ' 6 7 , 7 ( 0 6 q 7 d v n / l v w l q 0 h p r u \ 6 r x u f h % x i i h u l q 0 h p r u \ & k d q q h o & r q w u r o 7 d e o h l q 0 h p r u \ & k d q q h o 3 u l p d u \ & r q w u r o 6 w u x f w x u h & k d q q h o $ o w h u q d w h & r q w u r o 6 w u x f w x u h ' ( 6 7 3 h u l s k h u d o ' d w d 5 h j l v w h u 6 5 & ' 6 7 , 7 ( 0 6 8 q x v h g 6 5 & ' 6 7 , 7 ( 0 6 ' 6 7 3 7 $ 6 . $ 3 7 $ 6 . % 3 7 $ 6 . & 8 q x v h g , 7 ( 0 6 6 5 & 8 q x v h g 1 2 7 ( 6 $ s s o l f d w l r q k d v d q h h g w r f r s \ g d w d l w h p v i u r p w k u h h v h s d u d w h o r f d w l r q v l q p h p r u \ l q w r d s h u l s k h u d o g d w d u h j l v w h u $ s s o l f d w l r q v h w v x s ? ' 0 $ 3 w d v n o l v w l q p h p r u \ z k l f k f r q w d l q v w k h s r l q w h u v d q g f r q w u r o f r q i l j x u d w l r q i r u w k u h h ? ' 0 $ f r s \ 3 w d v n v $ s s o l f d w l r q v h w v x s w k h f k d q q h o s u l p d u \ f r q w u r o v w u x f w x u h w r f r s \ h d f k w d v n f r q i l j x u d w l r q r q h d w d w l p h w r w k h d o w h u q d w h f r q w u r o v w u x f w x u h z k h u h l w l v h [ h f x w h g e \ w k h ? ' 0 $ f r q w u r o o h u figure 7-6. peripheral scatter-gather, dma copy sequence july 03, 2014 358 texas instruments-production data micro direct memory access (dma) 6 5 & & 7 $ 6 . $ 6 5 & ' 6 7 & 2 3 , ( ' 6 5 & ' 6 7 & 2 3 , ( ' 3 5 , $ / 7 6 5 & ' 6 7 & 2 3 , ( ' 6 5 & ' 6 7 & 2 3 , ( ' 6 5 & ' 6 7 & 2 3 , ( ' 6 5 & ' 6 7 & 2 3 , ( ' 7 d v n / l v w l q 0 h p r u \ ? ' 0 $ & r q w u r o 7 d e o h l q 0 h p r u \ % x i i h u v l q 0 h p r u \ 7 $ 6 . % 7 $ 6 . & 3 5 , $ / 7 8 v l q j w k h f k d q q h o ? v s u l p d u \ f r q w u r o v w u x f w x u h w k h ? ' 0 $ f r q w u r o o h u f r s l h v w d v n $ f r q i l j x u d w l r q w r w k h f k d q q h o ? v d o w h u q d w h f r q w u r o v w u x f w x u h 7 k h q x v l q j w k h f k d q q h o ? v d o w h u q d w h f r q w u r o v w u x f w x u h w k h ? ' 0 $ f r q w u r o o h u f r s l h v g d w d i u r p w k h v r x u f h e x i i h u $ w r w k h s h u l s k h u d o g d w d u h j l v w h u 7 d v n / l v w l q 0 h p r u \ ? ' 0 $ & r q w u r o 7 d e o h l q 0 h p r u \ % x i i h u v l q 0 h p r u \ 8 v l q j w k h f k d q q h o ? v s u l p d u \ f r q w u r o v w u x f w x u h w k h ? ' 0 $ f r q w u r o o h u f r s l h v w d v n % f r q i l j x u d w l r q w r w k h f k d q q h o ? v d o w h u q d w h f r q w u r o v w u x f w x u h 7 k h q x v l q j w k h f k d q q h o ? v d o w h u q d w h f r q w u r o v w u x f w x u h w k h ? ' 0 $ f r q w u r o o h u f r s l h v g d w d i u r p w k h v r x u f h e x i i h u % w r w k h s h u l s k h u d o g d w d u h j l v w h u ? ' 0 $ & r q w u r o 7 d e o h l q 0 h p r u \ % x i i h u v l q 0 h p r u \ 8 v l q j w k h f k d q q h o ? v s u l p d u \ f r q w u r o v w u x f w x u h w k h ? ' 0 $ f r q w u r o o h u f r s l h v w d v n & f r q i l j x u d w l r q w r w k h f k d q q h o ? v d o w h u q d w h f r q w u r o v w u x f w x u h 7 k h q x v l q j w k h f k d q q h o ? v d o w h u q d w h f r q w u r o v w u x f w x u h w k h ? ' 0 $ f r q w u r o o h u f r s l h v g d w d i u r p w k h v r x u f h e x i i h u & w r w k h s h u l s k h u d o g d w d u h j l v w h u 3 5 , $ / 7 7 d v n / l v w l q 0 h p r u \ 7 $ 6 . $ 7 $ 6 . % 7 $ 6 . $ 7 $ 6 . & 3 h u l s k h u d o ' d w d 5 h j l v w h u 6 5 & % 6 5 & & 3 h u l s k h u d o ' d w d 5 h j l v w h u 6 5 & $ 6 5 & & 3 h u l s k h u d o ' d w d 5 h j l v w h u 6 5 & $ 6 5 & % 7 $ 6 . % 7 $ 6 . & 6 5 & % 6 5 & $ 7.2.7 transfer size and increment the dma controller supports transfer data sizes of 8, 16, or 32 bits. the source and destination data size must be the same for any given transfer. the source and destination address can be auto-incremented by bytes, half-words, or words, or can be set to no increment. the source and destination address increment values can be set independently, and it is not necessary for the address increment to match the data size as long as the increment is the same or larger than the data size. for example, it is possible to perform a transfer using 8-bit data size, but using an address increment of full words (4 bytes). the data to be transferred must be aligned in memory according to the data size (8, 16, or 32 bits). table 7-5 shows the configuration to read from a peripheral that supplies 8-bit data. table 7-5. dma read example: 8-bit peripheral configuration field 8 bits source data size 8 bits destination data size no increment source address increment byte destination address increment peripheral read fifo register source end pointer end of the data buffer in memory destination end pointer 7.2.8 peripheral interface each peripheral that supports dma has a single request and/or burst request signal that is asserted when the peripheral is ready to transfer data (see table 7-2 on page 348). the request signal can be disabled or enabled using the dma channel request mask set (dmareqmaskset) and dma channel request mask clear (dmareqmaskclr) registers. the dma request signal is disabled, or masked, when the channel request mask bit is set. when the request is not masked, the dma channel is configured correctly and enabled, and the peripheral asserts the request signal, the dma controller begins the transfer. note: when using dma to transfer data to and from a peripheral, the peripheral must disable all interrupts to the nvic. when a dma transfer is complete, the dma controller generates an interrupt, see interrupts and errors on page 360 for more information. for more information on how a specific peripheral interacts with the dma controller, refer to the dma operation section in the chapter that discusses that peripheral. 7.2.9 software request one dma channel is dedicated to software-initiated transfers. this channel also has a dedicated interrupt to signal completion of a dma transfer. a transfer is initiated by software by first configuring and enabling the transfer, and then issuing a software request using the dma channel software request (dmaswreq) register. for software-based transfers, the auto transfer mode should be used. it is possible to initiate a transfer on any channel using the dmaswreq register. if a request is initiated by software using a peripheral dma channel, then the completion interrupt occurs on the interrupt vector for the peripheral instead of the software interrupt vector. any channel may be used for software requests as long as the corresponding peripheral is not using dma for data transfer. 359 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 7.2.10 interrupts and errors when a dma transfer is complete, the dma controller generates a completion interrupt on the interrupt vector of the peripheral. therefore, if dma is used to transfer data for a peripheral and interrupts are used, then the interrupt handler for that peripheral must be designed to handle the dma transfer completion interrupt. if the transfer uses the software dma channel, then the completion interrupt occurs on the dedicated software dma interrupt vector (see table 7-6 on page 360). when dma is enabled for a peripheral, the dma controller stops the normal transfer interrupts for a peripheral from reaching the interrupt controller (the interrupts are still reported in the peripheral's interrupt registers). thus, when a large amount of data is transferred using dma, instead of receiving multiple interrupts from the peripheral as data flows, the interrupt controller receives only one interrupt when the transfer is complete. unmasked peripheral error interrupts continue to be sent to the interrupt controller. when a dma channel generates a completion interrupt, the chis bit corresponding to the peripheral channel is set in the dma channel interrupt status (dmachis) register (see page 395). this register can be used by the peripheral interrupt handler code to determine if the interrupt was caused by the dma channel or an error event reported by the peripheral's interrupt registers. the completion interrupt request from the dma controller is automatically cleared when the interrupt handler is activated. if the dma controller encounters a bus or memory protection error as it attempts to perform a data transfer, it disables the dma channel that caused the error and generates an interrupt on the dma error interrupt vector. the processor can read the dma bus error clear (dmaerrclr) register to determine if an error is pending. the errclr bit is set if an error occurred. the error can be cleared by writing a 1 to the errclr bit. table 7-6 shows the dedicated interrupt assignments for the dma controller. table 7-6. dma interrupt assignments assignment interrupt dma software channel transfer 46 dma error 47 7.3 initialization and configuration 7.3.1 module initialization before the dma controller can be used, it must be enabled in the system control block and in the peripheral. the location of the channel control structure must also be programmed. the following steps should be performed one time during system initialization: 1. the dma peripheral must be enabled in the system control block. to do this, set the udma bit of the system control rcgc2 register (see page 282). 2. enable the dma controller by setting the masteren bit of the dma configuration (dmacfg) register. 3. program the location of the channel control table by writing the base address of the table to the dma channel control base pointer (dmactlbase) register. the base address must be aligned on a 1024-byte boundary. july 03, 2014 360 texas instruments-production data micro direct memory access (dma) 7.3.2 configuring a memory-to-memory transfer dma channel 30 is dedicated for software-initiated transfers. however, any channel can be used for software-initiated, memory-to-memory transfer if the associated peripheral is not being used. 7.3.2.1 configure the channel attributes first, configure the channel attributes: 1. program bit 30 of the dma channel priority set (dmaprioset) or dma channel priority clear (dmaprioclr) registers to set the channel to high priority or default priority. 2. set bit 30 of the dma channel primary alternate clear (dmaaltclr) register to select the primary channel control structure for this transfer. 3. set bit 30 of the dma channel useburst clear (dmauseburstclr) register to allow the dma controller to respond to single and burst requests. 4. set bit 30 of the dma channel request mask clear (dmareqmaskclr) register to allow the dma controller to recognize requests for this channel. 7.3.2.2 configure the channel control structure now the channel control structure must be configured. this example transfers 256 words from one memory buffer to another. channel 30 is used for a software transfer, and the control structure for channel 30 is at offset 0x1e0 of the channel control table. the channel control structure for channel 30 is located at the offsets shown in table 7-7. table 7-7. channel control structure offsets for channel 30 description offset channel 30 source end pointer control table base + 0x1e0 channel 30 destination end pointer control table base + 0x1e4 channel 30 control word control table base + 0x1e8 configure the source and destination the source and destination end pointers must be set to the last address for the transfer (inclusive). 1. program the source end pointer at offset 0x1e0 to the address of the source buffer + 0x3fc. 2. program the destination end pointer at offset 0x1e4 to the address of the destination buffer + 0x3fc. the control word at offset 0x1e8 must be programmed according to table 7-8. table 7-8. channel control word configuration for memory transfer example description value bits field in dmachctl 32-bit destination address increment 2 31:30 dstinc 32-bit destination data size 2 29:28 dstsize 32-bit source address increment 2 27:26 srcinc 32-bit source data size 2 25:24 srcsize reserved 0 23:18 reserved 361 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 7-8. channel control word configuration for memory transfer example (continued) description value bits field in dmachctl arbitrates after 8 transfers 3 17:14 arbsize transfer 256 items 255 13:4 xfersize n/a for this transfer type 0 3 nxtuseburst use auto-request transfer mode 2 2:0 xfermode 7.3.2.3 start the transfer now the channel is configured and is ready to start. 1. enable the channel by setting bit 30 of the dma channel enable set (dmaenaset) register. 2. issue a transfer request by setting bit 30 of the dma channel software request (dmaswreq) register. the dma transfer begins. if the interrupt is enabled, then the processor is notified by interrupt when the transfer is complete. if needed, the status can be checked by reading bit 30 of the dmaenaset register. this bit is automatically cleared when the transfer is complete. the status can also be checked by reading the xfermode field of the channel control word at offset 0x1e8. this field is automatically cleared at the end of the transfer. 7.3.3 configuring a peripheral for simple transmit this example configures the dma controller to transmit a buffer of data to a peripheral. the peripheral has a transmit fifo with a trigger level of 4. the example peripheral uses dma channel 7. 7.3.3.1 configure the channel attributes first, configure the channel attributes: 1. configure bit 7 of the dma channel priority set (dmaprioset) or dma channel priority clear (dmaprioclr) registers to set the channel to high priority or default priority. 2. set bit 7 of the dma channel primary alternate clear (dmaaltclr) register to select the primary channel control structure for this transfer. 3. set bit 7 of the dma channel useburst clear (dmauseburstclr) register to allow the dma controller to respond to single and burst requests. 4. set bit 7 of the dma channel request mask clear (dmareqmaskclr) register to allow the dma controller to recognize requests for this channel. 7.3.3.2 configure the channel control structure this example transfers 64 bytes from a memory buffer to the peripheral's transmit fifo register using dma channel 7. the control structure for channel 7 is at offset 0x070 of the channel control table. the channel control structure for channel 7 is located at the offsets shown in table 7-9. table 7-9. channel control structure offsets for channel 7 description offset channel 7 source end pointer control table base + 0x070 july 03, 2014 362 texas instruments-production data micro direct memory access (dma) table 7-9. channel control structure offsets for channel 7 (continued) description offset channel 7 destination end pointer control table base + 0x074 channel 7 control word control table base + 0x078 configure the source and destination the source and destination end pointers must be set to the last address for the transfer (inclusive). because the peripheral pointer does not change, it simply points to the peripheral's data register. 1. program the source end pointer at offset 0x070 to the address of the source buffer + 0x3f. 2. program the destination end pointer at offset 0x074 to the address of the peripheral's transmit fifo register. the control word at offset 0x078 must be programmed according to table 7-10. table 7-10. channel control word configuration for peripheral transmit example description value bits field in dmachctl destination address does not increment 3 31:30 dstinc 8-bit destination data size 0 29:28 dstsize 8-bit source address increment 0 27:26 srcinc 8-bit source data size 0 25:24 srcsize reserved 0 23:18 reserved arbitrates after 4 transfers 2 17:14 arbsize transfer 64 items 63 13:4 xfersize n/a for this transfer type 0 3 nxtuseburst use basic transfer mode 1 2:0 xfermode note: in this example, it is not important if the peripheral makes a single request or a burst request. because the peripheral has a fifo that triggers at a level of 4, the arbitration size is set to 4. if the peripheral does make a burst request, then 4 bytes are transferred, which is what the fifo can accommodate. if the peripheral makes a single request (if there is any space in the fifo), then one byte is transferred at a time. if it is important to the application that transfers only be made in bursts, then the channel useburst set[7] bit should be set in the dma channel useburst set (dmauseburstset) register. 7.3.3.3 start the transfer now the channel is configured and is ready to start. 1. enable the channel by setting bit 7 of the dma channel enable set (dmaenaset) register. the dma controller is now configured for transfer on channel 7. the controller makes transfers to the peripheral whenever the peripheral asserts a dma request. the transfers continue until the entire buffer of 64 bytes has been transferred. when that happens, the dma controller disables the channel and sets the xfermode field of the channel control word to 0 (stopped). the status of the transfer can be checked by reading bit 7 of the dma channel enable set (dmaenaset) register. this bit is automatically cleared when the transfer is complete. the status can also be checked by reading the xfermode field of the channel control word at offset 0x078. this field is automatically cleared at the end of the transfer. 363 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller if peripheral interrupts are enabled, then the peripheral interrupt handler receives an interrupt when the entire transfer is complete. 7.3.4 configuring a peripheral for ping-pong receive this example configures the dma controller to continuously receive 8-bit data from a peripheral into a pair of 64-byte buffers. the peripheral has a receive fifo with a trigger level of 8. the example peripheral uses dma channel 8. 7.3.4.1 configure the channel attributes first, configure the channel attributes: 1. configure bit 8 of the dma channel priority set (dmaprioset) or dma channel priority clear (dmaprioclr) registers to set the channel to high priority or default priority. 2. set bit 8 of the dma channel primary alternate clear (dmaaltclr) register to select the primary channel control structure for this transfer. 3. set bit 8 of the dma channel useburst clear (dmauseburstclr) register to allow the dma controller to respond to single and burst requests. 4. set bit 8 of the dma channel request mask clear (dmareqmaskclr) register to allow the dma controller to recognize requests for this channel. 7.3.4.2 configure the channel control structure this example transfers bytes from the peripheral's receive fifo register into two memory buffers of 64 bytes each. as data is received, when one buffer is full, the dma controller switches to use the other. to use ping-pong buffering, both primary and alternate channel control structures must be used. the primary control structure for channel 8 is at offset 0x080 of the channel control table, and the alternate channel control structure is at offset 0x280. the channel control structures for channel 8 are located at the offsets shown in table 7-11. table 7-11. primary and alternate channel control structure offsets for channel 8 description offset channel 8 primary source end pointer control table base + 0x080 channel 8 primary destination end pointer control table base + 0x084 channel 8 primary control word control table base + 0x088 channel 8 alternate source end pointer control table base + 0x280 channel 8 alternate destination end pointer control table base + 0x284 channel 8 alternate control word control table base + 0x288 configure the source and destination the source and destination end pointers must be set to the last address for the transfer (inclusive). because the peripheral pointer does not change, it simply points to the peripheral's data register. both the primary and alternate sets of pointers must be configured. 1. program the primary source end pointer at offset 0x080 to the address of the peripheral's receive buffer. july 03, 2014 364 texas instruments-production data micro direct memory access (dma) 2. program the primary destination end pointer at offset 0x084 to the address of ping-pong buffer a + 0x3f. 3. program the alternate source end pointer at offset 0x280 to the address of the peripheral's receive buffer. 4. program the alternate destination end pointer at offset 0x284 to the address of ping-pong buffer b + 0x3f. the primary control word at offset 0x088 and the alternate control word at offset 0x288 are initially programmed the same way. 1. program the primary channel control word at offset 0x088 according to table 7-12. 2. program the alternate channel control word at offset 0x288 according to table 7-12. table 7-12. channel control word configuration for peripheral ping-pong receive example description value bits field in dmachctl 8-bit destination address increment 0 31:30 dstinc 8-bit destination data size 0 29:28 dstsize source address does not increment 3 27:26 srcinc 8-bit source data size 0 25:24 srcsize reserved 0 23:18 reserved arbitrates after 8 transfers 3 17:14 arbsize transfer 64 items 63 13:4 xfersize n/a for this transfer type 0 3 nxtuseburst use ping-pong transfer mode 3 2:0 xfermode note: in this example, it is not important if the peripheral makes a single request or a burst request. because the peripheral has a fifo that triggers at a level of 8, the arbitration size is set to 8. if the peripheral does make a burst request, then 8 bytes are transferred, which is what the fifo can accommodate. if the peripheral makes a single request (if there is any data in the fifo), then one byte is transferred at a time. if it is important to the application that transfers only be made in bursts, then the channel useburst set[8] bit should be set in the dma channel useburst set (dmauseburstset) register. 7.3.4.3 configure the peripheral interrupt an interrupt handler should be configured when using dma ping-pong mode, it is best to use an interrupt handler. however, the ping-pong mode can be configured without interrupts by polling. the interrupt handler is triggered after each buffer is complete. 1. configure and enable an interrupt handler for the peripheral. 7.3.4.4 enable the dma channel now the channel is configured and is ready to start. 1. enable the channel by setting bit 8 of the dma channel enable set (dmaenaset) register. 365 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 7.3.4.5 process interrupts the dma controller is now configured and enabled for transfer on channel 8. when the peripheral asserts the dma request signal, the dma controller makes transfers into buffer a using the primary channel control structure. when the primary transfer to buffer a is complete, it switches to the alternate channel control structure and makes transfers into buffer b. at the same time, the primary channel control word mode field is configured to indicate stopped, and an interrupt is when an interrupt is triggered, the interrupt handler must determine which buffer is complete and process the data or set a flag that the data must be processed by non-interrupt buffer processing code. then the next buffer transfer must be set up. in the interrupt handler: 1. read the primary channel control word at offset 0x088 and check the xfermode field. if the field is 0, this means buffer a is complete. if buffer a is complete, then: a. process the newly received data in buffer a or signal the buffer processing code that buffer a has data available. b. reprogram the primary channel control word at offset 0x88 according to table 7-12 on page 365. 2. read the alternate channel control word at offset 0x288 and check the xfermode field. if the field is 0, this means buffer b is complete. if buffer b is complete, then: a. process the newly received data in buffer b or signal the buffer processing code that buffer b has data available. b. reprogram the alternate channel control word at offset 0x288 according to table 7-12 on page 365. 7.3.5 configuring channel assignments channel assignments for each dma channel can be changed using the dmachasgn register. each bit represents a dma channel. if the bit is set, then the secondary function is used for the channel. refer to table 7-1 on page 346 for channel assignments. for example, to use ssi1 receive on channel 8 instead of uart0, set bit 8 of the dmachasgn register. 7.4 register map table 7-13 on page 367 lists the dma channel control structures and registers. the channel control structure shows the layout of one entry in the channel control table. the channel control table is located in system memory, and the location is determined by the application, that is, the base address is n/a (not applicable). in the table below, the offset for the channel control structures is the offset from the entry in the channel control table. see channel configuration on page 349 and table 7-3 on page 349 for a description of how the entries in the channel control table are located in memory. the dma register addresses are given as a hexadecimal increment, relative to the dma base address of 0x400f.f000. note that the dma module clock must be enabled before the registers can be programmed (see page 282). there must be a delay of 3 system clocks after the dma module clock is enabled before any dma module registers are accessed. july 03, 2014 366 texas instruments-production data micro direct memory access (dma) table 7-13. dma register map see page description reset type name offset dma channel control structure (offset from channel control table base) 369 dma channel source address end pointer - r/w dmasrcendp 0x000 370 dma channel destination address end pointer - r/w dmadstendp 0x004 371 dma channel control word - r/w dmachctl 0x008 dma registers (offset from dma base address) 376 dma status 0x001f.0000 ro dmastat 0x000 378 dma configuration - wo dmacfg 0x004 379 dma channel control base pointer 0x0000.0000 r/w dmactlbase 0x008 380 dma alternate channel control base pointer 0x0000.0200 ro dmaaltbase 0x00c 381 dma channel wait-on-request status 0xffff.ffc0 ro dmawaitstat 0x010 382 dma channel software request - wo dmaswreq 0x014 383 dma channel useburst set 0x0000.0000 r/w dmauseburstset 0x018 384 dma channel useburst clear - wo dmauseburstclr 0x01c 385 dma channel request mask set 0x0000.0000 r/w dmareqmaskset 0x020 386 dma channel request mask clear - wo dmareqmaskclr 0x024 387 dma channel enable set 0x0000.0000 r/w dmaenaset 0x028 388 dma channel enable clear - wo dmaenaclr 0x02c 389 dma channel primary alternate set 0x0000.0000 r/w dmaaltset 0x030 390 dma channel primary alternate clear - wo dmaaltclr 0x034 391 dma channel priority set 0x0000.0000 r/w dmaprioset 0x038 392 dma channel priority clear - wo dmaprioclr 0x03c 393 dma bus error clear 0x0000.0000 r/w dmaerrclr 0x04c 394 dma channel assignment 0x0000.0000 r/w dmachasgn 0x500 395 dma channel interrupt status 0x0000.0000 r/w1c dmachis 0x504 400 dma peripheral identification 4 0x0000.0004 ro dmaperiphid4 0xfd0 396 dma peripheral identification 0 0x0000.0030 ro dmaperiphid0 0xfe0 397 dma peripheral identification 1 0x0000.00b2 ro dmaperiphid1 0xfe4 398 dma peripheral identification 2 0x0000.000b ro dmaperiphid2 0xfe8 399 dma peripheral identification 3 0x0000.0000 ro dmaperiphid3 0xfec 401 dma primecell identification 0 0x0000.000d ro dmapcellid0 0xff0 402 dma primecell identification 1 0x0000.00f0 ro dmapcellid1 0xff4 403 dma primecell identification 2 0x0000.0005 ro dmapcellid2 0xff8 367 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 7-13. dma register map (continued) see page description reset type name offset 404 dma primecell identification 3 0x0000.00b1 ro dmapcellid3 0xffc 7.5 dma channel control structure the dma channel control structure holds the transfer settings for a dma channel. each channel has two control structures, which are located in a table in system memory. refer to channel configuration on page 349 for an explanation of the channel control table and the channel control structure. the channel control structure is one entry in the channel control table. each channel has a primary and alternate structure. the primary control structures are located at offsets 0x0, 0x10, 0x20 and so on. the alternate control structures are located at offsets 0x200, 0x210, 0x220, and so on. july 03, 2014 368 texas instruments-production data micro direct memory access (dma) register 1: dma channel source address end pointer (dmasrcendp), offset 0x000 dma channel source address end pointer (dmasrcendp) is part of the channel control structure and is used to specify the source address for a dma transfer. the dma controller can transfer data to and from the on-chip sram. however, because the flash memory and rom are located on a separate internal bus, it is not possible to transfer data from the flash memory or rom with the dma controller. note: the offset specified is from the base address of the control structure in system memory, not the dma module base address. dma channel source address end pointer (dmasrcendp) base n/a offset 0x000 type r/w, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 addr r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type - - - - - - - - - - - - - - - - reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 addr r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type - - - - - - - - - - - - - - - - reset description reset type name bit/field source address end pointer this field points to the last address of the dma transfer source (inclusive). if the source address is not incrementing (the srcinc field in the dmachctl register is 0x3), then this field points at the source location itself (such as a peripheral data register). - r/w addr 31:0 369 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 2: dma channel destination address end pointer (dmadstendp), offset 0x004 dma channel destination address end pointer (dmadstendp) is part of the channel control structure and is used to specify the destination address for a dma transfer. note: the offset specified is from the base address of the control structure in system memory, not the dma module base address. dma channel destination address end pointer (dmadstendp) base n/a offset 0x004 type r/w, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 addr r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type - - - - - - - - - - - - - - - - reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 addr r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type - - - - - - - - - - - - - - - - reset description reset type name bit/field destination address end pointer this field points to the last address of the dma transfer destination (inclusive). if the destination address is not incrementing (the dstinc field in the dmachctl register is 0x3), then this field points at the destination location itself (such as a peripheral data register). - r/w addr 31:0 july 03, 2014 370 texas instruments-production data micro direct memory access (dma) register 3: dma channel control word (dmachctl), offset 0x008 dma channel control word (dmachctl) is part of the channel control structure and is used to specify parameters of a dma transfer. note: the offset specified is from the base address of the control structure in system memory, not the dma module base address. dma channel control word (dmachctl) base n/a offset 0x008 type r/w, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 arbsize reserved srcsize srcinc dstsize dstinc r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type - - - - - - - - - - - - - - - - reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 xfermode nxtuseburst xfersize arbsize r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type - - - - - - - - - - - - - - - - reset description reset type name bit/field destination address increment this field configures the destination address increment. the address increment value must be equal or greater than the value of the destination size ( dstsize). description value byte increment by 8-bit locations 0x0 half-word increment by 16-bit locations 0x1 word increment by 32-bit locations 0x2 no increment address remains set to the value of the destination address end pointer ( dmadstendp ) for the channel 0x3 - r/w dstinc 31:30 371 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field destination data size this field configures the destination item data size. note: dstsize must be the same as srcsize. description value byte 8-bit data size 0x0 half-word 16-bit data size 0x1 word 32-bit data size 0x2 reserved 0x3 - r/w dstsize 29:28 source address increment this field configures the source address increment. the address increment value must be equal or greater than the value of the source size ( srcsize). description value byte increment by 8-bit locations 0x0 half-word increment by 16-bit locations 0x1 word increment by 32-bit locations 0x2 no increment address remains set to the value of the source address end pointer ( dmasrcendp ) for the channel 0x3 - r/w srcinc 27:26 source data size this field configures the source item data size. note: dstsize must be the same as srcsize. description value byte 8-bit data size. 0x0 half-word 16-bit data size. 0x1 word 32-bit data size. 0x2 reserved 0x3 - r/w srcsize 25:24 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. - r/w reserved 23:18 july 03, 2014 372 texas instruments-production data micro direct memory access (dma) description reset type name bit/field arbitration size this field configures the number of transfers that can occur before the dma controller re-arbitrates. the possible arbitration rate configurations represent powers of 2 and are shown below. description value 1 transfer arbitrates after each dma transfer 0x0 2 transfers 0x1 4 transfers 0x2 8 transfers 0x3 16 transfers 0x4 32 transfers 0x5 64 transfers 0x6 128 transfers 0x7 256 transfers 0x8 512 transfers 0x9 1024 transfers in this configuration, no arbitration occurs during the dma transfer because the maximum transfer size is 1024. 0xa-0xf - r/w arbsize 17:14 transfer size (minus 1) this field configures the total number of items to transfer. the value of this field is 1 less than the number to transfer (value 0 means transfer 1 item). the maximum value for this 10-bit field is 1023 which represents a transfer size of 1024 items. the transfer size is the number of items, not the number of bytes. if the data size is 32 bits, then this value is the number of 32-bit words to transfer. the dma controller updates this field immediately prior to entering the arbitration process, so it contains the number of outstanding items that is necessary to complete the dma cycle. - r/w xfersize 13:4 next useburst this field controls whether the useburst set[n] bit is automatically set for the last transfer of a peripheral scatter-gather operation. normally, for the last transfer, if the number of remaining items to transfer is less than the arbitration size, the dma controller uses single transfers to complete the transaction. if this bit is set, then the controller uses a burst transfer to complete the last transfer. - r/w nxtuseburst 3 373 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field dma transfer mode this field configures the operating mode of the dma cycle. refer to transfer modes on page 350 for a detailed explanation of transfer modes. because this register is in system ram, it has no reset value. therefore, this field should be initialized to 0 before the channel is enabled. description value stop 0x0 basic 0x1 auto-request 0x2 ping-pong 0x3 memory scatter-gather 0x4 alternate memory scatter-gather 0x5 peripheral scatter-gather 0x6 alternate peripheral scatter-gather 0x7 - r/w xfermode 2:0 xfermode bit field values. stop channel is stopped or configuration data is invalid. no more transfers can occur. basic for each trigger (whether from a peripheral or a software request), the dma controller performs the number of transfers specified by the arbsize field. auto-request the initial request (software- or peripheral-initiated) is sufficient to complete the entire transfer of xfersize items without any further requests. ping-pong this mode uses both the primary and alternate control structures for this channel. when the number of transfers specified by the xfersize field have completed for the current control structure (primary or alternate), the dma controller switches to the other one. these switches continue until one of the control structures is not set to ping-pong mode. at that point, the dma controller stops. an interrupt is generated on completion of the transfers configured by each control structure. see ping-pong on page 351. memory scatter-gather when using this mode, the primary control structure for the channel is configured to allow a list of operations (tasks) to be performed. the source address pointer specifies the start of a table of tasks to be copied to the alternate control structure for this channel. the xfermode field for the alternate control structure should be configured to 0x5 (alternate memory scatter-gather) to perform the task. when the task completes, the dma switches back to the primary channel control structure, which then copies the next task to the alternate control structure. this process continues until the table of tasks is empty. the last task must have an xfermode value other than 0x5. note that for continuous operation, the last task can update the primary channel control structure back to the start of the list or to another list. see memory scatter-gather on page 352. july 03, 2014 374 texas instruments-production data micro direct memory access (dma) alternate memory scatter-gather this value must be used in the alternate channel control data structure when the dma controller operates in memory scatter-gather mode. peripheral scatter-gather this value must be used in the primary channel control data structure when the dma controller operates in peripheral scatter-gather mode. in this mode, the dma controller operates exactly the same as in memory scatter-gather mode, except that instead of performing the number of transfers specified by the xfersize field in the alternate control structure at one time, the dma controller only performs the number of transfers specified by the arbsize field per trigger; see basic mode for details. see peripheral scatter-gather on page 356. alternate peripheral scatter-gather this value must be used in the alternate channel control data structure when the dma controller operates in peripheral scatter-gather mode. 7.6 dma register descriptions the register addresses given are relative to the dma base address of 0x400f.f000. 375 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 4: dma status (dmastat), offset 0x000 the dma status (dmastat) register returns the status of the dma controller. you cannot read this register when the dma controller is in the reset state. dma status (dmastat) base 0x400f.f000 offset 0x000 type ro, reset 0x001f.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 dmachans reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 masten reserved state reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 31:21 available dma channels minus 1 this field contains a value equal to the number of dma channels the dma controller is configured to use, minus one. the value of 0x1f corresponds to 32 dma channels. 0x1f ro dmachans 20:16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 15:8 control state machine status this field shows the current status of the control state machine. status can be one of the following. description value idle 0x0 reading channel controller data. 0x1 reading source end pointer. 0x2 reading destination end pointer. 0x3 reading source data. 0x4 writing destination data. 0x5 waiting for dma request to clear. 0x6 writing channel controller data. 0x7 stalled 0x8 done 0x9 undefined 0xa-0xf 0x0 ro state 7:4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 3:1 july 03, 2014 376 texas instruments-production data micro direct memory access (dma) description reset type name bit/field master enable status description value the dma controller is disabled. 0 the dma controller is enabled. 1 0 ro masten 0 377 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 5: dma configuration (dmacfg), offset 0x004 the dmacfg register controls the configuration of the dma controller. dma configuration (dmacfg) base 0x400f.f000 offset 0x004 type wo, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type - - - - - - - - - - - - - - - - reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 masten reserved wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type - - - - - - - - - - - - - - - - reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. - wo reserved 31:1 controller master enable description value disables the dma controller. 0 enables dma controller. 1 - wo masten 0 july 03, 2014 378 texas instruments-production data micro direct memory access (dma) register 6: dma channel control base pointer (dmactlbase), offset 0x008 the dmactlbase register must be configured so that the base pointer points to a location in system memory. the amount of system memory that must be assigned to the dma controller depends on the number of dma channels used and whether the alternate channel control data structure is used. see channel configuration on page 349 for details about the channel control table. the base address must be aligned on a 1024-byte boundary. this register cannot be read when the dma controller is in the reset state. dma channel control base pointer (dmactlbase) base 0x400f.f000 offset 0x008 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 addr r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved addr ro ro ro ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field channel control base address this field contains the pointer to the base address of the channel control table. the base address must be 1024-byte aligned. 0x0000.00 r/w addr 31:10 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 9:0 379 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 7: dma alternate channel control base pointer (dmaaltbase), offset 0x00c the dmaaltbase register returns the base address of the alternate channel control data. this register removes the necessity for application software to calculate the base address of the alternate channel control structures. this register cannot be read when the dma controller is in the reset state. dma alternate channel control base pointer (dmaaltbase) base 0x400f.f000 offset 0x00c type ro, reset 0x0000.0200 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 addr ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 addr ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 reset description reset type name bit/field alternate channel address pointer this field provides the base address of the alternate channel control structures. 0x0000.0200 ro addr 31:0 july 03, 2014 380 texas instruments-production data micro direct memory access (dma) register 8: dma channel wait-on-request status (dmawaitstat), offset 0x010 this read-only register indicates that the dma channel is waiting on a request. a peripheral can hold off the dma from performing a single request until the peripheral is ready for a burst request to enhance the dma performance. the use of this feature is dependent on the design of the peripheral and is not controllable by software in any way. this register cannot be read when the dma controller is in the reset state. dma channel wait-on-request status (dmawaitstat) base 0x400f.f000 offset 0x010 type ro, reset 0xffff.ffc0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 waitreq[n] ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 waitreq[n] ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field channel [n] wait status these bits provide the channel wait-on-request status. bit 0 corresponds to channel 0. description value the corresponding channel is waiting on a request. 1 the corresponding channel is not waiting on a request. 0 0xffff.ffc0 ro waitreq[n] 31:0 381 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 9: dma channel software request (dmaswreq), offset 0x014 each bit of the dmaswreq register represents the corresponding dma channel. setting a bit generates a request for the specified dma channel. dma channel software request (dmaswreq) base 0x400f.f000 offset 0x014 type wo, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 swreq[n] wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type - - - - - - - - - - - - - - - - reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 swreq[n] wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type - - - - - - - - - - - - - - - - reset description reset type name bit/field channel [n] software request these bits generate software requests. bit 0 corresponds to channel 0. description value generate a software request for the corresponding channel. 1 no request generated. 0 these bits are automatically cleared when the software request has been completed. - wo swreq[n] 31:0 july 03, 2014 382 texas instruments-production data micro direct memory access (dma) register 10: dma channel useburst set (dmauseburstset), offset 0x018 each bit of the dmauseburstset register represents the corresponding dma channel. setting a bit disables the channel's single request input from generating requests, configuring the channel to only accept burst requests. reading the register returns the status of useburst. if the amount of data to transfer is a multiple of the arbitration (burst) size, the corresponding set[n] bit is cleared after completing the final transfer. if there are fewer items remaining to transfer than the arbitration (burst) size, the dma controller automatically clears the corresponding set[n ] bit, allowing the remaining items to transfer using single requests. in order to resume transfers using burst requests, the corresponding bit must be set again. a bit should not be set if the corresponding peripheral does not support the burst request model. refer to request types on page 348 for more details about request types. dma channel useburst set (dmauseburstset) base 0x400f.f000 offset 0x018 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 set[n] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 set[n] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field channel [n] useburst set description value dma channel [n] responds to single or burst requests. 0 dma channel [n] responds only to burst requests. 1 bit 0 corresponds to channel 0. this bit is automatically cleared as described above. a bit can also be manually cleared by setting the corresponding clr[n] bit in the dmauseburstclr register. 0x0000.0000 r/w set[n] 31:0 383 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 11: dma channel useburst clear (dmauseburstclr), offset 0x01c each bit of the dmauseburstclr register represents the corresponding dma channel. setting a bit clears the corresponding set[n] bit in the dmauseburstset register. dma channel useburst clear (dmauseburstclr) base 0x400f.f000 offset 0x01c type wo, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 clr[n] wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type - - - - - - - - - - - - - - - - reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 clr[n] wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type - - - - - - - - - - - - - - - - reset description reset type name bit/field channel [n] useburst clear description value no effect. 0 setting a bit clears the corresponding set[n] bit in the dmauseburstset register meaning that dma channel [n] responds to single and burst requests. 1 - wo clr[n] 31:0 july 03, 2014 384 texas instruments-production data micro direct memory access (dma) register 12: dma channel request mask set (dmareqmaskset), offset 0x020 each bit of the dmareqmaskset register represents the corresponding dma channel. setting a bit disables dma requests for the channel. reading the register returns the request mask status. when a dma channel's request is masked, that means the peripheral can no longer request dma transfers. the channel can then be used for software-initiated transfers. dma channel request mask set (dmareqmaskset) base 0x400f.f000 offset 0x020 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 set[n] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 set[n] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field channel [n] request mask set description value the peripheral associated with channel [n] is enabled to request dma transfers. 0 the peripheral associated with channel [n] is not able to request dma transfers. channel [n] may be used for software-initiated transfers. 1 bit 0 corresponds to channel 0. a bit can only be cleared by setting the corresponding clr[n] bit in the dmareqmaskclr register. 0x0000.0000 r/w set[n] 31:0 385 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 13: dma channel request mask clear (dmareqmaskclr), offset 0x024 each bit of the dmareqmaskclr register represents the corresponding dma channel. setting a bit clears the corresponding set[n] bit in the dmareqmaskset register. dma channel request mask clear (dmareqmaskclr) base 0x400f.f000 offset 0x024 type wo, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 clr[n] wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type - - - - - - - - - - - - - - - - reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 clr[n] wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type - - - - - - - - - - - - - - - - reset description reset type name bit/field channel [n] request mask clear description value no effect. 0 setting a bit clears the corresponding set[n] bit in the dmareqmaskset register meaning that the peripheral associated with channel [n] is enabled to request dma transfers. 1 - wo clr[n] 31:0 july 03, 2014 386 texas instruments-production data micro direct memory access (dma) register 14: dma channel enable set (dmaenaset), offset 0x028 each bit of the dmaenaset register represents the corresponding dma channel. setting a bit enables the corresponding dma channel. reading the register returns the enable status of the channels. if a channel is enabled but the request mask is set ( dmareqmaskset ), then the channel can be used for software-initiated transfers. dma channel enable set (dmaenaset) base 0x400f.f000 offset 0x028 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 set[n] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 set[n] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field channel [n] enable set description value dma channel [n] is disabled. 0 dma channel [n] is enabled. 1 bit 0 corresponds to channel 0. a bit can only be cleared by setting the corresponding clr[n] bit in the dmaenaclr register. 0x0000.0000 r/w set[n] 31:0 387 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 15: dma channel enable clear (dmaenaclr), offset 0x02c each bit of the dmaenaclr register represents the corresponding dma channel. setting a bit clears the corresponding set[n] bit in the dmaenaset register. dma channel enable clear (dmaenaclr) base 0x400f.f000 offset 0x02c type wo, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 clr[n] wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type - - - - - - - - - - - - - - - - reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 clr[n] wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type - - - - - - - - - - - - - - - - reset description reset type name bit/field clear channel [n] enable clear description value no effect. 0 setting a bit clears the corresponding set[n] bit in the dmaenaset register meaning that channel [n] is disabled for dma transfers. 1 note: the controller disables a channel when it completes the dma cycle. - wo clr[n] 31:0 july 03, 2014 388 texas instruments-production data micro direct memory access (dma) register 16: dma channel primary alternate set (dmaaltset), offset 0x030 each bit of the dmaaltset register represents the corresponding dma channel. setting a bit configures the dma channel to use the alternate control data structure. reading the register returns the status of which control data structure is in use for the corresponding dma channel. dma channel primary alternate set (dmaaltset) base 0x400f.f000 offset 0x030 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 set[n] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 set[n] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field channel [n] alternate set description value dma channel [n] is using the primary control structure. 0 dma channel [n] is using the alternate control structure. 1 bit 0 corresponds to channel 0. a bit can only be cleared by setting the corresponding clr[n] bit in the dmaaltclr register. note: for ping-pong and scatter-gather cycle types, the dma controller automatically sets these bits to select the alternate channel control data structure. 0x0000.0000 r/w set[n] 31:0 389 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 17: dma channel primary alternate clear (dmaaltclr), offset 0x034 each bit of the dmaaltclr register represents the corresponding dma channel. setting a bit clears the corresponding set[n] bit in the dmaaltset register. dma channel primary alternate clear (dmaaltclr) base 0x400f.f000 offset 0x034 type wo, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 clr[n] wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type - - - - - - - - - - - - - - - - reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 clr[n] wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type - - - - - - - - - - - - - - - - reset description reset type name bit/field channel [n] alternate clear description value no effect. 0 setting a bit clears the corresponding set[n] bit in the dmaaltset register meaning that channel [n] is using the primary control structure. 1 note: for ping-pong and scatter-gather cycle types, the dma controller automatically sets these bits to select the alternate channel control data structure. - wo clr[n] 31:0 july 03, 2014 390 texas instruments-production data micro direct memory access (dma) register 18: dma channel priority set (dmaprioset), offset 0x038 each bit of the dmaprioset register represents the corresponding dma channel. setting a bit configures the dma channel to have a high priority level. reading the register returns the status of the channel priority mask. dma channel priority set (dmaprioset) base 0x400f.f000 offset 0x038 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 set[n] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 set[n] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field channel [n] priority set description value dma channel [n] is using the default priority level. 0 dma channel [n] is using a high priority level. 1 bit 0 corresponds to channel 0. a bit can only be cleared by setting the corresponding clr[n] bit in the dmaprioclr register. 0x0000.0000 r/w set[n] 31:0 391 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 19: dma channel priority clear (dmaprioclr), offset 0x03c each bit of the dmaprioclr register represents the corresponding dma channel. setting a bit clears the corresponding set[n] bit in the dmaprioset register. dma channel priority clear (dmaprioclr) base 0x400f.f000 offset 0x03c type wo, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 clr[n] wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type - - - - - - - - - - - - - - - - reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 clr[n] wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type - - - - - - - - - - - - - - - - reset description reset type name bit/field channel [n] priority clear description value no effect. 0 setting a bit clears the corresponding set[n] bit in the dmaprioset register meaning that channel [n] is using the default priority level. 1 - wo clr[n] 31:0 july 03, 2014 392 texas instruments-production data micro direct memory access (dma) register 20: dma bus error clear (dmaerrclr), offset 0x04c the dmaerrclr register is used to read and clear the dma bus error status. the error status is set if the dma controller encountered a bus error while performing a transfer. if a bus error occurs on a channel, that channel is automatically disabled by the dma controller. the other channels are unaffected. dma bus error clear (dmaerrclr) base 0x400f.f000 offset 0x04c type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 errclr reserved r/w1c ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:1 dma bus error status description value no bus error is pending. 0 a bus error is pending. 1 this bit is cleared by writing a 1 to it. 0 r/w1c errclr 0 393 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 21: dma channel assignment (dmachasgn), offset 0x500 each bit of the dmachasgn register represents the corresponding dma channel. setting a bit selects the secondary channel assignment as specified in table 7-1 on page 346. dma channel assignment (dmachasgn) base 0x400f.f000 offset 0x500 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 chasgn[n] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type - - - - - - - - - - - - - - - - reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 chasgn[n] r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type - - - - - - - - - - - - - - - - reset description reset type name bit/field channel [n] assignment select description value use the primary channel assignment. 0 use the secondary channel assignment. 1 - r/w chasgn[n] 31:0 july 03, 2014 394 texas instruments-production data micro direct memory access (dma) register 22: dma channel interrupt status (dmachis), offset 0x504 each bit of the dmachis register represents the corresponding dma channel. a bit is set when that dma channel causes a completion interrupt. the bits are cleared by a writing a 1. dma channel interrupt status (dmachis) base 0x400f.f000 offset 0x504 type r/w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 chis[n] r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 chis[n] r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field channel [n] interrupt status description value the corresponding dma channel caused an interrupt. 1 the corresponding dma channel has not caused an interrupt. 0 this bit is cleared by writing a 1 to it. 0x0000.0000 r/w1c chis[n] 31:0 395 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 23: dma peripheral identification 0 (dmaperiphid0), offset 0xfe0 the dmaperiphidn registers are hard-coded, and the fields within the registers determine the reset values. dma peripheral identification 0 (dmaperiphid0) base 0x400f.f000 offset 0xfe0 type ro, reset 0x0000.0030 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid0 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 dma peripheral id register [7:0] can be used by software to identify the presence of this peripheral. 0x30 ro pid0 7:0 july 03, 2014 396 texas instruments-production data micro direct memory access (dma) register 24: dma peripheral identification 1 (dmaperiphid1), offset 0xfe4 the dmaperiphidn registers are hard-coded, and the fields within the registers determine the reset values. dma peripheral identification 1 (dmaperiphid1) base 0x400f.f000 offset 0xfe4 type ro, reset 0x0000.00b2 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid1 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 1 0 0 1 1 0 1 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 dma peripheral id register [15:8] can be used by software to identify the presence of this peripheral. 0xb2 ro pid1 7:0 397 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 25: dma peripheral identification 2 (dmaperiphid2), offset 0xfe8 the dmaperiphidn registers are hard-coded, and the fields within the registers determine the reset values. dma peripheral identification 2 (dmaperiphid2) base 0x400f.f000 offset 0xfe8 type ro, reset 0x0000.000b 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid2 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 dma peripheral id register [23:16] can be used by software to identify the presence of this peripheral. 0x0b ro pid2 7:0 july 03, 2014 398 texas instruments-production data micro direct memory access (dma) register 26: dma peripheral identification 3 (dmaperiphid3), offset 0xfec the dmaperiphidn registers are hard-coded and the fields within the registers determine the reset values. dma peripheral identification 3 (dmaperiphid3) base 0x400f.f000 offset 0xfec type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 dma peripheral id register [31:24] can be used by software to identify the presence of this peripheral. 0x00 ro pid3 7:0 399 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 27: dma peripheral identification 4 (dmaperiphid4), offset 0xfd0 the dmaperiphidn registers are hard-coded, and the fields within the registers determine the reset values. dma peripheral identification 4 (dmaperiphid4) base 0x400f.f000 offset 0xfd0 type ro, reset 0x0000.0004 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid4 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 dma peripheral id register can be used by software to identify the presence of this peripheral. 0x04 ro pid4 7:0 july 03, 2014 400 texas instruments-production data micro direct memory access (dma) register 28: dma primecell identification 0 (dmapcellid0), offset 0xff0 the dmapcellidn registers are hard-coded, and the fields within the registers determine the reset values. dma primecell identification 0 (dmapcellid0) base 0x400f.f000 offset 0xff0 type ro, reset 0x0000.000d 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cid0 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 dma primecell id register [7:0] provides software a standard cross-peripheral identification system. 0x0d ro cid0 7:0 401 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 29: dma primecell identification 1 (dmapcellid1), offset 0xff4 the dmapcellidn registers are hard-coded, and the fields within the registers determine the reset values. dma primecell identification 1 (dmapcellid1) base 0x400f.f000 offset 0xff4 type ro, reset 0x0000.00f0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cid1 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 dma primecell id register [15:8] provides software a standard cross-peripheral identification system. 0xf0 ro cid1 7:0 july 03, 2014 402 texas instruments-production data micro direct memory access (dma) register 30: dma primecell identification 2 (dmapcellid2), offset 0xff8 the dmapcellidn registers are hard-coded, and the fields within the registers determine the reset values. dma primecell identification 2 (dmapcellid2) base 0x400f.f000 offset 0xff8 type ro, reset 0x0000.0005 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cid2 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 dma primecell id register [23:16] provides software a standard cross-peripheral identification system. 0x05 ro cid2 7:0 403 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 31: dma primecell identification 3 (dmapcellid3), offset 0xffc the dmapcellidn registers are hard-coded, and the fields within the registers determine the reset values. dma primecell identification 3 (dmapcellid3) base 0x400f.f000 offset 0xffc type ro, reset 0x0000.00b1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cid3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 dma primecell id register [31:24] provides software a standard cross-peripheral identification system. 0xb1 ro cid3 7:0 july 03, 2014 404 texas instruments-production data micro direct memory access (dma) 8 general-purpose input/outputs (gpios) the gpio module is composed of nine physical gpio blocks, each corresponding to an individual gpio port (port a, port b, port c, port d, port e, port f, port g, port h, port j). the gpio module supports up to 72 programmable input/output pins, depending on the peripherals being used. the gpio module has the following features: up to 72 gpios, depending on configuration highly flexible pin muxing allows use as gpio or one of several peripheral functions 5-v-tolerant in input configuration two means of port access: either advanced high-performance bus (ahb) with better back-to-back access performance, or the legacy advanced peripheral bus (apb) for backwards-compatibility with existing code fast toggle capable of a change every clock cycle for ports on ahb, every two clock cycles for ports on apb programmable control for gpio interrupts C interrupt generation masking C edge-triggered on rising, falling, or both C level-sensitive on high or low values bit masking in both read and write operations through address lines can be used to initiate an adc sample sequence pins configured as digital inputs are schmitt-triggered programmable control for gpio pad configuration C weak pull-up or pull-down resistors C 2-ma, 4-ma, and 8-ma pad drive for digital communication; up to four pads can sink 18-ma for high-current applications C slew rate control for the 8-ma drive C open drain enables C digital input enables 8.1 signal description gpio signals have alternate hardware functions. the following table lists the gpio pins and their analog and digital alternate functions. the ainx and vrefa analog signals are not 5-v tolerant and go through an isolation circuit before reaching their circuitry. these signals are configured by clearing the corresponding den bit in the gpio digital enable (gpioden) register and setting the corresponding amsel bit in the gpio analog mode select (gpioamsel) register. other analog 405 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller signals are 5-v tolerant and are connected directly to their circuitry ( c0-, c0+, c1-, c1+, c2-, c2+, usb0vbus, usb0id ). these signals are configured by clearing the den bit in the gpio digital enable (gpioden) register. all gpio signals are 5-v tolerant when configured as inputs except for pb0 and pb1 , which are limited to 3.6 v. the digital alternate hardware functions are enabled by setting the appropriate bit in the gpio alternate function select (gpioafsel) and gpioden registers and configuring the pmcx bit field in the gpio port control (gpiopctl) register to the numeric encoding shown in the table below. note that each pin must be programmed individually; no type of grouping is implied by the columns in the table. table entries that are shaded gray are the default values for the corresponding gpio pin. important: all gpio pins are configured as gpios and tri-stated by default ( gpioafsel =0, gpioden =0, gpiopdr =0, gpiopur =0, and gpiopctl =0, with the exception of the pins shown in the table below. a power-on-reset ( por ) or asserting rst puts the pins back to their default state. table 8-1. gpio pins with non-zero reset values gpiopctl gpiopur gpiopdr gpioden gpioafsel default state gpio pins 0x1 0 0 0 0 uart0 pa[1:0] 0x1 0 0 0 0 ssi0 pa[5:2] 0x1 0 0 0 0 i 2 c0 pb[3:2] 0x3 1 0 1 1 jtag/swd pc[3:0] table 8-2. gpio pins and alternate functions (100lqfp) digital function (gpiopctl pmcx bit field encoding) a analog function pinio 11 10 9 8 7 6 5 4 3 2 1 -- u1rx i2c1scl ------ u0rx -26 pa0 -- u1tx i2c1sda ------ u0tx -27 pa1 -- i2s0rxsd ---- pwm4 txd2 - ssi0clk -28 pa2 -- i2s0rxmclk ---- pwm5 txd1 - ssi0fss -29 pa3 -- i2s0txsck --- can0rx pwm6 txd0 - ssi0rx -30 pa4 -- i2s0txws --- can0tx pwm7 rxdv - ssi0tx -31 pa5 -- u1cts usb0epen - can0rx pwm4 pwm0 rxck ccp1 i2c1scl -34 pa6 -- u1dcd usb0pflt ccp3 can0tx pwm5 pwm1 rxer ccp4 i2c1sda -35 pa7 ------ u1rx -- pwm2 ccp0 usb0id 66 pb0 ------ u1tx ccp1 - pwm3 ccp2 usb0vbus 67 pb1 --- usb0epen -- ccp0 ccp3 - idx0 i2c0scl -72 pb2 --- usb0pflt --- fault3 - fault0 i2c0sda -65 pb3 --- epi0s23 u1rx idx0 can0rx u2rx --- ain10 c0- 92 pb4 --- epi0s22 u1tx ccp2 can0tx ccp0 ccp6 ccp5 c0o ain11 c1- 91 pb5 -- i2s0txsck -- ccp5 idx0 fault1 c0o ccp7 ccp1 vrefa c0+ 90 pb6 ---- rxd1 -- nmi --- -89 pb7 -------- tck swclk -- -80 pc0 july 03, 2014 406 texas instruments-production data general-purpose input/outputs (gpios) table 8-2. gpio pins and alternate functions (100lqfp) (continued) digital function (gpiopctl pmcx bit field encoding) a analog function pinio 11 10 9 8 7 6 5 4 3 2 1 -------- tms swdio -- -79 pc1 -------- tdi -- -78 pc2 -------- tdo swo -- -77 pc3 -- ccp1 epi0s2 - ccp4 ccp2 pwm6 txd3 pha0 ccp5 -25 pc4 --- epi0s3 - usb0epen ccp3 fault2 c0o c1o ccp1 c1+ 24 pc5 --- epi0s4 usb0pflt ccp0 u1rx pwm7 c2o phb0 ccp3 c2+ 23 pc6 --- epi0s5 c1o usb0pflt u1tx ccp0 - phb0 ccp4 c2- 22 pc7 -- u1cts i2s0rxsck rxdv ccp6 u1rx u2rx idx0 can0rx pwm0 ain15 10 pd0 phb1 ccp2 u1dcd i2s0rxws txer ccp7 u1tx u2tx pha0 can0tx pwm1 ain14 11 pd1 --- epi0s20 --- ccp5 pwm2 ccp6 u1rx ain13 12 pd2 --- epi0s21 --- ccp0 pwm3 ccp7 u1tx ain12 13 pd3 - epi0s19 u1ri i2s0rxsd --- txd3 - ccp3 ccp0 ain7 97 pd4 - epi0s28 u2rx i2s0rxmclk --- txd2 - ccp4 ccp2 ain6 98 pd5 - epi0s29 u2tx i2s0txsck --- txd1 -- fault0 ain5 99 pd6 - epi0s30 u1dtr i2s0txws --- txd0 ccp1 c0o idx0 ain4 100 pd7 -- usb0pflt epi0s8 ---- ccp3 ssi1clk pwm4 -74 pe0 --- epi0s9 -- ccp6 ccp2 fault0 ssi1fss pwm5 -75 pe1 --- epi0s24 -- ccp2 pha0 phb1 ssi1rx ccp4 ain9 95 pe2 --- epi0s25 -- ccp7 phb0 pha1 ssi1tx ccp1 ain8 96 pe3 -- i2s0txws - rxd0 ccp2 u2tx fault0 -- ccp3 ain3 6 pe4 -- i2s0txsd ------- ccp5 ain2 5 pe5 -- u1cts ------ c1o pwm4 ain1 2 pe6 -- u1dcd ------ c2o pwm5 ain0 1 pe7 -- u1dsr i2s0txsd --- rxck pwm0 phb0 can1rx -47 pf0 - ccp3 u1rts i2s0txmclk --- rxer pwm1 idx1 can1tx -61 pf1 -- ssi1clk ---- pwm2 phyint pwm4 - -60 pf2 -- ssi1fss ---- pwm3 mdc pwm5 - -59 pf3 -- ssi1rx epi0s12 --- fault0 mdio c0o ccp0 -58 pf4 -- ssi1tx epi0s15 ---- rxd3 c1o ccp2 -46 pf5 - u1rts i2s0txmclk ---- pha0 rxd2 c2o ccp1 -43 pf6 -- fault1 epi0s12 --- phb0 rxd1 - ccp4 -42 pf7 --- epi0s13 usb0epen -- pwm4 i2c1scl pwm0 u2rx -19 pg0 --- epi0s14 --- pwm5 i2c1sda pwm1 u2tx -18 pg1 -- i2s0rxsd idx1 --- fault0 col - pwm0 -17 pg2 -- i2s0rxmclk fault0 --- fault2 crs - pwm1 -16 pg3 - u1ri pwm6 epi0s15 --- fault1 rxd0 - ccp3 -41 pg4 - u1dtr i2s0rxsck pwm7 -- fault1 idx0 txen - ccp5 -40 pg5 - u1ri i2s0rxws fault1 --- pwm6 txck - pha1 -37 pg6 -- epi0s31 ccp5 --- pwm7 txer - phb1 -36 pg7 407 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 8-2. gpio pins and alternate functions (100lqfp) (continued) digital function (gpiopctl pmcx bit field encoding) a analog function pinio 11 10 9 8 7 6 5 4 3 2 1 -- pwm4 epi0s6 ----- pwm2 ccp6 -86 ph0 -- pwm5 epi0s7 ----- pwm3 ccp7 -85 ph1 -- txd3 epi0s1 --- fault3 - c1o idx1 -84 ph2 -- txd2 epi0s0 --- usb0epen - fault0 phb0 -83 ph3 ssi1clk - txd1 epi0s10 --- usb0pflt --- -76 ph4 ssi1fss fault2 txd0 epi0s11 ------- -63 ph5 ssi1rx pwm4 rxdv epi0s26 ------- -62 ph6 ssi1tx pwm5 - epi0s27 ---- rxck -- -15 ph7 i2c1scl pwm0 - epi0s16 ---- rxer -- -14 pj0 i2c1sda pwm1 usb0pflt epi0s17 ------- -87 pj1 - fault0 ccp0 epi0s18 ------- -39 pj2 - ccp6 u1cts epi0s19 ------- -50 pj3 - ccp4 u1dcd epi0s28 ------- -52 pj4 - ccp2 u1dsr epi0s29 ------- -53 pj5 - ccp1 u1rts epi0s30 ------- -54 pj6 - ccp0 u1dtr -------- -55 pj7 a. the digital signals that are shaded gray are the power-on default values for the corresponding gpio pin. table 8-3. gpio pins and alternate functions (108bga) digital function (gpiopctl pmcx bit field encoding) a analog function pinio 11 10 9 8 7 6 5 4 3 2 1 -- u1rx i2c1scl ------ u0rx -l3 pa0 -- u1tx i2c1sda ------ u0tx -m3 pa1 -- i2s0rxsd ---- pwm4 txd2 - ssi0clk -m4 pa2 -- i2s0rxmclk ---- pwm5 txd1 - ssi0fss -l4 pa3 -- i2s0txsck --- can0rx pwm6 txd0 - ssi0rx -l5 pa4 -- i2s0txws --- can0tx pwm7 rxdv - ssi0tx -m5 pa5 -- u1cts usb0epen - can0rx pwm4 pwm0 rxck ccp1 i2c1scl -l6 pa6 -- u1dcd usb0pflt ccp3 can0tx pwm5 pwm1 rxer ccp4 i2c1sda -m6 pa7 ------ u1rx -- pwm2 ccp0 usb0id e12 pb0 ------ u1tx ccp1 - pwm3 ccp2 usb0vbus d12 pb1 --- usb0epen -- ccp0 ccp3 - idx0 i2c0scl -a11 pb2 --- usb0pflt --- fault3 - fault0 i2c0sda -e11 pb3 --- epi0s23 u1rx idx0 can0rx u2rx --- ain10 c0- a6 pb4 --- epi0s22 u1tx ccp2 can0tx ccp0 ccp6 ccp5 c0o ain11 c1- b7 pb5 -- i2s0txsck -- ccp5 idx0 fault1 c0o ccp7 ccp1 vrefa c0+ a7 pb6 ---- rxd1 -- nmi --- -a8 pb7 july 03, 2014 408 texas instruments-production data general-purpose input/outputs (gpios) table 8-3. gpio pins and alternate functions (108bga) (continued) digital function (gpiopctl pmcx bit field encoding) a analog function pinio 11 10 9 8 7 6 5 4 3 2 1 -------- tck swclk -- -a9 pc0 -------- tms swdio -- -b9 pc1 -------- tdi -- -b8 pc2 -------- tdo swo -- -a10 pc3 -- ccp1 epi0s2 - ccp4 ccp2 pwm6 txd3 pha0 ccp5 -l1 pc4 --- epi0s3 - usb0epen ccp3 fault2 c0o c1o ccp1 c1+ m1 pc5 --- epi0s4 usb0pflt ccp0 u1rx pwm7 c2o phb0 ccp3 c2+ m2 pc6 --- epi0s5 c1o usb0pflt u1tx ccp0 - phb0 ccp4 c2- l2 pc7 -- u1cts i2s0rxsck rxdv ccp6 u1rx u2rx idx0 can0rx pwm0 ain15 g1 pd0 phb1 ccp2 u1dcd i2s0rxws txer ccp7 u1tx u2tx pha0 can0tx pwm1 ain14 g2 pd1 --- epi0s20 --- ccp5 pwm2 ccp6 u1rx ain13 h2 pd2 --- epi0s21 --- ccp0 pwm3 ccp7 u1tx ain12 h1 pd3 - epi0s19 u1ri i2s0rxsd --- txd3 - ccp3 ccp0 ain7 b5 pd4 - epi0s28 u2rx i2s0rxmclk --- txd2 - ccp4 ccp2 ain6 c6 pd5 - epi0s29 u2tx i2s0txsck --- txd1 -- fault0 ain5 a3 pd6 - epi0s30 u1dtr i2s0txws --- txd0 ccp1 c0o idx0 ain4 a2 pd7 -- usb0pflt epi0s8 ---- ccp3 ssi1clk pwm4 -b11 pe0 --- epi0s9 -- ccp6 ccp2 fault0 ssi1fss pwm5 -a12 pe1 --- epi0s24 -- ccp2 pha0 phb1 ssi1rx ccp4 ain9 a4 pe2 --- epi0s25 -- ccp7 phb0 pha1 ssi1tx ccp1 ain8 b4 pe3 -- i2s0txws - rxd0 ccp2 u2tx fault0 -- ccp3 ain3 b2 pe4 -- i2s0txsd ------- ccp5 ain2 b3 pe5 -- u1cts ------ c1o pwm4 ain1 a1 pe6 -- u1dcd ------ c2o pwm5 ain0 b1 pe7 -- u1dsr i2s0txsd --- rxck pwm0 phb0 can1rx -m9 pf0 - ccp3 u1rts i2s0txmclk --- rxer pwm1 idx1 can1tx -h12 pf1 -- ssi1clk ---- pwm2 phyint pwm4 - -j11 pf2 -- ssi1fss ---- pwm3 mdc pwm5 - -j12 pf3 -- ssi1rx epi0s12 --- fault0 mdio c0o ccp0 -l9 pf4 -- ssi1tx epi0s15 ---- rxd3 c1o ccp2 -l8 pf5 - u1rts i2s0txmclk ---- pha0 rxd2 c2o ccp1 -m8 pf6 -- fault1 epi0s12 --- phb0 rxd1 - ccp4 -k4 pf7 --- epi0s13 usb0epen -- pwm4 i2c1scl pwm0 u2rx -k1 pg0 --- epi0s14 --- pwm5 i2c1sda pwm1 u2tx -k2 pg1 -- i2s0rxsd idx1 --- fault0 col - pwm0 -j1 pg2 -- i2s0rxmclk fault0 --- fault2 crs - pwm1 -j2 pg3 - u1ri pwm6 epi0s15 --- fault1 rxd0 - ccp3 -k3 pg4 - u1dtr i2s0rxsck pwm7 -- fault1 idx0 txen - ccp5 -m7 pg5 409 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 8-3. gpio pins and alternate functions (108bga) (continued) digital function (gpiopctl pmcx bit field encoding) a analog function pinio 11 10 9 8 7 6 5 4 3 2 1 - u1ri i2s0rxws fault1 --- pwm6 txck - pha1 -l7 pg6 -- epi0s31 ccp5 --- pwm7 txer - phb1 -c10 pg7 -- pwm4 epi0s6 ----- pwm2 ccp6 -c9 ph0 -- pwm5 epi0s7 ----- pwm3 ccp7 -c8 ph1 -- txd3 epi0s1 --- fault3 - c1o idx1 -d11 ph2 -- txd2 epi0s0 --- usb0epen - fault0 phb0 -d10 ph3 ssi1clk - txd1 epi0s10 --- usb0pflt --- -b10 ph4 ssi1fss fault2 txd0 epi0s11 ------- -f10 ph5 ssi1rx pwm4 rxdv epi0s26 ------- -g3 ph6 ssi1tx pwm5 - epi0s27 ---- rxck -- -h3 ph7 i2c1scl pwm0 - epi0s16 ---- rxer -- -f3 pj0 i2c1sda pwm1 usb0pflt epi0s17 ------- -b6 pj1 - fault0 ccp0 epi0s18 ------- -k6 pj2 - ccp6 u1cts epi0s19 ------- - m10 pj3 - ccp4 u1dcd epi0s28 ------- -k11 pj4 - ccp2 u1dsr epi0s29 ------- -k12 pj5 - ccp1 u1rts epi0s30 ------- -l10 pj6 - ccp0 u1dtr -------- -l12 pj7 a. the digital signals that are shaded gray are the power-on default values for the corresponding gpio pin. 8.2 functional description each gpio port is a separate hardware instantiation of the same physical block (see figure 8-1 on page 411 and figure 8-2 on page 412). the lm3s9gn5 microcontroller contains nine ports and thus nine of these physical gpio blocks. note that not all pins may be implemented on every block. some gpio pins can function as i/o signals for the on-chip peripheral modules. for information on which gpio pins are used for alternate hardware functions, refer to table 24-5 on page 1248. july 03, 2014 410 texas instruments-production data general-purpose input/outputs (gpios) figure 8-1. digital i/o pads 411 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 3 d g & r q w u r o & r p p l w & r q w u r o 0 r g h & r q w u r o * 3 , 2 $ ) 6 ( / ' d w d & r q w u r o , q w h u u x s w & r q w u r o 0 8 ; 0 8 ; ' ( 0 8 ; ' l j l w d o , 2 3 d g , g h q w l i l f d w l r q 5 h j l v w h u v * 3 , 2 3 h u l s k , ' * 3 , 2 3 h u l s k , ' * 3 , 2 3 h u l s k , ' * 3 , 2 3 h u l s k , ' * 3 , 2 3 h u l s k , ' * 3 , 2 3 h u l s k , ' * 3 , 2 3 h u l s k , ' * 3 , 2 3 h u l s k , ' * 3 , 2 3 & h o o , ' * 3 , 2 3 & h o o , ' * 3 , 2 3 & h o o , ' * 3 , 2 3 & h o o , ' 3 d g , q s x w 3 d g 2 x w s x w ( q d e o h * 3 , 2 / 2 & . * 3 , 2 & 5 * 3 , 2 ' $ 7 $ * 3 , 2 ' , 5 * 3 , 2 , 6 * 3 , 2 , % ( * 3 , 2 , ( 9 * 3 , 2 , 0 * 3 , 2 5 , 6 * 3 , 2 0 , 6 * 3 , 2 , & 5 * 3 , 2 ' 5 5 * 3 , 2 ' 5 5 * 3 , 2 ' 5 5 * 3 , 2 6 / 5 * 3 , 2 3 8 5 * 3 , 2 3 ' 5 * 3 , 2 2 ' 5 * 3 , 2 ' ( 1 $ o w h u q d w h , q s x w $ o w h u q d w h 2 x w s x w $ o w h u q d w h 2 x w s x w ( q d e o h , q w h u u x s w * 3 , 2 , q s x w * 3 , 2 2 x w s x w * 3 , 2 2 x w s x w ( q d e o h 3 d g 2 x w s x w 3 d f n d j h , 2 3 l q 0 8 ; 3 h u l s k 3 h u l s k 3 h u l s k q 3 r u w & r q w u r o * 3 , 2 3 & 7 / figure 8-2. analog/digital i/o pads 8.2.1 data control the data control registers allow software to configure the operational modes of the gpios. the data direction register configures the gpio as an input or an output while the data register either captures incoming data or drives it out to the pads. caution C it is possible to create a software sequence that prevents the debugger from connecting to the stellaris ? microcontroller. if the program code loaded into fash immediately changes the jtag pins to their gpio functionality, the debugger may not have enough time to connect and halt the controller before the jtag pin functionality switches. as a result, the debugger may be locked out of the part. this issue can be avoided with a software routine that restores jtag functionality based on an external or software trigger. 8.2.1.1 data direction operation the gpio direction (gpiodir) register (see page 420) is used to configure each individual pin as an input or output. when the data direction bit is cleared, the gpio is configured as an input, and the corresponding data register bit captures and stores the value on the gpio port. when the data direction bit is set, the gpio is configured as an output, and the corresponding data register bit is driven out on the gpio port. july 03, 2014 412 texas instruments-production data general-purpose input/outputs (gpios) 3 d g & r q w u r o ' d w d & r q w u r o * 3 , 2 , q s x w * 3 , 2 2 x w s x w * 3 , 2 2 x w s x w ( q d e o h , q w h u u x s w & r q w u r o , q w h u u x s w 0 8 ; 0 8 ; * 3 , 2 ' 5 5 * 3 , 2 ' 5 5 * 3 , 2 ' 5 5 * 3 , 2 6 / 5 * 3 , 2 3 8 5 * 3 , 2 3 ' 5 * 3 , 2 2 ' 5 * 3 , 2 ' ( 1 * 3 , 2 $ 0 6 ( / * 3 , 2 , ( 9 * 3 , 2 , 6 * 3 , 2 , % ( * 3 , 2 , 0 * 3 , 2 5 , 6 * 3 , 2 0 , 6 * 3 , 2 , & 5 * 3 , 2 ' $ 7 $ * 3 , 2 ' , 5 , g h q w l i l f d w l r q 5 h j l v w h u v * 3 , 2 3 h u l s k , ' * 3 , 2 3 h u l s k , ' * 3 , 2 3 h u l s k , ' * 3 , 2 3 h u l s k , ' * 3 , 2 3 h u l s k , ' * 3 , 2 3 h u l s k , ' * 3 , 2 3 h u l s k , ' * 3 , 2 3 h u l s k , ' * 3 , 2 3 & h o o , ' * 3 , 2 3 & h o o , ' * 3 , 2 3 & h o o , ' * 3 , 2 3 & h o o , ' $ q d o r j & l u f x l w u \ i r u * 3 , 2 s l q v w k d w f r q q h f w w r w k h $ ' & l q s x w 0 8 ; $ ' & , v r o d w l r q & l u f x l w 3 d g 2 x w s x w ( q d e o h 3 d f n d j h , 2 3 l q 3 d g , q s x w 3 d g 2 x w s x w $ q d o r j ' l j l w d o , 2 3 d g & r p p l w & r q w u r o 0 r g h & r q w u r o * 3 , 2 $ ) 6 ( / * 3 , 2 / 2 & . * 3 , 2 & 5 $ o w h u q d w h , q s x w $ o w h u q d w h 2 x w s x w $ o w h u q d w h 2 x w s x w ( q d e o h 0 8 ; 3 h u l s k 3 h u l s k 3 h u l s k q 3 r u w & r q w u r o * 3 , 2 3 & 7 / ' ( 0 8 ; 8.2.1.2 data register operation to aid in the efficiency of software, the gpio ports allow for the modification of individual bits in the gpio data (gpiodata) register (see page 419) by using bits [9:2] of the address bus as a mask. in this manner, software drivers can modify individual gpio pins in a single instruction without affecting the state of the other pins. this method is more efficient than the conventional method of performing a read-modify-write operation to set or clear an individual gpio pin. to implement this feature, the gpiodata register covers 256 locations in the memory map. during a write, if the address bit associated with that data bit is set, the value of the gpiodata register is altered. if the address bit is cleared, the data bit is left unchanged. for example, writing a value of 0xeb to the address gpiodata + 0x098 has the results shown in figure 8-3, where u indicates that data is unchanged by the write. figure 8-3. gpiodata write example during a read, if the address bit associated with the data bit is set, the value is read. if the address bit associated with the data bit is cleared, the data bit is read as a zero, regardless of its actual value. for example, reading address gpiodata + 0x0c4 yields as shown in figure 8-4. figure 8-4. gpiodata read example 8.2.2 interrupt control the interrupt capabilities of each gpio port are controlled by a set of seven registers. these registers are used to select the source of the interrupt, its polarity, and the edge properties. when one or more gpio inputs cause an interrupt, a single interrupt output is sent to the interrupt controller for the entire gpio port. for edge-triggered interrupts, software must clear the interrupt to enable any further interrupts. for a level-sensitive interrupt, the external source must hold the level constant for the interrupt to be recognized by the controller. three registers define the edge or sense that causes interrupts: gpio interrupt sense (gpiois) register (see page 421) 413 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller x x x x x * 3 , 2 ' $ 7 $ [ ( % [ $ ' ' 5 > @ 5 h w x u q h g 9 d o x h * 3 , 2 ' $ 7 $ [ & $ ' ' 5 > @ gpio interrupt both edges (gpioibe) register (see page 422) gpio interrupt event (gpioiev) register (see page 423) interrupts are enabled/disabled via the gpio interrupt mask (gpioim) register (see page 424). when an interrupt condition occurs, the state of the interrupt signal can be viewed in two locations: the gpio raw interrupt status (gpioris) and gpio masked interrupt status (gpiomis) registers (see page 425 and page 426). as the name implies, the gpiomis register only shows interrupt conditions that are allowed to be passed to the interrupt controller. the gpioris register indicates that a gpio pin meets the conditions for an interrupt, but has not necessarily been sent to the interrupt controller. interrupts are cleared by writing a 1 to the appropriate bit of the gpio interrupt clear (gpioicr) register (see page 428). when programming the interrupt control registers ( gpiois , gpioibe , or gpioiev ), the interrupts should be masked ( gpioim cleared). writing any value to an interrupt control register can generate a spurious interrupt if the corresponding bits are enabled. 8.2.2.1 adc trigger source in addition to providing gpio functionality, pb4 can also be used as an external trigger for the adc. if pb4 is configured as a non-masked interrupt pin (the appropriate bit of gpioim is set), an interrupt for port b is generated, and an external trigger signal is sent to the adc. if the adc event multiplexer select (adcemux) register is configured to use the external trigger, an adc conversion is initiated. see page 641. if no other port b pins are being used to generate interrupts, the interrupt 0-31 set enable (en0) register can disable the port b interrupts, and the adc interrupt can be used to read back the converted data. otherwise, the port b interrupt handler must ignore and clear interrupts on pb4 and wait for the adc interrupt, or the adc interrupt must be disabled in the en0 register and the port b interrupt handler must poll the adc registers until the conversion is completed. see page 127 for more information. 8.2.3 mode control the gpio pins can be controlled by either software or hardware. software control is the default for most signals and corresponds to the gpio mode, where the gpiodata register is used to read or write the corresponding pins. when hardware control is enabled via the gpio alternate function select (gpioafsel) register (see page 429), the pin state is controlled by its alternate function (that is, the peripheral). further pin muxing options are provided through the gpio port control (gpiopctl) register which selects one of several peripheral functions for each gpio. for information on the configuration options, refer to table 24-5 on page 1248. note: if any pin is to be used as an adc input, the appropriate bit in the gpioamsel register must be set to disable the analog isolation circuit. 8.2.4 commit control the gpio commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. protection is provided for the nmi pin ( pb7 ) and the four jtag/swd pins ( pc[3:0] ). writes to protected bits of the gpio alternate function select (gpioafsel) register (see page 429), gpio pull up select (gpiopur) register (see page 435), gpio pull-down select (gpiopdr) register (see page 437), and gpio digital enable (gpioden) register (see july 03, 2014 414 texas instruments-production data general-purpose input/outputs (gpios) page 440) are not committed to storage unless the gpio lock (gpiolock) register (see page 442) has been unlocked and the appropriate bits of the gpio commit (gpiocr) register (see page 443) have been set. 8.2.5 pad control the pad control registers allow software to configure the gpio pads based on the application requirements. the pad control registers include the gpiodr2r , gpiodr4r , gpiodr8r , gpioodr , gpiopur , gpiopdr , gpioslr , and gpioden registers. these registers control drive strength, open-drain configuration, pull-up and pull-down resistors, slew-rate control and digital input enable for each gpio. 8.2.6 identification the identification registers configured at reset allow software to detect and identify the module as a gpio block. the identification registers include the gpioperiphid0 -gpioperiphid7 registers as well as the gpiopcellid0 -gpiopcellid3 registers. 8.3 initialization and configuration the gpio modules may be accessed via two different memory apertures. the legacy aperture, the advanced peripheral bus (apb), is backwards-compatible with previous stellaris parts. the other aperture, the advanced high-performance bus (ahb), offers the same register map but provides better back-to-back access performance than the apb bus. these apertures are mutually exclusive. the aperture enabled for a given gpio port is controlled by the appropriate bit in the gpiohbctl register (see page 225). to use the pins in a particular gpio port, the clock for the port must be enabled by setting the appropriate gpio port bit field ( gpion ) in the rcgc2 register (see page 282). when the internal por signal is asserted and until otherwise configured, all gpio pins are configured to be undriven (tristate): gpioafsel =0, gpioden =0, gpiopdr =0, and gpiopur =0, except for the pins shown in table 8-1 on page 406. table 8-4 on page 415 shows all possible configurations of the gpio pads and the control register settings required to achieve them. table 8-5 on page 416 shows how a rising edge interrupt is configured for pin 2 of a gpio port. table 8-4. gpio pad configuration examples gpio register bit value a configuration slr dr8r dr4r dr2r pdr pur den odr dir afsel x x x x ? ? 1 0 0 0 digital input (gpio) ? ? ? ? ? ? 1 0 1 0 digital output (gpio) ? ? ? ? x x 1 1 1 0 open drain output (gpio) ? ? ? ? x x 1 1 x 1 open drain input/output (i 2 c) x x x x ? ? 1 0 x 1 digital input (timer ccp) x x x x ? ? 1 0 x 1 digital input (qei) ? ? ? ? ? ? 1 0 x 1 digital output (pwm) ? ? ? ? ? ? 1 0 x 1 digital output (timer pwm) ? ? ? ? ? ? 1 0 x 1 digital input/output (ssi) 415 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 8-4. gpio pad configuration examples (continued) gpio register bit value a configuration slr dr8r dr4r dr2r pdr pur den odr dir afsel ? ? ? ? ? ? 1 0 x 1 digital input/output (uart) x x x x 0 0 0 0 0 0 analog input (comparator) ? ? ? ? ? ? 1 0 x 1 digital output (comparator) a. x=ignored (dont care bit) ?=can be either 0 or 1, depending on the configuration table 8-5. gpio interrupt configuration example pin 2 bit value a desired interrupt event trigger register 0 1 2 3 4 5 6 7 x x 0 x x x x x 0=edge 1=level gpiois x x 0 x x x x x 0=single edge 1=both edges gpioibe x x 1 x x x x x 0=low level, or falling edge 1=high level, or rising edge gpioiev 0 0 1 0 0 0 0 0 0=masked 1=not masked gpioim a. x=ignored (dont care bit) 8.4 register map table 8-7 on page 417 lists the gpio registers. each gpio port can be accessed through one of two bus apertures. the legacy aperture, the advanced peripheral bus (apb), is backwards-compatible with previous stellaris parts. the other aperture, the advanced high-performance bus (ahb), offers the same register map but provides better back-to-back access performance than the apb bus. important: the gpio registers in this chapter are duplicated in each gpio block; however, depending on the block, all eight bits may not be connected to a gpio pad. in those cases, writing to unconnected bits has no effect, and reading unconnected bits returns no meaningful data. the offset listed is a hexadecimal increment to the registers address, relative to that gpio ports base address: gpio port a (apb): 0x4000.4000 gpio port a (ahb): 0x4005.8000 gpio port b (apb): 0x4000.5000 gpio port b (ahb): 0x4005.9000 gpio port c (apb): 0x4000.6000 gpio port c (ahb): 0x4005.a000 gpio port d (apb): 0x4000.7000 gpio port d (ahb): 0x4005.b000 july 03, 2014 416 texas instruments-production data general-purpose input/outputs (gpios) gpio port e (apb): 0x4002.4000 gpio port e (ahb): 0x4005.c000 gpio port f (apb): 0x4002.5000 gpio port f (ahb): 0x4005.d000 gpio port g (apb): 0x4002.6000 gpio port g (ahb): 0x4005.e000 gpio port h (apb): 0x4002.7000 gpio port h (ahb): 0x4005.f000 gpio port j (apb): 0x4003.d000 gpio port j (ahb): 0x4006.0000 note that each gpio module clock must be enabled before the registers can be programmed (see page 282). there must be a delay of 3 system clocks after the gpio module clock is enabled before any gpio module registers are accessed. important: all gpio pins are configured as gpios and tri-stated by default ( gpioafsel =0, gpioden =0, gpiopdr =0, gpiopur =0, and gpiopctl =0, with the exception of the pins shown in the table below. a power-on-reset ( por ) or asserting rst puts the pins back to their default state. table 8-6. gpio pins with non-zero reset values gpiopctl gpiopur gpiopdr gpioden gpioafsel default state gpio pins 0x1 0 0 0 0 uart0 pa[1:0] 0x1 0 0 0 0 ssi0 pa[5:2] 0x1 0 0 0 0 i 2 c0 pb[3:2] 0x3 1 0 1 1 jtag/swd pc[3:0] the default register type for the gpiocr register is ro for all gpio pins with the exception of the nmi pin and the four jtag/swd pins ( pb7 and pc[3:0] ). these five pins are the only gpios that are protected by the gpiocr register. because of this, the register type for gpio port b7 and gpio port c[3:0] is r/w. the default reset value for the gpiocr register is 0x0000.00ff for all gpio pins, with the exception of the nmi pin and the four jtag/swd pins ( pb7 and pc[3:0] ). to ensure that the jtag port is not accidentally programmed as gpio pins, the pc[3:0] pins default to non-committable. similarly, to ensure that the nmi pin is not accidentally programmed as a gpio pin, the pb7 pin defaults to non-committable. because of this, the default reset value of gpiocr for gpio port b is 0x0000.007f while the default reset value of gpiocr for port c is 0x0000.00f0. table 8-7. gpio register map see page description reset type name offset 419 gpio data 0x0000.0000 r/w gpiodata 0x000 420 gpio direction 0x0000.0000 r/w gpiodir 0x400 421 gpio interrupt sense 0x0000.0000 r/w gpiois 0x404 422 gpio interrupt both edges 0x0000.0000 r/w gpioibe 0x408 423 gpio interrupt event 0x0000.0000 r/w gpioiev 0x40c 417 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 8-7. gpio register map (continued) see page description reset type name offset 424 gpio interrupt mask 0x0000.0000 r/w gpioim 0x410 425 gpio raw interrupt status 0x0000.0000 ro gpioris 0x414 426 gpio masked interrupt status 0x0000.0000 ro gpiomis 0x418 428 gpio interrupt clear 0x0000.0000 w1c gpioicr 0x41c 429 gpio alternate function select - r/w gpioafsel 0x420 431 gpio 2-ma drive select 0x0000.00ff r/w gpiodr2r 0x500 432 gpio 4-ma drive select 0x0000.0000 r/w gpiodr4r 0x504 433 gpio 8-ma drive select 0x0000.0000 r/w gpiodr8r 0x508 434 gpio open drain select 0x0000.0000 r/w gpioodr 0x50c 435 gpio pull-up select - r/w gpiopur 0x510 437 gpio pull-down select 0x0000.0000 r/w gpiopdr 0x514 439 gpio slew rate control select 0x0000.0000 r/w gpioslr 0x518 440 gpio digital enable - r/w gpioden 0x51c 442 gpio lock 0x0000.0001 r/w gpiolock 0x520 443 gpio commit - - gpiocr 0x524 445 gpio analog mode select 0x0000.0000 r/w gpioamsel 0x528 447 gpio port control - r/w gpiopctl 0x52c 449 gpio peripheral identification 4 0x0000.0000 ro gpioperiphid4 0xfd0 450 gpio peripheral identification 5 0x0000.0000 ro gpioperiphid5 0xfd4 451 gpio peripheral identification 6 0x0000.0000 ro gpioperiphid6 0xfd8 452 gpio peripheral identification 7 0x0000.0000 ro gpioperiphid7 0xfdc 453 gpio peripheral identification 0 0x0000.0061 ro gpioperiphid0 0xfe0 454 gpio peripheral identification 1 0x0000.0000 ro gpioperiphid1 0xfe4 455 gpio peripheral identification 2 0x0000.0018 ro gpioperiphid2 0xfe8 456 gpio peripheral identification 3 0x0000.0001 ro gpioperiphid3 0xfec 457 gpio primecell identification 0 0x0000.000d ro gpiopcellid0 0xff0 458 gpio primecell identification 1 0x0000.00f0 ro gpiopcellid1 0xff4 459 gpio primecell identification 2 0x0000.0005 ro gpiopcellid2 0xff8 460 gpio primecell identification 3 0x0000.00b1 ro gpiopcellid3 0xffc 8.5 register descriptions the remainder of this section lists and describes the gpio registers, in numerical order by address offset. july 03, 2014 418 texas instruments-production data general-purpose input/outputs (gpios) register 1: gpio data (gpiodata), offset 0x000 the gpiodata register is the data register. in software control mode, values written in the gpiodata register are transferred onto the gpio port pins if the respective pins have been configured as outputs through the gpio direction (gpiodir) register (see page 420). in order to write to gpiodata , the corresponding bits in the mask, resulting from the address bus bits [9:2], must be set. otherwise, the bit values remain unchanged by the write. similarly, the values read from this register are determined for each bit by the mask bit derived from the address used to access the data register, bits [9:2]. bits that are set in the address mask cause the corresponding bits in gpiodata to be read, and bits that are clear in the address mask cause the corresponding bits in gpiodata to be read as 0, regardless of their value. a read from gpiodata returns the last bit value written if the respective pins are configured as outputs, or it returns the value on the corresponding input pin when these are configured as inputs. all bits are cleared by a reset. gpio data (gpiodata) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0x000 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 data reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 gpio data this register is virtually mapped to 256 locations in the address space. to facilitate the reading and writing of data to these registers by independent drivers, the data read from and written to the registers are masked by the eight address lines [9:2]. reads from this register return its current state. writes to this register only affect bits that are not masked by addr[9:2] and are configured as outputs. see data register operation on page 413 for examples of reads and writes. 0x00 r/w data 7:0 419 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 2: gpio direction (gpiodir), offset 0x400 the gpiodir register is the data direction register. setting a bit in the gpiodir register configures the corresponding pin to be an output, while clearing a bit configures the corresponding pin to be an input. all bits are cleared by a reset, meaning all gpio pins are inputs by default. gpio direction (gpiodir) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0x400 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dir reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 gpio data direction description value corresponding pin is an input. 0 corresponding pins is an output. 1 0x00 r/w dir 7:0 july 03, 2014 420 texas instruments-production data general-purpose input/outputs (gpios) register 3: gpio interrupt sense (gpiois), offset 0x404 the gpiois register is the interrupt sense register. setting a bit in the gpiois register configures the corresponding pin to detect levels, while clearing a bit configures the corresponding pin to detect edges. all bits are cleared by a reset. gpio interrupt sense (gpiois) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0x404 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 is reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 gpio interrupt sense description value the edge on the corresponding pin is detected (edge-sensitive). 0 the level on the corresponding pin is detected (level-sensitive). 1 0x00 r/w is 7:0 421 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 4: gpio interrupt both edges (gpioibe), offset 0x408 the gpioibe register allows both edges to cause interrupts. when the corresponding bit in the gpio interrupt sense (gpiois) register (see page 421) is set to detect edges, setting a bit in the gpioibe register configures the corresponding pin to detect both rising and falling edges, regardless of the corresponding bit in the gpio interrupt event (gpioiev) register (see page 423). clearing a bit configures the pin to be controlled by the gpioiev register. all bits are cleared by a reset. gpio interrupt both edges (gpioibe) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0x408 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ibe reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 gpio interrupt both edges description value interrupt generation is controlled by the gpio interrupt event (gpioiev) register (see page 423). 0 both edges on the corresponding pin trigger an interrupt. 1 0x00 r/w ibe 7:0 july 03, 2014 422 texas instruments-production data general-purpose input/outputs (gpios) register 5: gpio interrupt event (gpioiev), offset 0x40c the gpioiev register is the interrupt event register. setting a bit in the gpioiev register configures the corresponding pin to detect rising edges or high levels, depending on the corresponding bit value in the gpio interrupt sense (gpiois) register (see page 421). clearing a bit configures the pin to detect falling edges or low levels, depending on the corresponding bit value in the gpiois register. all bits are cleared by a reset. gpio interrupt event (gpioiev) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0x40c type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 iev reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 gpio interrupt event description value a falling edge or a low level on the corresponding pin triggers an interrupt. 0 a rising edge or a high level on the corresponding pin triggers an interrupt. 1 0x00 r/w iev 7:0 423 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 6: gpio interrupt mask (gpioim), offset 0x410 the gpioim register is the interrupt mask register. setting a bit in the gpioim register allows interrupts that are generated by the corresponding pin to be sent to the interrupt controller on the combined interrupt signal. clearing a bit prevents an interrupt on the corresponding pin from being sent to the interrupt controller. all bits are cleared by a reset. gpio interrupt mask (gpioim) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0x410 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ime reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:8 gpio interrupt mask enable description value the interrupt from the corresponding pin is masked. 0 the interrupt from the corresponding pin is sent to the interrupt controller. 1 0x00 r/w ime 7:0 july 03, 2014 424 texas instruments-production data general-purpose input/outputs (gpios) register 7: gpio raw interrupt status (gpioris), offset 0x414 the gpioris register is the raw interrupt status register. a bit in this register is set when an interrupt condition occurs on the corresponding gpio pin. if the corresponding bit in the gpio interrupt mask (gpioim) register (see page 424) is set, the interrupt is sent to the interrupt controller. bits read as zero indicate that corresponding input pins have not initiated an interrupt. a bit in this register can be cleared by writing a 1 to the corresponding bit in the gpio interrupt clear (gpioicr) register. gpio raw interrupt status (gpioris) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0x414 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ris reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:8 gpio interrupt raw status description value an interrupt condition has occurred on the corresponding pin. 1 an interrupt condition has not occurred on the corresponding pin. 0 a bit is cleared by writing a 1 to the corresponding bit in the gpioicr register. 0x00 ro ris 7:0 425 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 8: gpio masked interrupt status (gpiomis), offset 0x418 the gpiomis register is the masked interrupt status register. if a bit is set in this register, the corresponding interrupt has triggered an interrupt to the interrupt controller. if a bit is clear, either no interrupt has been generated, or the interrupt is masked. in addition to providing gpio functionality, pb4 can also be used as an external trigger for the adc. if pb4 is configured as a non-masked interrupt pin (the appropriate bit of gpioim is set), an interrupt for port b is generated, and an external trigger signal is sent to the adc. if the adc event multiplexer select (adcemux) register is configured to use the external trigger, an adc conversion is initiated. see page 641. if no other port b pins are being used to generate interrupts, the interrupt 0-31 set enable (en0) register can disable the port b interrupts, and the adc interrupt can be used to read back the converted data. otherwise, the port b interrupt handler must ignore and clear interrupts on pb4 and wait for the adc interrupt, or the adc interrupt must be disabled in the en0 register and the port b interrupt handler must poll the adc registers until the conversion is completed. see page 127 for more information. gpiomis is the state of the interrupt after masking. gpio masked interrupt status (gpiomis) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0x418 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mis reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:8 july 03, 2014 426 texas instruments-production data general-purpose input/outputs (gpios) description reset type name bit/field gpio masked interrupt status description value an interrupt condition on the corresponding pin has triggered an interrupt to the interrupt controller. 1 an interrupt condition on the corresponding pin is masked or has not occurred. 0 a bit is cleared by writing a 1 to the corresponding bit in the gpioicr register. 0x00 ro mis 7:0 427 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 9: gpio interrupt clear (gpioicr), offset 0x41c the gpioicr register is the interrupt clear register. writing a 1 to a bit in this register clears the corresponding interrupt bit in the gpioris and gpiomis registers. writing a 0 has no effect. gpio interrupt clear (gpioicr) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0x41c type w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ic reserved w1c w1c w1c w1c w1c w1c w1c w1c ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:8 gpio interrupt clear description value the corresponding interrupt is cleared. 1 the corresponding interrupt is unaffected. 0 0x00 w1c ic 7:0 july 03, 2014 428 texas instruments-production data general-purpose input/outputs (gpios) register 10: gpio alternate function select (gpioafsel), offset 0x420 the gpioafsel register is the mode control select register. if a bit is clear, the pin is used as a gpio and is controlled by the gpio registers. setting a bit in this register configures the corresponding gpio line to be controlled by an associated peripheral. several possible peripheral functions are multiplexed on each gpio. the gpio port control (gpiopctl) register is used to select one of the possible functions. table 24-5 on page 1248 details which functions are muxed on each gpio pin. the reset value for this register is 0x0000.0000 for gpio ports that are not listed in the table below. important: all gpio pins are configured as gpios and tri-stated by default ( gpioafsel =0, gpioden =0, gpiopdr =0, gpiopur =0, and gpiopctl =0, with the exception of the pins shown in the table below. a power-on-reset ( por ) or asserting rst puts the pins back to their default state. table 8-8. gpio pins with non-zero reset values gpiopctl gpiopur gpiopdr gpioden gpioafsel default state gpio pins 0x1 0 0 0 0 uart0 pa[1:0] 0x1 0 0 0 0 ssi0 pa[5:2] 0x1 0 0 0 0 i 2 c0 pb[3:2] 0x3 1 0 1 1 jtag/swd pc[3:0] caution C it is possible to create a software sequence that prevents the debugger from connecting to the stellaris microcontroller. if the program code loaded into fash immediately changes the jtag pins to their gpio functionality, the debugger may not have enough time to connect and halt the controller before the jtag pin functionality switches. as a result, the debugger may be locked out of the part. this issue can be avoided with a software routine that restores jtag functionality based on an external or software trigger. the gpio commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. protection is provided for the nmi pin ( pb7 ) and the four jtag/swd pins ( pc[3:0] ). writes to protected bits of the gpio alternate function select (gpioafsel) register (see page 429), gpio pull up select (gpiopur) register (see page 435), gpio pull-down select (gpiopdr) register (see page 437), and gpio digital enable (gpioden) register (see page 440) are not committed to storage unless the gpio lock (gpiolock) register (see page 442) has been unlocked and the appropriate bits of the gpio commit (gpiocr) register (see page 443) have been set. when using the i 2 c module, in addition to setting the gpioafsel register bits for the i 2 c clock and data pins, the data pins should be set to open drain using the gpio open drain select (gpioodr) register (see examples in initialization and configuration on page 415). 429 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller gpio alternate function select (gpioafsel) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0x420 type r/w, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 afsel reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type - - - - - - - - 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 gpio alternate function select description value the associated pin functions as a gpio and is controlled by the gpio registers. 0 the associated pin functions as a peripheral signal and is controlled by the alternate hardware function. the reset value for this register is 0x0000.0000 for gpio ports that are not listed in table 8-1 on page 406. 1 - r/w afsel 7:0 july 03, 2014 430 texas instruments-production data general-purpose input/outputs (gpios) register 11: gpio 2-ma drive select (gpiodr2r), offset 0x500 the gpiodr2r register is the 2-ma drive control register. each gpio signal in the port can be individually configured without affecting the other pads. when setting the drv2 bit for a gpio signal, the corresponding drv4 bit in the gpiodr4r register and drv8 bit in the gpiodr8r register are automatically cleared by hardware. by default, all gpio pins have 2-ma drive. gpio 2-ma drive select (gpiodr2r) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0x500 type r/w, reset 0x0000.00ff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 drv2 reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 output pad 2-ma drive enable description value the corresponding gpio pin has 2-ma drive. 1 the drive for the corresponding gpio pin is controlled by the gpiodr4r or gpiodr8r register. 0 setting a bit in either the gpiodr4 register or the gpiodr8 register clears the corresponding 2-ma enable bit. the change is effective on the second clock cycle after the write if accessing gpio via the apb memory aperture. if using ahb access, the change is effective on the next clock cycle. 0xff r/w drv2 7:0 431 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 12: gpio 4-ma drive select (gpiodr4r), offset 0x504 the gpiodr4r register is the 4-ma drive control register. each gpio signal in the port can be individually configured without affecting the other pads. when setting the drv4 bit for a gpio signal, the corresponding drv2 bit in the gpiodr2r register and drv8 bit in the gpiodr8r register are automatically cleared by hardware. gpio 4-ma drive select (gpiodr4r) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0x504 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 drv4 reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 output pad 4-ma drive enable description value the corresponding gpio pin has 4-ma drive. 1 the drive for the corresponding gpio pin is controlled by the gpiodr2r or gpiodr8r register. 0 setting a bit in either the gpiodr2 register or the gpiodr8 register clears the corresponding 4-ma enable bit. the change is effective on the second clock cycle after the write if accessing gpio via the apb memory aperture. if using ahb access, the change is effective on the next clock cycle. 0x00 r/w drv4 7:0 july 03, 2014 432 texas instruments-production data general-purpose input/outputs (gpios) register 13: gpio 8-ma drive select (gpiodr8r), offset 0x508 the gpiodr8r register is the 8-ma drive control register. each gpio signal in the port can be individually configured without affecting the other pads. when setting the drv8 bit for a gpio signal, the corresponding drv2 bit in the gpiodr2r register and drv4 bit in the gpiodr4r register are automatically cleared by hardware. the 8-ma setting is also used for high-current operation. note: there is no configuration difference between 8-ma and high-current operation. the additional current capacity results from a shift in the v oh /v ol levels. see recommended operating conditions on page 1298 for further information. gpio 8-ma drive select (gpiodr8r) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0x508 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 drv8 reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 output pad 8-ma drive enable description value the corresponding gpio pin has 8-ma drive. 1 the drive for the corresponding gpio pin is controlled by the gpiodr2r or gpiodr4r register. 0 setting a bit in either the gpiodr2 register or the gpiodr4 register clears the corresponding 8-ma enable bit. the change is effective on the second clock cycle after the write if accessing gpio via the apb memory aperture. if using ahb access, the change is effective on the next clock cycle. 0x00 r/w drv8 7:0 433 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 14: gpio open drain select (gpioodr), offset 0x50c the gpioodr register is the open drain control register. setting a bit in this register enables the open-drain configuration of the corresponding gpio pad. when open-drain mode is enabled, the corresponding bit should also be set in the gpio digital enable (gpioden) register (see page 440). corresponding bits in the drive strength and slew rate control registers ( gpiodr2r , gpiodr4r , gpiodr8r , and gpioslr ) can be set to achieve the desired rise and fall times. the gpio acts as an input if the corresponding bit in the gpiodir register is cleared. if open drain is selected while the gpio is configured as an input, the gpio will remain an input and the open-drain selection has no effect until the gpio is changed to an output. when using the i 2 c module, in addition to configuring the pin to open drain, the gpio alternate function select (gpioafsel) register bits for the i 2 c clock and data pins should be set (see examples in initialization and configuration on page 415). gpio open drain select (gpioodr) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0x50c type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ode reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 output pad open drain enable description value the corresponding pin is configured as open drain. 1 the corresponding pin is not configured as open drain. 0 0x00 r/w ode 7:0 july 03, 2014 434 texas instruments-production data general-purpose input/outputs (gpios) register 15: gpio pull-up select (gpiopur), offset 0x510 the gpiopur register is the pull-up control register. when a bit is set, a weak pull-up resistor on the corresponding gpio signal is enabled. setting a bit in gpiopur automatically clears the corresponding bit in the gpio pull-down select (gpiopdr) register (see page 437). write access to this register is protected with the gpiocr register. bits in gpiocr that are cleared prevent writes to the equivalent bit in this register. important: all gpio pins are configured as gpios and tri-stated by default ( gpioafsel =0, gpioden =0, gpiopdr =0, gpiopur =0, and gpiopctl =0, with the exception of the pins shown in the table below. a power-on-reset ( por ) or asserting rst puts the pins back to their default state. table 8-9. gpio pins with non-zero reset values gpiopctl gpiopur gpiopdr gpioden gpioafsel default state gpio pins 0x1 0 0 0 0 uart0 pa[1:0] 0x1 0 0 0 0 ssi0 pa[5:2] 0x1 0 0 0 0 i 2 c0 pb[3:2] 0x3 1 0 1 1 jtag/swd pc[3:0] note: the gpio commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. protection is provided for the nmi pin ( pb7) and the four jtag/swd pins ( pc[3:0] ). writes to protected bits of the gpio alternate function select (gpioafsel) register (see page 429), gpio pull up select (gpiopur) register (see page 435), gpio pull-down select (gpiopdr) register (see page 437), and gpio digital enable (gpioden) register (see page 440) are not committed to storage unless the gpio lock (gpiolock) register (see page 442) has been unlocked and the appropriate bits of the gpio commit (gpiocr) register (see page 443) have been set. gpio pull-up select (gpiopur) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0x510 type r/w, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pue reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type - - - - - - - - 0 0 0 0 0 0 0 0 reset 435 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 pad weak pull-up enable description value the corresponding pin's weak pull-up resistor is disabled. 0 the corresponding pin's weak pull-up resistor is enabled. 1 setting a bit in the gpiopdr register clears the corresponding bit in the gpiopur register. the change is effective on the second clock cycle after the write if accessing gpio via the apb memory aperture. if using ahb access, the change is effective on the next clock cycle. the reset value for this register is 0x0000.0000 for gpio ports that are not listed in table 8-1 on page 406. - r/w pue 7:0 july 03, 2014 436 texas instruments-production data general-purpose input/outputs (gpios) register 16: gpio pull-down select (gpiopdr), offset 0x514 the gpiopdr register is the pull-down control register. when a bit is set, a weak pull-down resistor on the corresponding gpio signal is enabled. setting a bit in gpiopdr automatically clears the corresponding bit in the gpio pull-up select (gpiopur) register (see page 435). important: all gpio pins are configured as gpios and tri-stated by default ( gpioafsel =0, gpioden =0, gpiopdr =0, gpiopur =0, and gpiopctl =0, with the exception of the pins shown in the table below. a power-on-reset ( por ) or asserting rst puts the pins back to their default state. table 8-10. gpio pins with non-zero reset values gpiopctl gpiopur gpiopdr gpioden gpioafsel default state gpio pins 0x1 0 0 0 0 uart0 pa[1:0] 0x1 0 0 0 0 ssi0 pa[5:2] 0x1 0 0 0 0 i 2 c0 pb[3:2] 0x3 1 0 1 1 jtag/swd pc[3:0] note: the gpio commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. protection is provided for the nmi pin ( pb7) and the four jtag/swd pins ( pc[3:0] ). writes to protected bits of the gpio alternate function select (gpioafsel) register (see page 429), gpio pull up select (gpiopur) register (see page 435), gpio pull-down select (gpiopdr) register (see page 437), and gpio digital enable (gpioden) register (see page 440) are not committed to storage unless the gpio lock (gpiolock) register (see page 442) has been unlocked and the appropriate bits of the gpio commit (gpiocr) register (see page 443) have been set. gpio pull-down select (gpiopdr) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0x514 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pde reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 437 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 pad weak pull-down enable description value the corresponding pin's weak pull-down resistor is disabled. 0 the corresponding pin's weak pull-down resistor is enabled. 1 setting a bit in the gpiopur register clears the corresponding bit in the gpiopdr register. the change is effective on the second clock cycle after the write if accessing gpio via the apb memory aperture. if using ahb access, the change is effective on the next clock cycle. 0x00 r/w pde 7:0 july 03, 2014 438 texas instruments-production data general-purpose input/outputs (gpios) register 17: gpio slew rate control select (gpioslr), offset 0x518 the gpioslr register is the slew rate control register. slew rate control is only available when using the 8-ma drive strength option via the gpio 8-ma drive select (gpiodr8r) register (see page 433). gpio slew rate control select (gpioslr) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0x518 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 srl reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 slew rate limit enable (8-ma drive only) description value slew rate control is enabled for the corresponding pin. 1 slew rate control is disabled for the corresponding pin. 0 0x00 r/w srl 7:0 439 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 18: gpio digital enable (gpioden), offset 0x51c note: pins configured as digital inputs are schmitt-triggered. the gpioden register is the digital enable register. by default, all gpio signals except those listed below are configured out of reset to be undriven (tristate). their digital function is disabled; they do not drive a logic value on the pin and they do not allow the pin voltage into the gpio receiver. to use the pin as a digital input or output (either gpio or alternate function), the corresponding gpioden bit must be set. important: all gpio pins are configured as gpios and tri-stated by default ( gpioafsel =0, gpioden =0, gpiopdr =0, gpiopur =0, and gpiopctl =0, with the exception of the pins shown in the table below. a power-on-reset ( por ) or asserting rst puts the pins back to their default state. table 8-11. gpio pins with non-zero reset values gpiopctl gpiopur gpiopdr gpioden gpioafsel default state gpio pins 0x1 0 0 0 0 uart0 pa[1:0] 0x1 0 0 0 0 ssi0 pa[5:2] 0x1 0 0 0 0 i 2 c0 pb[3:2] 0x3 1 0 1 1 jtag/swd pc[3:0] note: the gpio commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. protection is provided for the nmi pin ( pb7) and the four jtag/swd pins ( pc[3:0] ). writes to protected bits of the gpio alternate function select (gpioafsel) register (see page 429), gpio pull up select (gpiopur) register (see page 435), gpio pull-down select (gpiopdr) register (see page 437), and gpio digital enable (gpioden) register (see page 440) are not committed to storage unless the gpio lock (gpiolock) register (see page 442) has been unlocked and the appropriate bits of the gpio commit (gpiocr) register (see page 443) have been set. july 03, 2014 440 texas instruments-production data general-purpose input/outputs (gpios) gpio digital enable (gpioden) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0x51c type r/w, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 den reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type - - - - - - - - 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 digital enable description value the digital functions for the corresponding pin are disabled. 0 the digital functions for the corresponding pin are enabled. the reset value for this register is 0x0000.0000 for gpio ports that are not listed in table 8-1 on page 406. 1 - r/w den 7:0 441 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 19: gpio lock (gpiolock), offset 0x520 the gpiolock register enables write access to the gpiocr register (see page 443). writing 0x4c4f.434b to the gpiolock register unlocks the gpiocr register. writing any other value to the gpiolock register re-enables the locked state. reading the gpiolock register returns the lock status rather than the 32-bit value that was previously written. therefore, when write accesses are disabled, or locked, reading the gpiolock register returns 0x0000.0001. when write accesses are enabled, or unlocked, reading the gpiolock register returns 0x0000.0000. gpio lock (gpiolock) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0x520 type r/w, reset 0x0000.0001 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lock r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 lock r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field gpio lock a write of the value 0x4c4f.434b unlocks the gpio commit (gpiocr) register for write access.a write of any other value or a write to the gpiocr register reapplies the lock, preventing any register updates. a read of this register returns the following values: description value the gpiocr register is locked and may not be modified. 0x1 the gpiocr register is unlocked and may be modified. 0x0 0x0000.0001 r/w lock 31:0 july 03, 2014 442 texas instruments-production data general-purpose input/outputs (gpios) register 20: gpio commit (gpiocr), offset 0x524 the gpiocr register is the commit register. the value of the gpiocr register determines which bits of the gpioafsel , gpiopur , gpiopdr , and gpioden registers are committed when a write to these registers is performed. if a bit in the gpiocr register is cleared, the data being written to the corresponding bit in the gpioafsel , gpiopur , gpiopdr , or gpioden registers cannot be committed and retains its previous value. if a bit in the gpiocr register is set, the data being written to the corresponding bit of the gpioafsel , gpiopur , gpiopdr , or gpioden registers is committed to the register and reflects the new value. the contents of the gpiocr register can only be modified if the status in the gpiolock register is unlocked. writes to the gpiocr register are ignored if the status in the gpiolock register is locked. important: this register is designed to prevent accidental programming of the registers that control connectivity to the nmi and jtag/swd debug hardware. by initializing the bits of the gpiocr register to 0 for pb7 and pc[3:0] , the nmi and jtag/swd debug port can only be converted to gpios through a deliberate set of writes to the gpiolock , gpiocr , and the corresponding registers. because this protection is currently only implemented on the nmi and jtag/swd pins on pb7 and pc[3:0] , all of the other bits in the gpiocr registers cannot be written with 0x0. these bits are hardwired to 0x1, ensuring that it is always possible to commit new values to the gpioafsel , gpiopur , gpiopdr , or gpioden register bits of these other pins. gpio commit (gpiocr) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0x524 type -, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cr reserved - - - - - - - - ro ro ro ro ro ro ro ro type - - - - - - - - 0 0 0 0 0 0 0 0 reset 443 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 gpio commit description value the corresponding gpioafsel , gpiopur , gpiopdr , or gpioden bits can be written. 1 the corresponding gpioafsel , gpiopur , gpiopdr , or gpioden bits cannot be written. 0 note: the default register type for the gpiocr register is ro for all gpio pins with the exception of the nmi pin and the four jtag/swd pins ( pb7 and pc[3:0] ). these five pins are the only gpios that are protected by the gpiocr register. because of this, the register type for gpio port b7 and gpio port c[3:0] is r/w. the default reset value for the gpiocr register is 0x0000.00ff for all gpio pins, with the exception of the nmi pin and the four jtag/swd pins ( pb7 and pc[3:0] ). to ensure that the jtag port is not accidentally programmed as gpio pins, the pc[3:0] pins default to non-committable. similarly, to ensure that the nmi pin is not accidentally programmed as a gpio pin, the pb7 pin defaults to non-committable. because of this, the default reset value of gpiocr for gpio port b is 0x0000.007f while the default reset value of gpiocr for port c is 0x0000.00f0. - - cr 7:0 july 03, 2014 444 texas instruments-production data general-purpose input/outputs (gpios) register 21: gpio analog mode select (gpioamsel), offset 0x528 important: this register is only valid for ports d and e; the corresponding base addresses for the remaining ports are not valid. if any pin is to be used as an adc input, the appropriate bit in gpioamsel must be set to disable the analog isolation circuit. the gpioamsel register controls isolation circuits to the analog side of a unified i/o pad. because the gpios may be driven by a 5-v source and affect analog operation, analog circuitry requires isolation from the pins when they are not used in their analog function. each bit of this register controls the isolation circuitry for the corresponding gpio signal. for information on which gpio pins can be used for adc functions, refer to table 24-5 on page 1248. gpio analog mode select (gpioamsel) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0x528 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 gpioamsel reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 445 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field gpio analog mode select description value the analog function of the pin is enabled, the isolation is disabled, and the pin is capable of analog functions. 1 the analog function of the pin is disabled, the isolation is enabled, and the pin is capable of digital functions as specified by the other gpio configuration registers. 0 note: this register and bits are only valid for gpio signals that share analog function through a unified i/o pad. the reset state of this register is 0 for all signals. 0x00 r/w gpioamsel 7:0 july 03, 2014 446 texas instruments-production data general-purpose input/outputs (gpios) register 22: gpio port control (gpiopctl), offset 0x52c the gpiopctl register is used in conjunction with the gpioafsel register and selects the specific peripheral signal for each gpio pin when using the alternate function mode. most bits in the gpioafsel register are cleared on reset, therefore most gpio pins are configured as gpios by default. when a bit is set in the gpioafsel register, the corresponding gpio signal is controlled by an associated peripheral. the gpiopctl register selects one out of a set of peripheral functions for each gpio, providing additional flexibility in signal definition. for information on the defined encodings for the bit fields in this register, refer to table 24-5 on page 1248. the reset value for this register is 0x0000.0000 for gpio ports that are not listed in the table below. note: if the same signal is assigned to two different gpio port pins, the signal is assigned to the port with the lowest letter and the assignment to the higher letter port is ignored. important: all gpio pins are configured as gpios and tri-stated by default ( gpioafsel =0, gpioden =0, gpiopdr =0, gpiopur =0, and gpiopctl =0, with the exception of the pins shown in the table below. a power-on-reset ( por ) or asserting rst puts the pins back to their default state. table 8-12. gpio pins with non-zero reset values gpiopctl gpiopur gpiopdr gpioden gpioafsel default state gpio pins 0x1 0 0 0 0 uart0 pa[1:0] 0x1 0 0 0 0 ssi0 pa[5:2] 0x1 0 0 0 0 i 2 c0 pb[3:2] 0x3 1 0 1 1 jtag/swd pc[3:0] gpio port control (gpiopctl) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0x52c type r/w, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 pmc4 pmc5 pmc6 pmc7 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type - - - - - - - - - - - - - - - - reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pmc0 pmc1 pmc2 pmc3 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type - - - - - - - - - - - - - - - - reset 447 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field port mux control 7 this field controls the configuration for gpio pin 7. - r/w pmc7 31:28 port mux control 6 this field controls the configuration for gpio pin 6. - r/w pmc6 27:24 port mux control 5 this field controls the configuration for gpio pin 5. - r/w pmc5 23:20 port mux control 4 this field controls the configuration for gpio pin 4. - r/w pmc4 19:16 port mux control 3 this field controls the configuration for gpio pin 3. - r/w pmc3 15:12 port mux control 2 this field controls the configuration for gpio pin 2. - r/w pmc2 11:8 port mux control 1 this field controls the configuration for gpio pin 1. - r/w pmc1 7:4 port mux control 0 this field controls the configuration for gpio pin 0. - r/w pmc0 3:0 july 03, 2014 448 texas instruments-production data general-purpose input/outputs (gpios) register 23: gpio peripheral identification 4 (gpioperiphid4), offset 0xfd0 the gpioperiphid4 , gpioperiphid5 , gpioperiphid6 , and gpioperiphid7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. gpio peripheral identification 4 (gpioperiphid4) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0xfd0 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid4 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 gpio peripheral id register [7:0] 0x00 ro pid4 7:0 449 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 24: gpio peripheral identification 5 (gpioperiphid5), offset 0xfd4 the gpioperiphid4 , gpioperiphid5 , gpioperiphid6 , and gpioperiphid7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. gpio peripheral identification 5 (gpioperiphid5) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0xfd4 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid5 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 gpio peripheral id register [15:8] 0x00 ro pid5 7:0 july 03, 2014 450 texas instruments-production data general-purpose input/outputs (gpios) register 25: gpio peripheral identification 6 (gpioperiphid6), offset 0xfd8 the gpioperiphid4 , gpioperiphid5 , gpioperiphid6 , and gpioperiphid7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. gpio peripheral identification 6 (gpioperiphid6) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0xfd8 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid6 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 gpio peripheral id register [23:16] 0x00 ro pid6 7:0 451 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 26: gpio peripheral identification 7 (gpioperiphid7), offset 0xfdc the gpioperiphid4 , gpioperiphid5 , gpioperiphid6 , and gpioperiphid7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. gpio peripheral identification 7 (gpioperiphid7) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0xfdc type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid7 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 gpio peripheral id register [31:24] 0x00 ro pid7 7:0 july 03, 2014 452 texas instruments-production data general-purpose input/outputs (gpios) register 27: gpio peripheral identification 0 (gpioperiphid0), offset 0xfe0 the gpioperiphid0 , gpioperiphid1 , gpioperiphid2 , and gpioperiphid3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. gpio peripheral identification 0 (gpioperiphid0) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0xfe0 type ro, reset 0x0000.0061 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid0 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 gpio peripheral id register [7:0] can be used by software to identify the presence of this peripheral. 0x61 ro pid0 7:0 453 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 28: gpio peripheral identification 1 (gpioperiphid1), offset 0xfe4 the gpioperiphid0 , gpioperiphid1 , gpioperiphid2 , and gpioperiphid3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. gpio peripheral identification 1 (gpioperiphid1) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0xfe4 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid1 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 gpio peripheral id register [15:8] can be used by software to identify the presence of this peripheral. 0x00 ro pid1 7:0 july 03, 2014 454 texas instruments-production data general-purpose input/outputs (gpios) register 29: gpio peripheral identification 2 (gpioperiphid2), offset 0xfe8 the gpioperiphid0 , gpioperiphid1 , gpioperiphid2 , and gpioperiphid3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. gpio peripheral identification 2 (gpioperiphid2) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0xfe8 type ro, reset 0x0000.0018 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid2 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 gpio peripheral id register [23:16] can be used by software to identify the presence of this peripheral. 0x18 ro pid2 7:0 455 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 30: gpio peripheral identification 3 (gpioperiphid3), offset 0xfec the gpioperiphid0 , gpioperiphid1 , gpioperiphid2 , and gpioperiphid3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. gpio peripheral identification 3 (gpioperiphid3) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0xfec type ro, reset 0x0000.0001 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 gpio peripheral id register [31:24] can be used by software to identify the presence of this peripheral. 0x01 ro pid3 7:0 july 03, 2014 456 texas instruments-production data general-purpose input/outputs (gpios) register 31: gpio primecell identification 0 (gpiopcellid0), offset 0xff0 the gpiopcellid0 , gpiopcellid1 , gpiopcellid2 , and gpiopcellid3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. the register is used as a standard cross-peripheral identification system. gpio primecell identification 0 (gpiopcellid0) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0xff0 type ro, reset 0x0000.000d 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cid0 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 gpio primecell id register [7:0] provides software a standard cross-peripheral identification system. 0x0d ro cid0 7:0 457 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 32: gpio primecell identification 1 (gpiopcellid1), offset 0xff4 the gpiopcellid0 , gpiopcellid1 , gpiopcellid2 , and gpiopcellid3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. the register is used as a standard cross-peripheral identification system. gpio primecell identification 1 (gpiopcellid1) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0xff4 type ro, reset 0x0000.00f0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cid1 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 gpio primecell id register [15:8] provides software a standard cross-peripheral identification system. 0xf0 ro cid1 7:0 july 03, 2014 458 texas instruments-production data general-purpose input/outputs (gpios) register 33: gpio primecell identification 2 (gpiopcellid2), offset 0xff8 the gpiopcellid0 , gpiopcellid1 , gpiopcellid2 , and gpiopcellid3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. the register is used as a standard cross-peripheral identification system. gpio primecell identification 2 (gpiopcellid2) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0xff8 type ro, reset 0x0000.0005 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cid2 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 gpio primecell id register [23:16] provides software a standard cross-peripheral identification system. 0x05 ro cid2 7:0 459 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 34: gpio primecell identification 3 (gpiopcellid3), offset 0xffc the gpiopcellid0 , gpiopcellid1 , gpiopcellid2 , and gpiopcellid3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. the register is used as a standard cross-peripheral identification system. gpio primecell identification 3 (gpiopcellid3) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 offset 0xffc type ro, reset 0x0000.00b1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cid3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 gpio primecell id register [31:24] provides software a standard cross-peripheral identification system. 0xb1 ro cid3 7:0 july 03, 2014 460 texas instruments-production data general-purpose input/outputs (gpios) 9 external peripheral interface (epi) the external peripheral interface is a high-speed parallel bus for external peripherals or memory. it has several modes of operation to interface gluelessly to many types of external devices. the external peripheral interface is similar to a standard microprocessor address/data bus, except that it must typically be connected to just one type of external device. enhanced capabilities include dma support, clocking control and support for external fifo buffers. the epi has the following features: 8/16/32-bit dedicated parallel bus for external peripherals and memory memory interface supports contiguous memory access independent of data bus width, thus enabling code execution directly from sdram, sram and flash memory blocking and non-blocking reads separates processor from timing details through use of an internal write fifo efficient transfers using micro direct memory access controller (dma) C separate channels for read and write C read channel request asserted by programmable levels on the internal non-blocking read fifo (nbrfifo) C write channel request asserted by empty on the internal write fifo (wfifo) the epi supports three primary functional modes: synchronous dynamic random access memory (sdram) mode, traditional host-bus mode, and general-purpose mode. the epi module also provides custom gpios; however, unlike regular gpios, the epi module uses a fifo in the same way as a communication mechanism and is speed-controlled using clocking. synchronous dynamic random access memory (sdram) mode C supports x16 (single data rate) sdram at up to 50 mhz C supports low-cost sdrams up to 64 mb (512 megabits) C includes automatic refresh and access to all banks/rows C includes a sleep/standby mode to keep contents active with minimal power draw C multiplexed address/data interface for reduced pin count host-bus mode C traditional x8 and x16 mcu bus interface capabilities C similar device compatibility options as pic, atmega, 8051, and others C access to sram, nor flash memory, and other devices, with up to 1 mb of addressing in unmultiplexed mode and 256 mb in multiplexed mode (512 mb in host-bus 16 mode with no byte selects) 461 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller C support of both muxed and de-muxed address and data C access to a range of devices supporting the non-address fifo x8 and x16 interface variant, with support for external fifo (xfifo) empty and full signals C speed controlled, with read and write data wait-state counters C chip select modes include ale, csn, dual csn and ale with dual csn C manual chip-enable (or use extra address pins) general-purpose mode C wide parallel interfaces for fast communications with cplds and fpgas C data widths up to 32 bits C data rates up to 150 mb/second C optional "address" sizes from 4 bits to 20 bits C optional clock output, read/write strobes, framing (with counter-based size), and clock-enable input general parallel gpio C 1 to 32 bits, fifoed with speed control C useful for custom peripherals or for digital data acquisition and actuator controls 9.1 epi block diagram figure 9-1 on page 463 provides a block diagram of a stellaris ? epi module. july 03, 2014 462 texas instruments-production data external peripheral interface (epi) figure 9-1. epi block diagram 9.2 signal description the following table lists the external signals of the epi controller and describes the function of each. the epi controller signals are alternate functions for gpio signals and default to be gpio signals at reset. the column in the table below titled "pin mux/pin assignment" lists the gpio pin placement for the epi signals. the afsel bit in the gpio alternate function select (gpioafsel) register (page 429) should be set to choose the epi controller function. the number in parentheses is the encoding that must be programmed into the pmcn field in the gpio port control (gpiopctl) register (page 447) to assign the epi signals to the specified gpio port pins. for more information on configuring gpios, see general-purpose input/outputs (gpios) on page 405. table 9-1. external peripheral interface signals (100lqfp) description buffer type a pin type pin mux / pin assignment pin number pin name epi module 0 signal 0. ttl i/o ph3 (8) 83 epi0s0 epi module 0 signal 1. ttl i/o ph2 (8) 84 epi0s1 epi module 0 signal 2. ttl i/o pc4 (8) 25 epi0s2 epi module 0 signal 3. ttl i/o pc5 (8) 24 epi0s3 epi module 0 signal 4. ttl i/o pc6 (8) 23 epi0s4 epi module 0 signal 5. ttl i/o pc7 (8) 22 epi0s5 epi module 0 signal 6. ttl i/o ph0 (8) 86 epi0s6 epi module 0 signal 7. ttl i/o ph1 (8) 85 epi0s7 epi module 0 signal 8. ttl i/o pe0 (8) 74 epi0s8 epi module 0 signal 9. ttl i/o pe1 (8) 75 epi0s9 epi module 0 signal 10. ttl i/o ph4 (8) 76 epi0s10 463 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller % d x g 5 d w h & r q w u r o & o r f n $ + % % x v , q w h u i d f h : l w k ' 0 $ : l g h 3 d u d o o h o , q w h u i d f h + r v w % x v 6 ' 5 $ 0 * h q h u d o 3 d u d o o h o * 3 , 2 $ + % ( 3 , 1 % 5 ) , ) 2 [ e l w v : ) , ) 2 [ e l w v table 9-1. external peripheral interface signals (100lqfp) (continued) description buffer type a pin type pin mux / pin assignment pin number pin name epi module 0 signal 11. ttl i/o ph5 (8) 63 epi0s11 epi module 0 signal 12. ttl i/o pf7 (8) pf4 (8) 42 58 epi0s12 epi module 0 signal 13. ttl i/o pg0 (8) 19 epi0s13 epi module 0 signal 14. ttl i/o pg1 (8) 18 epi0s14 epi module 0 signal 15. ttl i/o pg4 (8) pf5 (8) 41 46 epi0s15 epi module 0 signal 16. ttl i/o pj0 (8) 14 epi0s16 epi module 0 signal 17. ttl i/o pj1 (8) 87 epi0s17 epi module 0 signal 18. ttl i/o pj2 (8) 39 epi0s18 epi module 0 signal 19. ttl i/o pj3 (8) pd4 (10) 50 97 epi0s19 epi module 0 signal 20. ttl i/o pd2 (8) 12 epi0s20 epi module 0 signal 21. ttl i/o pd3 (8) 13 epi0s21 epi module 0 signal 22. ttl i/o pb5 (8) 91 epi0s22 epi module 0 signal 23. ttl i/o pb4 (8) 92 epi0s23 epi module 0 signal 24. ttl i/o pe2 (8) 95 epi0s24 epi module 0 signal 25. ttl i/o pe3 (8) 96 epi0s25 epi module 0 signal 26. ttl i/o ph6 (8) 62 epi0s26 epi module 0 signal 27. ttl i/o ph7 (8) 15 epi0s27 epi module 0 signal 28. ttl i/o pj4 (8) pd5 (10) 52 98 epi0s28 epi module 0 signal 29. ttl i/o pj5 (8) pd6 (10) 53 99 epi0s29 epi module 0 signal 30. ttl i/o pj6 (8) pd7 (10) 54 100 epi0s30 epi module 0 signal 31. ttl i/o pg7 (9) 36 epi0s31 a. the ttl designation indicates the pin has ttl-compatible voltage levels. table 9-2. external peripheral interface signals (108bga) description buffer type a pin type pin mux / pin assignment pin number pin name epi module 0 signal 0. ttl i/o ph3 (8) d10 epi0s0 epi module 0 signal 1. ttl i/o ph2 (8) d11 epi0s1 epi module 0 signal 2. ttl i/o pc4 (8) l1 epi0s2 epi module 0 signal 3. ttl i/o pc5 (8) m1 epi0s3 epi module 0 signal 4. ttl i/o pc6 (8) m2 epi0s4 epi module 0 signal 5. ttl i/o pc7 (8) l2 epi0s5 epi module 0 signal 6. ttl i/o ph0 (8) c9 epi0s6 epi module 0 signal 7. ttl i/o ph1 (8) c8 epi0s7 epi module 0 signal 8. ttl i/o pe0 (8) b11 epi0s8 epi module 0 signal 9. ttl i/o pe1 (8) a12 epi0s9 epi module 0 signal 10. ttl i/o ph4 (8) b10 epi0s10 july 03, 2014 464 texas instruments-production data external peripheral interface (epi) table 9-2. external peripheral interface signals (108bga) (continued) description buffer type a pin type pin mux / pin assignment pin number pin name epi module 0 signal 11. ttl i/o ph5 (8) f10 epi0s11 epi module 0 signal 12. ttl i/o pf7 (8) pf4 (8) k4 l9 epi0s12 epi module 0 signal 13. ttl i/o pg0 (8) k1 epi0s13 epi module 0 signal 14. ttl i/o pg1 (8) k2 epi0s14 epi module 0 signal 15. ttl i/o pg4 (8) pf5 (8) k3 l8 epi0s15 epi module 0 signal 16. ttl i/o pj0 (8) f3 epi0s16 epi module 0 signal 17. ttl i/o pj1 (8) b6 epi0s17 epi module 0 signal 18. ttl i/o pj2 (8) k6 epi0s18 epi module 0 signal 19. ttl i/o pj3 (8) pd4 (10) m10 b5 epi0s19 epi module 0 signal 20. ttl i/o pd2 (8) h2 epi0s20 epi module 0 signal 21. ttl i/o pd3 (8) h1 epi0s21 epi module 0 signal 22. ttl i/o pb5 (8) b7 epi0s22 epi module 0 signal 23. ttl i/o pb4 (8) a6 epi0s23 epi module 0 signal 24. ttl i/o pe2 (8) a4 epi0s24 epi module 0 signal 25. ttl i/o pe3 (8) b4 epi0s25 epi module 0 signal 26. ttl i/o ph6 (8) g3 epi0s26 epi module 0 signal 27. ttl i/o ph7 (8) h3 epi0s27 epi module 0 signal 28. ttl i/o pj4 (8) pd5 (10) k11 c6 epi0s28 epi module 0 signal 29. ttl i/o pj5 (8) pd6 (10) k12 a3 epi0s29 epi module 0 signal 30. ttl i/o pj6 (8) pd7 (10) l10 a2 epi0s30 epi module 0 signal 31. ttl i/o pg7 (9) c10 epi0s31 a. the ttl designation indicates the pin has ttl-compatible voltage levels. 9.3 functional description the epi controller provides a glueless, programmable interface to a variety of common external peripherals such as sdram x 16, host bus x8 and x16 devices, ram, nor flash memory, cplds and fpgas. in addition, the epi controller provides custom gpio that can use a fifo with speed control by using either the internal write fifo (wfifo) or the non-blocking read fifo (nbrfifo). the wfifo can hold 4 words of data that are written to the external interface at the rate controlled by the epi main baud rate (epibaud) register. the nbrfifo can hold 8 words of data and samples at the rate controlled by the epibaud register. the epi controller provides predictable operation and thus has an advantage over regular gpio which has more variable timing due to on-chip bus arbitration and delays across bus bridges. blocking reads stall the cpu until the transaction completes. non-blocking reads are performed in the background and allow the processor to continue operation. in addition, write data can also be stored in the wfifo to allow multiple writes with no stalls. 465 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller note: both the wtav bit field in the epiwfifocnt register and the wbusy bit in the epistat register must be polled to determine if there is a current write transaction from the wfifo. if both of these bits are clear, then a new bus access may begin. main read and write operations can be performed in subsets of the range 0x6000.0000 to 0xdfff.ffff. a read from an address mapped location uses the offset and size to control the address and size of the external operation. when performing a multi-value load, the read is done as a burst (when available) to maximize performance. a write to an address mapped location uses the offset and size to control the address and size of the external operation. when performing a multi-value store, the write is done as a burst (when available) to maximize performance. nand flash memory (x8) can be read natively. automatic programming support is not provided; programming must be done by the user following the manufacturer's protocol. automatic page ecc is also not supported, but can be performed in software. 9.3.1 non-blocking reads the epi controller supports a special kind of read called a non-blocking read, also referred to as a posted read. where a normal read stalls the processor or dma until the data is returned, a non-blocking read is performed in the background. a non-blocking read is configured by writing the start address into a epiraddrn register, the size per transaction into a epirsizen register, and then the count of operations into a epirpstdn register. after each read is completed, the result is written into the nbrfifo and the epiraddrn register is incremented by the size (1, 2, or 4). if the nbrfifo is filled, then the reads pause until space is made available. the nbrfifo can be configured to interrupt the processor or trigger the dma based on fullness using the epififolvl register. by using the trigger/interrupt method, the dma (or processor) can keep space available in the nbrfifo and allow the reads to continue unimpeded. when performing non-blocking reads, the sdram controller issues two additional read transactions after the burst request is terminated. the data for these additional transfers is discarded. this situation is transparent to the user other than the additional epi bus activity and can safely be ignored. two non-blocking read register sets are available to allow sequencing and ping-pong use. when one completes, the other then activates. so, for example, if 20 words are to be read from 0x100 and 10 words from 0x200, the epirpstd0 register can be set up with the read from 0x100 (with a count of 20), and the epirpstd1 register can be set up with the read from 0x200 (with a count of 10). when epirpstd0 finishes (count goes to 0), the epirpstd1 register then starts its operation. the nbrfifo has then passed 30 values. when used with the dma, it may transfer 30 values (simple sequence), or the primary/alternate model may be used to handle the first 20 in one way and the second 10 in another. it is also possible to reload the epirpstd0 register when it is finished (and the epirpstd1 register is active); thereby, keeping the interface constantly busy. to cancel a non-blocking read, the epirpstdn register is cleared. care must be taken, however if the register set was active to drain away any values read into the nbrfifo and ensure that any read in progress is allowed to complete. to ensure that the cancel is complete, the following algorithm is used (using the epirpstd0 register for example): epirpstd0 = 0; while (( epistat & 0x11) == 0x10) ; // we are active and busy july 03, 2014 466 texas instruments-production data external peripheral interface (epi) // if here, then other one is active or interface no longer busy cnt = ( epiraddr0 C original_address) / epirsize0 ; // count of values read cnt -= values_read_so_far; // cnt is now number left in fifo while (cnt--) value = epireadfifo ; // drain the above algorithm can be optimized in code; however, the important point is to wait for the cancel to complete because the external interface could have been in the process of reading a value when the cancel came in, and it must be allowed to complete. 9.3.2 dma operation the dma can be used to achieve maximum transfer rates on the epi through the nbrfifo and the wfifo. the dma has one channel for write and one for read. the write channel copies values to the wfifo when the wfifo is at the level specified by the epi fifo level selects (epififolvl) register. the non-blocking read channel copies values from the nbrfifo when the nbrfifo is at the level specified by the epififolvl register. for non-blocking reads, the start address, the size per transaction, and the count of elements must be programmed in the dma. note that both non-blocking read register sets can be used, and they fill the nbrfifo such that one runs to completion, then the next one starts (they do not interleave). using the nbrfifo provides the best possible transfer rate. for blocking reads, the dma software channel (or another unused channel) is used for memory-to-memory transfers (or memory to peripheral, where some other peripheral is used). in this situation, the dma stalls until the read is complete and is not able to service another channel until the read is done. as a result, the arbitration size should normally be programmed to one access at a time. the dma controller can also transfer from and to the nbrfifo and the wfifo using the dma software channel in memory mode, however, the dma is stalled once the nbrfifo is empty or the wfifo is full. note that when the dma controller is stalled, the core continues operation. see micro direct memory access (dma) on page 344 for more information on configuring the dma. the size of the fifos must be taken into consideration when configuring the dma to transfer data to and from the epi. the arbitration size should be 4 or less when writing to epi address space and 8 or less when reading from epi address space. 9.4 initialization and configuration to enable and initialize the epi controller, the following steps are necessary: 1. enable the epi module using the rcgc1 register. see page 270. 2. enable the clock to the appropriate gpio module via the rcgc2 register. see page 282. to find out which gpio port to enable, refer to signal description on page 463. 3. set the gpio afsel bits for the appropriate pins. see page 429. to determine which gpios to configure, see table 24-4 on page 1239. 4. configure the gpio current level and/or slew rate as specified for the mode selected. see page 431 and page 439. 467 july 03, 2014 texas instruments-production data stellaris lm3s9gn5 microcontroller 5. configure the pmcn fields in the gpiopctl register to assign the epi signals to the appropriate pins. see page 447 and table 24-5 on page 1248. 6. select the mode for the epi block to sdram, hb8, hb16, or general parallel use, using the mode field in the epi configuration (epicfg) register. set the mode-specific details (if needed) using the appropriate mode configuration epi host bus configuration (epihbncfgn) registers for the desired chip-select configuration. set the epi main baud rate (epibaud) register if the baud rate must be slower than the system clock rate. 7. configure the address mapping using the epi address map (epiaddrmap) register. the selected start address and range is dependent on the type of external device and maximum address (as appropriate). for example, for a 512-megabit sdram, program the eradr field to 0x1 for address 0x6000.0000 or 0x2 for address 0x8000.0000; and program the ersz field to 0x3 for 256 mb. if using general-purpose mode and no address at all, program the epadr field to 0x1 for address 0xa000.0000 or 0x2 for address 0xc000.0000; and program the epsz field to 0x0 for 256 bytes. 8. to read or write directly, use the mapped address area (configured with the epiaddrmap register). up to 4 or 5 writes can be performed at once without blocking. each read is blocked until the value is retrieved. 9. to perform a non-blocking read, see non-blocking reads on page 466. the following sub-sections describe the initialization and configuration for each of the modes of operation. care must be taken to initialize everything properly to ensure correct operation. control of the gpio states is also important, as changes may cause the external device to interpret pin states as actions or commands (see register descriptions on page 418). normally, a pull-up or pull-down is needed on the board to at least control the chip-select or chip-enable as the stellaris gpios come out of reset in tri-state. 9.4.1 sdram mode when activating the sdram mode, it is important to consider a few points: 1. generally, it takes over 100 s from when the mode is activated to when the first operation is allowed. the sdram controller begins the sdram initialization sequence as soon as the mode is selected and enabled via the epicfg register. it is important that the gpios are properly configured before the sdram mode is enabled, as the epi controller is relying on the gpio block's ability to drive the pins immediately. as part of the initialization sequence, the load mode register command is automatically sent to the sdram with a value of 0x27, which sets a cas latency of 2 and a full page burst length. 2. the initseq bit in the epi status (epistat) register can be checked to determine when the initialization sequence is complete. 3. when using a frequency range and/or refresh value other than the default value, it is important to configure the freq and rfsh fields in the epi sdram configuration (episdramcfg) register shortly after activating the mode. after the 100-s startup time, the epi block must be configured properly to keep the sdram contents stable. 4. the sleep bit in the episdramcfg register may be configured to put the sdram into a low-power self-refreshing state. it is important to note that the sdram mode must not be disabled once enabled, or else the sdram is no longer clocked and the contents are lost. july 03, 2014 468 texas instruments-production data external peripheral interface (epi) 5. before entering sleep mode, make sure all non-blocking reads and normal reads and writes have completed. if the system is running at 30 to 50 mhz, wait 2 epi clocks after clearing the sleep bit before executing non-blocking reads, or normal reads and writes. if the system is configured to greater than 50 mhz, wait 5 epi clocks before read and write transactions. for all other configurations, wait 1 epi clock. the size field of the episdramcfg register must be configured correctly based on the amount of sdram in the system. the freq field must be configured according to the value that represents the range being used. based on the range selected, the number of external clocks used between certain operations (for example, precharge or activate) is determined. if a higher frequency is given than is used, then the only downside is that the peripheral is slower (uses more cycles for these delays). if a lower frequency is given, incorrect operation occurs. see external peripheral interface (epi) on page 1307 for timing details for the sdram mode. 9.4.1.1 external signal connections table 9-3 on page 469 defines how epi module signals should be connected to sdrams. the table applies when using a sdram up to 512 megabits. note that the epi signals must use 8-ma drive when interfacing to sdram, see page 433. any unused epi controller signals can be used as gpios or another alternate function. table 9-3. epi sdram signal connections sdram signal a epi signal d0 a0 epi0s0 d1 a1 epi0s1 d2 a2 epi0s2 d3 a3 epi0s3 d4 a4 epi0s4 d5 a5 epi0s5 d6 a6 epi0s6 d7 a7 epi0s7 d8 a8 epi0s8 d9 a9 epi0s9 d10 a10 epi0s10 d11 a11 epi0s11 d12 a12 b epi0s12 d13 ba0 epi0s13 d14 ba1 epi0s14 d15 epi0s15 dqml epi0s16 dqmh epi0s17 casn epi0s18 rasn epi0s19 not used epi0s20-epi0s27 wen epi0s28 csn epi0s29 469 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 9-3. epi sdram signal connections (continued) sdram signal a epi signal cke epi0s30 clk epi0s31 a. if 2 signals are listed, connect the epi signal to both pins. b. only for 256/512 megabit sdrams 9.4.1.2 refresh configuration the refresh count is based on the external clock speed and the number of rows per bank as well as the refresh period. the rfsh field represents how many external clock cycles remain before an auto-refresh is required. the normal formula is: rfsh = (t refresh_us / number_rows) / ext_clock_period a refresh period is normally 64 ms, or 64000 s. the number of rows is normally 4096 or 8192. the ext_clock_period is a value expressed in sec and is derived by dividing 1000 by the clock speed expressed in mhz. so, 50 mhz is 1000/50=20 ns, or 0.02 s. a typical sdram is 4096 rows per bank if the system clock is running at 50 mhz with an epibaud register value of 0: rfsh = (64000/4096) / 0.02 = 15.625 s / 0.02 s = 781.25 the default value in the rfsh field is 750 decimal or 0x2ee to allow for a margin of safety and providing 15 s per refresh. it is important to note that this number should always be smaller or equal to what is required by the above equation. for example, if running the external clock at 25 mhz (40 ns per clock period), 390 is the highest number that may be used. note that the external clock may be 25 mhz when the system clock is 25 mhz or when the system clock is 50 mhz and configuring the count0 field in the epibaud register to 1 (divide by 2). if a number larger than allowed is used, the sdram is not refreshed often enough, and data is lost. 9.4.1.3 bus interface speed the epi controller sdram interface can operate up to 50 mhz. the count0 field in the epibaud register configures the speed of the epi clock. for system clock (sysclk) speeds up to 50 mhz, the count0 field can be 0x0000, and the sdram interface can run at the same speed as sysclk. however, if sysclk is running at higher speeds, the bus interface can run only as fast as half speed, and the count0 field must be configured to at least 0x0001. 9.4.1.4 non-blocking read cycle figure 9-2 on page 471 shows a non-blocking read cycle of n halfwords; n can be any number greater than or equal to 1. the cycle begins with the activate command and the row address on the epi0s[15:0] signals. with the programmed cas latency of 2, the read command with the column address on the epi0s[15:0] signals follows after 2 clock cycles. following one more nop cycle, data is read in on the epi0s[15:0] signals on every rising clock edge. the burst terminate command is issued during the cycle when the next-to-last halfword is read in. the dqmh and dqml signals are deasserted after the last halfword of data is received; the csn signal deasserts on the following clock cycle, signaling the end of the read cycle. at least one clock period of inactivity separates any two sdram cycles. july 03, 2014 470 texas instruments-production data external peripheral interface (epi) figure 9-2. sdram non-blocking read cycle 9.4.1.5 normal read cycle figure 9-3 on page 471 shows a normal read cycle of n halfwords; n can be 1 or 2. the cycle begins with the activate command and the row address on the epi0s[15:0] signals. with the programmed cas latency of 2, the read command with the column address on the epi0s[15:0] signals follows after 2 clock cycles. following one more nop cycle, data is read in on the epi0s[15:0] signals on every rising clock edge. the dqmh, dqml, and csn signals are deasserted after the last halfword of data is received, signaling the end of the cycle. at least one clock period of inactivity separates any two sdram cycles. figure 9-3. sdram normal read cycle 471 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 5 r z & r o x p q ' d w d ' d w d ' d w d q & / . ( 3 , 6 & . ( ( 3 , 6 & 6 q ( 3 , 6 : ( q ( 3 , 6 5 $ 6 q ( 3 , 6 & $ 6 q ( 3 , 6 ' 4 0 + ' 4 0 / ( 3 , 6 > @ $ ' > @ ( 3 , 6 > @ $ f w l y d w h 1 2 3 1 2 3 5 h d g 1 2 3 % x u v w 7 h u p $ ' > @ g u l y h q l q $ ' > @ g u l y h q r x w $ ' > @ g u l y h q r x w 5 r z & r o x p q ' d w d ' d w d & / . ( 3 , 6 & . ( ( 3 , 6 & 6 q ( 3 , 6 : ( q ( 3 , 6 5 $ 6 q ( 3 , 6 & $ 6 q ( 3 , 6 ' 4 0 + ' 4 0 / ( 3 , 6 > @ $ ' > @ ( 3 , 6 > @ $ f w l y d w h 1 2 3 1 2 3 5 h d g 1 2 3 $ ' > @ g u l y h q l q $ ' > @ g u l y h q r x w $ ' > @ g u l y h q r x w 9.4.1.6 write cycle figure 9-4 on page 472 shows a write cycle of n halfwords; n can be any number greater than or equal to 1. the cycle begins with the activate command and the row address on the epi0s[15:0] signals. with the programmed cas latency of 2, the write command with the column address on the epi0s[15:0] signals follows after 2 clock cycles. when writing to sdrams, the write command is presented with the first halfword of data. because the address lines and the data lines are multiplexed, the column address is modified to be (programmed address -1). during the write command, the dqmh and dqml signals are high, so no data is written to the sdram. on the next clock, the dqmh and dqml signals are asserted, and the data associated with the programmed address is written. the burst terminate command occurs during the clock cycle following the write of the last halfword of data. the wen, dqmh, dqml, and csn signals are deasserted after the last halfword of data is received, signaling the end of the access. at least one clock period of inactivity separates any two sdram cycles. figure 9-4. sdram write cycle 9.4.2 host bus mode host bus supports the traditional 8-bit and 16-bit interfaces popularized by the 8051 devices and sram devices. this interface is asynchronous and uses strobe pins to control activity. addressable memory can be doubled using host bus-16 mode as it performs half-word accesses. the epi0s0 is the lsb of the address and is equivalent to the internal cortex-m3 a1 address. epi0s0 should be connected to a0 of 16-bit memories. 9.4.2.1 control pins the main three strobes are address latch enable (ale), write (wrn), and read (rdn, sometimes called oen). note that the timings are designed for older logic and so are hold-time vs. setup-time specific. the polarity of the read and write strobes can be active high or active low by clearing or setting the rdhigh and wrhigh bits in the epi host-bus n configuration 2 (epihbncfg2) register. the ale can be changed to an active-low chip select signal, csn, through the epihbncfg2 register. the ale is best used for host-bus muxed mode in which epi address and data pins are shared. all host-bus accesses have an address phase followed by a data phase. the ale indicates to an july 03, 2014 472 texas instruments-production data external peripheral interface (epi) 5 r z & r o x p q ' d w d ' d w d ' d w d q & / . ( 3 , 6 & . ( ( 3 , 6 & 6 q ( 3 , 6 : ( q ( 3 , 6 5 $ 6 q ( 3 , 6 & $ 6 q ( 3 , 6 ' 4 0 + ' 4 0 / ( 3 , 6 > @ $ ' > @ ( 3 , 6 > @ $ f w l y d w h 1 2 3 1 2 3 : u l w h % x u v w 7 h u p $ ' > @ g u l y h q r x w $ ' > @ g u l y h q r x w external latch to capture the address then hold it until the data phase. csn is best used for host-bus unmuxed mode in which epi address and data pins are separate. the csn indicates when the address and data phases of a read or write access are occurring. both the ale and the csn modes can be enhanced to access external devices using settings in the epihbncfg2 register. wait states can be added to the data phase of the access using the wrws and rdws bits in the epihbncfg2 register. for fifo mode, the ale is not used, and two input holds are optionally supported to gate input and output to what the xfifo can handle. host-bus 8 and host-bus 16 modes are very configurable. the user has the ability to connect external devices to the epi signals, as well as control whether byte select signals are provided in hb16 mode. these capabilities depend on the configuration of the mode field in the epihbncfg register and the cscfg fieldin the epihbncfg2 register, and the bsel bit in the epihb16cfg register. the cscfgext bit extends the chip select configuration possibilities by providing the most significant bit of the cscfg field. if one of the dual-chip-select modes is selected ( cscfg is 0x2 or 0x3 in the epihbncfg2 register), both chip selects can share the peripheral or the memory space, or one chip select can use the peripheral space and the other can use the memory space. in the epiaddrmap register, if the epadr field is not 0x0 and the eradr field is 0x0, then the address specified by epadr is used for both chip selects, with cs0n being asserted when the msb of the address range is 0 and cs1n being asserted when the msb of the address range is 1. if the eradr field is not 0x0 and the epadr field is 0x0, then the address specified by eradr is used for both chip selects, with the msb performing the same delineation. if both the epadr and the eradr are not 0x0, then cs0n is asserted for either address range defined by epadr and cs1n is asserted for either address range defined by eradr. if the csbaud bit in the epihbncfg2 register is set in dual-chip select mode, the 2 chip selects can use different clock frequencies, wait states and strobe polarity. if the csbaud bit is clear, both chip selects use the clock frequency, wait states, and strobe polarity defined for cs0n. when bsel =1 in the epihb16cfg register, byte select signals are provided, so byte-sized data can be read and written at any address, however these signals reduce the available address width by 2 pins. the byte select signals are active low. bsel0n corresponds to the lsb of the halfword, and bsel1n corresponds to the msb of the halfword. when bsel =0, byte reads and writes at odd addresses only act on the even byte, and byte writes at even addresses write invalid values into the odd byte. as a result, accesses should be made as half-words (16-bits) or words (32-bits). in c/c++, programmers should use only short int and long int for accesses. also, because data accesses in hb16 mode with no byte selects are on 2-byte boundaries, the available address space is doubled. for example, 28 bits of address accesses 512 mb in this mode. table 9-4 on page 473 shows the capabilities of the hb8 and hb16 modes as well as the available address bits with the possible combinations of these bits. although the epi0s31 signal can be configured for the epi clock signal in host-bus mode, it is not required and should be configured as a gpio to reduce emi in the system. table 9-4. capabilities of host bus 8 and host bus 16 modes addressable memory available address byte access bsel max # of external devices cscfg mode host bus type 256 mb 28 bits always n/a 1 0x0, 0x1 0x0 hb8 128 mb 27 bits always n/a 2 0x2 0x0 hb8 64 mb 26 bits always n/a 2 0x3 0x0 hb8 473 july 03, 2014 texas instruments-production data stellaris lm3s9gn5 microcontroller table 9-4. capabilities of host bus 8 and host bus 16 modes (continued) addressable memory available address byte access bsel max # of external devices cscfg mode host bus type 1 mb 20 bits always n/a 1 0x0, 0x1 0x1 hb8 512 kb 19 bits always n/a 2 0x2 0x1 hb8 256 kb 18 bits always n/a 2 0x3 0x1 hb8 - none always n/a 1 0x1 0x3 hb8 - none always n/a 2 0x3 0x3 hb8 512 mb 28 bits a no 0 1 0x0, 0x1 0x0 hb16 128 mb 26 bits b yes 1 1 0x0, 0x1 0x0 hb16 256 mb 27 bits a no 0 2 0x2 0x0 hb16 64 mb 25 bits b yes 1 2 0x2 0x0 hb16 128 mb 26 bites a no 0 2 0x3 0x0 hb16 32 mb 24 bits b yes 1 2 0x3 0x0 hb16 8 kb 12 bits a no 0 1 0x0, 0x1 0x1 hb16 2 kb 10 bits b yes 1 1 0x0, 0x1 0x1 hb16 4 kb 11 bits a no 0 2 0x2 0x1 hb16 1 kb 9 bits b yes 1 2 0x2 0x1 hb16 2 kb 10 bits a no 0 2 0x3 0x1 hb16 512 b 8 bits b yes 1 2 0x3 0x1 hb16 - none no 0 1 0x1 0x3 hb16 - none yes 1 1 0x1 0x3 hb16 - none no 0 2 0x3 0x3 hb16 - none yes 1 2 0x3 0x3 hb16 a. if byte selects are not used, data accesses are on 2-byte boundaries. as a result, the available address space is doubled. b. two epi signals are used for byte selects, reducing the available address space by two bits. table 9-5 on page 474 shows how the epi[31:0] signals function while in host-bus 8 mode. notice that the signal configuration changes based on the address/data mode selected by the mode field in the epihb8cfg2 register and on the chip select configuration selected by the cscfg field in the same register. although the epi0s31 signal can be configured for the epi clock signal in host-bus mode, it is not required and should be configured as a gpio to reduce emi in the system. any unused epi controller signals can be used as gpios or another alternate function. table 9-5. epi host-bus 8 signal connections hb8 signal ( mode =xfifo) hb8 signal ( mode =adnomux (cont. read)) hb8 signal ( mode =admux) cscfg epi signal d0 d0 ad0 x a epi0s0 d1 d1 ad1 x epi0s1 d2 d2 ad2 x epi0s2 d3 d3 ad3 x epi0s3 d4 d4 ad4 x epi0s4 d5 d5 ad5 x epi0s5 july 03, 2014 474 texas instruments-production data external peripheral interface (epi) table 9-5. epi host-bus 8 signal connections (continued) hb8 signal ( mode =xfifo) hb8 signal ( mode =adnomux (cont. read)) hb8 signal ( mode =admux) cscfg epi signal d6 d6 ad6 x epi0s6 d7 d7 ad7 x epi0s7 - a0 a8 x epi0s8 - a1 a9 x epi0s9 - a2 a10 x epi0s10 - a3 a11 x epi0s11 - a4 a12 x epi0s12 - a5 a13 x epi0s13 - a6 a14 x epi0s14 - a7 a15 x epi0s15 - a8 a16 x epi0s16 - a9 a17 x epi0s17 - a10 a18 x epi0s18 - a11 a19 x epi0s19 - a12 a20 x epi0s20 - a13 a21 x epi0s21 - a14 a22 x epi0s22 - a15 a23 x epi0s23 - a16 a24 x epi0s24 - a17 a25 b 0x0 epi0s25 0x1 cs1n 0x2 - 0x3 fempty a18 a26 0x0 epi0s26 0x1 0x2 cs0n cs0n 0x3 ffull a19 a27 0x0 epi0s27 0x1 cs1n cs1n 0x2 0x3 rdn rdn/oen rdn/oen x epi0s28 wrn wrn wrn x epi0s29 - ale ale 0x0 epi0s30 csn csn csn 0x1 cs0n cs0n cs0n 0x2 - ale ale 0x3 clock c clock c clock c x epi0s31 a. "x" indicates the state of this field is a don't care. b. when an entry straddles several row, the signal configuration is the same for all rows. c. the clock signal is not required for this mode and has unspecified timing relationships to other signals. 475 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 9-6 on page 476 shows how the epi[31:0] signals function while in host-bus 16 mode. notice that the signal configuration changes based on the address/data mode selected by the mode field in the epihb16cfg2 register, on the chip select configuration selected by the cscfg field in the same register, and on whether byte selects are used as configured by the bsel bit in the epihb16cfg register. although the epi0s31 signal can be configured for the epi clock signal in host-bus mode, it is not required and should be configured as a gpio to reduce emi in the system. any unused epi controller signals can be used as gpios or another alternate function. table 9-6. epi host-bus 16 signal connections hb16 signal (mode =xfifo) hb16 signal ( mode =adnomux (cont. read)) hb16 signal ( mode =admux) bsel cscfg epi signal d0 d0 ad0 b x x a epi0s0 d1 d1 ad1 x x epi0s1 d2 d2 ad2 x x epi0s2 d3 d3 ad3 x x epi0s3 d4 d4 ad4 x x epi0s4 d5 d5 ad5 x x epi0s5 d6 d6 ad6 x x epi0s6 d7 d7 ad7 x x epi0s7 d8 d8 ad8 x x epi0s8 d9 d9 ad9 x x epi0s9 d10 d10 ad10 x x epi0s10 d11 d11 ad11 x x epi0s11 d12 d12 ad12 x x epi0s12 d13 d13 ad13 x x epi0s13 d14 d14 ad14 x x epi0s14 d15 d15 ad15 x x epi0s15 - a0 b a16 x x epi0s16 - a1 a17 x x epi0s17 - a2 a18 x x epi0s18 - a3 a19 x x epi0s19 - a4 a20 x x epi0s20 - a5 a21 x x epi0s21 - a6 a22 x x epi0s22 - a7 a23 0 x c epi0s23 1 july 03, 2014 476 texas instruments-production data external peripheral interface (epi) table 9-6. epi host-bus 16 signal connections (continued) hb16 signal (mode =xfifo) hb16 signal ( mode =adnomux (cont. read)) hb16 signal ( mode =admux) bsel cscfg epi signal - a8 a24 0 0x0 epi0s24 1 0 0x1 1 0 0x2 1 0 0x3 bsel0n bsel0n 1 - a9 a25 x 0x0 epi0s25 0x1 cs1n a9 a25 0 0x2 bsel0n bsel0n 1 -- a9 a25 0 0x3 bsel1n bsel1n 1 fempty a10 a26 0 0x0 epi0s26 bsel0n bsel0n 1 a10 a26 0 0x1 bsel0n bsel0n 1 a10 a26 0 0x2 bsel1n bsel1n 1 cs0n cs0n x 0x3 ffull a11 a27 0 0x0 epi0s27 bsel1n bsel1n 1 a11 a27 0 0x1 bsel1n bsel1n 1 cs1n cs1n x 0x2 x 0x3 rdn rdn/oen rdn/oen x x epi0s28 wrn wrn wrn x x epi0s29 - ale ale x 0x0 epi0s30 csn csn csn x 0x1 cs0n cs0n cs0n x 0x2 - ale ale x 0x3 clock d clock d clock d x x epi0s31 a. "x" indicates the state of this field is a don't care. b. in this mode, half-word accesses are used. a0 is the lsb of the address and is equivalent to the internal cortex-m3 a1 address. this pin should be connected to a0 of 16-bit memories. c. when an entry straddles several row, the signal configuration is the same for all rows. d. the clock signal is not required for this mode and has unspecified timing relationships to other signals. 477 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 9.4.2.2 sram support figure 9-5 on page 478 shows how to connect the epi signals to a 16-bit sram and a 16-bit flash memory with muxed address and memory using byte selects and dual chip selects with ale. this schematic is just an example of how to connect the signals; timing and loading have not been analyzed. in addition, not all bypass capacitors are shown. figure 9-5. example schematic for muxed host-bus 16 mode 9.4.2.3 speed of transactions the count0 field in the epibaud register must be configured to set the main transaction rate based on what the slave device can support (including wiring considerations). the main control july 03, 2014 478 texas instruments-production data external peripheral interface (epi) stellaris microcontrollers www.ti.com/stellaris austin tx, 78746 108 wild basin road, suite 350 texas instruments ?part number? 1/6/2011 ?desc2? ?desc1? ?project name? ?rev? epi16_example.sch of 1 1 ??? sheet part no. date revision designer filename description project r configuration assumes epihb16 mode = admux, bsel = 1, cscfg = 3 example schematic for signal connection purposes only. timing, loading and other analysis have not been validated 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 17 17 18 18 19 19 20 20 21 21 22 22 23 23 24 24 25 25 26 26 27 27 28 28 29 29 30 30 31 31 32 32 33 33 34 34 35 35 36 36 37 37 38 38 39 39 40 40 41 41 42 42 43 43 44 44 45 45 46 46 47 47 48 48 49 49 50 50 j1 con-epi-male c1 c0603 0.1uf c2 c0603 0.1uf c3 c0603 0.1uf c4 c0603 0.1uf 1 a4 2 a3 3 a2 4 a1 5 a0 6 ce 7 i/o0 8 i/o1 9 i/o2 10 i/o3 11 vcc 12 vss 13 i/o4 14 i/o5 15 i/o6 16 i/o7 17 we 18 a17 19 a16 20 a15 21 a14 22 a13 23 a12 24 a11 25 a10 26 a9 27 a8 28 nc 29 i/o8 30 i/o9 31 i/o10 32 i/o11 33 vcc 34 vss 35 i/o12 36 i/o13 37 i/o14 38 i/o15 39 ble 40 bhe 41 oe 42 a7 43 a6 44 a5 u2 cy62147 1 a15 2 a14 3 a13 4 a12 5 a11 6 a10 7 a9 8 a8 9 nc 10 nc 11 we 12 nc 13 nc 14 nc 15 nc 16 a18 17 a17 18 a7 19 a6 20 a5 21 a4 22 a3 23 a2 24 a1 25 a0 26 ce 27 vss 28 oe 29 dq0 30 dq8 31 dq1 32 dq9 33 dq2 34 dq10 35 dq3 36 dq11 37 vdd 38 dq4 39 dq12 40 dq5 41 dq13 42 dq6 43 dq14 44 dq7 45 dq15 46 vss 47 nc 48 a16 u3 sst39vf800a 1 1oe 2 1q1 3 1q2 4 gnd 5 1q3 6 1q4 7 vcc 8 1q5 9 1q6 10 gnd 11 1q7 12 1q8 13 2q1 14 2q2 15 gnd 16 2q3 17 2q4 18 vcc 19 2q5 20 2q6 21 gnd 22 2q7 23 2q8 24 2oe 25 2le 26 2d8 27 2d7 28 gnd 29 2d6 30 2d5 31 vcc 32 2d4 33 2d3 34 gnd 35 2d2 36 2d1 37 1d8 38 1d7 39 gnd 40 1d6 41 1d5 42 vcc 43 1d4 44 1d3 45 gnd 46 1d2 47 1d1 48 1le u1 74x16373 c8 c0603 0.1uf c9 c0603 0.1uf c7 c0603 0.1uf epi_16_bus +3.3v +5v gnd gnd epi13 epi14 epi27 epi16 epi21 epi20 epi30 epi29 epi28 epi19 epi25 epi22 epi23 epi24 epi0 epi1 epi2 epi3 epi4 epi5 epi6 epi7 epi8 epi9 epi10 epi11 epi12 epi15 epi18 epi17 epi31 epi26 gnd gnd epi0 epi1 epi2 epi3 epi4 epi5 epi6 epi7 epi8 epi9 epi10 epi11 epi12 epi13 epi14 epi15 epi30 +3.3v gnd gnd +3.3v gnd a[0:15] a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a[0:15] epi_16_bus epi_16_bus a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 epi16 epi17 epi0 epi1 epi2 epi3 epi4 epi5 epi6 epi7 epi8 epi9 epi10 epi11 epi12 epi13 epi14 epi15 epi28 epi29 epi26 epi25 epi24 a[0:15] epi_16_bus epi_16_bus a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 epi16 epi17 epi18 epi0 epi1 epi2 epi3 epi4 epi5 epi6 epi7 epi8 epi9 epi10 epi11 epi12 epi13 epi14 epi15 epi29 epi28 epi27 epi_16_bus +3.3v gnd +3.3v gnd gnd +3.3v +3.3v gnd transitions are normally ? the baud rate ( count0 = 1) because the epi block forces data vs. control to change on alternating clocks. when using dual chip selects, each chip select can access the bus using differing baud rates by setting the csbaud bit in the epihbncfg2 register. in this case, the count0 field controls the cs0n transactions, and the count1 field controls the cs1n transactions. additionally, the host-bus mode provides read and write wait states for the data portion to support different classes of device. these wait states stretch the data period (hold the rising edge of data strobe) and may be used in all four sub-modes. the wait states are set using the wrws and rdws bits in the epi host-bus n configuration (epihbncfg) register. 9.4.2.4 sub-modes of host bus 8/16 the epi controller supports four variants of the host-bus model using 8 or 16 bits of data in all four cases. the four sub-modes are selected using the mode bits in the epihbncfg register, and are: 1. address and data are muxed. this scheme is used by many 8051 devices, some microchip pic parts, and some atmega parts. when used for standard srams, a latch must be used between the microcontroller and the sram. this sub-mode is provided for compatibility with existing devices that support data transfers without a latch (that is, cplds). in general, the de-muxed sub-mode should normally be used. the ale configuration should be used in this mode, as all host-bus accesses have an address phase followed by a data phase. the ale indicates to an external latch to capture the address then hold until the data phase. the ale configuration is controlled by configuring the cscfg field to be 0x0 in the epihbncfg2 register. the ale can be enhanced to access two external devices with two separate csn signals. by configuring the cscfg field to be 0x3 in the epihbncfg2 register, epi0s30 functions as ale, epi0s27 functions as cs1n, and epi0s26 functions as cs0n. the csn is best used for host-bus unmuxed mode, in which epi address and data pins are separate. the csn indicates when the address and data phases of a read or write access are occurring. 2. address and data are separate with 8 or 16 bits of data and up to 20 bits of address (1 mb). this scheme is used by more modern 8051 devices, as well as some pic and atmega parts. this mode is generally used with real srams, many eeproms, and many nor flash memory devices. note that there is no hardware command write support for flash memory devices; this mode should only be used for flash memory devices programmed at manufacturing time. if a flash memory device must be written and does not support a direct programming model, the command mechanism must be performed in software. the csn configuration should be used in this mode. the csn signal indicates when the address and data phases of a read or write access is occurring. the csn configuration is controlled by configuring the cscfg field to be 0x1 in the epihbncfg2 register. 3. continuous read mode where address and data are separate. this sub-mode is used for real srams which can be read more quickly by only changing the address (and not using rdn/oen strobing). in this sub-mode, reads are performed by keeping the read mode selected (output enable is asserted) and then changing the address pins. the data pins are changed by the sram after the address pins change. for example, to read data from address 0x100 and then 0x101, the epi controller asserts the output-enable signal and then configures the address pins to 0x100; the epi controller then captures what is on the data pins and increments a0 to 1 (so the address is now 0x101); the epi controller then captures what is on the data pins. note that this mode consumes higher power because the sram must continuously drive the data pins. this mode is not practical in hb16 mode for normal srams because there are generally not enough address bits available. writes are not permitted in this mode. 4. fifo mode uses 8 or 16 bits of data, removes ale and address pins and optionally adds external xfifo full/empty flag inputs. this scheme is used by many devices, such as radios, 479 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller communication devices (including usb2 devices), and some fpga configurations (fifo through block ram). this sub-mode provides the data side of the normal host-bus interface, but is paced by the fifo control signals. it is important to consider that the xfifo full/empty control signals may stall the interface and could have an impact on blocking read latency from the processor or dma. the word bit in the epihbncfg2 register can be set to use memory more efficiently. by default, the epi controller uses data bits [7:0] for host-bus 8 accesses or bits [15:0] for host-bus 16 accesses. when the word bit is set, the epi controller can automatically route bytes of data onto the correct byte lanes such that bytes or words of data can be transferred on the correct byte or half-word bits on the entire bus. for example, the most significant byte of data will be transferred on bits [31:28] in host-bus 8 mode and the most significant word of data will be transferred on bits [31:16] of host-bus 16 mode. in addition, for the three modes above (1, 2, 4) that the host-bus 16 mode supports, byte select signals can be optionally implemented by setting the bsel bit in the epihb16cfg register. note: byte accesses should not be attempted if the bsel bit has not been enabled in host-bus 16 mode. see external peripheral interface (epi) on page 1307 for timing details for the host-bus mode. 9.4.2.5 bus operation bus operation is the same in host-bus 8 and host-bus 16 modes and is asynchronous. timing diagrams show both ale and csn operation, but only one signal or the other is used in all modes except for ale with dual chip selects mode ( cscfg field is 0x3 in the epihbncfg2 register). address and data on write cycles are held after the csn signal is deasserted. the optional hb16 byte select signals have the same timing as the address signals. if wait states are required in the bus access, they can be inserted during the data phase of the access using the wrws and rdws bits in the epihbncfg2 register. each wait state adds 2 epi clock cycles to the duration of the wrn or rdn strobe. during idle cycles, the address and muxed address data signals maintain the state of the last cycle. figure 9-6 on page 480 shows a basic host-bus read cycle. figure 9-7 on page 481 shows a basic host-bus write cycle. both of these figures show address and data signals in the non-multiplexed mode ( mode field ix 0x1 in the epihbncfg register). figure 9-6. host-bus read cycle, mode = 0x1, wrhigh = 0, rdhigh = 0 july 03, 2014 480 texas instruments-production data external peripheral interface (epi) ' d w d $ / ( ( 3 , 6 & 6 q ( 3 , 6 : 5 q ( 3 , 6 5 ' q 2 ( q ( 3 , 6 $ g g u h v v ' d w d % 6 ( / q % 6 ( / q d d % 6 ( / q d q g % 6 ( / q d u h d y d l o d e o h l q + r v w % x v p r g h r q o \ figure 9-7. host-bus write cycle, mode = 0x1, wrhigh = 0, rdhigh = 0 figure 9-8 on page 481 shows a write cycle with the address and data signals multiplexed ( mode field is 0x0 in the epihbncfg register). a read cycle would look similar, with the rdn strobe being asserted along with csn and data being latched on the rising edge of rdn. figure 9-8. host-bus write cycle with multiplexed address and data, mode = 0x0, wrhigh = 0, rdhigh = 0 when using ale with dual csn configuration ( cscfg field is 0x3 in the epihbncfg2 register), the appropriate csn signal is asserted at the same time as ale, as shown in figure 9-9 on page 482. 481 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller ' d w d $ / ( ( 3 , 6 & 6 q ( 3 , 6 : 5 q ( 3 , 6 5 ' q 2 ( q ( 3 , 6 $ g g u h v v ' d w d % 6 ( / q % 6 ( / q d d % 6 ( / q d q g % 6 ( / q d u h d y d l o d e o h l q + r v w % x v p r g h r q o \ ' d w d $ / ( ( 3 , 6 & 6 q ( 3 , 6 : 5 q ( 3 , 6 5 ' q 2 ( q ( 3 , 6 $ g g u h v v k l j k r u g h u q r q p x [ h g 0 x [ h g $ g g u h v v ' d w d $ g g u h v v % 6 ( / q % 6 ( / q d d % 6 ( / q d q g % 6 ( / q d u h d y d l o d e o h l q + r v w % x v p r g h r q o \ figure 9-9. host-bus write cycle with multiplexed address and data and ale with dual csn figure 9-10 on page 482 shows continuous read mode accesses. in this mode, reads are performed by keeping the read mode selected (output enable is asserted) and then changing the address pins. the data pins are changed by the sram after the address pins change. figure 9-10. continuous read mode accesses fifo mode accesses are the same as normal read and write accesses, except that the ale signal and address pins are not present. two input signals can be used to indicate when the xfifo is full or empty to gate transactions and avoid overruns and underruns. the ffull and fempty signals are synchronized and must be recognized as asserted by the microcontroller for 2 system clocks before they affect transaction status. the maxwait field in the epihbncfg register defines the maximum number of epi clocks to wait while the fempty or ffull signal is holding off a transaction. figure 9-11 on page 483 shows how the fempty signal should respond to a write and read from the xfifo. figure 9-12 on page 483 shows how the fempty and ffull signals should respond to 2 writes and 1 read from an external fifo that contains two entries. july 03, 2014 482 texas instruments-production data external peripheral interface (epi) ' d w d $ / ( ( 3 , 6 & 6 q & 6 q ( 3 , 6 ( 3 , 6 : 5 q ( 3 , 6 5 ' q 2 ( q ( 3 , 6 $ g g u h v v k l j k r u g h u q r q p x [ h g 0 x [ h g $ g g u h v v ' d w d $ g g u h v v % 6 ( / q % 6 ( / q d d % 6 ( / q d q g % 6 ( / q d u h d y d l o d e o h l q + r v w % x v p r g h r q o \ $ g g u 2 ( q $ g g u h v v ' d w d $ g g u $ g g u ' d w d ' d w d ' d w d figure 9-11. write followed by read to external fifo figure 9-12. two-entry fifo 9.4.3 general-purpose mode the general-purpose mode configuration (epigpcfg) register is used to configure the control, data, and address pins, if used. any unused epi controller signals can be used as gpios or another alternate function. the general-purpose configuration can be used for custom interfaces with fpgas, cplds, and digital data acquisition and actuator control. important: the rd2cyc bit in the epigpcfg register must be set at all times in general-purpose mode to ensure proper operation. general-purpose mode is designed for three general types of use: extremely high-speed clocked interfaces to fpgas and cplds. three sizes of data and optional address are supported. framing and clock-enable functions permit more optimized interfaces. general parallel gpio. from 1 to 32 pins may be written or read, with the speed precisely controlled by the epibaud register baud rate (when used with the wfifo and/or the nbrfifo) or by the rate of accesses from software or dma. examples of this type of use include: C reading 20 sensors at fixed time periods by configuring 20 pins to be inputs, configuring the count0 field in the epibaud register to some divider, and then using non-blocking reads. 483 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller ) ) 8 / / ( 3 , 6 ) ( 0 3 7 < ( 3 , 6 & 6 q ( 3 , 6 : 5 q ( 3 , 6 5 ' q ( 3 , 6 ' d w d ' d w d ' d w d ) ) 8 / / ( 3 , 6 ) ( 0 3 7 < ( 3 , 6 & 6 q ( 3 , 6 : 5 q ( 3 , 6 5 ' q ( 3 , 6 ' d w d ' d w d ' d w d ' d w d C implementing a very wide ganged pwm/pcm with fixed frequency for driving actuators, leds, etc. C implementing sdio 4-bit mode where commands are driven or captured on 6 pins with fixed timing, fed by the dma. general custom interfaces of any speed. the configuration allows for choice of an output clock (free-running or gated), a framing signal (with frame size), a ready input (to stretch transactions), a read and write strobe, an address (of varying sizes), and data (of varying sizes). additionally, provisions are made for separating data and address phases. the interface has the following optional features: use of the epi clock output is controlled by the clkpin bit in the epigpcfg register. unclocked uses include general-purpose i/o and asynchronous interfaces (optionally using rd and wr strobes). clocked interfaces allow for higher speeds and are much easier to connect to fpgas and cplds (which usually include input clocks). epi clock, if used, may be free running or gated depending on the clkgate bit in the epigpcfg register. a free-running epi clock requires another method for determining when data is live, such as the frame pin or rd/wr strobes. a gated clock approach uses a setup-time model in which the epi clock controls when transactions are starting and stopping. the gated clock is held high until a new transaction is started and goes high at the end of the cycle where rd/wr/frame and address (and data if write) are emitted. use of the ready input (irdy) from the external device is controlled by the rdyen bit in the epigpcfg register. the irdy signal uses epi0s27 and may only be used with a free-running clock. irdy gates transactions, no matter what state they are in. when irdy is deasserted, the transaction is held off from completing. use of the frame output (frame) is controlled by the frmpin bit in the epigpcfg register. the frame pin may be used whether the clock is output or not, and whether the clock is free running or not. it may also be used along with the irdy signal. the frame may be a pulse (one clock) or may be 50/50 split across the frame size (controlled by the frm50 bit in the epigpcfg register). the frame count (the size of the frame as specified by the frmcnt field in the epigpcfg register) may be between 1 and 15 clocks for pulsed and between 2 and 30 clocks for 50/50. the frame pin counts transactions and not clocks; a transaction is any clock where the rd or wr strobe is high (if used). so, if the frmcnt bit is set, then the frame pin pulses every other transaction; if 2-cycle reads and writes are used, it pulses every other address phase. frm50 must be used with this in mind as it may hold state for many clocks waiting for the next transaction. use of the rd and wr outputs is controlled by the rw bit in the epigpcfg register. for interfaces where the direction is known (in advance, related to frame size, or other means), these strobes are not needed. for most other interfaces, rd and wr are used so the external peripheral knows what transaction is taking place, and if any transaction is taking place. separation of address/request and data phases may be used on writes using the wr2cyc bit in the epigpcfg register. this configuration allows the external peripheral extra time to act. address and data phases must be separated on reads, and the rd2cyc bit in the epigpcfg register must be set. when configured to use an address as specified by the asize field in the epigpcfg register, the address is emitted on the with the rd strobe (first cycle) and data is july 03, 2014 484 texas instruments-production data external peripheral interface (epi) expected to be returned on the next cycle (when rd is not asserted). if no address is used, then rd is asserted on the first cycle and data is captured on the second cycle (when rd is not asserted), allowing more setup time for data. for writes, the output may be in one or two cycles. in the two-cycle case, the address (if any) is emitted on the first cycle with the wr strobe and the data is emitted on the second cycle (with wr not asserted). although split address and write data phases are not normally needed for logic reasons, it may be useful to make read and write timings match. if 2-cycle reads or writes are used, the rw bit is automatically set. address may be emitted (controlled by the asize field in the epigpcfg register). the address may be up to 4 bits (16 possible values), up to 12 bits (4096 possible values), or up to 20 bits (1 m possible values). size of address limits size of data, for example, 4 bits of address support up to 24 bits data. 4-bit address uses epi0s[27:24] ; 12-bit address uses epi0s[27:16]; 20-bit address uses epi0s[27:8] . the address signals may be used by the external peripheral as an address, code (command), or for other unrelated uses (such as a chip enable). if the chosen address/data combination does not use all of the epi signals, the unused pins can be used as gpios or for other functions. for example, when using a 4-bit address with an 8-bit data, the pins assigned to epis0[23:8] can be assigned to other functions. data may be 8 bits, 16 bits, 24 bits, or 32 bits (controlled by the dsize field in the epigpcfg register). 32-bit data cannot be used with address or epi clock or any other signal. 24-bit data can only be used with 4-bit address or no address. 32-bit data requires that either the wr2cyc bit or the rd2cyc bit in the epigpcfg register is set. memory can be used more efficiently by using the word access mode. by default, the epi controller uses data bits [7:0] when the dsize field in the epigpcfg register is 0x0; data bits [15:0] when the dsize field is 0x1; data bits [23:0] when the dsize field is 0x2; and data bits [31:0] when the dsize field is 0x3. when the word bit in the epigpcfg2 register is set, the epi controller automatically routes bytes of data onto the correct byte lanes such that data can be stored in bits [31:8] for dsize =0x0 and bits [31:16] for dsize=0x1. when using the epi controller as a gpio interface, writes are fifoed (up to 4 can be held at any time), and up to 32 pins are changed using the epibaud clock rate specified by count0. as a result, output pin control can be very precisely controlled as a function of time. by contrast, when writing to normal gpios, writes can only occur 8-bits at a time and take up to two clock cycles to complete. in addition, the write itself may be further delayed by the bus due to dma or draining of a previous write. with both gpio and the epi controller, reads may be performed directly, in which case the current pin states are read back. with the epi controller, the non-blocking interface may also be used to perform reads based on a fixed time rule via the epibaud clock rate. table 9-7 on page 485 shows how the epi0s[31:0] signals function while in general-purpose mode. notice that the address connections vary depending on the data-width restrictions of the external peripheral. table 9-7. epi general purpose signal connections general- purpose signal (d32) general- purpose signal (d24, a4) general- purpose signal (d16, a12) general-purpose signal (d8, a20) epi signal d0 d0 d0 d0 epi0s0 d1 d1 d1 d1 epi0s1 d2 d2 d2 d2 epi0s2 485 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 9-7. epi general purpose signal connections (continued) general- purpose signal (d32) general- purpose signal (d24, a4) general- purpose signal (d16, a12) general-purpose signal (d8, a20) epi signal d3 d3 d3 d3 epi0s3 d4 d4 d4 d4 epi0s4 d5 d5 d5 d5 epi0s5 d6 d6 d6 d6 epi0s6 d7 d7 d7 d7 epi0s7 d8 d8 d8 a0 epi0s8 d9 d9 d9 a1 epi0s9 d10 d10 d10 a2 epi0s10 d11 d11 d11 a3 epi0s11 d12 d12 d12 a4 epi0s12 d13 d13 d13 a5 epi0s13 d14 d14 d14 a6 epi0s14 d15 d15 d15 a7 epi0s15 d16 d16 a0 a a8 epi0s16 d17 d17 a1 a9 epi0s17 d18 d18 a2 a10 epi0s18 d19 d19 a3 a11 epi0s19 d20 d20 a4 a12 epi0s20 d21 d21 a5 a13 epi0s21 d22 d22 a6 a14 epi0s22 d23 d23 a7 a15 epi0s23 d24 a0 b a8 a16 epi0s24 d25 a1 a9 a17 epi0s25 d26 a2 a10 a18 epi0s26 d27 a3/irdy c a11/irdy c a19/irdy c epi0s27 d28 wr wr wr epi0s28 d29 rd rd rd epi0s29 d30 frame frame frame epi0s30 d31 clock clock clock epi0s31 a. in this mode, half-word accesses are used. ao is the lsb of the address and is equivalent to the system a1 address. b. in this mode, word accesses are used. ao is the lsb of the address and is equivalent to the system a2 address. c. this signal is irdy if the rdyen bit in the epigpcfg register is set. 9.4.3.1 bus operation a basic access is 1 epi clock for write cycles and 2 epi clocks for read cycles. an additional epi clock can be inserted into a write cycle by setting the wr2cyc bit in the epigpcfg register. note that the rd2cyc bit must always be set in the epigpcfg register. july 03, 2014 486 texas instruments-production data external peripheral interface (epi) figure 9-13. single-cycle write access, frm50=0, frmcnt=0, wrcyc=0 figure 9-14. two-cycle read, write accesses, frm50=0, frmcnt=0, rdcyc=1, wrcyc=1 487 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller ' d w d & o r f n ( 3 , 6 ) u d p h ( 3 , 6 5 ' ( 3 , 6 : 5 ( 3 , 6 $ g g u h v v ' d w d 5 h d g ' d w d ' d w d & / 2 & . ( 3 , 6 ) 5 $ 0 ( ( 3 , 6 5 ' ( 3 , 6 : 5 ( 3 , 6 $ g g u h v v ' d w d : u l w h figure 9-15. read accesses, frm50=0, frmcnt=0, rdcyc=1 frame signal operation the operation of the frame signal is controlled by the frmcnt and frm50 bits. when frm50 is clear, the frame signal is high whenever the wr or rd strobe is high. when frmcnt is clear, the frame signal is simply the logical or of the wr and rd strobes so the frame signal is high during every read or write access, see figure 9-16 on page 488. figure 9-16. frame signal operation, frm50=0 and frmcnt=0 if the frmcnt field is 0x1, then the frame signal pulses high during every other read or write access, see figure 9-17 on page 488. figure 9-17. frame signal operation, frm50=0 and frmcnt=1 if the frmcnt field is 0x2 and frm50 is clear, then the frame signal pulses high during every third access, and so on for every value of frmcnt , see figure 9-18 on page 489. july 03, 2014 488 texas instruments-production data external peripheral interface (epi) $ g g u & / 2 & . ( 3 , 6 ) 5 $ 0 ( ( 3 , 6 5 ' ( 3 , 6 : 5 ( 3 , 6 $ g g u h v v ' d w d $ g g u $ g g u ' d w d ' d w d ' d w d & o r f n ( 3 , 6 ) u d p h ( 3 , 6 5 ' ( 3 , 6 : 5 ( 3 , 6 & o r f n ( 3 , 6 ) u d p h ( 3 , 6 5 ' ( 3 , 6 : 5 ( 3 , 6 figure 9-18. frame signal operation, frm50=0 and frmcnt=2 when frm50 is set, the frame signal transitions on the rising edge of either the wr or rd strobes. when frmcnt =0, the frame signal transitions on the rising edge of wr or rd for every access, see figure 9-19 on page 489. figure 9-19. frame signal operation, frm50=1 and frmcnt=0 when frmcnt =1, the frame signal transitions on the rising edge of the wr or rd strobes for every other access, see figure 9-20 on page 489. figure 9-20. frame signal operation, frm50=1 and frmcnt=1 when frmcnt =2, the frame signal transitions the rising edge of the wr or rd strobes for every third access, and so on for every value of frmcnt , see figure 9-21 on page 489. figure 9-21. frame signal operation, frm50=1 and frmcnt=2 489 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller & o r f n ( 3 , 6 ) u d p h ( 3 , 6 5 ' ( 3 , 6 : 5 ( 3 , 6 & o r f n ( 3 , 6 ) u d p h ( 3 , 6 5 ' ( 3 , 6 : 5 ( 3 , 6 & o r f n ( 3 , 6 ) u d p h ( 3 , 6 5 ' ( 3 , 6 : 5 ( 3 , 6 & / 2 & . ( 3 , 6 ) 5 $ 0 ( ( 3 , 6 5 ' ( 3 , 6 : 5 ( 3 , 6 irdy signal operation the ready input (irdy) signal can be used to lengthen bus cycles and is enabled by the rdyen bit in the epigpcfg register. irdy is input on epi0s27 and may only be used with a free-running clock ( clkgate is clear). if irdy is deasserted, further transactions are held off until the irdy signal is asserted again. irdy is sampled on the falling edge of the epi clock and gates transactions, no matter what state they are in. a two-cycle access has two phases in the bus cycle. the first clock is the address phase, and the second clock is the data phase. if irdy is sampled low at the start of the address phase, as shown in figure 26-19 on page 1312, then the address phase is extended (frame, rd, and address are all asserted) until after irdy has been sampled high again. data is sampled on the subsequent rising edge. if irdy is sampled low at the start of the data phase, as shown in figure 9-22 on page 490, the frame, rd, address, and data signals behave as they would during a normal transaction in t1. the data phase (t2) is extended with only address being asserted until irdy is recognized as asserted again. data is latched on the subsequent rising edge. figure 9-22. irdy signal operation, frm50=0, frmcnt=0, and rd2cyc=1 epi clock operation if the clkgate bit in the epigpcfg register is clear, the epi clock always toggles when general-purpose mode is enabled. if clkgate is set, the clock is output only when a transaction is occurring, otherwise the clock is held high. if the wr2cyc bit is clear, the epi clock begins toggling 1 cycle before the wr strobe goes high. if the wr2cyc bit is set, the epi clock begins toggling when the wr strobe goes high. the clock stops toggling after the first rising edge after the wr strobe is deasserted. the rd strobe operates in the same manner as the wr strobe when the wr2cyc bit is set, as the rd2cyc bit must always be set. see figure 9-23 on page 491 and figure 9-24 on page 491. july 03, 2014 490 texas instruments-production data external peripheral interface (epi) & o r f n ( 3 , 6 ) u d p h ( 3 , 6 5 ' ( 3 , 6 l 5 ' < ( 3 , 6 $ g g u h v v ' d w d 7 7 7 7 figure 9-23. epi clock operation, clkgate=1, wr2cyc=0 figure 9-24. epi clock operation, clkgate=1, wr2cyc=1 9.5 register map table 9-8 on page 491 lists the epi registers. the offset listed is a hexadecimal increment to the registers address, relative to the base address of 0x400d.0000. note that the epi controller clock must be enabled before the registers can be programmed (see page 270). there must be a delay of 3 system clocks after the epi module clock is enabled before any epi module registers are accessed. note: a back-to-back write followed by a read of the same register reads the value that written by the first write access, not the value from the second write access. (this situation only occurs when the processor core attempts this action, the dma does not do this.). to read back what was just written, another instruction must be generated between the write and read. read-write does not have this issue, so use of read-write for clear of error interrupt cause is not affected. table 9-8. external peripheral interface (epi) register map see page description reset type name offset 493 epi configuration 0x0000.0000 r/w epicfg 0x000 494 epi main baud rate 0x0000.0000 r/w epibaud 0x004 496 epi sdram configuration 0x82ee.0000 r/w episdramcfg 0x010 498 epi host-bus 8 configuration 0x0000.ff00 r/w epihb8cfg 0x010 501 epi host-bus 16 configuration 0x0000.ff00 r/w epihb16cfg 0x010 505 epi general-purpose configuration 0x0000.0000 r/w epigpcfg 0x010 510 epi host-bus 8 configuration 2 0x0000.0000 r/w epihb8cfg2 0x014 491 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller : 5 ( 3 , 6 $ g g u h v v ' d w d & o r f n ( 3 , 6 & o r f n ( 3 , 6 : 5 ( 3 , 6 $ g g u h v v ' d w d table 9-8. external peripheral interface (epi) register map (continued) see page description reset type name offset 513 epi host-bus 16 configuration 2 0x0000.0000 r/w epihb16cfg2 0x014 516 epi general-purpose configuration 2 0x0000.0000 r/w epigpcfg2 0x014 517 epi address map 0x0000.0000 r/w epiaddrmap 0x01c 519 epi read size 0 0x0000.0003 r/w epirsize0 0x020 520 epi read address 0 0x0000.0000 r/w epiraddr0 0x024 521 epi non-blocking read data 0 0x0000.0000 r/w epirpstd0 0x028 519 epi read size 1 0x0000.0003 r/w epirsize1 0x030 520 epi read address 1 0x0000.0000 r/w epiraddr1 0x034 521 epi non-blocking read data 1 0x0000.0000 r/w epirpstd1 0x038 523 epi status 0x0000.0000 ro epistat 0x060 525 epi read fifo count - ro epirfifocnt 0x06c 526 epi read fifo - ro epireadfifo 0x070 526 epi read fifo alias 1 - ro epireadfifo1 0x074 526 epi read fifo alias 2 - ro epireadfifo2 0x078 526 epi read fifo alias 3 - ro epireadfifo3 0x07c 526 epi read fifo alias 4 - ro epireadfifo4 0x080 526 epi read fifo alias 5 - ro epireadfifo5 0x084 526 epi read fifo alias 6 - ro epireadfifo6 0x088 526 epi read fifo alias 7 - ro epireadfifo7 0x08c 527 epi fifo level selects 0x0000.0033 r/w epififolvl 0x200 529 epi write fifo count 0x0000.0004 ro epiwfifocnt 0x204 530 epi interrupt mask 0x0000.0000 r/w epiim 0x210 531 epi raw interrupt status 0x0000.0004 ro epiris 0x214 533 epi masked interrupt status 0x0000.0000 ro epimis 0x218 534 epi error and interrupt status and clear 0x0000.0000 r/w1c epieisc 0x21c 9.6 register descriptions this section lists and describes the epi registers, in numerical order by address offset. july 03, 2014 492 texas instruments-production data external peripheral interface (epi) register 1: epi configuration (epicfg), offset 0x000 important: the mode field determines which configuration register is accessed for offsets 0x010 and 0x014. any write to the epicfg register resets the register contents at offsets 0x010 and 0x014. the configuration register is used to enable the block, select a mode, and select the basic pin use (based on the mode). note that attempting to program an undefined mode field clears the blken bit and disables the epi controller. epi configuration (epicfg) base 0x400d.0000 offset 0x000 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mode blken reserved r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:5 block enable description value the epi controller is disabled. 0 the epi controller is enabled. 1 0 r/w blken 4 mode select description value general purpose general-purpose mode. control, address, and data pins are configured using the epigpcfg and epigpcfg2 registers. 0x0 sdram supports sdr sdram. control, address, and data pins are configured using the episdramcfg register. 0x1 8-bit host-bus (hb8) host-bus 8-bit interface (also known as the mcu interface). control, address, and data pins are configured using the epihb8cfg and epihb8cfg2 registers. 0x2 16-bit host-bus (hb16) host-bus 16-bit interface (standard sram). control, address, and data pins are configured using the epihb16cfg and epihb16cfg2 registers. 0x3 reserved 0x3-0xf 0x0 r/w mode 3:0 493 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 2: epi main baud rate (epibaud), offset 0x004 the system clock is used internally to the epi controller. the baud rate counter can be used to divide the system clock down to control the speed on the external interface. if the mode selected emits an external epi clock, this register defines the epi clock emitted. if the mode selected does not use an epi clock, this register controls the speed of changes on the external interface. care must be taken to program this register properly so that the speed of the external bus corresponds to the speed of the external peripheral and puts acceptable current load on the pins. count0 is the bit field used in all modes except in hb8 and hb16 modes with dual chip selects when different baud rates are selected, see page 510 and page 513. if different baud rates are used, count0 is associated with the address range specified by cs0n and count1 is associated with the address range specified by cs1. the countn field is not a straight divider or count. the epi clock on epi0s31 is related to the countn field and the system clock as follows: if countn = 0, otherwise: where the symbol around countn /2 is the floor operator, meaning the largest integer less than or equal to countn/2. so, for example, a countn of 0x0001 results in a clock rate of ?(system clock); a countn of 0x0002 or 0x0003 results in a clock rate of ?(system clock). epi main baud rate (epibaud) base 0x400d.0000 offset 0x004 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 count1 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 count0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field baud rate counter 1 this bit field is only valid with multiple chip selects which are enabled when the cscfg field is 0x2 or 0x3 and the csbaud bit is set in the epihbncfg2 register. this bit field contains a counter used to divide the system clock by the count. a count of 0 means the system clock is used as is. 0x0000 ro count1 31:16 july 03, 2014 494 texas instruments-production data external peripheral interface (epi) kfreq systemcloc eq epiclockfr = 2 1 2 ? ? ? ? ? ? + ? ? ? ? ? ? = countn kfreq systemcloc eq epiclockfr description reset type name bit/field baud rate counter 0 this bit field contains a counter used to divide the system clock by the count. a count of 0 means the system clock is used as is. 0x0000 r/w count0 15:0 495 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 3: epi sdram configuration (episdramcfg), offset 0x010 important: the mode field in the epicfg register determines which configuration register is accessed for offsets 0x010 and 0x014. to access episdramcfg , the mode field must be 0x1. the sdram configuration register is used to specify several parameters for the sdram controller. note that this register is reset when the mode field in the epicfg register is changed. if another mode is selected and the sdram mode is selected again, the values must be reinitialized. the sdram interface is designed to interface to x16 sdr sdrams of 64 mhz or higher, with the address and data pins overlapped (wire ored on the board). see table 9-3 on page 469 for pin assignments. epi sdram configuration (episdramcfg) base 0x400d.0000 offset 0x010 type r/w, reset 0x82ee.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rfsh reserved freq r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro r/w r/w type 0 1 1 1 0 1 1 1 0 1 0 0 0 0 0 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 size reserved sleep reserved r/w r/w ro ro ro ro ro ro ro r/w ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field epi frequency range this field configures the frequency range used for delay references by internal counters. this epi frequency is the system frequency with the divider programmed by the count0 bit in the epibaudn register bit. this field affects the power up, precharge, and auto refresh delays. this field does not affect the refresh counting, which is configured separately using the rfsh field (and is based on system clock rate and number of rows per bank). the ranges are: description value 0 - 15 mhz 0x0 15 - 30 mhz 0x1 30 - 50 mhz 0x2 50 - 100 mhz 0x3 0x2 r/w freq 31:30 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 29:27 refresh counter this field contains the refresh counter in system clocks. the reset value of 0x2ee provides a refresh period of 64 ms when using a 50 mhz clock. 0x2ee r/w rfsh 26:16 july 03, 2014 496 texas instruments-production data external peripheral interface (epi) description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 15:10 sleep mode description value no effect. 0 the sdram is put into low power state, but is self-refreshed. 1 0 r/w sleep 9 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 8:2 size of sdram the value of this field affects address pins and behavior. description value 64 megabits (8mb) 0x0 128 megabits (16mb) 0x1 256 megabits (32mb) 0x2 512 megabits (64mb) 0x3 0x0 r/w size 1:0 497 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 4: epi host-bus 8 configuration (epihb8cfg), offset 0x010 important: the mode field in the epicfg register determines which configuration register is accessed for offsets 0x010 and 0x014. to access epihb8cfg , the mode field must be 0x2. the host bus 8 configuration register is activated when the hb8 mode is selected. the hb8 mode supports muxed address/data (overlay of lower 8 address and all 8 data pins), separate address/data, and address-less fifo mode. note that this register is reset when the mode field in the epicfg register is changed. if another mode is selected and the hb8 mode is selected again, the values must be reinitialized. this mode is intended to support srams, flash memory (read), fifos, cplds/fpgas, and devices with an mcu/hostbus slave or 8-bit fifo interface support. refer to table 9-5 on page 474 for information on signal configuration controlled by this register and the epihb8cfg2 register. if less address pins are required, the corresponding afsel bit (page 429) should not be enabled so the epi controller does not drive those pins, and they are available as standard gpios. epi host-bus 8 mode can be configured to use one chip select with and without the use of ale. if an alternative to chip selects are required, a chip enable can be handled in one of three ways: 1. manually control via gpios. 2. associate one or more upper address pins to ce. because ce is normally cen, lower addresses are not used. for example, if pins epi0s27 and epi0s26 are used for device 1 and 0 respectively, then address 0x6800.0000 accesses device 0 (device 1 has its cen high), and 0x6400.0000 accesses device 1 (device 0 has its cen high). the pull-up behavior on the corresponding gpios must be properly configured to ensure that the pins are disabled when the interface is not in use. 3. with certain srams, the ale can be used as cen because the address remains stable after the ale strobe. the subsequent wrn or rdn signals write or read when ale is low thus providing cen functionality. epi host-bus 8 configuration (epihb8cfg) base 0x400d.0000 offset 0x010 type r/w, reset 0x0000.ff00 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved rdhigh wrhigh xfeen xffen reserved ro ro ro ro r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mode reserved rdws wrws maxwait r/w r/w ro ro r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:24 july 03, 2014 498 texas instruments-production data external peripheral interface (epi) description reset type name bit/field external fifo full enable description value no effect. 0 an external fifo full signal can be used to control write cycles. if this bit is set and the ffull full signal is high, xfifo writes are stalled. 1 0 r/w xffen 23 external fifo empty enable description value no effect. 0 an external fifo empty signal can be used to control read cycles. if this bit is set and the fempty signal is high, xfifo reads are stalled. 1 0 r/w xfeen 22 write strobe polarity description value the write strobe for cs0n is wrn (active low). 0 the write strobe for cs0n is wr (active high). 1 0 r/w wrhigh 21 read strobe polarity description value the read strobe for cs0n is rdn (active low). 0 the read strobe for cs0n is rd (active high). 1 0 r/w rdhigh 20 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 19:16 maximum wait this field defines the maximum number of external clocks to wait while an external fifo ready signal is holding off a transaction (ffull and fempty). when the maxwait value is reached the errris interrupt status bit is set in the epiris register. when this field is clear, the transaction can be held off forever without a system interrupt. note: when the mode field is configured to be 0x2 and the blken bit is set in the epicfg register, enabling hb8 mode, this field defaults to 0xff. 0xff r/w maxwait 15:8 499 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field write wait states this field adds wait states to the data phase of cs0n (the address phase is not affected). the effect is to delay the rising edge of wrn (or the falling edge of wr). each wait state adds 2 epi clock cycles to the access time. description value active wrn is 2 epi clocks. 0x0 active wrn is 4 epi clocks. 0x1 active wrn is 6 epi clocks. 0x2 active wrn is 8 epi clocks. 0x3 this field is used in conjunction with the epibaud register. 0x0 r/w wrws 7:6 read wait states this field adds wait states to the data phase of cs0n (the address phase is not affected). the effect is to delay the rising edge of rdn/oen (or the falling edge of rd). each wait state adds 2 epi clock cycles to the access time. description value active rdn is 2 epi clocks. 0x0 active rdn is 4 epi clocks. 0x1 active rdn is 6 epi clocks. 0x2 active rdn is 8 epi clocks. 0x3 this field is used in conjunction with the epibaud register 0x0 r/w rdws 5:4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 3:2 host bus sub-mode this field determines which of four host bus 8 sub-modes to use. sub-mode use is determined by the connected external peripheral. see table 9-5 on page 474 for information on how this bit field affects the operation of the epi signals. description value admux C ad[7:0] data and address are muxed. 0x0 adnonmux C d[7:0] data and address are separate. 0x1 continuous read - d[7:0] this mode is the same as adnonmux, but uses address switch for multiple reads instead of oen strobing. 0x2 xfifo C d[7:0] this mode adds xfifo controls with sense of xfifo full and xfifo empty. this mode uses no address or ale. 0x3 0x0 r/w mode 1:0 july 03, 2014 500 texas instruments-production data external peripheral interface (epi) register 5: epi host-bus 16 configuration (epihb16cfg), offset 0x010 important: the mode field in the epicfg register determines which configuration register is accessed for offsets 0x010 and 0x014. to access epihb16cfg , the mode field must be 0x3. the host bus 16 sub-configuration register is activated when the hb16 mode is selected. the hb16 mode supports muxed address/data (overlay of lower 16 address and all 16 data pins), separated address/data, and address-less fifo mode. note that this register is reset when the mode field in the epicfg register is changed. if another mode is selected and the hb16 mode is selected again, the values must be reinitialized. this mode is intended to support srams, flash memory (read), fifos, and cplds/fpgas, and devices with an mcu/hostbus slave or 16-bit fifo interface support. refer to table 9-6 on page 476 for information on signal configuration controlled by this register and the epihb16cfg2 register. if less address pins are required, the corresponding afsel bit (page 429) should not be enabled so the epi controller does not drive those pins, and they are available as standard gpios. epi host-bus 16 mode can be configured to use one to four chip selects with and without the use of ale. if an alternative to chip selects are required, a chip enable can be handled in one of three ways: 1. manually control via gpios. 2. associate one or more upper address pins to ce. because ce is normally cen, lower addresses are not used. for example, if pins epi0s27 and epi0s26 are used for device 1 and 0 respectively, then address 0x6800.0000 accesses device 0 (device 1 has its cen high), and 0x6400.0000 accesses device 1 (device 0 has its cen high). the pull-up behavior on the corresponding gpios must be properly configured to ensure that the pins are disabled when the interface is not in use. 3. with certain srams, the ale can be used as cen because the address remains stable after the ale strobe. the subsequent wrn or rdn signals write or read when ale is low thus providing cen functionality. epi host-bus 16 configuration (epihb16cfg) base 0x400d.0000 offset 0x010 type r/w, reset 0x0000.ff00 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved rdhigh wrhigh xfeen xffen reserved ro ro ro ro r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mode bsel reserved rdws wrws maxwait r/w r/w r/w ro r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 reset 501 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:24 external fifo full enable description value no effect. 0 an external fifo full signal can be used to control write cycles. if this bit is set and the ffull signal is high, xfifo writes are stalled. 1 0 r/w xffen 23 external fifo empty enable description value an external fifo empty signal can be used to control read cycles. if this bit is set and the fempty signal is high, xfifo reads are stalled. 1 no effect. 0 0 r/w xfeen 22 write strobe polarity description value the write strobe for cs0n is wrn (active low). 0 the write strobe for cs0n is wr (active high). 1 0 r/w wrhigh 21 read strobe polarity description value the read strobe for cs0n is rdn (active low). 0 the read strobe is rd (active high). 1 0 r/w rdhigh 20 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 19:16 maximum wait this field defines the maximum number of external clocks to wait while an external fifo ready signal is holding off a transaction (ffull and fempty). when this field is clear, the transaction can be held off forever without a system interrupt. note: when the mode field is configured to be 0x3 and the blken bit is set in the epicfg register, enabling hb16 mode, this field defaults to 0xff. 0xff r/w maxwait 15:8 july 03, 2014 502 texas instruments-production data external peripheral interface (epi) description reset type name bit/field write wait states this field adds wait states to the data phase of cs0n (the address phase is not affected). the effect is to delay the rising edge of wrn (or the falling edge of wr). each wait state adds 2 epi clock cycles to the access time. description value active wrn is 2 epi clocks. 0x0 active wrn is 4 epi clocks. 0x1 active wrn is 6 epi clocks. 0x2 active wrn is 8 epi clocks. 0x3 this field is used in conjunction with the epibaud register. 0x0 r/w wrws 7:6 read wait states this field adds wait states to the data phase of cs0n (the address phase is not affected). the effect is to delay the rising edge of rdn/oen (or the falling edge of rd). each wait state adds 2 epi clock cycles to the access time. description value active rdn is 2 epi clocks. 0x0 active rdn is 4 epi clocks. 0x1 active rdn is 6 epi clocks. 0x2 active rdn is 8 epi clocks. 0x3 this field is used in conjunction with the epibaud register 0x0 r/w rdws 5:4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 3 byte select configuration this bit enables byte select operation. description value no byte selects data is read and written as 16 bits. 0 enable byte selects two epi signals function as byte select signals to allow 8-bit transfers. see table 9-6 on page 476 for details on which epi signals are used. 1 0 r/w bsel 2 503 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field host bus sub-mode this field determines which of three host bus 16 sub-modes to use. sub-mode use is determined by the connected external peripheral. see table 9-6 on page 476 for information on how this bit field affects the operation of the epi signals. description value admux C ad[15:0] data and address are muxed. 0x0 adnonmux C d[15:0] data and address are separate. this mode is not practical in hb16 mode for normal peripherals because there are generally not enough address bits available. 0x1 continuous read - d[15:0] this mode is the same as adnonmux, but uses address switch for multiple reads instead of oen strobing. this mode is not practical in hb16 mode for normal srams because there are generally not enough address bits available. 0x2 xfifo C d[15:0] this mode adds xfifo controls with sense of xfifo full and xfifo empty. this mode uses no address or ale. 0x3 0x0 r/w mode 1:0 july 03, 2014 504 texas instruments-production data external peripheral interface (epi) register 6: epi general-purpose configuration (epigpcfg), offset 0x010 important: the mode field in the epicfg register determines which configuration register is accessed for offsets 0x010 and 0x014. to access epigpcfg , the mode field must be 0x0. the rd2cyc bit must be set at all times in general-purpose mode to ensure proper operation. the general-purpose configuration register is used to configure the control, data, and address pins. this mode can be used for custom interfaces with fpgas, cplds, and for digital data acquisition and actuator control. note that this register is reset when the mode field in the epicfg register is changed. if another mode is selected and the general-purpose mode is selected again, the register the values must be reinitialized. this mode is designed for 3 general types of use: extremely high-speed clocked interfaces to fpgas and cplds, with 3 sizes of data and optional address. framing and clock-enable permit more optimized interfaces. general parallel gpio. from 1 to 32 pins may be written or read, with the speed precisely controlled by the baud rate in the epibaud register (when used with the nbrfifo and/or the wfifo) or by rate of accesses from software or dma. general custom interfaces of any speed. the configuration allows for choice of an output clock (free running or gated), a framing signal (with frame size), a ready input (to stretch transactions), read and write strobes, address of varying sizes, and data of varying sizes. additionally, provisions are made for splitting address and data phases on the external interface. epi general-purpose configuration (epigpcfg) base 0x400d.0000 offset 0x010 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved rd2cyc wr2cyc reserved rw frmcnt frm50 frmpin rdyen reserved clkgate clkpin ro ro r/w r/w ro r/w r/w r/w r/w r/w r/w r/w r/w ro r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dsize reserved asize reserved maxwait r/w r/w ro ro r/w r/w ro ro r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field clock pin description value no clock output. 0 epi0s31 functions as the epi clock output. 1 the epi clock is generated from the count0 field in the epibaud register (as is the system clock which is divided down from it). 0 r/w clkpin 31 505 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field clock gated description value the epi clock is free running. 0 the epi clock is output only when there is data to write or read (current transaction); otherwise the epi clock is held low. 1 note that epi0s27 is an irdy signal if rdyen is set. clkgate is ignored if clkpin is 0 or if the count0 field in the epibaud register is cleared. 0 r/w clkgate 30 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 29 ready enable description value the external peripheral does not drive an irdy signal and is assumed to be ready always. 0 the external peripheral drives an irdy signal into pin epi0s27. 1 the ready enable signal may only be used with a free-running epi clock (clkgate=0). the external irdy signal is sampled on the falling edge of the epi clock. setup and hold times must be met to ensure registration on the next falling epi clock edge. this bit is ignored if clkpin is 0 or clkgate is 1. 0 r/w rdyen 28 framing pin description value no framing signal is output. 0 a framing signal is output on epi0s30. 1 framing has no impact on data itself, but forms a context for the external peripheral. when used with a free-running epi clock, the frame signal forms the valid signal. when used with a gated epi clock, it is usually used to form a frame size. 0 r/w frmpin 27 50/50 frame description value the frame signal is output as a single pulse, and then held low for the count. 0 the frame signal is output as 50/50 duty cycle using count (see frmcnt). 1 this bit is ignored if frmpin is 0. 0 r/w frm50 26 july 03, 2014 506 texas instruments-production data external peripheral interface (epi) description reset type name bit/field frame count this field specifies the size of the frame in epi clocks. the frame counter is used to determine the frame size. the count is frmcnt +1. so, a frmcnt of 0 forms a pure transaction valid signal (held high during transactions, low otherwise). a frmcnt of 0 with frm50 set inverts the frame signal on each transaction. a frmcnt of 1 means the frame signal is inverted every other transaction; a value of 15 means every sixteenth transaction. if frm50 is set, the frame is held high for frmcnt +1 transactions, then held low for that many transactions, and so on. if frm50 is clear, the frame is pulsed high for one epi clock and then low for frmcnt epi clocks. this field is ignored if frmpin is 0. 0x0 r/w frmcnt 25:22 read and write description value rd and wr strobes are not output. 0 rd and wr strobes are asserted on epi0s29 and epi0s28. rd is asserted high on the rising edge of the epi clock when a read is being performed. wr is asserted high on the rising edge of the epi clock when a write is being performed 1 this bit is forced to 1 when rd2cyc and/or wr2cyc is 1. 0 r/w rw 21 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 20 2-cycle writes description value data is output on the same epi clock cycle as the address. 0 writes are two epi clock cycles long, with address on one epi clock cycle (with the wr strobe asserted) and data written on the following epi clock cycle (with wr strobe de-asserted). the next address (if any) is in the cycle following. 1 when this bit is set, then the rw bit is forced to be set. 0 r/w wr2cyc 19 2-cycle reads description value data is captured on the epi clock cycle with read strobe asserted. 0 reads are two epi clock cycles, with address on one epi clock cycle (with the rd strobe asserted) and data captured on the following epi clock cycle (with the rd strobe de-asserted). the next address (if any) is in the cycle following. 1 when this bit is set, then the rw bit is forced to be set. caution C this bit must be set at all times in general-purpose mode to ensure proper operation. 0 r/w rd2cyc 18 507 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 17:16 maximum wait this field defines the maximum number of epi clocks to wait while the irdy signal (see rdyen ) is holding off a transaction. if this field is 0, the transaction is held forever. if the maximum wait of 255 clocks (maxwait =0xff) is exceeded, an error interrupt occurs and the transaction is aborted/ignored. note: when the mode field is configured to be 0x0 and the blken bit is set in the epicfg register, enabling general-purpose mode, this field defaults to 0xff. 0x00 r/w maxwait 15:8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 7:6 address bus size this field defines the size of the address bus. the address can be up to 4-bits wide with a 24-bit data bus, up to 12-bits wide with a 16-bit data bus, and up to 20-bits wide with an 8-bit data bus. if the full address bus is not used, use the least significant address bits. any unused address bits can be used as gpios by clearing the afsel bit for the corresponding gpios. also, if rdyen is 1, then the address sizes are 1 smaller (3, 11, 19). the values are: description value no address 0x0 up to 4 bits wide. 0x1 up to 12 bits wide. this size cannot be used with 24-bit data. 0x2 up to 20 bits wide. this size cannot be used with data sizes other than 8. 0x3 0x0 r/w asize 5:4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 3:2 july 03, 2014 508 texas instruments-production data external peripheral interface (epi) description reset type name bit/field size of data bus this field defines the size of the data bus (starting at epi0s0 ). subsets of these numbers can be created by clearing the afsel bit for the corresponding gpios. note that size 32 may not be used with clock, frame, address, or other control. the values are: description value 8 bits wide ( epi0s0 to epi0s7) 0x0 16 bits wide ( epi0s0 to epi0s15) 0x1 24 bits wide ( epi0s0 to epi0s23) 0x2 32 bits wide ( epi0s0 to epi0s31) this size may not be used with an epi clock. this value is normally used for acquisition input and actuator control as well as other general-purpose uses that require 32 bits per direction. 0x3 0x0 r/w dsize 1:0 509 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 7: epi host-bus 8 configuration 2 (epihb8cfg2), offset 0x014 important: the mode field in the epicfg register determines which configuration register is accessed for offsets 0x010 and 0x014. to access epihb8cfg2 , the mode field must be 0x2. this register is used to configure operation while in host-bus 8 mode. note that this register is reset when the mode field in the epicfg register is changed. if another mode is selected and the host-bus 8 mode is selected again, the values must be reinitialized. epi host-bus 8 configuration 2 (epihb8cfg2) base 0x400d.0000 offset 0x014 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved rdhigh wrhigh reserved cscfg csbaud reserved word ro ro ro ro r/w r/w ro ro r/w r/w r/w ro ro ro ro r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved rdws wrws reserved ro ro ro ro r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field word access mode by default, the epi controller uses data bits [7:0] for host-bus 8 accesses. when using word access mode, the epi controller can automatically route bytes of data onto the correct byte lanes such that data can be stored in bits [31:8]. when word is set, short and long variables can be used in c programs. description value word access mode is disabled. 0 word access mode is enabled. 1 0 r/w word 31 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 30:27 chip select baud rate description value same baud rate both cs0n and cs1n use the baud rate for the external bus that is defined by the count0 field in the epibaud register. 0 different baud rates cs0n uses the baud rate for the external bus that is defined by the count0 field in the epibaud register. cs1n uses the baud rate defined by the count1 field in the epibaud register. 1 0 r/w csbaud 26 july 03, 2014 510 texas instruments-production data external peripheral interface (epi) description reset type name bit/field chip select configuration this field controls the chip select options, including an ale format, a single chip select, two chip selects, and an ale combined with two chip selects. description value ale configuration epi0s30 is used as an address latch (ale). the ale signal is generally used when the address and data are muxed ( hb8mode field in the epihb8cfg register is 0x0). the ale signal is used by an external latch to hold the address through the bus cycle. 0x0 csn configuration epi0s30 is used as a chip select (csn). when using this mode, the address and data are generally not muxed ( hb8mode field in the epihb8cfg register is 0x1). however, if address and data muxing is needed, the wr signal ( epi0s29 ) and the rd signal ( epi0s28 ) can be used to latch the address when csn is low. 0x1 dual csn configuration epi0s30 is used as cs0n and epi0s27 is used as cs1n. whether cs0n or cs1n is asserted is determined by two methods. if only external ram or external per is enabled in the address map, the most significant address bit for a respective external address map controls cs0n or cs1n. if both external ram and external per is enabled, cs0n is mapped to per and cs1n is mapped to ram. this configuration can be used for a ram bank split between 2 devices as well as when using both an external ram and an external peripheral. 0x2 ale with dual csn configuration epi0s30 is used as address latch (ale), epi0s27 is used as cs1n, and epi0s26 is used as cs0n. whether cs0n or cs1n is asserted is determined by the most significant address bit for a respective external address map. 0x3 0x0 r/w cscfg 25:24 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 23:22 cs1n write strobe polarity this field is used if the csbaud bit in the epihbncfg2 register is enabled. description value the write strobe for cs1n accesses is wrn (active low). 0 the write strobe for cs1n accesses is wr (active high). 1 0 r/w wrhigh 21 511 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field cs1n read strobe polarity this field is used if the csbaud bit in the epihbncfg2 register is enabled. description value the read strobe for cs1n accesses is rdn (active low). 0 the read strobe for cs1n accesses is rd (active high). 1 0 r/w rdhigh 20 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 19:8 cs1n write wait states this field adds wait states to the data phase of cs1n accesses (the address phase is not affected). the effect is to delay the rising edge of wrn (or the falling edge of wr). each wait state encoding adds 2 epi clock cycles to the access time. description value active wrn is 2 epi clocks. 0x0 active wrn is 4 epi clocks 0x1 active wrn is 6 epi clocks 0x2 active wrn is 8 epi clocks 0x3 0x0 r/w wrws 7:6 cs1n read wait states this field adds wait states to the data phase of cs1n accesses (the address phase is not affected). the effect is to delay the rising edge of rdn/oen (or the falling edge of rd). each wait state encoding adds 2 epi clock cycles to the access time. description value active rdn is 2 epi clocks 0x0 active rdn is 4 epi clocks 0x1 active rdn is 6 epi clocks 0x2 active rdn is 8 epi clocks 0x3 0x0 r/w rdws 5:4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 3:0 july 03, 2014 512 texas instruments-production data external peripheral interface (epi) register 8: epi host-bus 16 configuration 2 (epihb16cfg2), offset 0x014 important: the mode field in the epicfg register determines which configuration register is accessed for offsets 0x010 and 0x014. to access epihb16cfg2 , the mode field must be 0x3. this register is used to configure operation while in host-bus 16 mode. note that this register is reset when the mode field in the epicfg register is changed. if another mode is selected and the host-bus 16 mode is selected again, the values must be reinitialized. epi host-bus 16 configuration 2 (epihb16cfg2) base 0x400d.0000 offset 0x014 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved rdhigh wrhigh reserved cscfg csbaud reserved word ro ro ro ro r/w r/w ro ro r/w r/w r/w ro ro ro ro r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved wrws reserved ro ro ro ro ro ro r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field word access mode by default, the epi controller uses data bits [15:0] for host-bus 16 accesses. when using word access mode, the epi controller can automatically route bytes of data onto the correct byte lanes such that data can be stored in bits [31:16]. when word is set, long variables can be used in c programs. description value word access mode is disabled. 0 word access mode is enabled. 1 0 r/w word 31 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 30:27 chip select baud rate description value same baud rate all csn use the baud rate for the external bus that is defined by the count0 field in the epibaud register. 0 different baud rates cs0n uses the baud rate for the external bus that is defined by the count0 field in the epibaud register. cs1n uses the baud rate defined by the count1 field in the epibaud register. 1 0 r/w csbaud 26 513 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field chip select configuration this field controls the chip select options, including an ale format, a single chip select, two chip selects, and an ale combined with two chip selects. description value ale configuration epi0s30 is used as an address latch (ale). when using this mode, the address and data should be muxed ( hb16mode field in the epihb16cfg register should be configured to 0x0). if needed, the address can be latched by external logic. 0x0 csn configuration epi0s30 is used as a chip select (csn). when using this mode, the address and data should not be muxed ( mode field in the epihb16cfg register should be configured to 0x1). in this mode, the wr signal ( epi0s29 ) and the rd signal (epi0s28) are used to latch the address when csn is low. 0x1 dual csn configuration epi0s30 is used as cs0n and epi0s27 is used as cs1n. whether cs0n or cs1n is asserted is determined by the most significant address bit for a respective external address map. this configuration can be used for a ram bank split between 2 devices as well as when using both an external ram and an external peripheral. 0x2 ale with dual csn configuration epi0s30 is used as address latch (ale), epi0s27 is used as cs1n, and epi0s26 is used as cs0n. whether cs0n or cs1n is asserted is determined by the most significant address bit for a respective external address map. 0x3 0x0 r/w cscfg 25:24 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 23:22 cs1n write strobe polarity this field is used if csbaud bit of the epihbncfg2 register is enabled. description value the write strobe for cs1n accesses is wrn (active low). 0 the write strobe for cs1n accesses is wr (active high). 1 0 r/w wrhigh 21 cs1n read strobe polarity this field is used if csbaud bit of the epihbncfg2 register is enabled. description value the read strobe for cs1n accesses is rdn (active low). 0 the read strobe for cs1n accesses is rd (active high). 1 0 r/w rdhigh 20 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 19:8 july 03, 2014 514 texas instruments-production data external peripheral interface (epi) description reset type name bit/field cs1n write wait states this field adds wait states to the data phase of cs1n accesses (the address phase is not affected). the effect is to delay the rising edge of wrn (or the falling edge of wr). each wait state encoding adds 2 epi clock cycles to the access time. description value active wrn is 2 epi clocks 0x0 active wrn is 4 epi clocks. 0x1 active wrn is 6 epi clocks 0x2 active wrn is 8 epi clocks 0x3 0x0 r/w wrws 7:6 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 5:0 515 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 9: epi general-purpose configuration 2 (epigpcfg2), offset 0x014 important: the mode field in the epicfg register determines which configuration register is accessed for offsets 0x010 and 0x014. to access epigpcfg2 , the mode field must be 0x0. this register is used to configure operation while in general-purpose mode. note that this register is reset when the mode field in the epicfg register is changed. if another mode is selected and the general-purpose mode is selected again, the values must be reinitialized. epi general-purpose configuration 2 (epigpcfg2) base 0x400d.0000 offset 0x014 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved word ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field word access mode by default, the epi controller uses data bits [7:0] when the dsize field in the epigpcfg register is 0x0; data bits [15:0] when the dsize field is 0x1; data bits [23:0] when the dsize field is 0x2; and data bits [31:0] when the dsize field is 0x3. when using word access mode, the epi controller can automatically route bytes of data onto the correct byte lanes such that data can be stored in bits [31:8] for dsize =0x0 and bits [31:16] for dsize =0x1. for dsize =0x2 or 0x3, this bit must be clear. description value word access mode is disabled. 0 word access mode is enabled. 1 0 r/w word 31 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000.0000 ro reserved 30:0 july 03, 2014 516 texas instruments-production data external peripheral interface (epi) register 10: epi address map (epiaddrmap), offset 0x01c this register enables address mapping. the epi controller can directly address memory and peripherals. in addition, the epi controller supports address mapping to allow indirect accesses in the external ram and external peripheral areas. if the external device is a peripheral, including a fifo or a directly addressable device, the epsz and epadr bit fields should be configured for the address space. if the external device is sdram, sram, or nor flash memory, the eradr and ersz bit fields should be configured for the address space. if one of the dual chip select modes is selected ( cscfg is 0x2 or 0x3 in the epihbncfg2 register), both chip selects can share the peripheral or the memory space, or one chip select can use the peripheral space and the other can use the memory space. in the epiaddrmap register, if the epadr field is not 0x0 and the eradr field is 0x0, then the address specified by epadr is used for both chip selects, with cs0n being asserted when the msb of the address range is 0 and cs1n being asserted when the msb of the address range is 1. if the eradr field is not 0x0 and the epadr field is 0x0, then the address specified by eradr is used for both chip selects, with the msb performing the same delineation. if both the epadr and the eradr are not 0x0 , then cs0n is asserted for either address range defined by epadr and cs1n is asserted for either address range defined by eradr. epi address map (epiaddrmap) base 0x400d.0000 offset 0x01c type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 eradr ersz epadr epsz reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 external peripheral size this field selects the size of the external peripheral. if the size of the external peripheral is larger, a bus fault occurs. if the size of the external peripheral is smaller, it wraps (upper address bits unused). note: when not using byte selects in host-bus 16, data is accessed on 2-byte boundaries. as a result, the available address space is double the amount shown below. description value 256 bytes; lower address range: 0x00 to 0xff 0x0 64 kb; lower address range: 0x0000 to 0xffff 0x1 16 mb; lower address range: 0x00.0000 to 0xff.ffff 0x2 512 mb; lower address range: 0x000.0000 to 0x1fff.ffff 0x3 0x0 r/w epsz 7:6 517 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field external peripheral address this field selects address mapping for the external peripheral area. description value not mapped 0x0 at 0xa000.0000 0x1 at 0xc000.0000 0x2 reserved 0x3 0x0 r/w epadr 5:4 external ram size this field selects the size of mapped ram. if the size of the external memory is larger, a bus fault occurs. if the size of the external memory is smaller, it wraps (upper address bits unused): description value 256 bytes; lower address range: 0x00 to 0xff 0x0 64 kb; lower address range: 0x0000 to 0xffff 0x1 16 mb; lower address range: 0x00.0000 to 0xff.ffff 0x2 512 mb; lower address range: 0x000.0000 to 0x1fff.ffff 0x3 0x0 r/w ersz 3:2 external ram address selects address mapping for external ram area: description value not mapped 0x0 at 0x6000.0000 0x1 at 0x8000.0000 0x2 reserved 0x3 0x0 r/w eradr 1:0 july 03, 2014 518 texas instruments-production data external peripheral interface (epi) register 11: epi read size 0 (epirsize0), offset 0x020 register 12: epi read size 1 (epirsize1), offset 0x030 this register selects the size of transactions when performing non-blocking reads with the epirpstdn registers. this size affects how the external address is incremented. the size field must match the external data width as configured in the epihbncfg or epigpcfg register if the word bit is clear in the epihbncfg2 or epigpcfg2 register. if the word bit is set, the size field must be greater than or equal to the external data width. sdram mode uses a 16-bit data interface. if size is 0x1, data is returned on the least significant bits (d[7:0]), and the remaining bits d[31:8] are all zeros, therefore the data on bits d[15:8] is lost. if size is 0x2, data is returned on the least significant bits (d[15:0]), and the remaining bits d[31:16] are all zeros. note that changing this register while a read is active has an unpredictable effect. epi read size 0 (epirsize0) base 0x400d.0000 offset 0x020 type r/w, reset 0x0000.0003 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 size reserved r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:2 current size description value reserved 0x0 byte (8 bits) 0x1 half-word (16 bits) 0x2 word (32 bits) 0x3 0x3 r/w size 1:0 519 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 13: epi read address 0 (epiraddr0), offset 0x024 register 14: epi read address 1 (epiraddr1), offset 0x034 this register holds the current address value. when performing non-blocking reads via the epirpstdn registers, this registers value forms the address (when used by the mode). that is, when an epirpstdn register is written with a non-0 value, this register is used as the first address. after each read, it is incremented by the size specified by the corresponding epirsizen register. thus at the end of a read, this register contains the next address for the next read. for example, if the last read was 0x20, and the size is word, then the register contains 0x24. when a non-blocking read is cancelled, this register contains the next address that would have been read had it not been cancelled. for example, if reading by bytes and 0x103 had been read but not 0x104, this register contains 0x104. in this manner, the system can determine the number of values in the nbrfifo to drain. note that changing this register while a read is active has an unpredictable effect due to race condition. epi read address 0 (epiraddr0) base 0x400d.0000 offset 0x024 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 addr reserved r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 addr r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 31:29 current address next address to read. 0x000.0000 r/w addr 28:0 july 03, 2014 520 texas instruments-production data external peripheral interface (epi) register 15: epi non-blocking read data 0 (epirpstd0), offset 0x028 register 16: epi non-blocking read data 1 (epirpstd1), offset 0x038 this register sets up a non-blocking read via the external interface. a non-blocking read is started by writing to this register with the count (other than 0). clearing this register terminates an active non-blocking read as well as cancelling any that are pending. this register should always be cleared before writing a value other than 0; failure to do so can cause improper operation. note that both nbr channels can be enabled at the same time, but nbr channel 0 has the highest priority and channel 1 does not start until channel 0 is finished. the first address is based on the corresponding epiraddrn register. the address register is incremented by the size specified by the epirsizen register after each read. if the size is less than a word, only the least significant bits of data are filled into the nbrfifo; the most significant bits are cleared. note that all three registers may be written using one stm instruction, such as with a structure copy in c/c++. the data may be read from the epireadfifo register after the read cycle is completed. the interrupt mechanism is normally used to trigger the fifo reads via isr or dma. if the countdown has not reached 0 and the nbrfifo is full, the external interface waits until a nbrfifo entry becomes available to continue. note: if a blocking read or write is performed through the address mapped area (at 0x6000.0000 through 0xdfff.ffff), any current non-blocking read is paused (at the next safe boundary), and the blocking request is inserted. after completion of any blocking reads or writes, the non-blocking reads continue from where they were paused. the other way to read data is via the address mapped locations (see the epiaddrmap register), but this method is blocking (core or dma waits until result is returned). to cancel a non-blocking read, clear this register. to make sure that all values read are drained from the nbrfifo, the epistat register must be consulted to be certain that bits nbrbusy and active are cleared. one of these registers should not be cleared until either the other epirpstdn register becomes active or the external interface is not busy. at that point, the corresponding epiraddrn register indicates how many values were read. epi non-blocking read data 0 (epirpstd0) base 0x400d.0000 offset 0x028 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 postcnt reserved r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0 ro reserved 31:13 521 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field post count a write of a non-zero value starts a read operation for that count. note that it is the software's responsibility to handle address wrap-around. reading this register provides the current count. a write of 0 cancels a non-blocking read (whether active now or pending). prior to writing a non-zero value, this register must first be cleared. 0x000 r/w postcnt 12:0 july 03, 2014 522 texas instruments-production data external peripheral interface (epi) register 17: epi status (epistat), offset 0x060 this register indicates which non-blocking read register is currently active; it also indicates whether the external interface is busy performing a write or non-blocking read (it cannot be performing a blocking read, as the bus would be blocked and as a result, this register could not be accessed). this register is useful to determining which non-blocking read register is active when both are loaded with values and when implementing sequencing or sharing. this register is also useful when canceling non-blocking reads, as it shows how many values were read by the canceled side. epi status (epistat) base 0x400d.0000 offset 0x060 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 active reserved nbrbusy wbusy initseq xfempty xffull celow reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:10 clock enable low this bit provides information on the clock status when in general-purpose mode and the rdyen bit is set. description value the external device is not gating the clock. 0 0 ro celow 9 external fifo full this bit provides information on the xfifo when in the fifo sub-mode of the host bus n mode with the xffen bit set in the epihbncfg register. the epi0s26 signal reflects the status of this bit. description value the external device is not gating the clock. 0 the xfifo is signaling as full (the fifo full signal is high). attempts to write in this case are stalled until the xfifo full signal goes low or the counter times out as specified by the maxwait field. 1 0 ro xffull 8 523 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field external fifo empty this bit provides information on the xfifo when in the fifo sub-mode of the host bus n mode with the xfeen bit set in the epihbncfg register. the epi0s27 signal reflects the status of this bit. description value the external device is not gating the clock. 0 the xfifo is signaling as empty (the fifo empty signal is high). attempts to read in this case are stalled until the xfifo empty signal goes low or the counter times out as specified by the maxwait field. 1 0 ro xfempty 7 initialization sequence description value the sdram interface is not in the wakeup period. 0 the sdram interface is running through the wakeup period (greater than 100 s). if an attempt is made to read or write the sdram during this period, the access is held off until the wakeup period is complete. 1 0 ro initseq 6 write busy description value the external interface is not performing a write. 0 the external interface is performing a write. 1 0 ro wbusy 5 non-blocking read busy description value the external interface is not performing a non-blocking read. 0 the external interface is performing a non-blocking read, or if the non-blocking read is paused due to a write. 1 0 ro nbrbusy 4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 3:1 register active description value if nbrbusy is set, the epirpstd0 register is active. if the nbrbusy bit is clear, then neither epirpstdx register is active. 0 the epirpstd1 register is active. 1 0 ro active 0 july 03, 2014 524 texas instruments-production data external peripheral interface (epi) register 18: epi read fifo count (epirfifocnt), offset 0x06c this register returns the number of values in the nbrfifo (the data in the nbrfifo can be read via the epireadfifo register). a race is possible, but that only means that more values may come in after this register has been read. epi read fifo count (epirfifocnt) base 0x400d.0000 offset 0x06c type ro, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 count reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type - - - - 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:4 fifo count number of filled entries in the nbrfifo. - ro count 3:0 525 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 19: epi read fifo (epireadfifo), offset 0x070 register 20: epi read fifo alias 1 (epireadfifo1), offset 0x074 register 21: epi read fifo alias 2 (epireadfifo2), offset 0x078 register 22: epi read fifo alias 3 (epireadfifo3), offset 0x07c register 23: epi read fifo alias 4 (epireadfifo4), offset 0x080 register 24: epi read fifo alias 5 (epireadfifo5), offset 0x084 register 25: epi read fifo alias 6 (epireadfifo6), offset 0x088 register 26: epi read fifo alias 7 (epireadfifo7), offset 0x08c important: this register is read-sensitive. see the register description for details. this register returns the contents of the nbrfifo or 0 if the nbrfifo is empty. each read returns the data that is at the top of the nbrfifo, and then empties that value from the nbrfifo. the alias registers can be used with the ldmia instruction for more efficient operation (for up to 8 registers). see cortex?-m3/m4 instruction set technical user's manual for more information on the ldmia instruction. epi read fifo (epireadfifo) base 0x400d.0000 offset 0x070 type ro, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 data ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type - - - - - - - - - - - - - - - - reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 data ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type - - - - - - - - - - - - - - - - reset description reset type name bit/field reads data this field contains the data that is at the top of the nbrfifo. after being read, the nbrfifo entry is removed. - ro data 31:0 july 03, 2014 526 texas instruments-production data external peripheral interface (epi) register 27: epi fifo level selects (epififolvl), offset 0x200 this register allows selection of the fifo levels which trigger an interrupt to the interrupt controller or, more efficiently, a dma request to the dma. the nbrfifo select triggers on fullness such that it triggers on match or above (more full). the wfifo triggers on emptiness such that it triggers on match or below (less entries). it should be noted that the fifo triggers are not identical to other such fifos in stellaris peripherals. in particular, empty and full triggers are provided to avoid wait states when using blocking operations. the settings in this register are only meaningful if the dma is active or the interrupt is enabled. additionally, this register allows protection against writes stalling and notification of performing blocking reads which stall for extra time due to preceding writes. the two functions behave in a non-orthogonal way because read and write are not orthogonal. the write error bit configures the system such that an attempted write to an already full wfifo abandons the write and signals an error interrupt to prevent accidental latencies due to stalling writes. the read error bit configures the system such that after a read has been stalled due to any preceding writes in the wfifo, the error interrupt is generated. note that the excess stall is not prevented, but an interrupt is generated after the fact to notify that it has happened. epi fifo level selects (epififolvl) base 0x400d.0000 offset 0x200 type r/w, reset 0x0000.0033 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rserr wferr reserved r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rdfifo reserved wrfifo reserved r/w r/w r/w ro r/w r/w r/w ro ro ro ro ro ro ro ro ro type 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:18 write full error description value the write full error interrupt is disabled. writes are stalled when the wfifo is full until a space becomes available but an error is not generated. note that the cortex-m3 write buffer may hide that stall if no other memory transactions are attempted during that time. 0 this bit enables the write full error interrupt ( wtfull in the epieisc register) to be generated when a write is attempted and the wfifo is full. the write stalls until a wfifo entry becomes available. 1 0 r/w wferr 17 527 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field read stall error description value the read stalled error interrupt is disabled. reads behave as normal and are stalled until any preceding writes have completed and the read has returned a result. 0 this bit enables the read stalled error interrupt ( rstall in the epieisc register) to be generated when a read is attempted and the wfifo is not empty. the read is still stalled during the time the wfifo drains, but this error notifies the application that this excess delay has occurred. 1 note that the configuration of this bit has no effect on non-blocking reads. 0 r/w rserr 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 15:7 write fifo this field configures the trigger point for the wfifo. description value trigger when there are any spaces available in the wfifo. 0x0 reserved 0x1 trigger when there are up to 3 spaces available in the wfifo. 0x2 trigger when there are up to 2 spaces available in the wfifo. 0x3 trigger when there is 1 space available in the wfifo. 0x4 reserved 0x5-0x7 0x3 r/w wrfifo 6:4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 3 read fifo this field configures the trigger point for the nbrfifo. description value reserved 0x0 trigger when there are 1 or more entries in the nbrfifo. 0x1 trigger when there are 2 or more entries in the nbrfifo. 0x2 trigger when there are 4 or more entries in the nbrfifo. 0x3 trigger when there are 6 or more entries in the nbrfifo. 0x4 trigger when there are 7 or more entries in the nbrfifo. 0x5 trigger when there are 8 entries in the nbrfifo. 0x6 reserved 0x7 0x3 r/w rdfifo 2:0 july 03, 2014 528 texas instruments-production data external peripheral interface (epi) register 28: epi write fifo count (epiwfifocnt), offset 0x204 this register contains the number of slots currently available in the wfifo. this register may be used for polled writes to avoid stalling and for blocking reads to avoid excess stalling (due to undrained writes). an example use for writes may be: for (idx = 0; idx < cnt; idx++) { while (epiwfifocnt == 0) ; *ext_ram = *mydata++; } the above code ensures that writes to the address mapped location do not occur unless the wfifo has room. although polling makes the code wait (spinning in the loop), it does not prevent interrupts being serviced due to bus stalling. epi write fifo count (epiwfifocnt) base 0x400d.0000 offset 0x204 type ro, reset 0x0000.0004 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 wtav reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:3 available write transactions the number of write transactions available in the wfifo. when clear, a write is stalled waiting for a slot to become free (from a preceding write completing). 0x4 ro wtav 2:0 529 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 29: epi interrupt mask (epiim), offset 0x210 this register is the interrupt mask set or clear register. for each interrupt source (read, write, and error), a mask value of 1 allows the interrupt source to trigger an interrupt to the interrupt controller; a mask value of 0 prevents the interrupt source from triggering an interrupt. note that interrupt masking has no effect on dma, which operates off the raw source of the read and write interrupts. epi interrupt mask (epiim) base 0x400d.0000 offset 0x210 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 errim rdim wrim reserved r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 31:3 write fifo empty interrupt mask description value wrris in the epiris register is masked and does not cause an interrupt. 0 wrris in the epiris register is not masked and can trigger an interrupt to the interrupt controller. 1 0 r/w wrim 2 read fifo full interrupt mask description value rdris in the epiris register is masked and does not cause an interrupt. 0 rdris in the epiris register is not masked and can trigger an interrupt to the interrupt controller. 1 0 r/w rdim 1 error interrupt mask description value erris in the epiris register is masked and does not cause an interrupt. 0 erris in the epiris register is not masked and can trigger an interrupt to the interrupt controller. 1 0 r/w errim 0 july 03, 2014 530 texas instruments-production data external peripheral interface (epi) register 30: epi raw interrupt status (epiris), offset 0x214 this register is the raw interrupt status register. on a read, it gives the current state of each interrupt source. a write has no effect. note that raw status for read and write is set or cleared based on fifo fullness as controlled by epififolvl . raw status for error is held until the error is cleared by writing to the epieisc register. epi raw interrupt status (epiris) base 0x400d.0000 offset 0x214 type ro, reset 0x0000.0004 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 errris rdris wrris reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 31:3 write raw interrupt status description value the number of available entries in the wfifo is above the range specified by the wrfifo field in the epififolvl register. 0 the number of available entries in the wfifo is within the trigger range specified by the wrfifo field in the epififolvl register. 1 this bit is cleared when the level in the wfifo is above the trigger point programmed by the wrfifo field. 1 ro wrris 2 read raw interrupt status description value the number of valid entries in the nbrfifo is below the trigger range specified by the rdfifo field in the epififolvl register. 0 the number of valid entries in the nbrfifo is in the trigger range specified by the rdfifo field in the epififolvl register. 1 this bit is cleared when the level in the nbrfifo is below the trigger point programmed by the rdfifo field. 0 ro rdris 1 531 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field error raw interrupt status the error interrupt occurs in the following situations: wfifo full. for a full wfifo to generate an error interrupt, the wferr bit in the epififolvl register must be set. read stalled. for a stalled read to generate an error interrupt, the rserr bit in the epififolvl register must be set. timeout. if the maxwait field in the epigpcfg register is configured to a value other than 0, a timeout error occurs when irdy or xfifo not-ready signals hold a transaction for more than the count in the maxwait field. description value an error has not occurred. 0 a wfifo full, a read stalled, or a timeout error has occurred. 1 to determine which error occurred, read the status of the epi error interrupt status and clear (epieisc) register. this bit is cleared by writing a 1 to the bit in the epieisc register that caused the interrupt. 0 ro errris 0 july 03, 2014 532 texas instruments-production data external peripheral interface (epi) register 31: epi masked interrupt status (epimis), offset 0x218 this register is the masked interrupt status register. on read, it gives the current state of each interrupt source (read, write, and error) after being masked via the epiim register. a write has no effect. the values returned are the anding of the epiim and epiris registers. if a bit is set in this register, the interrupt is sent to the interrupt controller. epi masked interrupt status (epimis) base 0x400d.0000 offset 0x218 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 errmis rdmis wrmis reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 31:3 write masked interrupt status description value the number of available entries in the wfifo is above the range specified by the trigger level or the interrupt is masked. 0 the number of available entries in the wfifo is within the range specified by the trigger level (the wrfifo field in the epififolvl register) and the wrim bit in the epiim register is set, triggering an interrupt to the interrupt controller. 1 0 ro wrmis 2 read masked interrupt status description value the number of valid entries in the nbrfifo is below the range specified by the trigger level or the interrupt is masked. 0 the number of valid entries in the nbrfifo is within the range specified by the trigger level (the rdfifo field in the epififolvl register) and the rdim bit in the epiim register is set, triggering an interrupt to the interrupt controller. 1 0 ro rdmis 1 error masked interrupt status description value an error has not occurred or the interrupt is masked. 0 a wfifo full, a read stalled, or a timeout error has occurred and the erim bit in the epiim register is set, triggering an interrupt to the interrupt controller. 1 0 ro errmis 0 533 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 32: epi error and interrupt status and clear (epieisc), offset 0x21c this register is used to clear a pending error interrupt. clearing any defined bit in the epieisc has no effect; setting a bit clears the error source and the raw error returns to 0. when any of these bits are read as set it indicates that the errris bit in the epiris register is set and an epi controller error is sent to the interrupt controller if the erim bit in the epiim register is set. if any of bits [2:0] are written as 1, the register bit being written to, as well as the erris bit in the epiris register and the erim bit in the epiim register are cleared. note that writing to this register and reading back immediately (pipelined by the processor) returns the old register contents. one cycle is needed between write and read. epi error and interrupt status and clear (epieisc) base 0x400d.0000 offset 0x21c type r/w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tout rstall wtfull reserved r/w1c r/w1c r/w1c ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 31:3 write fifo full error description value the wferr bit is not enabled or no writes are stalled. 0 the wferr bit is enabled and a write is stalled due to the wfifo being full. 1 writing a 1 to this bit clears it, as well as as the errris and erim bits. 0 r/w1c wtfull 2 read stalled error description value the rserr bit is not enabled or no pending reads are stalled. 0 the rserr bit is enabled and a pending read is stalled due to writes in the wfifo. 1 writing a 1 to this bit clears it, as well as as the errris and erim bits. 0 r/w1c rstall 1 july 03, 2014 534 texas instruments-production data external peripheral interface (epi) description reset type name bit/field timeout error this bit is the timeout error source. the timeout error occurs when the irdy or xfifo not-ready signals hold a transaction for more than the count in the maxwait field (when not 0). description value no timeout error has occurred. 0 a timeout error has occurred. 1 writing a 1 to this bit clears it, as well as as the errris and erim bits. 0 r/w1c tout 0 535 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 10 general-purpose timers programmable timers can be used to count or time external events that drive the timer input pins. the stellaris ? general-purpose timer module (gptm) contains four gptm blocks. each gptm block provides two 16-bit timers/counters (referred to as timer a and timer b) that can be configured to operate independently as timers or event counters, or concatenated to operate as one 32-bit timer or one 32-bit real-time clock (rtc). timers can also be used to trigger dma transfers. in addition, timers can be used to trigger analog-to-digital conversions (adc). the adc trigger signals from all of the general-purpose timers are ored together before reaching the adc module, so only one timer should be used to trigger adc events. the gpt module is one timing resource available on the stellaris microcontrollers. other timer resources include the system timer (systick) (see 112) and the pwm timer in the pwm module (see pwm timer on page 1115). the general-purpose timer module (gptm) contains four gptm blocks with the following functional options: operating modes: C 16- or 32-bit programmable one-shot timer C 16- or 32-bit programmable periodic timer C 16-bit general-purpose timer with an 8-bit prescaler C 32-bit real-time clock (rtc) when using an external 32.768-khz clock as the input C 16-bit input-edge count- or time-capture modes C 16-bit pwm mode with software-programmable output inversion of the pwm signal count up or down eight capture compare pwm pins (ccp) daisy chaining of timer modules to allow a single timer to initiate multiple timing events adc event trigger user-enabled stalling when the microcontroller asserts cpu halt flag during debug (excluding rtc mode) ability to determine the elapsed time between the assertion of the timer interrupt and entry into the interrupt service routine. efficient transfers using micro direct memory access controller (dma) C dedicated channel for each timer C burst request generated on timer interrupt july 03, 2014 536 texas instruments-production data general-purpose timers 10.1 block diagram in the block diagram, the specific capture compare pwm (ccp) pins available depend on the stellaris device. see table 10-1 on page 537 for the available ccp pins and their timer assignments. figure 10-1. gptm module block diagram table 10-1. available ccp pins odd ccp pin even ccp pin 16-bit up/down counter timer - ccp0 timera timer 0 ccp1 - timerb - ccp2 timera timer 1 ccp3 - timerb - ccp4 timera timer 2 ccp5 - timerb - ccp6 timera timer 3 ccp7 - timerb 10.2 signal description the following table lists the external signals of the gp timer module and describes the function of each. the gp timer signals are alternate functions for some gpio signals and default to be gpio signals at reset. the column in the table below titled "pin mux/pin assignment" lists the possible gpio pin placements for these gp timer signals. the afsel bit in the gpio alternate function select (gpioafsel) register (page 429) should be set to choose the gp timer function. the number in parentheses is the encoding that must be programmed into the pmcn field in the gpio port 537 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller & o r f n ( g j h ' h w h f w 5 7 & ' l y l g h u & o r f n ( g j h ' h w h f w . + ] r u ( y h q & & 3 3 l q 2 g g & & 3 3 l q 7 $ & r p s d u d w r u 7 % & r p s d u d w r u * 3 7 0 7 % 5 * 3 7 0 7 $ 5 7 l p h u $ , q w h u u x s w 7 l p h u % , q w h u u x s w 6 \ v w h p & o r f n [ ' r z q & r x q w h u 0 r g h v [ ) ) ) ) 8 s & r x q w h u 0 r g h v [ ' r z q & r x q w h u 0 r g h v [ ) ) ) ) 8 s & r x q w h u 0 r g h v ( q ( q , q w h u u x s w & r q i l j * 3 7 0 & ) * * 3 7 0 5 , 6 * 3 7 0 , & 5 * 3 7 0 0 , 6 * 3 7 0 , 0 5 * 3 7 0 & 7 / * 3 7 0 7 $ 9 * 3 7 0 7 % 9 7 l p h u $ ) u h h 5 x q q l q j 9 d o x h 7 l p h u % ) u h h 5 x q q l q j 9 d o x h 7 l p h u $ & r q w u r o * 3 7 0 7 $ 3 0 5 * 3 7 0 7 $ , / 5 * 3 7 0 7 $ 0 $ 7 & + 5 * 3 7 0 7 $ 3 5 * 3 7 0 7 $ 0 5 7 l p h u % & r q w u r o * 3 7 0 7 % 3 0 5 * 3 7 0 7 % , / 5 * 3 7 0 7 % 0 $ 7 & + 5 * 3 7 0 7 % 3 5 * 3 7 0 7 % 0 5 control (gpiopctl) register (page 447) to assign the gp timer signal to the specified gpio port pin. for more information on configuring gpios, see general-purpose input/outputs (gpios) on page 405. table 10-2. general-purpose timers signals (100lqfp) description buffer type a pin type pin mux / pin assignment pin number pin name capture/compare/pwm 0. ttl i/o pd3 (4) pc7 (4) pc6 (6) pj2 (9) pj7 (10) pf4 (1) pb0 (1) pb2 (5) pb5 (4) pd4 (1) 13 22 23 39 55 58 66 72 91 97 ccp0 capture/compare/pwm 1. ttl i/o pc5 (1) pc4 (9) pa6 (2) pf6 (1) pj6 (10) pb1 (4) pb6 (1) pe3 (1) pd7 (3) 24 25 34 43 54 67 90 96 100 ccp1 capture/compare/pwm 2. ttl i/o pe4 (6) pd1 (10) pc4 (5) pf5 (1) pj5 (10) pb1 (1) pe1 (4) pb5 (6) pe2 (5) pd5 (1) 6 11 25 46 53 67 75 91 95 98 ccp2 capture/compare/pwm 3. ttl i/o pe4 (1) pc6 (1) pc5 (5) pa7 (7) pg4 (1) pf1 (10) pb2 (4) pe0 (3) pd4 (2) 6 23 24 35 41 61 72 74 97 ccp3 capture/compare/pwm 4. ttl i/o pc7 (1) pc4 (6) pa7 (2) pf7 (1) pj4 (10) pe2 (1) pd5 (2) 22 25 35 42 52 95 98 ccp4 july 03, 2014 538 texas instruments-production data general-purpose timers table 10-2. general-purpose timers signals (100lqfp) (continued) description buffer type a pin type pin mux / pin assignment pin number pin name capture/compare/pwm 5. ttl i/o pe5 (1) pd2 (4) pc4 (1) pg7 (8) pg5 (1) pb6 (6) pb5 (2) 5 12 25 36 40 90 91 ccp5 capture/compare/pwm 6. ttl i/o pd0 (6) pd2 (2) pj3 (10) pe1 (5) ph0 (1) pb5 (3) 10 12 50 75 86 91 ccp6 capture/compare/pwm 7. ttl i/o pd1 (6) pd3 (2) ph1 (1) pb6 (2) pe3 (5) 11 13 85 90 96 ccp7 a. the ttl designation indicates the pin has ttl-compatible voltage levels. table 10-3. general-purpose timers signals (108bga) description buffer type a pin type pin mux / pin assignment pin number pin name capture/compare/pwm 0. ttl i/o pd3 (4) pc7 (4) pc6 (6) pj2 (9) pj7 (10) pf4 (1) pb0 (1) pb2 (5) pb5 (4) pd4 (1) h1 l2 m2 k6 l12 l9 e12 a11 b7 b5 ccp0 capture/compare/pwm 1. ttl i/o pc5 (1) pc4 (9) pa6 (2) pf6 (1) pj6 (10) pb1 (4) pb6 (1) pe3 (1) pd7 (3) m1 l1 l6 m8 l10 d12 a7 b4 a2 ccp1 capture/compare/pwm 2. ttl i/o pe4 (6) pd1 (10) pc4 (5) pf5 (1) pj5 (10) pb1 (1) pe1 (4) pb5 (6) pe2 (5) pd5 (1) b2 g2 l1 l8 k12 d12 a12 b7 a4 c6 ccp2 539 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 10-3. general-purpose timers signals (108bga) (continued) description buffer type a pin type pin mux / pin assignment pin number pin name capture/compare/pwm 3. ttl i/o pe4 (1) pc6 (1) pc5 (5) pa7 (7) pg4 (1) pf1 (10) pb2 (4) pe0 (3) pd4 (2) b2 m2 m1 m6 k3 h12 a11 b11 b5 ccp3 capture/compare/pwm 4. ttl i/o pc7 (1) pc4 (6) pa7 (2) pf7 (1) pj4 (10) pe2 (1) pd5 (2) l2 l1 m6 k4 k11 a4 c6 ccp4 capture/compare/pwm 5. ttl i/o pe5 (1) pd2 (4) pc4 (1) pg7 (8) pg5 (1) pb6 (6) pb5 (2) b3 h2 l1 c10 m7 a7 b7 ccp5 capture/compare/pwm 6. ttl i/o pd0 (6) pd2 (2) pj3 (10) pe1 (5) ph0 (1) pb5 (3) g1 h2 m10 a12 c9 b7 ccp6 capture/compare/pwm 7. ttl i/o pd1 (6) pd3 (2) ph1 (1) pb6 (2) pe3 (5) g2 h1 c8 a7 b4 ccp7 a. the ttl designation indicates the pin has ttl-compatible voltage levels. 10.3 functional description the main components of each gptm block are two free-running up/down counters (referred to as timer a and timer b), two match registers, two prescaler match registers, two shadow registers, and two load/initialization registers and their associated control functions. the exact functionality of each gptm is controlled by software and configured through the register interface. timer a and timer b can be used individually, in which case they have a 16-bit counting range. in addition, timer a and timer b can be concatenated to provide a 32-bit counting range. note that the prescaler can only be used when the timers are used individually. the available modes for each gptm block are shown in table 10-4 on page 541. note that when counting down in one-shot or periodic modes, the prescaler acts as a true prescaler and contains the least-significant bits of the count. when counting up in one-shot or periodic modes, the prescaler acts as a timer extension and holds the most-significant bits of the count. in input edge count mode, the prescaler always acts as a timer extension, regardless of the count direction. july 03, 2014 540 texas instruments-production data general-purpose timers table 10-4. general-purpose timer capabilities prescaler size a counter size count direction timer use mode 8-bit 16-bit up or down individual one-shot - 32-bit up or down concatenated 8-bit 16-bit up or down individual periodic - 32-bit up or down concatenated - 32-bit up concatenated rtc 8-bit 16-bit down individual edge count - 16-bit down individual edge time - 16-bit down individual pwm a. the prescaler is only available when the timers are used individually software configures the gptm using the gptm configuration (gptmcfg) register (see page 553), the gptm timer a mode (gptmtamr) register (see page 554), and the gptm timer b mode (gptmtbmr) register (see page 556). when in one of the concatentated modes, timer a and timer b can only operate in one mode. however, when configured in an individual mode, timer a and timer b can be independently configured in any combination of the individual modes. 10.3.1 gptm reset conditions after reset has been applied to the gptm module, the module is in an inactive state, and all control registers are cleared and in their default states. counters timer a and timer b are initialized to all 1s, along with their corresponding load registers: the gptm timer a interval load (gptmtailr) register (see page 571) and the gptm timer b interval load (gptmtbilr) register (see page 572) and shadow registers: the gptm timer a value (gptmtav) register (see page 581) and the gptm timer b value (gptmtbv) register (see page 582). the prescale counters are initialized to 0x00: the gptm timer a prescale (gptmtapr) register (see page 575) and the gptm timer b prescale (gptmtbpr) register (see page 576). 10.3.2 timer modes this section describes the operation of the various timer modes. when using timer a and timer b in concatenated mode, only the timer a control and status bits must be used; there is no need to use timer b control and status bits. the gptm is placed into individual/split mode by writing a value of 0x4 to the gptm configuration (gptmcfg) register (see page 553). in the following sections, the variable " n " is used in bit field and register names to imply either a timer a function or a timer b function. throughout this section, the timeout event in down-count mode is 0x0 and in up-count mode is the value in the gptm timer n interval load (gptmtnilr) and the optional gptm timer n prescale (gptmtnpr) registers. 10.3.2.1 one-shot/periodic timer mode the selection of one-shot or periodic mode is determined by the value written to the tnmr field of the gptm timer n mode (gptmtnmr) register (see page 554). the timer is configured to count up or down using the tncdir bit in the gptmtnmr register. when software sets the tnen bit in the gptm control (gptmctl) register (see page 558), the timer begins counting up from 0x0 or down from its preloaded value. alternatively, if the tnwot bit is set in the gptmtnmr register, once the tnen bit is set, the timer waits for a trigger to begin counting (see the section called wait-for-trigger mode on page 543). table 10-5 on page 542 shows the values that are loaded into the timer registers when the timer is enabled. 541 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 10-5. counter values when the timer is enabled in periodic or one-shot modes count up mode count down mode register 0x0 gptmtnilr tnr 0x0 gptmtnilr tnv when the timer is counting down and it reaches the timeout event (0x0), the timer reloads its start value from the gptmtnilr and the gptmtnpr registers on the next cycle. when the timer is counting up and it reaches the timeout event (the value in the gptmtnilr and the optional gptmtnpr registers), the timer reloads with 0x0. if configured to be a one-shot timer, the timer stops counting and clears the tnen bit in the gptmctl register. if configured as a periodic timer, the timer starts counting again on the next cycle. in periodic, snap-shot mode ( tnmr field is 0x2 and the tnsnaps bit is set in the gptmtnmr register), the value of the timer at the time-out event is loaded into the gptmtnr register. the free-running counter value is shown in the gptmtnv register. in this manner, software can determine the time elapsed from the interrupt assertion to the isr entry by examining the snapshot values and the current value of the free-running timer. snapshot mode is not available when the timer is configured in one-shot mode. in addition to reloading the count value, the gptm generates interrupts and triggers when it reaches the time-out event. the gptm sets the tntoris bit in the gptm raw interrupt status (gptmris) register (see page 563), and holds it until it is cleared by writing the gptm interrupt clear (gptmicr) register (see page 569). if the time-out interrupt is enabled in the gptm interrupt mask (gptmimr) register (see page 561), the gptm also sets the tntomis bit in the gptm masked interrupt status (gptmmis) register (see page 566). by setting the tnmie bit in the gptmtnmr register, an interrupt condition can also be generated when the timer value equals the value loaded into the gptm timer n match (gptmtnmatchr) and gptm timer n prescale match (gptmtnpmr) registers. this interrupt has the same status, masking, and clearing functions as the time-out interrupt, but uses the match interrupt bits instead (for example, the raw interrupt status is monitored via tnmris bit in the gptm raw interrupt status (gptmris) register). note that the interrupt status bits are not updated by the hardware unless the tnmie bit in the gptmtnmr register is set, which is different than the behavior for the time-out interrupt. the adc trigger is enabled by setting the tnote bit in gptmctl . the dma trigger is enabled by configuring and enabling the appropriate dma channel. see channel configuration on page 349. if software updates the gptmtnilr register while the counter is counting down, the counter loads the new value on the next clock cycle and continues counting from the new value. if software updates the gptmtnilr register while the counter is counting up, the timeout event is changed on the next cycle to the new value. if software updates the gptm timer n value (gptmtnv) register while the counter is counting up or down, the counter loads the new value on the next clock cycle and continues counting from the new value.. if the tnstall bit in the gptmctl register is set, the timer freezes counting while the processor is halted by the debugger. the timer resumes counting when the processor resumes execution. the following table shows a variety of configurations for a 16-bit free-running timer while using the prescaler. all values assume an 80-mhz clock with tc=12.5 ns (clock period). the prescaler can only be used when a 16/32-bit timer is configured in 16-bit mode. table 10-6. 16-bit timer with prescaler configurations units max time # of timer clocks (tc) a prescale (8-bit value) ms 0.8192 1 00000000 ms 1.6384 2 00000001 july 03, 2014 542 texas instruments-production data general-purpose timers table 10-6. 16-bit timer with prescaler configurations (continued) units max time # of timer clocks (tc) a prescale (8-bit value) ms 2.4576 3 00000010 -- -- -- ------------ ms 208.0768 254 11111101 ms 208.896 255 11111110 ms 209.7152 256 11111111 a. tc is the clock period. wait-for-trigger mode the wait-for-trigger mode allows daisy chaining of the timer modules such that once configured, a single timer can initiate mulitple timing events using the timer triggers. wait-for-trigger mode is enabled by setting the tnwot bit in the gptmtnmr register. when the tnwot bit is set, timer n+1 does not begin counting until the timer in the previous position in the daisy chain (timer n) reaches its time-out event. the daisy chain is configured such that gptm1 always follows gptm0, gptm2 follows gptm1, and so on. if timer a is in 32-bit mode (controlled by the gptmcfg bit in the gptmcfg register), it triggers timer a in the next module. if timer a is in 16-bit mode, it triggers timer b in the same module, and timer b triggers timer a in the next module. care must be taken that the tawot bit is never set in gptm0. figure 10-2 on page 543 shows how the gptmcfg bit affects the daisy chain. this function is valid for both one-shot and periodic modes. figure 10-2. timer daisy chain 10.3.2.2 real-time clock timer mode in real-time clock (rtc) mode, the concatenated versions of the timer a and timer b registers are configured as an up-counter. when rtc mode is selected for the first time after reset, the counter is loaded with a value of 0x1. all subsequent load values must be written to the gptm timer a interval load (gptmtailr) register (see page 571). table 10-7 on page 543 shows the values that are loaded into the timer registers when the timer is enabled. table 10-7. counter values when the timer is enabled in rtc mode count up mode count down mode register 0x1 not available tnr 0x1 not available tnv 543 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller * 3 7 l p h u 1 7 l p h u % 7 l p h u $ * 3 7 0 & ) * * 3 7 l p h u 1 7 l p h u % 7 l p h u $ * 3 7 0 & ) * 7 l p h u % $ ' & 7 u l j j h u 7 l p h u $ $ ' & 7 u l j j h u 7 l p h u % $ ' & 7 u l j j h u 7 l p h u $ $ ' & 7 u l j j h u the input clock on a ccp input is required to be 32.768 khz in rtc mode. the clock signal is then divided down to a 1-hz rate and is passed along to the input of the counter. when software writes the taen bit in the gptmctl register, the counter starts counting up from its preloaded value of 0x1. when the current count value matches the preloaded value in the gptmtamatchr register, the gptm asserts the rtcris bit in gptmris and continues counting until either a hardware reset, or it is disabled by software (clearing the taen bit). when the timer value reaches the terminal count, the timer rolls over and continues counting up from 0x0. if the rtc interrupt is enabled in gptmimr , the gptm also sets the rtcmis bit in gptmmis and generates a controller interrupt. the status flags are cleared by writing the rtccint bit in gptmicr . in this mode, the gptmtnr and gptmtnv registers always have the same value. in addition to generating interrupts, a dma trigger can be generated. the dma trigger is enabled by configuring and enabling the appropriate dma channel. see channel configuration on page 349. if the tastall bit in the gptmctl register is set, the timer does not freeze when the processor is halted by the debugger if the rtcen bit is set in gptmctl . 10.3.2.3 input edge-count mode note: for rising-edge detection, the input signal must be high for at least two system clock periods following the rising edge. similarly, for falling-edge detection, the input signal must be low for at least two system clock periods following the falling edge. based on this criteria, the maximum input frequency for edge detection is 1/4 of the system frequency. in edge-count mode, the timer is configured as a 24-bit down-counter including the optional prescaler with the upper count value stored in the gptm timer n prescale (gptmtnpr) register and the lower bits in the gptmtnr register. in this mode, the timer is capable of capturing three types of events: rising edge, falling edge, or both. to place the timer in edge-count mode, the tncmr bit of the gptmtnmr register must be cleared. the type of edge that the timer counts is determined by the tnevent fields of the gptmctl register. during initialization, the gptmtnmatchr and gptmtnpmr registers are configured so that the difference between the value in the gptmtnilr and gptmtnpr registers and the gptmtnmatchr and gptmtnpmr registers equals the number of edge events that must be counted. table 10-8 on page 544 shows the values that are loaded into the timer registers when the timer is enabled. table 10-8. counter values when the timer is enabled in input edge-count mode count up mode count down mode register not available gptmtnilr tnr not available gptmtnilr tnv when software writes the tnen bit in the gptm control (gptmctl) register, the timer is enabled for event capture. each input event on the ccp pin decrements the counter by 1 until the event count matches gptmtnmatchr and gptmtnpmr . when the counts match, the gptm asserts the cnmris bit in the gptm raw interrupt status (gptmris) register, and holds it until it is cleared by writing the gptm interrupt clear (gptmicr) register. if the capture mode match interrupt is enabled in the gptm interrupt mask (gptmimr) register, the gptm also sets the cnmmis bit in the gptm masked interrupt status (gptmmis) register. in this mode, the gptmtnr register holds the count of the input events while the gptmtnv register holds the free-running timer value. in addition to generating interrupts, an adc and/or a dma trigger can be generated. the adc trigger is enabled by setting the tnote bit in gptmctl .the dma trigger is enabled by configuring and enabling the appropriate dma channel. see channel configuration on page 349. july 03, 2014 544 texas instruments-production data general-purpose timers after the match value is reached, the counter is then reloaded using the value in gptmtnilr and gptmtnpr registers, and stopped because the gptm automatically clears the tnen bit in the gptmctl register. once the event count has been reached, all further events are ignored until tnen is re-enabled by software. figure 10-3 on page 545 shows how input edge-count mode works. in this case, the timer start value is set to gptmtnilr =0x000a and the match value is set to gptmtnmatchr =0x0006 so that four edge events are counted. the counter is configured to detect both edges of the input signal. note that the last two edges are not counted because the timer automatically clears the tnen bit after the current count matches the value in the gptmtnmatchr register. figure 10-3. input edge-count mode example 10.3.2.4 input edge-time mode note: for rising-edge detection, the input signal must be high for at least two system clock periods following the rising edge. similarly, for falling edge detection, the input signal must be low for at least two system clock periods following the falling edge. based on this criteria, the maximum input frequency for edge detection is 1/4 of the system frequency. the prescaler is not available in 16-bit input edge-time mode. in edge-time mode, the timer is configured as a 16-bit down-counter. in this mode, the timer is initialized to the value loaded in the gptmtnilr register. the timer is capable of capturing three types of events: rising edge, falling edge, or both. the timer is placed into edge-time mode by setting the tncmr bit in the gptmtnmr register, and the type of event that the timer captures is determined by the tnevent fields of the gptmctl register. table 10-9 on page 545 shows the values that are loaded into the timer registers when the timer is enabled. table 10-9. counter values when the timer is enabled in input event-count mode count up mode count down mode register not available gptmtnilr tnr not available gptmtnilr tnv 545 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller , q s x w 6 l j q d o 7 l p h u v w r s v i o d j v d v v h u w h g 7 l p h u u h o r d g r q q h [ w f \ f o h , j q r u h g , j q r u h g & r x q w [ $ [ [ [ [ when software writes the tnen bit in the gptmctl register, the timer is enabled for event capture. when the selected input event is detected, the current timer counter value is captured in the gptmtnr register and is available to be read by the microcontroller. the gptm then asserts the cneris bit in the gptm raw interrupt status (gptmris) register, and holds it until it is cleared by writing the gptm interrupt clear (gptmicr) register. if the capture mode event interrupt is enabled in the gptm interrupt mask (gptmimr) register, the gptm also sets the cnemis bit in the gptm masked interrupt status (gptmmis) register. in this mode, the gptmtnr register holds the time at which the selected input event occurred while the gptmtnv register holds the free-running timer value. these registers can be read to determine the time that elapsed between the interrupt assertion and the entry into the isr. in addition to generating interrupts, an adc and/or a dma trigger can be generated. the adc trigger is enabled by setting the tnote bit in gptmctl .the dma trigger is enabled by configuring and enabling the appropriate dma channel. see channel configuration on page 349. after an event has been captured, the timer does not stop counting. it continues to count until the tnen bit is cleared. when the timer reaches the timeout value, it is reloaded with the value from the gptmtnilr register. figure 10-4 on page 546 shows how input edge timing mode works. in the diagram, it is assumed that the start value of the timer is the default value of 0xffff, and the timer is configured to capture rising edge events. each time a rising edge event is detected, the current count value is loaded into the gptmtnr register, and is held there until another rising edge is detected (at which point the new count value is loaded into the gptmtnr register). figure 10-4. 16-bit input edge-time mode example 10.3.2.5 pwm mode note: the prescaler is not available in 16-bit pwm mode. the gptm supports a simple pwm generation mode. in pwm mode, the timer is configured as a 16-bit down-counter with a start value (and thus period) defined by the gptmtnilr register. in this mode, the pwm frequency and period are synchronous events and therefore guaranteed to be july 03, 2014 546 texas instruments-production data general-purpose timers * 3 7 0 7 q 5 < , q s x w 6 l j q d o 7 l p h & r x q w * 3 7 0 7 q 5 ; * 3 7 0 7 q 5 = = ; < [ ) ) ) ) glitch free. pwm mode is enabled with the gptmtnmr register by setting the tnams bit to 0x1, the tncmr bit to 0x0, and the tnmr field to 0x1 or 0x2. table 10-10 on page 547 shows the values that are loaded into the timer registers when the timer is enabled. table 10-10. counter values when the timer is enabled in pwm mode count up mode count down mode register not available gptmtnilr gptmtnr not available gptmtnilr gptmtnv when software writes the tnen bit in the gptmctl register, the counter begins counting down until it reaches the 0x0 state. on the next counter cycle in periodic mode, the counter reloads its start value from the gptmtnilr register and continues counting until disabled by software clearing the tnen bit in the gptmctl register. no interrupts or status bits are asserted in pwm mode. in this mode, the gptmtnr and gptmtnv registers always have the same value. the output pwm signal asserts when the counter is at the value of the gptmtnilr register (its start state), and is deasserted when the counter value equals the value in the gptmtnmatchr register. software has the capability of inverting the output pwm signal by setting the tnpwml bit in the gptmctl register. figure 10-5 on page 547 shows how to generate an output pwm with a 1-ms period and a 66% duty cycle assuming a 50-mhz input clock and tnpwml =0 (duty cycle would be 33% for the tnpwml =1 configuration). for this example, the start value is gptmtnilr =0xc350 and the match value is gptmtnmatchr =0x411a. figure 10-5. 16-bit pwm mode example 547 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 2 x w s x w 6 l j q d o 7 l p h & r x q w * 3 7 0 7 q 5 * 3 7 0 q 0 5 * 3 7 0 7 q 5 * 3 7 0 q 0 5 [ & [ $ 7 q 3 : 0 / 7 q 3 : 0 / 7 q ( 1 v h w 10.3.3 dma operation the timers each have a dedicated dma channel and can provide a request signal to the dma controller. the request is a burst type and occurs whenever a timer raw interrupt condition occurs. the arbitration size of the dma transfer should be set to the amount of data that should be transferred whenever a timer event occurs. for example, to transfer 256 items, 8 items at a time every 10 ms, configure a timer to generate a periodic timeout at 10 ms. configure the dma transfer for a total of 256 items, with a burst size of 8 items. each time the timer times out, the dma controller transfers 8 items, until all 256 items have been transferred. no other special steps are needed to enable timers for dma operation. refer to micro direct memory access (dma) on page 344 for more details about programming the dma controller. 10.3.4 accessing concatenated register values the gptm is placed into concatenated mode by writing a 0x0 or a 0x1 to the gptmcfg bit field in the gptm configuration (gptmcfg) register. in both configurations, certain registers are concatenated to form pseudo 32-bit registers. these registers include: gptm timer a interval load (gptmtailr) register [15:0], see page 571 gptm timer b interval load (gptmtbilr) register [15:0], see page 572 gptm timer a (gptmtar) register [15:0], see page 579 gptm timer b (gptmtbr) register [15:0], see page 580 gptm timer a value (gptmtav) register [15:0], see page 581 gptm timer b value (gptmtbv) register [15:0], see page 582 gptm timer a match (gptmtamatchr) register [15:0], see page 573 gptm timer b match (gptmtbmatchr) register [15:0], see page 574 in the 32-bit modes, the gptm translates a 32-bit write access to gptmtailr into a write access to both gptmtailr and gptmtbilr . the resulting word ordering for such a write operation is: gptmtbilr[15:0]:gptmtailr[15:0] likewise, a 32-bit read access to gptmtar returns the value: gptmtbr[15:0]:gptmtar[15:0] a 32-bit read access to gptmtav returns the value: gptmtbv[15:0]:gptmtav[15:0] 10.4 initialization and configuration to use a gptm, the appropriate timern bit must be set in the rcgc1 register (see page 270). if using any ccp pins, the clock to the appropriate gpio module must be enabled via the rcgc1 register (see page 270). to find out which gpio port to enable, refer to table 24-4 on page 1239. configure the pmcn fields in the gpiopctl register to assign the ccp signals to the appropriate pins (see page 447 and table 24-5 on page 1248). july 03, 2014 548 texas instruments-production data general-purpose timers this section shows module initialization and configuration examples for each of the supported timer modes. 10.4.1 one-shot/periodic timer mode the gptm is configured for one-shot and periodic modes by the following sequence: 1. ensure the timer is disabled (the tnen bit in the gptmctl register is cleared) before making any changes. 2. write the gptm configuration register (gptmcfg) with a value of 0x0000.0000. 3. configure the tnmr field in the gptm timer n mode register (gptmtnmr) : a. write a value of 0x1 for one-shot mode. b. write a value of 0x2 for periodic mode. 4. optionally configure the tnsnaps, tnwot, tnmte , and tncdir bits in the gptmtnmr register to select whether to capture the value of the free-running timer at time-out, use an external trigger to start counting, configure an additional trigger or interrupt, and count up or down. 5. load the start value into the gptm timer n interval load register (gptmtnilr) . 6. if interrupts are required, set the appropriate bits in the gptm interrupt mask register (gptmimr) . 7. set the tnen bit in the gptmctl register to enable the timer and start counting. 8. poll the gptmris register or wait for the interrupt to be generated (if enabled). in both cases, the status flags are cleared by writing a 1 to the appropriate bit of the gptm interrupt clear register (gptmicr) . if the tnmie bit in the gptmtnmr register is set, the rtcris bit in the gptmris register is set, and the timer continues counting. in one-shot mode, the timer stops counting after the time-out event. to re-enable the timer, repeat the sequence. a timer configured in periodic mode reloads the timer and continues counting after the time-out event. 10.4.2 real-time clock (rtc) mode to use the rtc mode, the timer must have a 32.768-khz input signal on an even ccp input. to enable the rtc feature, follow these steps: 1. ensure the timer is disabled (the taen bit is cleared) before making any changes. 2. write the gptm configuration register (gptmcfg) with a value of 0x0000.0001. 3. write the match value to the gptm timer n match register (gptmtnmatchr) . 4. set/clear the rtcen bit in the gptm control register (gptmctl) as needed. 5. if interrupts are required, set the rtcim bit in the gptm interrupt mask register (gptmimr) . 6. set the taen bit in the gptmctl register to enable the timer and start counting. 549 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller when the timer count equals the value in the gptmtnmatchr register, the gptm asserts the rtcris bit in the gptmris register and continues counting until timer a is disabled or a hardware reset. the interrupt is cleared by writing the rtccint bit in the gptmicr register. 10.4.3 input edge-count mode a timer is configured to input edge-count mode by the following sequence: 1. ensure the timer is disabled (the tnen bit is cleared) before making any changes. 2. write the gptm configuration (gptmcfg) register with a value of 0x0000.0004. 3. in the gptm timer mode (gptmtnmr) register, write the tncmr field to 0x0 and the tnmr field to 0x3. 4. configure the type of event(s) that the timer captures by writing the tnevent field of the gptm control (gptmctl) register. 5. if a prescaler is to be used, write the prescale value to the gptm timer n prescale register (gptmtnpr) . 6. load the timer start value into the gptm timer n interval load (gptmtnilr) register. 7. load the event count into the gptm timer n match (gptmtnmatchr) register. 8. if interrupts are required, set the cnmim bit in the gptm interrupt mask (gptmimr) register. 9. set the tnen bit in the gptmctl register to enable the timer and begin waiting for edge events. 10. poll the cnmris bit in the gptmris register or wait for the interrupt to be generated (if enabled). in both cases, the status flags are cleared by writing a 1 to the cnmcint bit of the gptm interrupt clear (gptmicr) register. when counting down in input edge-count mode, the timer stops after the programmed number of edge events has been detected. to re-enable the timer, ensure that the tnen bit is cleared and repeat #4 on page 550 through #9 on page 550. 10.4.4 input edge timing mode a timer is configured to input edge timing mode by the following sequence: 1. ensure the timer is disabled (the tnen bit is cleared) before making any changes. 2. write the gptm configuration (gptmcfg) register with a value of 0x0000.0004. 3. in the gptm timer mode (gptmtnmr) register, write the tncmr field to 0x1 and the tnmr field to 0x3. 4. configure the type of event that the timer captures by writing the tnevent field of the gptm control (gptmctl) register. 5. load the timer start value into the gptm timer n interval load (gptmtnilr) register. 6. if interrupts are required, set the cneim bit in the gptm interrupt mask (gptmimr) register. 7. set the tnen bit in the gptm control (gptmctl) register to enable the timer and start counting. july 03, 2014 550 texas instruments-production data general-purpose timers 8. poll the cneris bit in the gptmris register or wait for the interrupt to be generated (if enabled). in both cases, the status flags are cleared by writing a 1 to the cnecint bit of the gptm interrupt clear (gptmicr) register. the time at which the event happened can be obtained by reading the gptm timer n (gptmtnr) register. in input edge timing mode, the timer continues running after an edge event has been detected, but the timer interval can be changed at any time by writing the gptmtnilr register. the change takes effect at the next cycle after the write. 10.4.5 pwm mode a timer is configured to pwm mode using the following sequence: 1. ensure the timer is disabled (the tnen bit is cleared) before making any changes. 2. write the gptm configuration (gptmcfg) register with a value of 0x0000.0004. 3. in the gptm timer mode (gptmtnmr) register, set the tnams bit to 0x1, the tncmr bit to 0x0, and the tnmr field to 0x2. 4. configure the output state of the pwm signal (whether or not it is inverted) in the tn pwml field of the gptm control (gptmctl) register. 5. load the timer start value into the gptm timer n interval load (gptmtnilr) register. 6. load the gptm timer n match (gptmtnmatchr) register with the match value. 7. set the tnen bit in the gptm control (gptmctl) register to enable the timer and begin generation of the output pwm signal. in pwm timing mode, the timer continues running after the pwm signal has been generated. the pwm period can be adjusted at any time by writing the gptmtnilr register, and the change takes effect at the next cycle after the write. 10.5 register map table 10-11 on page 551 lists the gptm registers. the offset listed is a hexadecimal increment to the registers address, relative to that timers base address: timer 0: 0x4003.0000 timer 1: 0x4003.1000 timer 2: 0x4003.2000 timer 3: 0x4003.3000 note that the gp timer module clock must be enabled before the registers can be programmed (see page 270). there must be a delay of 3 system clocks after the timer module clock is enabled before any timer module registers are accessed. table 10-11. timers register map see page description reset type name offset 553 gptm configuration 0x0000.0000 r/w gptmcfg 0x000 554 gptm timer a mode 0x0000.0000 r/w gptmtamr 0x004 551 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 10-11. timers register map (continued) see page description reset type name offset 556 gptm timer b mode 0x0000.0000 r/w gptmtbmr 0x008 558 gptm control 0x0000.0000 r/w gptmctl 0x00c 561 gptm interrupt mask 0x0000.0000 r/w gptmimr 0x018 563 gptm raw interrupt status 0x0000.0000 ro gptmris 0x01c 566 gptm masked interrupt status 0x0000.0000 ro gptmmis 0x020 569 gptm interrupt clear 0x0000.0000 w1c gptmicr 0x024 571 gptm timer a interval load 0xffff.ffff r/w gptmtailr 0x028 572 gptm timer b interval load 0x0000.ffff r/w gptmtbilr 0x02c 573 gptm timer a match 0xffff.ffff r/w gptmtamatchr 0x030 574 gptm timer b match 0x0000.ffff r/w gptmtbmatchr 0x034 575 gptm timer a prescale 0x0000.0000 r/w gptmtapr 0x038 576 gptm timer b prescale 0x0000.0000 r/w gptmtbpr 0x03c 577 gptm timera prescale match 0x0000.0000 r/w gptmtapmr 0x040 578 gptm timerb prescale match 0x0000.0000 r/w gptmtbpmr 0x044 579 gptm timer a 0xffff.ffff ro gptmtar 0x048 580 gptm timer b 0x0000.ffff ro gptmtbr 0x04c 581 gptm timer a value 0xffff.ffff rw gptmtav 0x050 582 gptm timer b value 0x0000.ffff rw gptmtbv 0x054 10.6 register descriptions the remainder of this section lists and describes the gptm registers, in numerical order by address offset. july 03, 2014 552 texas instruments-production data general-purpose timers register 1: gptm configuration (gptmcfg), offset 0x000 this register configures the global operation of the gptm module. the value written to this register determines whether the gptm is in 32- or 16-bit mode. important: bits in this register should only be changed when the taen and tben bits in the gptmctl register are cleared. gptm configuration (gptmcfg) timer 0 base: 0x4003.0000 timer 1 base: 0x4003.1000 timer 2 base: 0x4003.2000 timer 3 base: 0x4003.3000 offset 0x000 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 gptmcfg reserved r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:3 gptm configuration the gptmcfg values are defined as follows: description value 32-bit timer configuration. 0x0 32-bit real-time clock (rtc) counter configuration. 0x1 reserved 0x2-0x3 16-bit timer configuration. the function is controlled by bits 1:0 of gptmtamr and gptmtbmr . 0x4 reserved 0x5-0x7 0x0 r/w gptmcfg 2:0 553 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 2: gptm timer a mode (gptmtamr), offset 0x004 this register configures the gptm based on the configuration selected in the gptmcfg register. when in pwm mode, set the taams bit, clear the tacmr bit, and configure the tamr field to 0x1 or 0x2. this register controls the modes for timer a when it is used individually. when timer a and timer b are concatenated, this register controls the modes for both timer a and timer b, and the contents of gptmtbmr are ignored. important: bits in this register should only be changed when the taen bit in the gptmctl register is cleared. gptm timer a mode (gptmtamr) timer 0 base: 0x4003.0000 timer 1 base: 0x4003.1000 timer 2 base: 0x4003.2000 timer 3 base: 0x4003.3000 offset 0x004 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tamr tacmr taams tacdir tamie tawot tasnaps reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 gptm timer a snap-shot mode description value snap-shot mode is disabled. 0 if timer a is configured in the periodic mode, the actual free-running value of timer a is loaded at the time-out event into the gptm timer a (gptmtar) register. if the timer prescaler is used, the prescaler snapshot is loaded into the gptm timer a (gptmtapr). 1 0 r/w tasnaps 7 gptm timer a wait-on-trigger description value timer a begins counting as soon as it is enabled. 0 if timer a is enabled ( taen is set in the gptmctl register), timer a does not begin counting until it receives a trigger from the timer in the previous position in the daisy chain, see figure 10-2 on page 543. this function is valid for both one-shot and periodic modes. 1 this bit must be clear for gp timer module 0, timer a. 0 r/w tawot 6 july 03, 2014 554 texas instruments-production data general-purpose timers description reset type name bit/field gptm timer a match interrupt enable description value the match interrupt is disabled. 0 an interrupt is generated when the match value in the gptmtamatchr register is reached in the one-shot and periodic modes. 1 0 r/w tamie 5 gptm timer a count direction description value the timer counts down. 0 when in one-shot or periodic mode, the timer counts up. when counting up, the timer starts from a value of 0x0. 1 when in pwm or rtc mode, the status of this bit is ignored. pwm mode always counts down and rtc mode always counts up. 0 r/w tacdir 4 gptm timer a alternate mode select the taams values are defined as follows: description value capture mode is enabled. 0 pwm mode is enabled. 1 note: to enable pwm mode, you must also clear the tacmr bit and configure the tamr field to 0x1 or 0x2. 0 r/w taams 3 gptm timer a capture mode the tacmr values are defined as follows: description value edge-count mode 0 edge-time mode 1 0 r/w tacmr 2 gptm timer a mode the tamr values are defined as follows: description value reserved 0x0 one-shot timer mode 0x1 periodic timer mode 0x2 capture mode 0x3 the timer mode is based on the timer configuration defined by bits 2:0 in the gptmcfg register. 0x0 r/w tamr 1:0 555 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 3: gptm timer b mode (gptmtbmr), offset 0x008 this register configures the gptm based on the configuration selected in the gptmcfg register. when in pwm mode, set the tbams bit, clear the tbcmr bit, and configure the tbmr field to 0x1 or 0x2. this register controls the modes for timer b when it is used individually. when timer a and timer b are concatenated, this register is ignored and gptmtbmr controls the modes for both timer a and timer b. important: bits in this register should only be changed when the tben bit in the gptmctl register is cleared. gptm timer b mode (gptmtbmr) timer 0 base: 0x4003.0000 timer 1 base: 0x4003.1000 timer 2 base: 0x4003.2000 timer 3 base: 0x4003.3000 offset 0x008 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tbmr tbcmr tbams tbcdir tbmie tbwot tbsnaps reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 gptm timer b snap-shot mode description value snap-shot mode is disabled. 0 if timer b is configured in the periodic mode, the actual free-running value of timer b is loaded at the time-out event into the gptm timer b (gptmtbr) register. if the timer prescaler is used, the prescaler snapshot is loaded into the gptm timer b (gptmtbpr). 1 0 r/w tbsnaps 7 gptm timer b wait-on-trigger description value timer b begins counting as soon as it is enabled. 0 if timer b is enabled ( tben is set in the gptmctl register), timer b does not begin counting until it receives an it receives a trigger from the timer in the previous position in the daisy chain, see figure 10-2 on page 543. this function is valid for both one-shot and periodic modes. 1 0 r/w tbwot 6 july 03, 2014 556 texas instruments-production data general-purpose timers description reset type name bit/field gptm timer b match interrupt enable description value the match interrupt is disabled. 0 an interrupt is generated when the match value in the gptmtbmatchr register is reached in the one-shot and periodic modes. 1 0 r/w tbmie 5 gptm timer b count direction description value the timer counts down. 0 when in one-shot or periodic mode, the timer counts up. when counting up, the timer starts from a value of 0x0. 1 when in pwm or rtc mode, the status of this bit is ignored. pwm mode always counts down and rtc mode always counts up. 0 r/w tbcdir 4 gptm timer b alternate mode select the tbams values are defined as follows: description value capture mode is enabled. 0 pwm mode is enabled. 1 note: to enable pwm mode, you must also clear the tbcmr bit and configure the tbmr field to 0x1 or 0x2. 0 r/w tbams 3 gptm timer b capture mode the tbcmr values are defined as follows: description value edge-count mode 0 edge-time mode 1 0 r/w tbcmr 2 gptm timer b mode the tbmr values are defined as follows: description value reserved 0x0 one-shot timer mode 0x1 periodic timer mode 0x2 capture mode 0x3 the timer mode is based on the timer configuration defined by bits 2:0 in the gptmcfg register. 0x0 r/w tbmr 1:0 557 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 4: gptm control (gptmctl), offset 0x00c this register is used alongside the gptmcfg and gmtmtnmr registers to fine-tune the timer configuration, and to enable other features such as timer stall and the output trigger. the output trigger can be used to initiate transfers on the adc module. important: bits in this register should only be changed when the tnen bit for the respective timer is cleared. gptm control (gptmctl) timer 0 base: 0x4003.0000 timer 1 base: 0x4003.1000 timer 2 base: 0x4003.2000 timer 3 base: 0x4003.3000 offset 0x00c type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 taen tastall taevent rtcen taote tapwml reserved tben tbstall tbevent reserved tbote tbpwml reserved r/w r/w r/w r/w r/w r/w r/w ro r/w r/w r/w r/w ro r/w r/w ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0 ro reserved 31:15 gptm timer b pwm output level the tbpwml values are defined as follows: description value output is unaffected. 0 output is inverted. 1 0 r/w tbpwml 14 gptm timer b output trigger enable the tbote values are defined as follows: description value the output timer b adc trigger is disabled. 0 the output timer b adc trigger is enabled. 1 in addition, the adc must be enabled and the timer selected as a trigger source with the emn bit in the adcemux register (see page 641). 0 r/w tbote 13 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 12 july 03, 2014 558 texas instruments-production data general-purpose timers description reset type name bit/field gptm timer b event mode the tbevent values are defined as follows: description value positive edge 0x0 negative edge 0x1 reserved 0x2 both edges 0x3 0x0 r/w tbevent 11:10 gptm timer b stall enable the tbstall values are defined as follows: description value timer b continues counting while the processor is halted by the debugger. 0 timer b freezes counting while the processor is halted by the debugger. 1 if the processor is executing normally, the tbstall bit is ignored. 0 r/w tbstall 9 gptm timer b enable the tben values are defined as follows: description value timer b is disabled. 0 timer b is enabled and begins counting or the capture logic is enabled based on the gptmcfg register. 1 0 r/w tben 8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7 gptm timer a pwm output level the tapwml values are defined as follows: description value output is unaffected. 0 output is inverted. 1 0 r/w tapwml 6 gptm timer a output trigger enable the taote values are defined as follows: description value the output timer a adc trigger is disabled. 0 the output timer a adc trigger is enabled. 1 in addition, the adc must be enabled and the timer selected as a trigger source with the emn bit in the adcemux register (see page 641). 0 r/w taote 5 559 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field gptm rtc stall enable the rtcen values are defined as follows: description value rtc counting freezes while the processor is halted by the debugger. 0 rtc counting continues while the processor is halted by the debugger. 1 if the rtcen bit is set, it prevents the timer from stalling in all operating modes, even if tnstall is set. 0 r/w rtcen 4 gptm timer a event mode the taevent values are defined as follows: description value positive edge 0x0 negative edge 0x1 reserved 0x2 both edges 0x3 0x0 r/w taevent 3:2 gptm timer a stall enable the tastall values are defined as follows: description value timer a continues counting while the processor is halted by the debugger. 0 timer a freezes counting while the processor is halted by the debugger. 1 if the processor is executing normally, the tastall bit is ignored. 0 r/w tastall 1 gptm timer a enable the taen values are defined as follows: description value timer a is disabled. 0 timer a is enabled and begins counting or the capture logic is enabled based on the gptmcfg register. 1 0 r/w taen 0 july 03, 2014 560 texas instruments-production data general-purpose timers register 5: gptm interrupt mask (gptmimr), offset 0x018 this register allows software to enable/disable gptm controller-level interrupts. setting a bit enables the corresponding interrupt, while clearing a bit disables it. gptm interrupt mask (gptmimr) timer 0 base: 0x4003.0000 timer 1 base: 0x4003.1000 timer 2 base: 0x4003.2000 timer 3 base: 0x4003.3000 offset 0x018 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tatoim camim caeim rtcim tamim reserved tbtoim cbmim cbeim tbmim reserved r/w r/w r/w r/w r/w ro ro ro r/w r/w r/w r/w ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0 ro reserved 31:12 gptm timer b match interrupt mask the tbmim values are defined as follows: description value interrupt is disabled. 0 interrupt is enabled. 1 0 r/w tbmim 11 gptm timer b capture mode event interrupt mask the cbeim values are defined as follows: description value interrupt is disabled. 0 interrupt is enabled. 1 0 r/w cbeim 10 gptm timer b capture mode match interrupt mask the cbmim values are defined as follows: description value interrupt is disabled. 0 interrupt is enabled. 1 0 r/w cbmim 9 561 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field gptm timer b time-out interrupt mask the tbtoim values are defined as follows: description value interrupt is disabled. 0 interrupt is enabled. 1 0 r/w tbtoim 8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7:5 gptm timer a match interrupt mask the tamim values are defined as follows: description value interrupt is disabled. 0 interrupt is enabled. 1 0 r/w tamim 4 gptm rtc interrupt mask the rtcim values are defined as follows: description value interrupt is disabled. 0 interrupt is enabled. 1 0 r/w rtcim 3 gptm timer a capture mode event interrupt mask the caeim values are defined as follows: description value interrupt is disabled. 0 interrupt is enabled. 1 0 r/w caeim 2 gptm timer a capture mode match interrupt mask the camim values are defined as follows: description value interrupt is disabled. 0 interrupt is enabled. 1 0 r/w camim 1 gptm timer a time-out interrupt mask the tatoim values are defined as follows: description value interrupt is disabled. 0 interrupt is enabled. 1 0 r/w tatoim 0 july 03, 2014 562 texas instruments-production data general-purpose timers register 6: gptm raw interrupt status (gptmris), offset 0x01c this register shows the state of the gptm's internal interrupt signal. these bits are set whether or not the interrupt is masked in the gptmimr register. each bit can be cleared by writing a 1 to its corresponding bit in gptmicr . gptm raw interrupt status (gptmris) timer 0 base: 0x4003.0000 timer 1 base: 0x4003.1000 timer 2 base: 0x4003.2000 timer 3 base: 0x4003.3000 offset 0x01c type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tatoris camris caeris rtcris tamris reserved tbtoris cbmris cberis tbmris reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0 ro reserved 31:12 gptm timer b match raw interrupt description value the tbmie bit is set in the gptmtbmr register, and the match values in the gptmtbmatchr and (optionally) gptmtbpmr registers have been reached when configured in one-shot or periodic mode. 1 the match value has not been reached. 0 this bit is cleared by writing a 1 to the tbmcint bit in the gptmicr register. 0 ro tbmris 11 gptm timer b capture mode event raw interrupt description value a capture mode event has occurred for timer b. this interrupt asserts when the subtimer is configured in input edge-time mode. 1 the capture mode event for timer b has not occurred. 0 this bit is cleared by writing a 1 to the cbecint bit in the gptmicr register. 0 ro cberis 10 563 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field gptm timer b capture mode match raw interrupt description value the capture mode match has occurred for timer b. this interrupt asserts when the values in the gptmtbr and gptmtbpr match the values in the gptmtbmatchr and gptmtbpmr when configured in input edge-time mode. 1 the capture mode match for timer b has not occurred. 0 this bit is cleared by writing a 1 to the cbmcint bit in the gptmicr register. 0 ro cbmris 9 gptm timer b time-out raw interrupt description value timer b has timed out. this interrupt is asserted when a one-shot or periodic mode timer reaches it's count limit (0 or the value loaded into gptmtbilr , depending on the count direction). 1 timer b has not timed out. 0 this bit is cleared by writing a 1 to the tbtocint bit in the gptmicr register. 0 ro tbtoris 8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7:5 gptm timer a match raw interrupt description value the tamie bit is set in the gptmtamr register, and the match value in the gptmtamatchr and (optionally) gptmtapmr registers have been reached when configured in one-shot or periodic mode. 1 the match value has not been reached. 0 this bit is cleared by writing a 1 to the tamcint bit in the gptmicr register. 0 ro tamris 4 gptm rtc raw interrupt description value the rtc event has occurred. 1 the rtc event has not occurred. 0 this bit is cleared by writing a 1 to the rtccint bit in the gptmicr register. 0 ro rtcris 3 july 03, 2014 564 texas instruments-production data general-purpose timers description reset type name bit/field gptm timer a capture mode event raw interrupt description value a capture mode event has occurred for timer a. this interrupt asserts when the subtimer is configured in input edge-time mode. 1 the capture mode event for timer a has not occurred. 0 this bit is cleared by writing a 1 to the caecint bit in the gptmicr register. 0 ro caeris 2 gptm timer a capture mode match raw interrupt description value a capture mode match has occurred for timer a. this interrupt asserts when the values in the gptmtar and gptmtapr match the values in the gptmtamatchr and gptmtapmr when configured in input edge-time mode. 1 the capture mode match for timer a has not occurred. 0 this bit is cleared by writing a 1 to the camcint bit in the gptmicr register. 0 ro camris 1 gptm timer a time-out raw interrupt description value timer a has timed out. this interrupt is asserted when a one-shot or periodic mode timer reaches it's count limit (0 or the value loaded into gptmtailr , depending on the count direction). 1 timer a has not timed out. 0 this bit is cleared by writing a 1 to the tatocint bit in the gptmicr register. 0 ro tatoris 0 565 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 7: gptm masked interrupt status (gptmmis), offset 0x020 this register show the state of the gptm's controller-level interrupt. if an interrupt is unmasked in gptmimr , and there is an event that causes the interrupt to be asserted, the corresponding bit is set in this register. all bits are cleared by writing a 1 to the corresponding bit in gptmicr . gptm masked interrupt status (gptmmis) timer 0 base: 0x4003.0000 timer 1 base: 0x4003.1000 timer 2 base: 0x4003.2000 timer 3 base: 0x4003.3000 offset 0x020 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tatomis cammis caemis rtcmis tammis reserved tbtomis cbmmis cbemis tbmmis reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0 ro reserved 31:12 gptm timer b match masked interrupt description value an unmasked timer b mode match interrupt has occurred. 1 a timer b mode match interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the tbmcint bit in the gptmicr register. 0 ro tbmmis 11 gptm timer b capture mode event masked interrupt description value an unmasked capture b event interrupt has occurred. 1 a capture b event interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the cbecint bit in the gptmicr register. 0 ro cbemis 10 july 03, 2014 566 texas instruments-production data general-purpose timers description reset type name bit/field gptm timer b capture mode match masked interrupt description value an unmasked capture b match interrupt has occurred. 1 a capture b mode match interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the cbmcint bit in the gptmicr register. 0 ro cbmmis 9 gptm timer b time-out masked interrupt description value an unmasked timer b time-out interrupt has occurred. 1 a timer b time-out interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the tbtocint bit in the gptmicr register. 0 ro tbtomis 8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7:5 gptm timer a match masked interrupt description value an unmasked timer a mode match interrupt has occurred. 1 a timer a mode match interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the tamcint bit in the gptmicr register. 0 ro tammis 4 gptm rtc masked interrupt description value an unmasked rtc event interrupt has occurred. 1 an rtc event interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the rtccint bit in the gptmicr register. 0 ro rtcmis 3 gptm timer a capture mode event masked interrupt description value an unmasked capture a event interrupt has occurred. 1 a capture a event interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the caecint bit in the gptmicr register. 0 ro caemis 2 567 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field gptm timer a capture mode match masked interrupt description value an unmasked capture a match interrupt has occurred. 1 a capture a mode match interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the camcint bit in the gptmicr register. 0 ro cammis 1 gptm timer a time-out masked interrupt description value an unmasked timer a time-out interrupt has occurred. 1 a timer a time-out interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the tatocint bit in the gptmicr register. 0 ro tatomis 0 july 03, 2014 568 texas instruments-production data general-purpose timers register 8: gptm interrupt clear (gptmicr), offset 0x024 this register is used to clear the status bits in the gptmris and gptmmis registers. writing a 1 to a bit clears the corresponding bit in the gptmris and gptmmis registers. gptm interrupt clear (gptmicr) timer 0 base: 0x4003.0000 timer 1 base: 0x4003.1000 timer 2 base: 0x4003.2000 timer 3 base: 0x4003.3000 offset 0x024 type w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tatocint camcint caecint rtccint tamcint reserved tbtocint cbmcint cbecint tbmcint reserved w1c w1c w1c w1c w1c ro ro ro w1c w1c w1c w1c ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0 ro reserved 31:12 gptm timer b match interrupt clear writing a 1 to this bit clears the tbmris bit in the gptmris register and the tbmmis bit in the gptmmis register. 0 w1c tbmcint 11 gptm timer b capture mode event interrupt clear writing a 1 to this bit clears the cberis bit in the gptmris register and the cbemis bit in the gptmmis register. 0 w1c cbecint 10 gptm timer b capture mode match interrupt clear writing a 1 to this bit clears the cbmris bit in the gptmris register and the cbmmis bit in the gptmmis register. 0 w1c cbmcint 9 gptm timer b time-out interrupt clear writing a 1 to this bit clears the tbtoris bit in the gptmris register and the tbtomis bit in the gptmmis register. 0 w1c tbtocint 8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7:5 gptm timer a match interrupt clear writing a 1 to this bit clears the tamris bit in the gptmris register and the tammis bit in the gptmmis register. 0 w1c tamcint 4 gptm rtc interrupt clear writing a 1 to this bit clears the rtcris bit in the gptmris register and the rtcmis bit in the gptmmis register. 0 w1c rtccint 3 gptm timer a capture mode event interrupt clear writing a 1 to this bit clears the caeris bit in the gptmris register and the caemis bit in the gptmmis register. 0 w1c caecint 2 569 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field gptm timer a capture mode match interrupt clear writing a 1 to this bit clears the camris bit in the gptmris register and the cammis bit in the gptmmis register. 0 w1c camcint 1 gptm timer a time-out raw interrupt writing a 1 to this bit clears the tatoris bit in the gptmris register and the tatomis bit in the gptmmis register. 0 w1c tatocint 0 july 03, 2014 570 texas instruments-production data general-purpose timers register 9: gptm timer a interval load (gptmtailr), offset 0x028 when the timer is counting down, this register is used to load the starting count value into the timer. when the timer is counting up, this register sets the upper bound for the timeout event. when a gptm is configured to one of the 32-bit modes, gptmtailr appears as a 32-bit register (the upper 16-bits correspond to the contents of the gptm timer b interval load (gptmtbilr) register). in a 16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state of gptmtbilr . gptm timer a interval load (gptmtailr) timer 0 base: 0x4003.0000 timer 1 base: 0x4003.1000 timer 2 base: 0x4003.2000 timer 3 base: 0x4003.3000 offset 0x028 type r/w, reset 0xffff.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 tailr r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tailr r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field gptm timer a interval load register writing this field loads the counter for timer a. a read returns the current value of gptmtailr . 0xffff.ffff r/w tailr 31:0 571 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 10: gptm timer b interval load (gptmtbilr), offset 0x02c when the timer is counting down, this register is used to load the starting count value into the timer. when the timer is counting up, this register sets the upper bound for the timeout event. when a gptm is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of the gptmtailr register. reads from this register return the current value of timer b and writes are ignored. in a 16-bit mode, bits 15:0 are used for the load value. bits 31:16 are reserved in both cases. gptm timer b interval load (gptmtbilr) timer 0 base: 0x4003.0000 timer 1 base: 0x4003.1000 timer 2 base: 0x4003.2000 timer 3 base: 0x4003.3000 offset 0x02c type r/w, reset 0x0000.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 tbilr r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tbilr r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field gptm timer b interval load register writing this field loads the counter for timer b. a read returns the current value of gptmtbilr . when a gptm is in 32-bit mode, writes are ignored, and reads return the current value of gptmtbilr . 0x0000.ffff r/w tbilr 31:0 july 03, 2014 572 texas instruments-production data general-purpose timers register 11: gptm timer a match (gptmtamatchr), offset 0x030 this register is loaded with a match value. interrupts can be generated when the timer value is equal to the value in this register in one-shot or periodic mode. in edge-count mode, this register along with gptmtailr , determines how many edge events are counted. the total number of edge events counted is equal to the value in gptmtailr minus this value. in pwm mode, this value along with gptmtailr , determines the duty cycle of the output pwm signal. when a gptm is configured to one of the 32-bit modes, gptmtamatchr appears as a 32-bit register (the upper 16-bits correspond to the contents of the gptm timer b match (gptmtbmatchr) register). in a 16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state of gptmtbmatchr . gptm timer a match (gptmtamatchr) timer 0 base: 0x4003.0000 timer 1 base: 0x4003.1000 timer 2 base: 0x4003.2000 timer 3 base: 0x4003.3000 offset 0x030 type r/w, reset 0xffff.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 tamr r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tamr r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field gptm timer a match register this value is compared to the gptmtar register to determine match events. 0xffff.ffff r/w tamr 31:0 573 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 12: gptm timer b match (gptmtbmatchr), offset 0x034 this register is loaded with a match value. interrupts can be generated when the timer value is equal to the value in this register in one-shot or periodic mode. in edge-count mode, this register along with gptmtbilr , determines how many edge events are counted. the total number of edge events counted is equal to the value in gptmtbilr minus this value. in pwm mode, this value along with gptmtbilr , determines the duty cycle of the output pwm signal. when a gptm is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of the gptmtamatchr register. reads from this register return the current match value of timer b and writes are ignored. in a 16-bit mode, bits 15:0 are used for the match value. bits 31:16 are reserved in both cases. gptm timer b match (gptmtbmatchr) timer 0 base: 0x4003.0000 timer 1 base: 0x4003.1000 timer 2 base: 0x4003.2000 timer 3 base: 0x4003.3000 offset 0x034 type r/w, reset 0x0000.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 tbmr r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tbmr r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field gptm timer b match register this value is compared to the gptmtbr register to determine match events. 0x0000.ffff r/w tbmr 31:0 july 03, 2014 574 texas instruments-production data general-purpose timers register 13: gptm timer a prescale (gptmtapr), offset 0x038 this register allows software to extend the range of the 16-bit timers in periodic and one-shot modes. in edge-count mode, this register is the msb of the 24-bit count value. gptm timer a prescale (gptmtapr) timer 0 base: 0x4003.0000 timer 1 base: 0x4003.1000 timer 2 base: 0x4003.2000 timer 3 base: 0x4003.3000 offset 0x038 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tapsr reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:8 gptm timer a prescale the register loads this value on a write. a read returns the current value of the register. refer to table 10-6 on page 542 for more details and an example. 0x00 r/w tapsr 7:0 575 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 14: gptm timer b prescale (gptmtbpr), offset 0x03c this register allows software to extend the range of the 16-bit timers in periodic and one-shot modes. in edge-count mode, this register is the msb of the 24-bit count value. gptm timer b prescale (gptmtbpr) timer 0 base: 0x4003.0000 timer 1 base: 0x4003.1000 timer 2 base: 0x4003.2000 timer 3 base: 0x4003.3000 offset 0x03c type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tbpsr reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:8 gptm timer b prescale the register loads this value on a write. a read returns the current value of this register. refer to table 10-6 on page 542 for more details and an example. 0x00 r/w tbpsr 7:0 july 03, 2014 576 texas instruments-production data general-purpose timers register 15: gptm timera prescale match (gptmtapmr), offset 0x040 this register effectively extends the range of gptmtamatchr to 24 bits when operating in 16-bit one-shot or periodic mode. gptm timera prescale match (gptmtapmr) timer 0 base: 0x4003.0000 timer 1 base: 0x4003.1000 timer 2 base: 0x4003.2000 timer 3 base: 0x4003.3000 offset 0x040 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tapsmr reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:8 gptm timera prescale match this value is used alongside gptmtamatchr to detect timer match events while using a prescaler. 0x00 r/w tapsmr 7:0 577 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 16: gptm timerb prescale match (gptmtbpmr), offset 0x044 this register effectively extends the range of gptmtbmatchr to 24 bits when operating in 16-bit one-shot or periodic mode. gptm timerb prescale match (gptmtbpmr) timer 0 base: 0x4003.0000 timer 1 base: 0x4003.1000 timer 2 base: 0x4003.2000 timer 3 base: 0x4003.3000 offset 0x044 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tbpsmr reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:8 gptm timerb prescale match this value is used alongside gptmtbmatchr to detect timer match events while using a prescaler. 0x00 r/w tbpsmr 7:0 july 03, 2014 578 texas instruments-production data general-purpose timers register 17: gptm timer a (gptmtar), offset 0x048 this register shows the current value of the timer a counter in all cases except for input edge count and time modes. in the input edge count mode, this register contains the number of edges that have occurred. in the input edge time mode, this register contains the time at which the last edge event took place. also in input edge-count mode, bits 23:16 contain the upper 8 bits of the count. when a gptm is configured to one of the 32-bit modes, gptmtar appears as a 32-bit register (the upper 16-bits correspond to the contents of the gptm timer b (gptmtbr) register). in the16-bit input edge count, input edge time, and pwm modes, bits 15:0 contain the value of the counter and bits 23:16 contain the value of the prescaler, which is the upper 8 bits of the count. bits 31:24 always read as 0. to read the value of the prescaler in 16-bit one-shot and periodic modes, read bits [23:16] in the gptmtav register. gptm timer a (gptmtar) timer 0 base: 0x4003.0000 timer 1 base: 0x4003.1000 timer 2 base: 0x4003.2000 timer 3 base: 0x4003.3000 offset 0x048 type ro, reset 0xffff.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 tar ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tar ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field gptm timer a register a read returns the current value of the gptm timer a count register , in all cases except for input edge count and time modes. in the input edge count mode, this register contains the number of edges that have occurred. in the input edge time mode, this register contains the time at which the last edge event took place. 0xffff.ffff ro tar 31:0 579 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 18: gptm timer b (gptmtbr), offset 0x04c this register shows the current value of the timer b counter in all cases except for input edge count and time modes. in the input edge count mode, this register contains the number of edges that have occurred. in the input edge time mode, this register contains the time at which the last edge event took place. also in input edge-count mode, bits 23:16 contain the upper 8 bits of the count. when a gptm is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of the gptmtar register. reads from this register return the current value of timer b. in a 16-bit mode, bits 15:0 contain the value of the counter and bits 23:16 contain the value of the prescaler in input edge count, input edge time, and pwm modes, which is the upper 8 bits of the count. bits 31:24 always read as 0. to read the value of the prescaler in 16-bit one-shot and periodic modes, read bits [23:16] in the gptmtbv register. gptm timer b (gptmtbr) timer 0 base: 0x4003.0000 timer 1 base: 0x4003.1000 timer 2 base: 0x4003.2000 timer 3 base: 0x4003.3000 offset 0x04c type ro, reset 0x0000.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 tbr ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tbr ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field gptm timer b register a read returns the current value of the gptm timer b count register , in all cases except for input edge count and time modes. in the input edge count mode, this register contains the number of edges that have occurred. in the input edge time mode, this register contains the time at which the last edge event took place. 0x0000.ffff ro tbr 31:0 july 03, 2014 580 texas instruments-production data general-purpose timers register 19: gptm timer a value (gptmtav), offset 0x050 when read, this register shows the current, free-running value of timer a in all modes. software can use this value to determine the time elapsed between an interrupt and the isr entry when using the snapshot feature with the periodic operating mode. when written, the value written into this register is loaded into the gptmtar register on the next clock cycle. in input edge-count mode, bits 23:16 contain the upper 8 bits of the count. when a gptm is configured to one of the 32-bit modes, gptmtav appears as a 32-bit register (the upper 16-bits correspond to the contents of the gptm timer b value (gptmtbv) register). in a 16-bit mode, bits 15:0 contain the value of the counter and bits 23:16 contain the current, free-running value of the prescaler, which is the upper 8 bits of the count in input edge count, input edge time, pwm and one-shot or periodic up count modes. in one-shot or periodic down count modes, the prescaler stored in 23:16 is a true prescaler, meaning bits 23:16 count down before decrementing the value in bits 15:0. the prescaler in bits 31:24 always reads as 0. gptm timer a value (gptmtav) timer 0 base: 0x4003.0000 timer 1 base: 0x4003.1000 timer 2 base: 0x4003.2000 timer 3 base: 0x4003.3000 offset 0x050 type rw, reset 0xffff.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 tav rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tav rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field gptm timer a value a read returns the current, free-running value of timer a in all modes. when written, the value written into this register is loaded into the gptmtar register on the next clock cycle. note: in 16-bit mode, only the lower 16-bits of the gptmtav register can be written with a new value. writes to the prescaler bits have no effect. 0xffff.ffff rw tav 31:0 581 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 20: gptm timer b value (gptmtbv), offset 0x054 when read, this register shows the current, free-running value of timer b in all modes. software can use this value to determine the time elapsed between an interrupt and the isr entry. when written, the value written into this register is loaded into the gptmtbr register on the next clock cycle. in input edge-count mode, bits 23:16 contain the upper 8 bits of the count. when a gptm is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of the gptmtav register. reads from this register return the current free-running value of timer b. in a 16-bit mode, bits 15:0 contain the value of the counter and bits 23:16 contain the current, free-running value of the prescaler, which is the upper 8 bits of the count in input edge count, input edge time, pwm and one-shot or periodic up count modes. in one-shot or periodic down count modes, the prescaler stored in 23:16 is a true prescaler, meaning bits 23:16 count down before decrementing the value in bits 15:0. the prescaler in bits 31:24 always reads as 0. gptm timer b value (gptmtbv) timer 0 base: 0x4003.0000 timer 1 base: 0x4003.1000 timer 2 base: 0x4003.2000 timer 3 base: 0x4003.3000 offset 0x054 type rw, reset 0x0000.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 tbv rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tbv rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field gptm timer b value a read returns the current, free-running value of timer a in all modes. when written, the value written into this register is loaded into the gptmtar register on the next clock cycle. note: in 16-bit mode, only the lower 16-bits of the gptmtbv register can be written with a new value. writes to the prescaler bits have no effect. 0x0000.ffff rw tbv 31:0 july 03, 2014 582 texas instruments-production data general-purpose timers 11 watchdog timers a watchdog timer can generate an interrupt or a reset when a time-out value is reached. the watchdog timer is used to regain control when a system has failed due to a software error or due to the failure of an external device to respond in the expected way. the lm3s9gn5 microcontroller has two watchdog timer modules, one module is clocked by the system clock (watchdog timer 0) and the other is clocked by the piosc (watchdog timer 1). the two modules are identical except that wdt1 is in a different clock domain, and therefore requires synchronizers. as a result, wdt1 has a bit defined in the watchdog timer control (wdtctl) register to indicate when a write to a wdt1 register is complete. software can use this bit to ensure that the previous access has completed before starting the next access. the stellaris ? lm3s9gn5 controller has two watchdog timer modules with the following features: 32-bit down counter with a programmable load register separate watchdog clock with an enable programmable interrupt generation logic with interrupt masking lock register protection from runaway software reset generation logic with an enable/disable user-enabled stalling when the microcontroller asserts the cpu halt flag during debug the watchdog timer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. once the watchdog timer has been configured, the lock register can be written to prevent the timer configuration from being inadvertently altered. 583 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 11.1 block diagram figure 11-1. wdt module block diagram 11.2 functional description the watchdog timer module generates the first time-out signal when the 32-bit counter reaches the zero state after being enabled; enabling the counter also enables the watchdog timer interrupt. after the first time-out event, the 32-bit counter is re-loaded with the value of the watchdog timer load (wdtload) register, and the timer resumes counting down from that value. once the watchdog timer has been configured, the watchdog timer lock (wdtlock) register is written, which prevents the timer configuration from being inadvertently altered by software. if the timer counts down to its zero state again before the first time-out interrupt is cleared, and the reset signal has been enabled by setting the resen bit in the wdtctl register, the watchdog timer asserts its reset signal to the system. if the interrupt is cleared before the 32-bit counter reaches its second time-out, the 32-bit counter is loaded with the value in the wdtload register, and counting resumes from that value. if wdtload is written with a new value while the watchdog timer counter is counting, then the counter is loaded with the new value and continues counting. july 03, 2014 584 texas instruments-production data watchdog timers & r q w u r o & o r f n , q w h u u x s w * h q h u d w l r q : ' 7 & 7 / : ' 7 , & 5 : ' 7 5 , 6 : ' 7 0 , 6 : ' 7 / 2 & . : ' 7 7 ( 6 7 : ' 7 / 2 $ ' : ' 7 9 $ / 8 ( & r p s d u d w r u % l w ' r z q & r x q w h u [ , q w h u u x s w 6 \ v w h p & o r f n 3 , 2 6 & , g h q w l i l f d w l r q 5 h j l v w h u v : ' 7 3 & h o o , ' : ' 7 3 h u l s k , ' : ' 7 3 h u l s k , ' : ' 7 3 & h o o , ' : ' 7 3 h u l s k , ' : ' 7 3 h u l s k , ' : ' 7 3 & h o o , ' : ' 7 3 h u l s k , ' : ' 7 3 h u l s k , ' : ' 7 3 & h o o , ' : ' 7 3 h u l s k , ' : ' 7 3 h u l s k , ' writing to wdtload does not clear an active interrupt. an interrupt must be specifically cleared by writing to the watchdog interrupt clear (wdticr) register. the watchdog module interrupt and reset generation can be enabled or disabled as required. when the interrupt is re-enabled, the 32-bit counter is preloaded with the load register value and not its last state. 11.2.1 register access timing because the watchdog timer 1 module has an independent clocking domain, its registers must be written with a timing gap between accesses. software must guarantee that this delay is inserted between back-to-back writes to wdt1 registers or between a write followed by a read to the registers. the timing for back-to-back reads from the wdt1 module has no restrictions. the wrc bit in the watchdog control (wdtctl) register for wdt1 indicates that the required timing gap has elapsed. this bit is cleared on a write operation and set once the write completes, indicating to software that another write or read may be started safely. software should poll wdtctl for wrc =1 prior to accessing another register. note that wdt0 does not have this restriction as it runs off the system clock. 11.3 initialization and configuration to use the wdt, its peripheral clock must be enabled by setting the wdt bit in the rcgc0n register, see page 262. the watchdog timer is configured using the following sequence: 1. load the wdtload register with the desired timer load value. 2. if wdt1, wait for the wrc bit in the wdtctl register to be set. 3. if the watchdog is configured to trigger system resets, set the resen bit in the wdtctl register. 4. if wdt1, wait for the wrc bit in the wdtctl register to be set. 5. set the inten bit in the wdtctl register to enable the watchdog and lock the control register. if software requires that all of the watchdog registers are locked, the watchdog timer module can be fully locked by writing any value to the wdtlock register. to unlock the watchdog timer, write a value of 0x1acc.e551. to service the watchdog, periodically reload the count value into the wdtload register to restart the count. the interrupt can be enabled using the inten bit in the wdtctl register to allow the processor to attempt corrective action if the watchdog is not serviced often enough. the resen bit in the wdtctl can be set so that the system resets if the failure is not recoverable using the isr. 11.4 register map table 11-1 on page 586 lists the watchdog registers. the offset listed is a hexadecimal increment to the registers address, relative to the watchdog timer base address: wdt0: 0x4000.0000 wdt1: 0x4000.1000 note that the watchdog timer module clock must be enabled before the registers can be programmed (see page 262). 585 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 11-1. watchdog timers register map see page description reset type name offset 587 watchdog load 0xffff.ffff r/w wdtload 0x000 588 watchdog value 0xffff.ffff ro wdtvalue 0x004 589 watchdog control 0x0000.0000 (wdt0) 0x8000.0000 (wdt1) r/w wdtctl 0x008 591 watchdog interrupt clear - wo wdticr 0x00c 592 watchdog raw interrupt status 0x0000.0000 ro wdtris 0x010 593 watchdog masked interrupt status 0x0000.0000 ro wdtmis 0x014 594 watchdog test 0x0000.0000 r/w wdttest 0x418 595 watchdog lock 0x0000.0000 r/w wdtlock 0xc00 596 watchdog peripheral identification 4 0x0000.0000 ro wdtperiphid4 0xfd0 597 watchdog peripheral identification 5 0x0000.0000 ro wdtperiphid5 0xfd4 598 watchdog peripheral identification 6 0x0000.0000 ro wdtperiphid6 0xfd8 599 watchdog peripheral identification 7 0x0000.0000 ro wdtperiphid7 0xfdc 600 watchdog peripheral identification 0 0x0000.0005 ro wdtperiphid0 0xfe0 601 watchdog peripheral identification 1 0x0000.0018 ro wdtperiphid1 0xfe4 602 watchdog peripheral identification 2 0x0000.0018 ro wdtperiphid2 0xfe8 603 watchdog peripheral identification 3 0x0000.0001 ro wdtperiphid3 0xfec 604 watchdog primecell identification 0 0x0000.000d ro wdtpcellid0 0xff0 605 watchdog primecell identification 1 0x0000.00f0 ro wdtpcellid1 0xff4 606 watchdog primecell identification 2 0x0000.0006 ro wdtpcellid2 0xff8 607 watchdog primecell identification 3 0x0000.00b1 ro wdtpcellid3 0xffc 11.5 register descriptions the remainder of this section lists and describes the wdt registers, in numerical order by address offset. july 03, 2014 586 texas instruments-production data watchdog timers register 1: watchdog load (wdtload), offset 0x000 this register is the 32-bit interval value used by the 32-bit counter. when this register is written, the value is immediately loaded and the counter restarts counting down from the new value. if the wdtload register is loaded with 0x0000.0000, an interrupt is immediately generated. watchdog load (wdtload) wdt0 base: 0x4000.0000 wdt1 base: 0x4000.1000 offset 0x000 type r/w, reset 0xffff.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 wdtload r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 wdtload r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field watchdog load value 0xffff.ffff r/w wdtload 31:0 587 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 2: watchdog value (wdtvalue), offset 0x004 this register contains the current count value of the timer. watchdog value (wdtvalue) wdt0 base: 0x4000.0000 wdt1 base: 0x4000.1000 offset 0x004 type ro, reset 0xffff.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 wdtvalue ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 wdtvalue ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field watchdog value current value of the 32-bit down counter. 0xffff.ffff ro wdtvalue 31:0 july 03, 2014 588 texas instruments-production data watchdog timers register 3: watchdog control (wdtctl), offset 0x008 this register is the watchdog control register. the watchdog timer can be configured to generate a reset signal (on second time-out) or an interrupt on time-out. when the watchdog interrupt has been enabled by setting the inten bit, all subsequent writes to the inten bit are ignored. the only mechanism that can re-enable writes to this bit is a hardware reset. important: because the watchdog timer 1 module has an independent clocking domain, its registers must be written with a timing gap between accesses. software must guarantee that this delay is inserted between back-to-back writes to wdt1 registers or between a write followed by a read to the registers. the timing for back-to-back reads from the wdt1 module has no restrictions. the wrc bit in the watchdog control (wdtctl) register for wdt1 indicates that the required timing gap has elapsed. this bit is cleared on a write operation and set once the write completes, indicating to software that another write or read may be started safely. software should poll wdtctl for wrc =1 prior to accessing another register. note that wdt0 does not have this restriction as it runs off the system clock and therefore does not have a wrc bit. watchdog control (wdtctl) wdt0 base: 0x4000.0000 wdt1 base: 0x4000.1000 offset 0x008 type r/w, reset 0x0000.0000 (wdt0) and 0x8000.0000 (wdt1) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved wrc ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 inten resen reserved r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field write complete the wrc values are defined as follows: description value a write access to one of the wdt1 registers is in progress. 0 a write access is not in progress, and wdt1 registers can be read or written. 1 note: this bit is reserved for wdt0 and has a reset value of 0. 1 ro wrc 31 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000.000 ro reserved 30:2 589 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field watchdog reset enable the resen values are defined as follows: description value disabled. 0 enable the watchdog module reset output. 1 0 r/w resen 1 watchdog interrupt enable the inten values are defined as follows: description value interrupt event disabled (once this bit is set, it can only be cleared by a hardware reset). 0 interrupt event enabled. once enabled, all writes are ignored. 1 0 r/w inten 0 july 03, 2014 590 texas instruments-production data watchdog timers register 4: watchdog interrupt clear (wdticr), offset 0x00c this register is the interrupt clear register. a write of any value to this register clears the watchdog interrupt and reloads the 32-bit counter from the wdtload register. value for a read or reset is indeterminate. watchdog interrupt clear (wdticr) wdt0 base: 0x4000.0000 wdt1 base: 0x4000.1000 offset 0x00c type wo, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 wdtintclr wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type - - - - - - - - - - - - - - - - reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 wdtintclr wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type - - - - - - - - - - - - - - - - reset description reset type name bit/field watchdog interrupt clear - wo wdtintclr 31:0 591 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 5: watchdog raw interrupt status (wdtris), offset 0x010 this register is the raw interrupt status register. watchdog interrupt events can be monitored via this register if the controller interrupt is masked. watchdog raw interrupt status (wdtris) wdt0 base: 0x4000.0000 wdt1 base: 0x4000.1000 offset 0x010 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 wdtris reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:1 watchdog raw interrupt status description value a watchdog time-out event has occurred. 1 the watchdog has not timed out. 0 0 ro wdtris 0 july 03, 2014 592 texas instruments-production data watchdog timers register 6: watchdog masked interrupt status (wdtmis), offset 0x014 this register is the masked interrupt status register. the value of this register is the logical and of the raw interrupt bit and the watchdog interrupt enable bit. watchdog masked interrupt status (wdtmis) wdt0 base: 0x4000.0000 wdt1 base: 0x4000.1000 offset 0x014 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 wdtmis reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:1 watchdog masked interrupt status description value a watchdog time-out event has been signalled to the interrupt controller. 1 the watchdog has not timed out or the watchdog timer interrupt is masked. 0 0 ro wdtmis 0 593 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 7: watchdog test (wdttest), offset 0x418 this register provides user-enabled stalling when the microcontroller asserts the cpu halt flag during debug. watchdog test (wdttest) wdt0 base: 0x4000.0000 wdt1 base: 0x4000.1000 offset 0x418 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved stall reserved ro ro ro ro ro ro ro ro r/w ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:9 watchdog stall enable description value if the microcontroller is stopped with a debugger, the watchdog timer stops counting. once the microcontroller is restarted, the watchdog timer resumes counting. 1 the watchdog timer continues counting if the microcontroller is stopped with a debugger. 0 0 r/w stall 8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 7:0 july 03, 2014 594 texas instruments-production data watchdog timers register 8: watchdog lock (wdtlock), offset 0xc00 writing 0x1acc.e551 to the wdtlock register enables write access to all other registers. writing any other value to the wdtlock register re-enables the locked state for register writes to all the other registers. reading the wdtlock register returns the lock status rather than the 32-bit value written. therefore, when write accesses are disabled, reading the wdtlock register returns 0x0000.0001 (when locked; otherwise, the returned value is 0x0000.0000 (unlocked)). watchdog lock (wdtlock) wdt0 base: 0x4000.0000 wdt1 base: 0x4000.1000 offset 0xc00 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 wdtlock r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 wdtlock r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field watchdog lock a write of the value 0x1acc.e551 unlocks the watchdog registers for write access. a write of any other value reapplies the lock, preventing any register updates. a read of this register returns the following values: description value locked 0x0000.0001 unlocked 0x0000.0000 0x0000.0000 r/w wdtlock 31:0 595 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 9: watchdog peripheral identification 4 (wdtperiphid4), offset 0xfd0 the wdtperiphidn registers are hard-coded and the fields within the register determine the reset value. watchdog peripheral identification 4 (wdtperiphid4) wdt0 base: 0x4000.0000 wdt1 base: 0x4000.1000 offset 0xfd0 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid4 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 wdt peripheral id register [7:0] 0x00 ro pid4 7:0 july 03, 2014 596 texas instruments-production data watchdog timers register 10: watchdog peripheral identification 5 (wdtperiphid5), offset 0xfd4 the wdtperiphidn registers are hard-coded and the fields within the register determine the reset value. watchdog peripheral identification 5 (wdtperiphid5) wdt0 base: 0x4000.0000 wdt1 base: 0x4000.1000 offset 0xfd4 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid5 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 wdt peripheral id register [15:8] 0x00 ro pid5 7:0 597 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 11: watchdog peripheral identification 6 (wdtperiphid6), offset 0xfd8 the wdtperiphidn registers are hard-coded and the fields within the register determine the reset value. watchdog peripheral identification 6 (wdtperiphid6) wdt0 base: 0x4000.0000 wdt1 base: 0x4000.1000 offset 0xfd8 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid6 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 wdt peripheral id register [23:16] 0x00 ro pid6 7:0 july 03, 2014 598 texas instruments-production data watchdog timers register 12: watchdog peripheral identification 7 (wdtperiphid7), offset 0xfdc the wdtperiphidn registers are hard-coded and the fields within the register determine the reset value. watchdog peripheral identification 7 (wdtperiphid7) wdt0 base: 0x4000.0000 wdt1 base: 0x4000.1000 offset 0xfdc type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid7 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 wdt peripheral id register [31:24] 0x00 ro pid7 7:0 599 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 13: watchdog peripheral identification 0 (wdtperiphid0), offset 0xfe0 the wdtperiphidn registers are hard-coded and the fields within the register determine the reset value. watchdog peripheral identification 0 (wdtperiphid0) wdt0 base: 0x4000.0000 wdt1 base: 0x4000.1000 offset 0xfe0 type ro, reset 0x0000.0005 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid0 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 watchdog peripheral id register [7:0] 0x05 ro pid0 7:0 july 03, 2014 600 texas instruments-production data watchdog timers register 14: watchdog peripheral identification 1 (wdtperiphid1), offset 0xfe4 the wdtperiphidn registers are hard-coded and the fields within the register determine the reset value. watchdog peripheral identification 1 (wdtperiphid1) wdt0 base: 0x4000.0000 wdt1 base: 0x4000.1000 offset 0xfe4 type ro, reset 0x0000.0018 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid1 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 watchdog peripheral id register [15:8] 0x18 ro pid1 7:0 601 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 15: watchdog peripheral identification 2 (wdtperiphid2), offset 0xfe8 the wdtperiphidn registers are hard-coded and the fields within the register determine the reset value. watchdog peripheral identification 2 (wdtperiphid2) wdt0 base: 0x4000.0000 wdt1 base: 0x4000.1000 offset 0xfe8 type ro, reset 0x0000.0018 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid2 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 watchdog peripheral id register [23:16] 0x18 ro pid2 7:0 july 03, 2014 602 texas instruments-production data watchdog timers register 16: watchdog peripheral identification 3 (wdtperiphid3), offset 0xfec the wdtperiphidn registers are hard-coded and the fields within the register determine the reset value. watchdog peripheral identification 3 (wdtperiphid3) wdt0 base: 0x4000.0000 wdt1 base: 0x4000.1000 offset 0xfec type ro, reset 0x0000.0001 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 watchdog peripheral id register [31:24] 0x01 ro pid3 7:0 603 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 17: watchdog primecell identification 0 (wdtpcellid0), offset 0xff0 the wdtpcellidn registers are hard-coded and the fields within the register determine the reset value. watchdog primecell identification 0 (wdtpcellid0) wdt0 base: 0x4000.0000 wdt1 base: 0x4000.1000 offset 0xff0 type ro, reset 0x0000.000d 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cid0 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 watchdog primecell id register [7:0] 0x0d ro cid0 7:0 july 03, 2014 604 texas instruments-production data watchdog timers register 18: watchdog primecell identification 1 (wdtpcellid1), offset 0xff4 the wdtpcellidn registers are hard-coded and the fields within the register determine the reset value. watchdog primecell identification 1 (wdtpcellid1) wdt0 base: 0x4000.0000 wdt1 base: 0x4000.1000 offset 0xff4 type ro, reset 0x0000.00f0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cid1 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 watchdog primecell id register [15:8] 0xf0 ro cid1 7:0 605 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 19: watchdog primecell identification 2 (wdtpcellid2), offset 0xff8 the wdtpcellidn registers are hard-coded and the fields within the register determine the reset value. watchdog primecell identification 2 (wdtpcellid2) wdt0 base: 0x4000.0000 wdt1 base: 0x4000.1000 offset 0xff8 type ro, reset 0x0000.0006 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cid2 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 watchdog primecell id register [23:16] 0x06 ro cid2 7:0 july 03, 2014 606 texas instruments-production data watchdog timers register 20: watchdog primecell identification 3 (wdtpcellid3 ), offset 0xffc the wdtpcellidn registers are hard-coded and the fields within the register determine the reset value. watchdog primecell identification 3 (wdtpcellid3) wdt0 base: 0x4000.0000 wdt1 base: 0x4000.1000 offset 0xffc type ro, reset 0x0000.00b1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cid3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 watchdog primecell id register [31:24] 0xb1 ro cid3 7:0 607 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 12 analog-to-digital converter (adc) an analog-to-digital converter (adc) is a peripheral that converts a continuous analog voltage to a discrete digital number. two identical converter modules are included, which share 16 input channels. the stellaris ? adc module features 12-bit conversion resolution and supports 16 input channels, plus an internal temperature sensor. each adc module contains four programmable sequencers allowing the sampling of multiple analog input sources without controller intervention. each sample sequencer provides flexible programming with fully configurable input source, trigger events, interrupt generation, and sequencer priority. a digital comparator function is included which allows the conversion value to be diverted to a digital comparator module. each adc module provides eight digital comparators. each digital comparator evaluates the adc conversion value against its two user-defined values to determine the operational range of the signal. the trigger source for adc0 and adc1 may be independent or the two adc modules may operate from the same trigger source and operate on the same or different inputs. a phase shifter can delay the start of sampling by a specified phase angle. when using both adc modules, it is possible to configure the converters to start the conversions coincidentally or within a relative phase from each other, see sample phase control on page 614. the stellaris lm3s9gn5 microcontroller provides two adc modules with each having the following features: 16 shared analog input channels 12-bit precision adc with an accurate 10-bit data compatibility mode single-ended and differential-input configurations on-chip internal temperature sensor maximum sample rate of one million samples/second optional phase shift in sample time programmable from 22.5o to 337.5o four programmable sample conversion sequencers from one to eight entries long, with corresponding conversion result fifos flexible trigger control C controller (software) C timers C analog comparators C pwm C gpio hardware averaging of up to 64 samples digital comparison unit providing eight digital comparators converter uses an internal 3-v reference or an external reference july 03, 2014 608 texas instruments-production data analog-to-digital converter (adc) power and ground for the analog circuitry is separate from the digital power and ground efficient transfers using micro direct memory access controller (dma) C dedicated channel for each sample sequencer C adc module uses burst requests for dma 12.1 block diagram the stellaris microcontroller contains two identical analog-to-digital converter modules. these two modules, adc0 and adc1, share the same 16 analog input channels. each adc module operates independently and can therefore execute different sample sequences, sample any of the analog input channels at any time, and generate different interrupts and triggers. figure 12-1 on page 609 shows how the two modules are connected to analog inputs and the system bus. figure 12-1. implementation of two adc blocks figure 12-2 on page 610 provides details on the internal configuration of the adc controls and data registers. 609 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller , q s x w & k d q q h o v 7 u l j j h u v , q w h u u x s w v 7 u l j j h u v $ ' & $ ' & , q w h u u x s w v 7 u l j j h u v figure 12-2. adc module block diagram 12.2 signal description the following table lists the external signals of the adc module and describes the function of each. the adc signals are analog functions for some gpio signals. the column in the table below titled "pin mux/pin assignment" lists the gpio pin placement for the adc signals. the ainx and vrefa analog signals are not 5-v tolerant and go through an isolation circuit before reaching their circuitry. these signals are configured by clearing the corresponding den bit in the gpio digital enable (gpioden) register and setting the corresponding amsel bit in the gpio analog mode select (gpioamsel) register. for more information on configuring gpios, see general-purpose input/outputs (gpios) on page 405. table 12-1. adc signals (100lqfp) description buffer type a pin type pin mux / pin assignment pin number pin name analog-to-digital converter input 0. analog i pe7 1 ain0 analog-to-digital converter input 1. analog i pe6 2 ain1 analog-to-digital converter input 2. analog i pe5 5 ain2 analog-to-digital converter input 3. analog i pe4 6 ain3 analog-to-digital converter input 4. analog i pd7 100 ain4 analog-to-digital converter input 5. analog i pd6 99 ain5 analog-to-digital converter input 6. analog i pd5 98 ain6 analog-to-digital converter input 7. analog i pd4 97 ain7 analog-to-digital converter input 8. analog i pe3 96 ain8 analog-to-digital converter input 9. analog i pe2 95 ain9 july 03, 2014 610 texas instruments-production data analog-to-digital converter (adc) $ q d o r j , q s x w v $ , 1 [ 7 u l j j h u ( y h q w v 6 6 , q w h u u x s w 6 6 , q w h u u x s w 6 6 , q w h u u x s w 6 6 , q w h u u x s w $ ' & , 6 & $ ' & 5 , 6 $ ' & , 0 , q w h u u x s w & r q w u r o $ ' & ' & , 6 & 6 6 6 6 6 6 6 6 & r p s d u d w r u * 3 , 2 3 % 7 l p h u 3 : 0 & r p s d u d w r u * 3 , 2 3 % 7 l p h u 3 : 0 & r p s d u d w r u * 3 , 2 3 % 7 l p h u 3 : 0 & r p s d u d w r u * 3 , 2 3 % 7 l p h u 3 : 0 $ ' & ( 0 8 ; $ ' & 3 6 6 , & r q w u r o 6 w d w x v $ ' & 8 6 7 $ 7 $ ' & 2 6 7 $ 7 $ ' & $ & 7 6 6 $ ' & 6 6 3 5 , ' l j l w d o & r p s d u d w r u $ ' & 6 6 2 3 q $ ' & 6 6 ' & q $ ' & ' & & 7 / q $ ' & ' & & 0 3 q $ q d o r j w r ' l j l w d o & r q y h u w h u + d u g z d u h $ y h u d j h u $ ' & 6 $ & $ ' & 6 6 ) 6 7 $ 7 $ ' & 6 6 & 7 / $ ' & 6 6 0 8 ; 6 d p s o h 6 h t x h q f h u $ ' & 6 6 ) 6 7 $ 7 $ ' & 6 6 & 7 / $ ' & 6 6 0 8 ; 6 d p s o h 6 h t x h q f h u $ ' & 6 6 ) 6 7 $ 7 $ ' & 6 6 & 7 / $ ' & 6 6 0 8 ; 6 d p s o h 6 h t x h q f h u $ ' & 6 6 ) 6 7 $ 7 $ ' & 6 6 & 7 / $ ' & 6 6 0 8 ; 6 d p s o h 6 h t x h q f h u 3 : 0 7 u l j j h u ' & , q w h u u x s w v , q w h u q d o 9 r o w d j h 5 h i ( [ w h u q d o 9 r o w d j h 5 h i 9 5 ( ) $ $ ' & & 7 / $ ' & 6 3 & ) , ) 2 % o r f n $ ' & 6 6 ) , ) 2 $ ' & 6 6 ) , ) 2 $ ' & 6 6 ) , ) 2 $ ' & 6 6 ) , ) 2 $ ' & ' & 5 , & table 12-1. adc signals (100lqfp) (continued) description buffer type a pin type pin mux / pin assignment pin number pin name analog-to-digital converter input 10. analog i pb4 92 ain10 analog-to-digital converter input 11. analog i pb5 91 ain11 analog-to-digital converter input 12. analog i pd3 13 ain12 analog-to-digital converter input 13. analog i pd2 12 ain13 analog-to-digital converter input 14. analog i pd1 11 ain14 analog-to-digital converter input 15. analog i pd0 10 ain15 this input provides a reference voltage used to specify the input voltage at which the adc converts to a maximum value. in other words, the voltage that is applied to vrefa is the voltage with which an ainn signal is converted to 4095. the vrefa input is limited to the range specified in table 26-23 on page 1314 . analog i pb6 90 vrefa a. the ttl designation indicates the pin has ttl-compatible voltage levels. table 12-2. adc signals (108bga) description buffer type a pin type pin mux / pin assignment pin number pin name analog-to-digital converter input 0. analog i pe7 b1 ain0 analog-to-digital converter input 1. analog i pe6 a1 ain1 analog-to-digital converter input 2. analog i pe5 b3 ain2 analog-to-digital converter input 3. analog i pe4 b2 ain3 analog-to-digital converter input 4. analog i pd7 a2 ain4 analog-to-digital converter input 5. analog i pd6 a3 ain5 analog-to-digital converter input 6. analog i pd5 c6 ain6 analog-to-digital converter input 7. analog i pd4 b5 ain7 analog-to-digital converter input 8. analog i pe3 b4 ain8 analog-to-digital converter input 9. analog i pe2 a4 ain9 analog-to-digital converter input 10. analog i pb4 a6 ain10 analog-to-digital converter input 11. analog i pb5 b7 ain11 analog-to-digital converter input 12. analog i pd3 h1 ain12 analog-to-digital converter input 13. analog i pd2 h2 ain13 analog-to-digital converter input 14. analog i pd1 g2 ain14 analog-to-digital converter input 15. analog i pd0 g1 ain15 this input provides a reference voltage used to specify the input voltage at which the adc converts to a maximum value. in other words, the voltage that is applied to vrefa is the voltage with which an ainn signal is converted to 4095. the vrefa input is limited to the range specified in table 26-23 on page 1314 . analog i pb6 a7 vrefa a. the ttl designation indicates the pin has ttl-compatible voltage levels. 611 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 12.3 functional description the stellaris adc collects sample data by using a programmable sequence-based approach instead of the traditional single or double-sampling approaches found on many adc modules. each sample sequence is a fully programmed series of consecutive (back-to-back) samples, allowing the adc to collect data from multiple input sources without having to be re-configured or serviced by the processor. the programming of each sample in the sample sequence includes parameters such as the input source and mode (differential versus single-ended input), interrupt generation on sample completion, and the indicator for the last sample in the sequence. in addition, the dma can be used to more efficiently move data from the sample sequencers without cpu intervention. 12.3.1 sample sequencers the sampling control and data capture is handled by the sample sequencers. all of the sequencers are identical in implementation except for the number of samples that can be captured and the depth of the fifo. table 12-3 on page 612 shows the maximum number of samples that each sequencer can capture and its corresponding fifo depth. each sample that is captured is stored in the fifo. in this implementation, each fifo entry is a 32-bit word, with the lower 12 bits containing the conversion result. table 12-3. samples and fifo depth of sequencers depth of fifo number of samples sequencer 1 1 ss3 4 4 ss2 4 4 ss1 8 8 ss0 for a given sample sequence, each sample is defined by bit fields in the adc sample sequence input multiplexer select (adcssmuxn) and adc sample sequence control (adcssctln) registers, where "n" corresponds to the sequence number. the adcssmuxn fields select the input pin, while the adcssctln fields contain the sample control bits corresponding to parameters such as temperature sensor selection, interrupt enable, end of sequence, and differential input mode. sample sequencers are enabled by setting the respective asenn bit in the adc active sample sequencer (adcactss) register and should be configured before being enabled. sampling is then initiated by setting the ssn bit in the adc processor sample sequence initiate (adcpssi) register. in addition, sample sequences may be initiated on multiple adc modules simultaneously using the gsync and syncwait bits in the adcpssi register during the configuration of each adc module. for more information on using these bits, refer to page 651. when configuring a sample sequence, multiple uses of the same input pin within the same sequence are allowed. in the adcssctln register, the ien bits can be set for any combination of samples, allowing interrupts to be generated after every sample in the sequence if necessary. also, the end bit can be set at any point within a sample sequence. for example, if sequencer 0 is used, the end bit can be set in the nibble associated with the fifth sample, allowing sequencer 0 to complete execution of the sample sequence after the fifth sample. after a sample sequence completes execution, the result data can be retrieved from the adc sample sequence result fifo (adcssfifon) registers. the fifos are simple circular buffers that read a single address to "pop" result data. for software debug purposes, the positions of the fifo head and tail pointers are visible in the adc sample sequence fifo status (adcssfstatn) registers along with full and empty status flags. if a write is attempted when the fifo is full, the write does not occur and an overflow condition is indicated. overflow and underflow conditions are monitored using the adcostat and adcustat registers. july 03, 2014 612 texas instruments-production data analog-to-digital converter (adc) 12.3.2 module control outside of the sample sequencers, the remainder of the control logic is responsible for tasks such as: interrupt generation dma operation sequence prioritization trigger configuration comparator configuration external voltage reference sample phase control most of the adc control logic runs at the adc clock rate of 16 mhz. the internal adc divider is configured for 16-mhz operation automatically by hardware when the system xtal is selected with the pll. 12.3.2.1 interrupts the register configurations of the sample sequencers and digital comparators dictate which events generate raw interrupts, but do not have control over whether the interrupt is actually sent to the interrupt controller. the adc module's interrupt signals are controlled by the state of the mask bits in the adc interrupt mask (adcim) register. interrupt status can be viewed at two locations: the adc raw interrupt status (adcris) register, which shows the raw status of the various interrupt signals; and the adc interrupt status and clear (adcisc) register, which shows active interrupts that are enabled by the adcim register. sequencer interrupts are cleared by writing a 1 to the corresponding in bit in adcisc . digital comparator interrupts are cleared by writing a 1 to the adc digital comparator interrupt status and clear (adcdcisc) register. 12.3.2.2 dma operation dma may be used to increase efficiency by allowing each sample sequencer to operate independently and transfer data without processor intervention or reconfiguration. the adc module provides a request signal from each sample sequencer to the associated dedicated channel of the dma controller. the adc does not support single transfer requests. a burst transfer request is asserted when the interrupt bit for the sample sequence is set ( ie bit in the adcssctln register is set). the arbitration size of the dma transfer must be a power of 2, and the associated ie bits in the addssctln register must be set. for example, if the dma channel of ss0 has an arbitration size of four, the ie3 bit (4th sample) and the ie7 bit (8th sample) must be set. thus the dma request occurs every time 4 samples have been acquired. no other special steps are needed to enable the adc module for dma operation. refer to the micro direct memory access (dma) on page 344 for more details about programming the dma controller. 12.3.2.3 prioritization when sampling events (triggers) happen concurrently, they are prioritized for processing by the values in the adc sample sequencer priority (adcsspri) register. valid priority values are in the range of 0-3, with 0 being the highest priority and 3 being the lowest. multiple active sample 613 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller sequencer units with the same priority do not provide consistent results, so software must ensure that all active sample sequencer units have a unique priority value. 12.3.2.4 sampling events sample triggering for each sample sequencer is defined in the adc event multiplexer select (adcemux) register. trigger sources include processor (default), analog comparators, an external signal on gpio pb4 , a gp timer, a pwm generator, and continuous sampling. the processor triggers sampling by setting the ssx bits in the adc processor sample sequence initiate (adcpssi) register. care must be taken when using the continuous sampling trigger. if a sequencer's priority is too high, it is possible to starve other lower priority sequencers. generally, a sample sequencer using continuous sampling should be set to the lowest priority. continuous sampling can be used with a digital comparator to cause an interrupt when a particular voltage is seen on an input. 12.3.2.5 sample phase control the trigger source for adc0 and adc1 may be independent or the two adc modules may operate from the same trigger source and operate on the same or different inputs. if the converters are running at the same sample rate, they may be configured to start the conversions coincidentally or with one of 15 different discrete phases relative to each other. the sample time can be delayed from the standard sampling time in 22.5 increments up to 337.5o using the adc sample phase control (adcspc) register. figure 12-3 on page 614 shows an example of various phase relationships at a 1 msps rate. figure 12-3. adc sample phases this feature can be used to double the sampling rate of an input. both adc module 0 and adc module 1 can be programmed to sample the same input. adc module 0 could sample at the standard position (the phase field in the adcspc register is 0x0). adc module 1 can be configured to sample at 180 ( phase = 0x8). the two modules can be be synchronized using the gsync and syncwait bits in the adc processor sample sequence initiate (adcpssi) register. software could then combine the results from the two modules to create a sample rate of two million samples/second at 16 mhz as shown in figure 12-4 on page 615. july 03, 2014 614 texas instruments-production data analog-to-digital converter (adc) $ ' & 6 d p s o h & o r f n 3 + $ 6 ( [ ? 3 + $ 6 ( [ ? 3 + $ 6 ( [ ( ? 3 + $ 6 ( [ ) ? figure 12-4. doubling the adc sample rate using the adcspc register, adc0 and adc1 may provide a number of interesting applications: coincident sampling of different signals. the sample sequence steps run coincidently in both converters. C adc module 0, adcspc = 0x0, sampling ain0 C adc module 1, adcspc = 0x0, sampling ain1 skewed sampling of the same signal. the sample sequence steps are 1/2 of an adc clock (500 s for a 1ms/s adc) out of phase with each other. this configuration doubles the conversion bandwidth of a single input when software combines the results as shown in figure 12-5 on page 615. C adc module 0, adcspc = 0x0, sampling ain0 C adc module 1, adcspc = 0x8, sampling ain0 figure 12-5. skewed sampling 12.3.3 hardware sample averaging circuit higher precision results can be generated using the hardware averaging circuit, however, the improved results are at the cost of throughput. up to 64 samples can be accumulated and averaged to form a single data entry in the sequencer fifo. throughput is decreased proportionally to the 615 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller $ ' & 6 d p s o h & o r f n * 6 < 1 & $ ' & 3 + $ 6 ( [ ? $ ' & 3 + $ 6 ( [ ? 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 $ ' & $ ' & 6 number of samples in the averaging calculation. for example, if the averaging circuit is configured to average 16 samples, the throughput is decreased by a factor of 16. by default the averaging circuit is off, and all data from the converter passes through to the sequencer fifo. the averaging hardware is controlled by the adc sample averaging control (adcsac) register (see page 653). a single averaging circuit has been implemented, thus all input channels receive the same amount of averaging whether they are single-ended or differential. figure 12-6 shows an example in which the adcsac register is set to 0x2 for 4x hardware oversampling and the ie1 bit is set for the sample sequence, resulting in an interrupt after the second averaged value is stored in the fifo. figure 12-6. sample averaging example 12.3.4 analog-to-digital converter the analog-to-digital converter (adc) module uses a successive approximation register (sar) architecture to deliver a 12-bit, low-power, high-precision conversion value. the adc defaults to a 10-bit conversion result, providing backwards compatibility with previous generations of stellaris microcontrollers. to enable 12-bit resolution, set the res bit in the adc control (adcctl) register. the successive-approximation algorithm uses a current mode d/a converter to achieve lower settling time, resulting in higher conversion speeds for the a/d converter. in addition, built-in sample-and-hold circuitry with offset-calibration circuitry improves conversion accuracy. the adc must be run from the pll or a 16-mhz clock source. figure 12-7 shows the adc input equivalency diagram; for parameter values, see analog-to-digital converter (adc) on page 1313. july 03, 2014 616 texas instruments-production data analog-to-digital converter (adc) $ % & ' $ % & ' , 1 7 figure 12-7. adc input equivalency diagram the adc operates from both the 3.3-v analog and 1.2-v digital power supplies. the adc clock can be configured to reduce power consumption when adc conversions are not required (see system control on page 203). the analog inputs are connected to the adc through specially balanced input paths to minimize the distortion and cross-talk on the inputs. detailed information on the adc power supplies and analog inputs can be found in analog-to-digital converter (adc) on page 1313. 12.3.4.1 internal voltage reference the band-gap circuitry generates an internal 3.0 v reference that can be used by the adc to produce a conversion value from the selected analog input. the range of this conversion value is from 0x000 to 0xfff in 12-bit mode, or 0x3ff in 10-bit mode. in single-ended-input mode, the 0x000 value corresponds to an analog input voltage of 0.0 v; the 0xfff in 12-bit mode, or 0x3ff in 10-bit mode value corresponds to an analog input voltage of 3.0 v. this configuration results in a resolution of approximately 0.7 mv in 12-bit mode and 2.9 mv per adc code in 10-bit mode. while the analog input pads can handle voltages beyond this range, the analog input voltages must remain within the limits prescribed by electrical characteristics on page 1298 to produce accurate results. figure 12-8 on page 618 shows the adc conversion function of the analog inputs. 617 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 6 w h o o d u l v ? 0 l f u r f r q w u r o o h u 6 d p s o h d q g k r o g $ ' & f r q y h u w h u & $ ' & 5 $ ' & 9 ' ' e l w f r q y h u w h u , / 9 , 1 ( 6 ' & o d p s ( 6 ' & o d p s figure 12-8. internal voltage conversion result 12.3.4.2 external voltage reference the adc can use an external voltage reference to produce the conversion value from the selected analog input by configuring the vref field in the adc control (adcctl) register. the vref field specifies whether to use the internal, an external reference in the 3.0 v range, or an external reference in the 1.0 v range. while the range of the conversion value remains the same (0x000 to 0xfff or 0x3ff), the analog voltage associated with the 0xfff or 0x3ff value corresponds to the value of the voltage when using the 3.0-v setting and three times the voltage when using the 1.0-v setting, resulting in a smaller voltage resolution per adc code. ground is always used as the reference level for the minimum conversion value. while the analog input pads can handle voltages beyond this range, the analog input voltages must remain within the limits prescribed by electrical characteristics on page 1298 to produce accurate results. the v refa specification defines the useful range for the external voltage reference, see table 26-23 on page 1314. care must be taken to supply a reference voltage of acceptable quality. figure 12-9 on page 619 shows the adc conversion function of the analog inputs when using anthe 3.0-v setting on the external voltage reference. figure 12-10 on page 619 shows the adc conversion function when using the 1.0-v setting on the external voltage reference. the external voltage reference can be more accurate than the internal reference by using a high-precision source or trimming the source. july 03, 2014 618 texas instruments-production data analog-to-digital converter (adc) [ ) ) ) [ ) ) 9 , 1 [ % ) ) [ ) ) [ ) ) [ ) ) [ ) ) [ ) ) 9 9 9 9 9 , q s x w 6 d w x u d w l r q e l w e l w figure 12-9. external voltage conversion result with 3.0-v setting figure 12-10. external voltage conversion result with 1.0-v setting 619 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 9 , 1 9 9 ' ' , q s x w 6 d w x u d w l r q 9 5 ( ) $ 9 5 ( ) $ [ ) ) ) [ ) ) [ % ) ) [ ) ) [ ) ) [ ) ) [ ) ) [ ) ) e l w e l w 9 , 1 9 9 ' ' , q s x w 6 d w x u d w l r q 9 5 ( ) $ 9 5 ( ) $ [ ) ) ) [ ) ) [ % ) ) [ ) ) [ ) ) [ ) ) [ ) ) [ ) ) e l w e l w 12.3.5 differential sampling in addition to traditional single-ended sampling, the adc module supports differential sampling of two analog input channels. to enable differential sampling, software must set the dn bit in the adcssctl0n register in a step's configuration nibble. when a sequence step is configured for differential sampling, the input pair to sample must be configured in the adcssmuxn register. differential pair 0 samples analog inputs 0 and 1; differential pair 1 samples analog inputs 2 and 3; and so on (see table 12-4 on page 620). the adc does not support other differential pairings such as analog input 0 with analog input 3. table 12-4. differential sampling pairs analog inputs differential pair 0 and 1 0 2 and 3 1 4 and 5 2 6 and 7 3 8 and 9 4 10 and 11 5 12 and 13 6 14 and 15 7 the voltage sampled in differential mode is the difference between the odd and even channels: ?v (differential voltage) = v in_even (even channel) C v in_odd (odd channel), therefore: if ?v = 0, then the conversion result = 0x1ff for 10-bit and 0x7ff for 12-bit if ?v > 0, then the conversion result > 0x1ff (range is 0x1ffC0x3ff) for 10-bit and > 0x7ff (range is 0x7ff - 0xfff) for 12-bit if ?v < 0, then the conversion result < 0x1ff (range is 0C0x1ff) for 10-bit and < 0x7ff (range is 0 - 0x7ff) for 12-bit the differential pairs assign polarities to the analog inputs: the even-numbered input is always positive, and the odd-numbered input is always negative. in order for a valid conversion result to appear, the negative input must be in the range of 1.5 v of the positive input. if an analog input is greater than 3 v or less than 0 v (the valid range for analog inputs), the input voltage is clipped, meaning it appears as either 3 v or 0 v , respectively, to the adc. figure 12-11 on page 621 shows an example of the negative input centered at 1.5 v. in this configuration, the differential range spans from -1.5 v to 1.5 v. figure 12-12 on page 621 shows an example where the negative input is centered at 0.75 v, meaning inputs on the positive input saturate past a differential voltage of -0.75 v because the input voltage is less than 0 v. figure 12-13 on page 622 shows an example of the negative input centered at 2.25 v, where inputs on the positive channel saturate past a differential voltage of 0.75 v since the input voltage would be greater than 3 v. july 03, 2014 620 texas instruments-production data analog-to-digital converter (adc) figure 12-11. differential sampling range, v in_odd = 1.5 v figure 12-12. differential sampling range, v in_odd = 0.75 v 621 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 9 , 1 b ( 9 ( 1 d v v in odd 1.5 v - input saturation 0xfff 0x7ff 12-bit 10-bit 0x3ff 0x1ff [ ) ) ) [ ) ) [ ) ) 9 9 9 9 , 1 b ( 9 ( 1 d v -1.5 v -0.75 v 1.5 v - input saturation 12-bit 10-bit 0x3ff 0x1ff 0x0ff figure 12-13. differential sampling range, v in_odd = 2.25 v 12.3.6 internal temperature sensor the temperature sensor's primary purpose is to notify the system that the internal temperature is too high or low for reliable operation. the temperature sensor does not have a separate enable, because it also contains the bandgap reference and must always be enabled. the reference is supplied to other analog modules; not just the adc. the internal temperature sensor provides an analog temperature reading as well as a reference voltage. this reference voltage, senso , is given by the following equation: senso = 2.7 - ((t + 55) / 75) this relation is shown in figure 12-14 on page 623. july 03, 2014 622 texas instruments-production data analog-to-digital converter (adc) [ ) ) ) [ % ) ) [ ) ) 9 9 9 9 , 1 b ( 9 ( 1 d v -1.5 v 0.75 v 1.5 v - input saturation 12-bit 0x3ff 0x2ff 0x1ff 10-bit figure 12-14. internal temperature sensor characteristic the temperature sensor reading can be sampled in a sample sequence by setting the tsn bit in the adcssctln register. the temperature reading from the temperature sensor can also be given as a function of the adc value. the following formula calculates temperature (in ) based on the adc reading: temperature = 147.5 - ((225 adc) / 4095) 12.3.7 digital comparator unit an adc is commonly used to sample an external signal and to monitor its value to ensure that it remains in a given range. to automate this monitoring procedure and reduce the amount of processor overhead that is required, each module provides eight digital comparators. conversions from the adc that are sent to the digital comparators are compared against the user programmable limits in the adc digital comparator range (adcdccmpn) registers. if the observed signal moves out of the acceptable range, a processor interrupt can be generated and/or a trigger can be sent to the pwm module. the digital comparators four operational modes (once, always, hysteresis once, hysteresis always) can be applied to three separate regions (low band, mid band, high band) as defined by the user. 12.3.7.1 output functions adc conversions can either be stored in the adc sample sequence fifos or compared using the digital comparator resources as defined by the sndcop bits in the adc sample sequence n operation (adcssopn) register. these selected adc conversions are used by their respective digital comparator to monitor the external signal. each comparator has two possible output functions: processor interrupts and triggers. 623 july 03, 2014 texas instruments-production data stellaris ? 6 h q v r u 6 h q v r u 9 7 9 9 9 7 h p s ? & ? & ? & each function has its own state machine to track the monitored signal. even though the interrupt and trigger functions can be enabled individually or both at the same time, the same conversion data is used by each function to determine if the right conditions have been met to assert the associated output. interrupts the digital comparator interrupt function is enabled by setting the cie bit in the adc digital comparator control (adcdcctln) register. this bit enables the interrupt function state machine to start monitoring the incoming adc conversions. when the appropriate set of conditions is met, and the dconssx bit is set in the adcim register, an interrupt is sent to the interrupt controller. triggers the digital comparator trigger function is enabled by setting the cte bit in the adcdcctln register. this bit enables the trigger function state machine to start monitoring the incoming adc conversions. when the appropriate set of conditions is met, the corresponding digital comparator trigger to the pwm module is asserted 12.3.7.2 operational modes four operational modes are provided to support a broad range of applications and multiple possible signaling requirements: always, once, hysteresis always, and hysteresis once. the operational mode is selected using the cim or ctm field in the adcdcctln register. always mode in the always operational mode, the associated interrupt or trigger is asserted whenever the adc conversion value meets its comparison criteria. the result is a string of assertions on the interrupt or trigger while the conversions are within the appropriate range. once mode in the once operational mode, the associated interrupt or trigger is asserted whenever the adc conversion value meets its comparison criteria, and the previous adc conversion value did not. the result is a single assertion of the interrupt or trigger when the conversions are within the appropriate range. hysteresis-always mode the hysteresis-always operational mode can only be used in conjunction with the low-band or high-band regions because the mid-band region must be crossed and the opposite region entered to clear the hysteresis condition. in the hysteresis-always mode, the associated interrupt or trigger is asserted in the following cases: 1) the adc conversion value meets its comparison criteria or 2) a previous adc conversion value has met the comparison criteria, and the hysteresis condition has not been cleared by entering the opposite region. the result is a string of assertions on the interrupt or trigger that continue until the opposite region is entered. hysteresis-once mode the hysteresis-once operational mode can only be used in conjunction with the low-band or high-band regions because the mid-band region must be crossed and the opposite region entered to clear the hysteresis condition. in the hysteresis-once mode, the associated interrupt or trigger is asserted only when the adc conversion value meets its comparison criteria, the hysteresis condition is clear, and the previous adc conversion did not meet the comparison criteria. the result is a single assertion on the interrupt or trigger. july 03, 2014 624 texas instruments-production data analog-to-digital converter (adc) 12.3.7.3 function ranges the two comparison values, comp0 and comp1 , in the adc digital comparator range (adcdccmpn) register effectively break the conversion area into three distinct regions. these regions are referred to as the low-band (less than or equal to comp0 ), mid-band (greater than comp0 but less than or equal to comp1 ), and high-band (greater than comp1 ) regions. comp0 and comp1 may be programmed to the same value, effectively creating two regions, but comp1 must always be greater than or equal to the value of comp0 . a comp1 value that is less than comp0 generates unpredictable results. low-band operation to operate in the low-band region, either the cic field or the ctc field in the adcdcctln register must be programmed to 0x0. this setting causes interrupts or triggers to be generated in the low-band region as defined by the programmed operational mode. an example of the state of the interrupt/trigger signal in the low-band region for each of the operational modes is shown in figure 12-15 on page 625. note that a "0" in a column following the operational mode name (always, once, hysteresis always, and hysteresis once) indicates that the interrupt or trigger signal is de-asserted and a "1" indicates that the signal is asserted. figure 12-15. low-band operation (cic=0x0 and/or ctc=0x0) mid-band operation to operate in the mid-band region, either the cic field or the ctc field in the adcdcctln register must be programmed to 0x1. this setting causes interrupts or triggers to be generated in the mid-band region according the operation mode. only the always and once operational modes are available in the mid-band region. an example of the state of the interrupt/trigger signal in the mid-band region for each of the allowed operational modes is shown in figure 12-16 on page 626. note that a "0" in 625 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller $ o z d \ v 2 q f h + \ v w h u h v l v $ o z d \ v + \ v w h u h v l v 2 q f h & 2 0 3 & 2 0 3 a column following the operational mode name (always or once) indicates that the interrupt or trigger signal is de-asserted and a "1" indicates that the signal is asserted. figure 12-16. mid-band operation (cic=0x1 and/or ctc=0x1) high-band operation to operate in the high-band region, either the cic field or the ctc field in the adcdcctln register must be programmed to 0x3. this setting causes interrupts or triggers to be generated in the high-band region according the operation mode. an example of the state of the interrupt/trigger signal in the high-band region for each of the allowed operational modes is shown in figure 12-17 on page 627. note that a "0" in a column following the operational mode name (always, once, hysteresis always, and hysteresis once) indicates that the interrupt or trigger signal is de-asserted and a "1" indicates that the signal is asserted. july 03, 2014 626 texas instruments-production data analog-to-digital converter (adc) $ o z d \ v 2 q f h + \ v w h u h v l v $ o z d \ v + \ v w h u h v l v 2 q f h & 2 0 3 & 2 0 3 figure 12-17. high-band operation (cic=0x3 and/or ctc=0x3) 12.4 initialization and configuration in order for the adc module to be used, the pll must be enabled and programmed to a supported crystal frequency in the rcc register (see page 219). using unsupported frequencies can cause faulty operation in the adc module. 12.4.1 module initialization initialization of the adc module is a simple process with very few steps: enabling the clock to the adc, disabling the analog isolation circuit associated with all inputs that are to be used, and reconfiguring the sample sequencer priorities (if needed). the initialization sequence for the adc is as follows: 1. enable the adc clock by using the rcgc0 register (see page 262). 2. enable the clock to the appropriate gpio modules via the rcgc2 register (see page 282). to find out which gpio ports to enable, refer to signal description on page 610. 3. set the gpio afsel bits for the adc input pins (see page 429). to determine which gpios to configure, see table 24-4 on page 1239. 4. configure the ainx and vrefa signals to be analog inputs by clearing the corresponding den bit in the gpio digital enable (gpioden) register (see page 440). 5. disable the analog isolation circuit for all adc input pins that are to be used by writing a 1 to the appropriate bits of the gpioamsel register (see page 445) in the associated gpio block. 627 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller $ o z d \ v 2 q f h + \ v w h u h v l v $ o z d \ v + \ v w h u h v l v 2 q f h & 2 0 3 & 2 0 3 6. if required by the application, reconfigure the sample sequencer priorities in the adcsspri register. the default configuration has sample sequencer 0 with the highest priority and sample sequencer 3 as the lowest priority. 12.4.2 sample sequencer configuration configuration of the sample sequencers is slightly more complex than the module initialization because each sample sequencer is completely programmable. the configuration for each sample sequencer should be as follows: 1. ensure that the sample sequencer is disabled by clearing the corresponding asenn bit in the adcactss register. programming of the sample sequencers is allowed without having them enabled. disabling the sequencer during programming prevents erroneous execution if a trigger event were to occur during the configuration process. 2. configure the trigger event for the sample sequencer in the adcemux register. 3. for each sample in the sample sequence, configure the corresponding input source in the adcssmuxn register. 4. for each sample in the sample sequence, configure the sample control bits in the corresponding nibble in the adcssctln register. when programming the last nibble, ensure that the end bit is set. failure to set the end bit causes unpredictable behavior. 5. if interrupts are to be used, set the corresponding mask bit in the adcim register. 6. enable the sample sequencer logic by setting the corresponding asenn bit in the adcactss register. 12.5 register map table 12-5 on page 628 lists the adc registers. the offset listed is a hexadecimal increment to the registers address, relative to that adc module's base address of: adc0: 0x4003.8000 adc1: 0x4003.9000 note that the adc module clock must be enabled before the registers can be programmed (see page 262). there must be a delay of 3 system clocks after the adc module clock is enabled before any adc module registers are accessed. table 12-5. adc register map see page description reset type name offset 631 adc active sample sequencer 0x0000.0000 r/w adcactss 0x000 632 adc raw interrupt status 0x0000.0000 ro adcris 0x004 634 adc interrupt mask 0x0000.0000 r/w adcim 0x008 636 adc interrupt status and clear 0x0000.0000 r/w1c adcisc 0x00c 639 adc overflow status 0x0000.0000 r/w1c adcostat 0x010 641 adc event multiplexer select 0x0000.0000 r/w adcemux 0x014 july 03, 2014 628 texas instruments-production data analog-to-digital converter (adc) table 12-5. adc register map (continued) see page description reset type name offset 646 adc underflow status 0x0000.0000 r/w1c adcustat 0x018 647 adc sample sequencer priority 0x0000.3210 r/w adcsspri 0x020 649 adc sample phase control 0x0000.0000 r/w adcspc 0x024 651 adc processor sample sequence initiate - r/w adcpssi 0x028 653 adc sample averaging control 0x0000.0000 r/w adcsac 0x030 654 adc digital comparator interrupt status and clear 0x0000.0000 r/w1c adcdcisc 0x034 656 adc control 0x0000.0000 r/w adcctl 0x038 657 adc sample sequence input multiplexer select 0 0x0000.0000 r/w adcssmux0 0x040 659 adc sample sequence control 0 0x0000.0000 r/w adcssctl0 0x044 662 adc sample sequence result fifo 0 - ro adcssfifo0 0x048 663 adc sample sequence fifo 0 status 0x0000.0100 ro adcssfstat0 0x04c 665 adc sample sequence 0 operation 0x0000.0000 r/w adcssop0 0x050 667 adc sample sequence 0 digital comparator select 0x0000.0000 r/w adcssdc0 0x054 669 adc sample sequence input multiplexer select 1 0x0000.0000 r/w adcssmux1 0x060 670 adc sample sequence control 1 0x0000.0000 r/w adcssctl1 0x064 662 adc sample sequence result fifo 1 - ro adcssfifo1 0x068 663 adc sample sequence fifo 1 status 0x0000.0100 ro adcssfstat1 0x06c 672 adc sample sequence 1 operation 0x0000.0000 r/w adcssop1 0x070 673 adc sample sequence 1 digital comparator select 0x0000.0000 r/w adcssdc1 0x074 669 adc sample sequence input multiplexer select 2 0x0000.0000 r/w adcssmux2 0x080 670 adc sample sequence control 2 0x0000.0000 r/w adcssctl2 0x084 662 adc sample sequence result fifo 2 - ro adcssfifo2 0x088 663 adc sample sequence fifo 2 status 0x0000.0100 ro adcssfstat2 0x08c 672 adc sample sequence 2 operation 0x0000.0000 r/w adcssop2 0x090 673 adc sample sequence 2 digital comparator select 0x0000.0000 r/w adcssdc2 0x094 675 adc sample sequence input multiplexer select 3 0x0000.0000 r/w adcssmux3 0x0a0 676 adc sample sequence control 3 0x0000.0002 r/w adcssctl3 0x0a4 662 adc sample sequence result fifo 3 - ro adcssfifo3 0x0a8 663 adc sample sequence fifo 3 status 0x0000.0100 ro adcssfstat3 0x0ac 677 adc sample sequence 3 operation 0x0000.0000 r/w adcssop3 0x0b0 678 adc sample sequence 3 digital comparator select 0x0000.0000 r/w adcssdc3 0x0b4 679 adc digital comparator reset initial conditions 0x0000.0000 r/w adcdcric 0xd00 629 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 12-5. adc register map (continued) see page description reset type name offset 684 adc digital comparator control 0 0x0000.0000 r/w adcdcctl0 0xe00 684 adc digital comparator control 1 0x0000.0000 r/w adcdcctl1 0xe04 684 adc digital comparator control 2 0x0000.0000 r/w adcdcctl2 0xe08 684 adc digital comparator control 3 0x0000.0000 r/w adcdcctl3 0xe0c 684 adc digital comparator control 4 0x0000.0000 r/w adcdcctl4 0xe10 684 adc digital comparator control 5 0x0000.0000 r/w adcdcctl5 0xe14 684 adc digital comparator control 6 0x0000.0000 r/w adcdcctl6 0xe18 684 adc digital comparator control 7 0x0000.0000 r/w adcdcctl7 0xe1c 687 adc digital comparator range 0 0x0000.0000 r/w adcdccmp0 0xe40 687 adc digital comparator range 1 0x0000.0000 r/w adcdccmp1 0xe44 687 adc digital comparator range 2 0x0000.0000 r/w adcdccmp2 0xe48 687 adc digital comparator range 3 0x0000.0000 r/w adcdccmp3 0xe4c 687 adc digital comparator range 4 0x0000.0000 r/w adcdccmp4 0xe50 687 adc digital comparator range 5 0x0000.0000 r/w adcdccmp5 0xe54 687 adc digital comparator range 6 0x0000.0000 r/w adcdccmp6 0xe58 687 adc digital comparator range 7 0x0000.0000 r/w adcdccmp7 0xe5c 12.6 register descriptions the remainder of this section lists and describes the adc registers, in numerical order by address offset. july 03, 2014 630 texas instruments-production data analog-to-digital converter (adc) register 1: adc active sample sequencer (adcactss), offset 0x000 this register controls the activation of the sample sequencers. each sample sequencer can be enabled or disabled independently. adc active sample sequencer (adcactss) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x000 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 asen0 asen1 asen2 asen3 reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:4 adc ss3 enable description value sample sequencer 3 is enabled. 1 sample sequencer 3 is disabled. 0 0 r/w asen3 3 adc ss2 enable description value sample sequencer 2 is enabled. 1 sample sequencer 2 is disabled. 0 0 r/w asen2 2 adc ss1 enable description value sample sequencer 1 is enabled. 1 sample sequencer 1 is disabled. 0 0 r/w asen1 1 adc ss0 enable description value sample sequencer 0 is enabled. 1 sample sequencer 0 is disabled. 0 0 r/w asen0 0 631 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 2: adc raw interrupt status (adcris), offset 0x004 this register shows the status of the raw interrupt signal of each sample sequencer. these bits may be polled by software to look for interrupt conditions without sending the interrupts to the interrupt controller. adc raw interrupt status (adcris) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x004 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 inrdc reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 inr0 inr1 inr2 inr3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 31:17 digital comparator raw interrupt status description value at least one bit in the adcdcisc register is set, meaning that a digital comparator interrupt has occurred. 1 all bits in the adcdcisc register are clear. 0 0 ro inrdc 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 15:4 ss3 raw interrupt status description value a sample has completed conversion and the respective adcssctl3 ien bit is set, enabling a raw interrupt. 1 an interrupt has not occurred. 0 this bit is cleared by writing a 1 to the in3 bit in the adcisc register. 0 ro inr3 3 ss2 raw interrupt status description value a sample has completed conversion and the respective adcssctl2 ien bit is set, enabling a raw interrupt. 1 an interrupt has not occurred. 0 this bit is cleared by writing a 1 to the in2 bit in the adcisc register. 0 ro inr2 2 july 03, 2014 632 texas instruments-production data analog-to-digital converter (adc) description reset type name bit/field ss1 raw interrupt status description value a sample has completed conversion and the respective adcssctl1 ien bit is set, enabling a raw interrupt. 1 an interrupt has not occurred. 0 this bit is cleared by writing a 1 to the in1 bit in the adcisc register. 0 ro inr1 1 ss0 raw interrupt status description value a sample has completed conversion and the respective adcssctl0 ien bit is set, enabling a raw interrupt. 1 an interrupt has not occurred. 0 this bit is cleared by writing a 1 to the in0 bit in the adcisc register. 0 ro inr0 0 633 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 3: adc interrupt mask (adcim), offset 0x008 this register controls whether the sample sequencer and digital comparator raw interrupt signals are sent to the interrupt controller. each raw interrupt signal can be masked independently. only a single dconssn bit should be set at any given time. setting more than one of these bits results in the inrdc bit from the adcris register being masked, and no interrupt is generated on any of the sample sequencer interrupt lines. adc interrupt mask (adcim) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x008 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 dconss0 dconss1 dconss2 dconss3 reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mask0 mask1 mask2 mask3 reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 31:20 digital comparator interrupt on ss3 description value the raw interrupt signal from the digital comparators ( inrdc bit in the adcris register) is sent to the interrupt controller on the ss3 interrupt line. 1 the status of the digital comparators does not affect the ss3 interrupt status. 0 0 r/w dconss3 19 digital comparator interrupt on ss2 description value the raw interrupt signal from the digital comparators ( inrdc bit in the adcris register) is sent to the interrupt controller on the ss2 interrupt line. 1 the status of the digital comparators does not affect the ss2 interrupt status. 0 0 r/w dconss2 18 digital comparator interrupt on ss1 description value the raw interrupt signal from the digital comparators ( inrdc bit in the adcris register) is sent to the interrupt controller on the ss1 interrupt line. 1 the status of the digital comparators does not affect the ss1 interrupt status. 0 0 r/w dconss1 17 july 03, 2014 634 texas instruments-production data analog-to-digital converter (adc) description reset type name bit/field digital comparator interrupt on ss0 description value the raw interrupt signal from the digital comparators ( inrdc bit in the adcris register) is sent to the interrupt controller on the ss0 interrupt line. 1 the status of the digital comparators does not affect the ss0 interrupt status. 0 0 r/w dconss0 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 15:4 ss3 interrupt mask description value the raw interrupt signal from sample sequencer 3 ( adcris register inr3 bit) is sent to the interrupt controller. 1 the status of sample sequencer 3 does not affect the ss3 interrupt status. 0 0 r/w mask3 3 ss2 interrupt mask description value the raw interrupt signal from sample sequencer 2 ( adcris register inr2 bit) is sent to the interrupt controller. 1 the status of sample sequencer 2 does not affect the ss2 interrupt status. 0 0 r/w mask2 2 ss1 interrupt mask description value the raw interrupt signal from sample sequencer 1 ( adcris register inr1 bit) is sent to the interrupt controller. 1 the status of sample sequencer 1 does not affect the ss1 interrupt status. 0 0 r/w mask1 1 ss0 interrupt mask description value the raw interrupt signal from sample sequencer 0 ( adcris register inr0 bit) is sent to the interrupt controller. 1 the status of sample sequencer 0 does not affect the ss0 interrupt status. 0 0 r/w mask0 0 635 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 4: adc interrupt status and clear (adcisc), offset 0x00c this register provides the mechanism for clearing sample sequencer interrupt conditions and shows the status of interrupts generated by the sample sequencers and the digital comparators which have been sent to the interrupt controller. when read, each bit field is the logical and of the respective inr and mask bits. sample sequencer interrupts are cleared by writing a 1 to the corresponding bit position. digital comparator interrupts are cleared by writing a 1 to the appropriate bits in the adcdcisc register. if software is polling the adcris instead of generating interrupts, the sample sequence inrn bits are still cleared via the adcisc register, even if the inn bit is not set. adc interrupt status and clear (adcisc) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x00c type r/w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 dcinss0 dcinss1 dcinss2 dcinss3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 in0 in1 in2 in3 reserved r/w1c r/w1c r/w1c r/w1c ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 31:20 digital comparator interrupt status on ss3 description value both the inrdc bit in the adcris register and the dconss3 bit in the adcim register are set, providing a level-based interrupt to the interrupt controller. 1 no interrupt has occurred or the interrupt is masked. 0 this bit is cleared by writing a 1 to it. clearing this bit also clears the inrdc bit in the adcris register. 0 ro dcinss3 19 digital comparator interrupt status on ss2 description value both the inrdc bit in the adcris register and the dconss2 bit in the adcim register are set, providing a level-based interrupt to the interrupt controller. 1 no interrupt has occurred or the interrupt is masked. 0 this bit is cleared by writing a 1 to it. clearing this bit also clears the inrdc bit in the adcris register. 0 ro dcinss2 18 july 03, 2014 636 texas instruments-production data analog-to-digital converter (adc) description reset type name bit/field digital comparator interrupt status on ss1 description value both the inrdc bit in the adcris register and the dconss1 bit in the adcim register are set, providing a level-based interrupt to the interrupt controller. 1 no interrupt has occurred or the interrupt is masked. 0 this bit is cleared by writing a 1 to it. clearing this bit also clears the inrdc bit in the adcris register. 0 ro dcinss1 17 digital comparator interrupt status on ss0 description value both the inrdc bit in the adcris register and the dconss0 bit in the adcim register are set, providing a level-based interrupt to the interrupt controller. 1 no interrupt has occurred or the interrupt is masked. 0 this bit is cleared by writing a 1 to it. clearing this bit also clears the inrdc bit in the adcris register. 0 ro dcinss0 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 15:4 ss3 interrupt status and clear description value both the inr3 bit in the adcris register and the mask3 bit in the adcim register are set, providing a level-based interrupt to the interrupt controller. 1 no interrupt has occurred or the interrupt is masked. 0 this bit is cleared by writing a 1. clearing this bit also clears the inr3 bit in the adcris register. 0 r/w1c in3 3 ss2 interrupt status and clear description value both the inr2 bit in the adcris register and the mask2 bit in the adcim register are set, providing a level-based interrupt to the interrupt controller. 1 no interrupt has occurred or the interrupt is masked. 0 this bit is cleared by writing a 1. clearing this bit also clears the inr2 bit in the adcris register. 0 r/w1c in2 2 637 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field ss1 interrupt status and clear description value both the inr1 bit in the adcris register and the mask1 bit in the adcim register are set, providing a level-based interrupt to the interrupt controller. 1 no interrupt has occurred or the interrupt is masked. 0 this bit is cleared by writing a 1. clearing this bit also clears the inr1 bit in the adcris register. 0 r/w1c in1 1 ss0 interrupt status and clear description value both the inr0 bit in the adcris register and the mask0 bit in the adcim register are set, providing a level-based interrupt to the interrupt controller. 1 no interrupt has occurred or the interrupt is masked. 0 this bit is cleared by writing a 1. clearing this bit also clears the inr0 bit in the adcris register. 0 r/w1c in0 0 july 03, 2014 638 texas instruments-production data analog-to-digital converter (adc) register 5: adc overflow status (adcostat), offset 0x010 this register indicates overflow conditions in the sample sequencer fifos. once the overflow condition has been handled by software, the condition can be cleared by writing a 1 to the corresponding bit position. adc overflow status (adcostat) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x010 type r/w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ov0 ov1 ov2 ov3 reserved r/w1c r/w1c r/w1c r/w1c ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:4 ss3 fifo overflow description value the fifo for sample sequencer 3 has hit an overflow condition, meaning that the fifo is full and a write was requested. when an overflow is detected, the most recent write is dropped. 1 the fifo has not overflowed. 0 this bit is cleared by writing a 1. 0 r/w1c ov3 3 ss2 fifo overflow description value the fifo for sample sequencer 2 has hit an overflow condition, meaning that the fifo is full and a write was requested. when an overflow is detected, the most recent write is dropped. 1 the fifo has not overflowed. 0 this bit is cleared by writing a 1. 0 r/w1c ov2 2 ss1 fifo overflow description value the fifo for sample sequencer 1 has hit an overflow condition, meaning that the fifo is full and a write was requested. when an overflow is detected, the most recent write is dropped. 1 the fifo has not overflowed. 0 this bit is cleared by writing a 1. 0 r/w1c ov1 1 639 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field ss0 fifo overflow description value the fifo for sample sequencer 0 has hit an overflow condition, meaning that the fifo is full and a write was requested. when an overflow is detected, the most recent write is dropped. 1 the fifo has not overflowed. 0 this bit is cleared by writing a 1. 0 r/w1c ov0 0 july 03, 2014 640 texas instruments-production data analog-to-digital converter (adc) register 6: adc event multiplexer select (adcemux), offset 0x014 the adcemux selects the event (trigger) that initiates sampling for each sample sequencer. each sample sequencer can be configured with a unique trigger source. adc event multiplexer select (adcemux) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x014 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 em0 em1 em2 em3 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 641 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field ss3 trigger select this field selects the trigger source for sample sequencer 3. the valid configurations for this field are: event value processor (default) the trigger is initiated by setting the ssn bit in the adcpssi register. 0x0 analog comparator 0 this trigger is configured by the analog comparator control 0 (acctl0) register (page 1108). 0x1 analog comparator 1 this trigger is configured by the analog comparator control 1 (acctl1) register (page 1108). 0x2 analog comparator 2 this trigger is configured by the analog comparator control 2 (acctl2) register (page 1108). 0x3 external (gpio pb4) this trigger is connected to the gpio interrupt for pb4 (see adc trigger source on page 414). 0x4 note: pb4 can be used to trigger the adc. however, the pb4/ ain10 pin cannot be used as both a gpio and an analog input. timer in addition, the trigger must be enabled with the tnote bit in the gptmctl register (page 558). 0x5 pwm0 the pwm generator 0 trigger can be configured with the pwm0 interrupt and trigger enable (pwm0inten) register (page 1156). 0x6 pwm1 the pwm generator 1 trigger can be configured with the pwm1inten register (page 1156). 0x7 pwm2 the pwm generator 2 trigger can be configured with the pwm2inten register (page 1156). 0x8 pwm3 the pwm generator 3 trigger can be configured with the pwm3inten register (page 1156). 0x9 reserved 0xa-0xe always (continuously sample) 0xf 0x0 r/w em3 15:12 july 03, 2014 642 texas instruments-production data analog-to-digital converter (adc) description reset type name bit/field ss2 trigger select this field selects the trigger source for sample sequencer 2. the valid configurations for this field are: event value processor (default) the trigger is initiated by setting the ssn bit in the adcpssi register. 0x0 analog comparator 0 this trigger is configured by the analog comparator control 0 (acctl0) register (page 1108). 0x1 analog comparator 1 this trigger is configured by the analog comparator control 1 (acctl1) register (page 1108). 0x2 analog comparator 2 this trigger is configured by the analog comparator control 2 (acctl2) register (page 1108). 0x3 external (gpio pb4) this trigger is connected to the gpio interrupt for pb4 (see adc trigger source on page 414). 0x4 note: pb4 can be used to trigger the adc. however, the pb4/ ain10 pin cannot be used as both a gpio and an analog input. timer in addition, the trigger must be enabled with the tnote bit in the gptmctl register (page 558). 0x5 pwm0 the pwm generator 0 trigger can be configured with the pwm0 interrupt and trigger enable (pwm0inten) register (page 1156). 0x6 pwm1 the pwm generator 1 trigger can be configured with the pwm1inten register (page 1156). 0x7 pwm2 the pwm generator 2 trigger can be configured with the pwm2inten register (page 1156). 0x8 pwm3 the pwm generator 3 trigger can be configured with the pwm3inten register (page 1156). 0x9 reserved 0xa-0xe always (continuously sample) 0xf 0x0 r/w em2 11:8 643 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field ss1 trigger select this field selects the trigger source for sample sequencer 1. the valid configurations for this field are: event value processor (default) the trigger is initiated by setting the ssn bit in the adcpssi register. 0x0 analog comparator 0 this trigger is configured by the analog comparator control 0 (acctl0) register (page 1108). 0x1 analog comparator 1 this trigger is configured by the analog comparator control 1 (acctl1) register (page 1108). 0x2 analog comparator 2 this trigger is configured by the analog comparator control 2 (acctl2) register (page 1108). 0x3 external (gpio pb4) this trigger is connected to the gpio interrupt for pb4 (see adc trigger source on page 414). 0x4 note: pb4 can be used to trigger the adc. however, the pb4/ ain10 pin cannot be used as both a gpio and an analog input. timer in addition, the trigger must be enabled with the tnote bit in the gptmctl register (page 558). 0x5 pwm0 the pwm generator 0 trigger can be configured with the pwm0 interrupt and trigger enable (pwm0inten) register (page 1156). 0x6 pwm1 the pwm generator 1 trigger can be configured with the pwm1inten register (page 1156). 0x7 pwm2 the pwm generator 2 trigger can be configured with the pwm2inten register (page 1156). 0x8 pwm3 the pwm generator 3 trigger can be configured with the pwm3inten register (page 1156). 0x9 reserved 0xa-0xe always (continuously sample) 0xf 0x0 r/w em1 7:4 july 03, 2014 644 texas instruments-production data analog-to-digital converter (adc) description reset type name bit/field ss0 trigger select this field selects the trigger source for sample sequencer 0 the valid configurations for this field are: event value processor (default) the trigger is initiated by setting the ssn bit in the adcpssi register. 0x0 analog comparator 0 this trigger is configured by the analog comparator control 0 (acctl0) register (page 1108). 0x1 analog comparator 1 this trigger is configured by the analog comparator control 1 (acctl1) register (page 1108). 0x2 analog comparator 2 this trigger is configured by the analog comparator control 2 (acctl2) register (page 1108). 0x3 external (gpio pb4) this trigger is connected to the gpio interrupt for pb4 (see adc trigger source on page 414). 0x4 note: pb4 can be used to trigger the adc. however, the pb4/ ain10 pin cannot be used as both a gpio and an analog input. timer in addition, the trigger must be enabled with the tnote bit in the gptmctl register (page 558). 0x5 pwm0 the pwm generator 0 trigger can be configured with the pwm0 interrupt and trigger enable (pwm0inten) register (page 1156). 0x6 pwm1 the pwm generator 1 trigger can be configured with the pwm1inten register (page 1156). 0x7 pwm2 the pwm generator 2 trigger can be configured with the pwm2inten register (page 1156). 0x8 pwm3 the pwm generator 3 trigger can be configured with the pwm3inten register (page 1156). 0x9 reserved 0xa-0xe always (continuously sample) 0xf 0x0 r/w em0 3:0 645 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 7: adc underflow status (adcustat), offset 0x018 this register indicates underflow conditions in the sample sequencer fifos. the corresponding underflow condition is cleared by writing a 1 to the relevant bit position. adc underflow status (adcustat) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x018 type r/w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 uv0 uv1 uv2 uv3 reserved r/w1c r/w1c r/w1c r/w1c ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:4 ss3 fifo underflow the valid configurations for this field are shown below. this bit is cleared by writing a 1. description value the fifo for the sample sequencer has hit an underflow condition, meaning that the fifo is empty and a read was requested. the problematic read does not move the fifo pointers, and 0s are returned. 1 the fifo has not underflowed. 0 0 r/w1c uv3 3 ss2 fifo underflow the valid configurations are the same as those for the uv3 field. this bit is cleared by writing a 1. 0 r/w1c uv2 2 ss1 fifo underflow the valid configurations are the same as those for the uv3 field. this bit is cleared by writing a 1. 0 r/w1c uv1 1 ss0 fifo underflow the valid configurations are the same as those for the uv3 field. this bit is cleared by writing a 1. 0 r/w1c uv0 0 july 03, 2014 646 texas instruments-production data analog-to-digital converter (adc) register 8: adc sample sequencer priority (adcsspri), offset 0x020 this register sets the priority for each of the sample sequencers. out of reset, sequencer 0 has the highest priority, and sequencer 3 has the lowest priority. when reconfiguring sequence priorities, each sequence must have a unique priority for the adc to operate properly. adc sample sequencer priority (adcsspri) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x020 type r/w, reset 0x0000.3210 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ss0 reserved ss1 reserved ss2 reserved ss3 reserved r/w r/w ro ro r/w r/w ro ro r/w r/w ro ro r/w r/w ro ro type 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0 ro reserved 31:14 ss3 priority this field contains a binary-encoded value that specifies the priority encoding of sample sequencer 3. a priority encoding of 0x0 is highest and 0x3 is lowest. the priorities assigned to the sequencers must be uniquely mapped. the adc may not operate properly if two or more fields are equal. 0x3 r/w ss3 13:12 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 11:10 ss2 priority this field contains a binary-encoded value that specifies the priority encoding of sample sequencer 2. a priority encoding of 0x0 is highest and 0x3 is lowest. the priorities assigned to the sequencers must be uniquely mapped. the adc may not operate properly if two or more fields are equal. 0x2 r/w ss2 9:8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 7:6 ss1 priority this field contains a binary-encoded value that specifies the priority encoding of sample sequencer 1. a priority encoding of 0x0 is highest and 0x3 is lowest. the priorities assigned to the sequencers must be uniquely mapped. the adc may not operate properly if two or more fields are equal. 0x1 r/w ss1 5:4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 3:2 647 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field ss0 priority this field contains a binary-encoded value that specifies the priority encoding of sample sequencer 0. a priority encoding of 0x0 is highest and 0x3 is lowest. the priorities assigned to the sequencers must be uniquely mapped. the adc may not operate properly if two or more fields are equal. 0x0 r/w ss0 1:0 july 03, 2014 648 texas instruments-production data analog-to-digital converter (adc) register 9: adc sample phase control (adcspc), offset 0x024 this register allows the adc module to sample at one of 16 different discrete phases from 0.0 through 337.5. for example, the sample rate could be effectively doubled by sampling a signal using one adc module configured with the standard sample time and the second adc module configured with a 180.0 phase lag. note: care should be taken when the phase field is non-zero, as the resulting delay in sampling the ainx input may result in undesirable system consequences. the time from adc trigger to sample is increased and could make the response time longer than anticipated. the added latency could have ramifications in the system design. designers should carefully consider the impact of this delay. adc sample phase control (adcspc) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x024 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 phase reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:4 649 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field phase difference this field selects the sample phase difference from the standard sample time. description value adc sample lags by 0.0 0x0 adc sample lags by 22.5 0x1 adc sample lags by 45.0 0x2 adc sample lags by 67.5 0x3 adc sample lags by 90.0 0x4 adc sample lags by 112.5 0x5 adc sample lags by 135.0 0x6 adc sample lags by 157.5 0x7 adc sample lags by 180.0 0x8 adc sample lags by 202.5 0x9 adc sample lags by 225.0 0xa adc sample lags by 247.5 0xb adc sample lags by 270.0 0xc adc sample lags by 292.5 0xd adc sample lags by 315.0 0xe adc sample lags by 337.5 0xf 0x0 r/w phase 3:0 july 03, 2014 650 texas instruments-production data analog-to-digital converter (adc) register 10: adc processor sample sequence initiate (adcpssi), offset 0x028 this register provides a mechanism for application software to initiate sampling in the sample sequencers. sample sequences can be initiated individually or in any combination. when multiple sequences are triggered simultaneously, the priority encodings in adcsspri dictate execution order. this register also provides a means to configure and then initiate concurrent sampling on all adc modules. to do this, the first adc module should be configured. the adcpssi register for that module should then be written. the appropriate ss bits should be set along with the syncwait bit. additional adc modules should then be configured following the same procedure. once the final adc module is configured, its adcpssi register should be written with the appropriate ss bits set along with the gsync bit. all of the adc modules then begin concurrent sampling according to their configuration. adc processor sample sequence initiate (adcpssi) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x028 type r/w, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved syncwait reserved gsync ro ro ro ro ro ro ro ro ro ro ro r/w ro ro ro r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ss0 ss1 ss2 ss3 reserved wo wo wo wo ro ro ro ro ro ro ro ro ro ro ro ro type - - - - 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field global synchronize description value this bit initiates sampling in multiple adc modules at the same time. any adc module that has been initialized by setting an ssn bit and the syncwait bit starts sampling once this bit is written. 1 this bit is cleared once sampling has been initiated. 0 0 r/w gsync 31 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 30:28 synchronize wait description value this bit allows the sample sequences to be initiated, but delays sampling until the gsync bit is set. 1 sampling begins when a sample sequence has been initiated. 0 0 r/w syncwait 27 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0 ro reserved 26:4 651 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field ss3 initiate description value begin sampling on sample sequencer 3, if the sequencer is enabled in the adcactss register. 1 no effect. 0 only a write by software is valid; a read of this register returns no meaningful data. - wo ss3 3 ss2 initiate description value begin sampling on sample sequencer 2, if the sequencer is enabled in the adcactss register. 1 no effect. 0 only a write by software is valid; a read of this register returns no meaningful data. - wo ss2 2 ss1 initiate description value begin sampling on sample sequencer 1, if the sequencer is enabled in the adcactss register. 1 no effect. 0 only a write by software is valid; a read of this register returns no meaningful data. - wo ss1 1 ss0 initiate description value begin sampling on sample sequencer 0, if the sequencer is enabled in the adcactss register. 1 no effect. 0 only a write by software is valid; a read of this register returns no meaningful data. - wo ss0 0 july 03, 2014 652 texas instruments-production data analog-to-digital converter (adc) register 11: adc sample averaging control (adcsac), offset 0x030 this register controls the amount of hardware averaging applied to conversion results. the final conversion result stored in the fifo is averaged from 2 avg consecutive adc samples at the specified adc speed. if avg is 0, the sample is passed directly through without any averaging. if avg=6, then 64 consecutive adc samples are averaged to generate one result in the sequencer fifo. an avg=7 provides unpredictable results. adc sample averaging control (adcsac) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x030 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 avg reserved r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:3 hardware averaging control specifies the amount of hardware averaging that will be applied to adc samples. the avg field can be any value between 0 and 6. entering a value of 7 creates unpredictable results. description value no hardware oversampling 0x0 2x hardware oversampling 0x1 4x hardware oversampling 0x2 8x hardware oversampling 0x3 16x hardware oversampling 0x4 32x hardware oversampling 0x5 64x hardware oversampling 0x6 reserved 0x7 0x0 r/w avg 2:0 653 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 12: adc digital comparator interrupt status and clear (adcdcisc), offset 0x034 this register provides status and acknowledgement of digital comparator interrupts. one bit is provided for each comparator. adc digital comparator interrupt status and clear (adcdcisc) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x034 type r/w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dcint0 dcint1 dcint2 dcint3 dcint4 dcint5 dcint6 dcint7 reserved r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 digital comparator 7 interrupt status and clear description value digital comparator 7 has generated an interrupt. 1 no interrupt. 0 this bit is cleared by writing a 1. 0 r/w1c dcint7 7 digital comparator 6 interrupt status and clear description value digital comparator 6 has generated an interrupt. 1 no interrupt. 0 this bit is cleared by writing a 1. 0 r/w1c dcint6 6 digital comparator 5 interrupt status and clear description value digital comparator 5 has generated an interrupt. 1 no interrupt. 0 this bit is cleared by writing a 1. 0 r/w1c dcint5 5 july 03, 2014 654 texas instruments-production data analog-to-digital converter (adc) description reset type name bit/field digital comparator 4 interrupt status and clear description value digital comparator 4 has generated an interrupt. 1 no interrupt. 0 this bit is cleared by writing a 1. 0 r/w1c dcint4 4 digital comparator 3 interrupt status and clear description value digital comparator 3 has generated an interrupt. 1 no interrupt. 0 this bit is cleared by writing a 1. 0 r/w1c dcint3 3 digital comparator 2 interrupt status and clear description value digital comparator 2 has generated an interrupt. 1 no interrupt. 0 this bit is cleared by writing a 1. 0 r/w1c dcint2 2 digital comparator 1 interrupt status and clear description value digital comparator 1 has generated an interrupt. 1 no interrupt. 0 this bit is cleared by writing a 1. 0 r/w1c dcint1 1 digital comparator 0 interrupt status and clear description value digital comparator 0 has generated an interrupt. 1 no interrupt. 0 this bit is cleared by writing a 1. 0 r/w1c dcint0 0 655 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 13: adc control (adcctl), offset 0x038 this register configures various adc module attributes, including the adc resolution and the voltage reference. the resolution of the adc defaults to 10-bit for backwards compatibility with other members of the stellaris family, but can be configured to 12-bit resolution. the voltage reference for the conversion can be the internal 3.0-v reference, an external voltage reference in the range of 2.4 v to 3.06 v, or an external voltage reference in the range of 0.8 v to 1.02 v. adc control (adcctl) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x038 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 vref reserved res reserved r/w r/w ro ro r/w ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:5 sample resolution description value the adc returns 12-bit data to the fifos. 1 the adc returns 10-bit data to the fifos. 0 0 r/w res 4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 3:2 voltage reference select description value internal reference the internal reference as the voltage reference. the conversion range is from 0 v to 3.0 v. 0x0 3.0 v external reference a 3.0 v external vrefa input is the voltage reference. the adc conversion range is 0.0 v to the voltage of the vrefa input. 0x1 reserved 0x2 1.0 v external reference a 1.0 v external vrefa input is the voltage reference. the adc conversion range is 0.0 v to three times the voltage of the vrefa input. 0x3 0x0 r/w vref 1:0 july 03, 2014 656 texas instruments-production data analog-to-digital converter (adc) register 14: adc sample sequence input multiplexer select 0 (adcssmux0), offset 0x040 this register defines the analog input configuration for each sample in a sequence executed with sample sequencer 0. this register is 32 bits wide and contains information for eight possible samples. adc sample sequence input multiplexer select 0 (adcssmux0) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x040 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 mux4 mux5 mux6 mux7 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mux0 mux1 mux2 mux3 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field 8th sample input select the mux7 field is used during the eighth sample of a sequence executed with the sample sequencer. it specifies which of the analog inputs is sampled for the analog-to-digital conversion. the value set here indicates the corresponding pin, for example, a value of 0x1 indicates the input is ain1. 0x0 r/w mux7 31:28 7th sample input select the mux6 field is used during the seventh sample of a sequence executed with the sample sequencer. it specifies which of the analog inputs is sampled for the analog-to-digital conversion. 0x0 r/w mux6 27:24 6th sample input select the mux5 field is used during the sixth sample of a sequence executed with the sample sequencer. it specifies which of the analog inputs is sampled for the analog-to-digital conversion. 0x0 r/w mux5 23:20 5th sample input select the mux4 field is used during the fifth sample of a sequence executed with the sample sequencer. it specifies which of the analog inputs is sampled for the analog-to-digital conversion. 0x0 r/w mux4 19:16 4th sample input select the mux3 field is used during the fourth sample of a sequence executed with the sample sequencer. it specifies which of the analog inputs is sampled for the analog-to-digital conversion. 0x0 r/w mux3 15:12 3rd sample input select the mux2 field is used during the third sample of a sequence executed with the sample sequencer. it specifies which of the analog inputs is sampled for the analog-to-digital conversion. 0x0 r/w mux2 11:8 657 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field 2nd sample input select the mux1 field is used during the second sample of a sequence executed with the sample sequencer. it specifies which of the analog inputs is sampled for the analog-to-digital conversion. 0x0 r/w mux1 7:4 1st sample input select the mux0 field is used during the first sample of a sequence executed with the sample sequencer. it specifies which of the analog inputs is sampled for the analog-to-digital conversion. 0x0 r/w mux0 3:0 july 03, 2014 658 texas instruments-production data analog-to-digital converter (adc) register 15: adc sample sequence control 0 (adcssctl0), offset 0x044 this register contains the configuration information for each sample for a sequence executed with a sample sequencer. when configuring a sample sequence, the end bit must be set for the final sample, whether it be after the first sample, eighth sample, or any sample in between. this register is 32 bits wide and contains information for eight possible samples. adc sample sequence control 0 (adcssctl0) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x044 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 d4 end4 ie4 ts4 d5 end5 ie5 ts5 d6 end6 ie6 ts6 d7 end7 ie7 ts7 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 d0 end0 ie0 ts0 d1 end1 ie1 ts1 d2 end2 ie2 ts2 d3 end3 ie3 ts3 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field 8th sample temp sensor select description value the temperature sensor is read during the eighth sample of the sample sequence. 1 the input pin specified by the adcssmuxn register is read during the eighth sample of the sample sequence. 0 0 r/w ts7 31 8th sample interrupt enable description value the raw interrupt signal ( inr0 bit) is asserted at the end of the eighth sample's conversion. if the mask0 bit in the adcim register is set, the interrupt is promoted to the interrupt controller. 1 the raw interrupt is not asserted to the interrupt controller. 0 it is legal to have multiple samples within a sequence generate interrupts. 0 r/w ie7 30 8th sample is end of sequence description value the eighth sample is the last sample of the sequence. 1 another sample in the sequence is the final sample. 0 it is possible to end the sequence on any sample position. software must set an endn bit somewhere within the sequence. samples defined after the sample containing a set endn bit are not requested for conversion even though the fields may be non-zero. 0 r/w end7 29 659 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field 8th sample diff input select description value the analog input is differentially sampled. the corresponding adcssmuxn nibble must be set to the pair number "i", where the paired inputs are "2i and 2i+1". 1 the analog inputs are not differentially sampled. 0 because the temperature sensor does not have a differential option, this bit must not be set when the ts7 bit is set. 0 r/w d7 28 7th sample temp sensor select same definition as ts7 but used during the seventh sample. 0 r/w ts6 27 7th sample interrupt enable same definition as ie7 but used during the seventh sample. 0 r/w ie6 26 7th sample is end of sequence same definition as end7 but used during the seventh sample. 0 r/w end6 25 7th sample diff input select same definition as d7 but used during the seventh sample. 0 r/w d6 24 6th sample temp sensor select same definition as ts7 but used during the sixth sample. 0 r/w ts5 23 6th sample interrupt enable same definition as ie7 but used during the sixth sample. 0 r/w ie5 22 6th sample is end of sequence same definition as end7 but used during the sixth sample. 0 r/w end5 21 6th sample diff input select same definition as d7 but used during the sixth sample. 0 r/w d5 20 5th sample temp sensor select same definition as ts7 but used during the fifth sample. 0 r/w ts4 19 5th sample interrupt enable same definition as ie7 but used during the fifth sample. 0 r/w ie4 18 5th sample is end of sequence same definition as end7 but used during the fifth sample. 0 r/w end4 17 5th sample diff input select same definition as d7 but used during the fifth sample. 0 r/w d4 16 4th sample temp sensor select same definition as ts7 but used during the fourth sample. 0 r/w ts3 15 4th sample interrupt enable same definition as ie7 but used during the fourth sample. 0 r/w ie3 14 july 03, 2014 660 texas instruments-production data analog-to-digital converter (adc) description reset type name bit/field 4th sample is end of sequence same definition as end7 but used during the fourth sample. 0 r/w end3 13 4th sample diff input select same definition as d7 but used during the fourth sample. 0 r/w d3 12 3rd sample temp sensor select same definition as ts7 but used during the third sample. 0 r/w ts2 11 3rd sample interrupt enable same definition as ie7 but used during the third sample. 0 r/w ie2 10 3rd sample is end of sequence same definition as end7 but used during the third sample. 0 r/w end2 9 3rd sample diff input select same definition as d7 but used during the third sample. 0 r/w d2 8 2nd sample temp sensor select same definition as ts7 but used during the second sample. 0 r/w ts1 7 2nd sample interrupt enable same definition as ie7 but used during the second sample. 0 r/w ie1 6 2nd sample is end of sequence same definition as end7 but used during the second sample. 0 r/w end1 5 2nd sample diff input select same definition as d7 but used during the second sample. 0 r/w d1 4 1st sample temp sensor select same definition as ts7 but used during the first sample. 0 r/w ts0 3 1st sample interrupt enable same definition as ie7 but used during the first sample. 0 r/w ie0 2 1st sample is end of sequence same definition as end7 but used during the first sample. 0 r/w end0 1 1st sample diff input select same definition as d7 but used during the first sample. 0 r/w d0 0 661 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 16: adc sample sequence result fifo 0 (adcssfifo0), offset 0x048 register 17: adc sample sequence result fifo 1 (adcssfifo1), offset 0x068 register 18: adc sample sequence result fifo 2 (adcssfifo2), offset 0x088 register 19: adc sample sequence result fifo 3 (adcssfifo3), offset 0x0a8 important: this register is read-sensitive. see the register description for details. this register contains the conversion results for samples collected with the sample sequencer (the adcssfifo0 register is used for sample sequencer 0, adcssfifo1 for sequencer 1, adcssfifo2 for sequencer 2, and adcssfifo3 for sequencer 3). reads of this register return conversion result data in the order sample 0, sample 1, and so on, until the fifo is empty. if the fifo is not properly handled by software, overflow and underflow conditions are registered in the adcostat and adcustat registers. adc sample sequence result fifo n (adcssfifon) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x048 type ro, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 data reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type - - - - - - - - - - - - 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0 ro reserved 31:12 conversion result data - ro data 11:0 july 03, 2014 662 texas instruments-production data analog-to-digital converter (adc) register 20: adc sample sequence fifo 0 status (adcssfstat0), offset 0x04c register 21: adc sample sequence fifo 1 status (adcssfstat1), offset 0x06c register 22: adc sample sequence fifo 2 status (adcssfstat2), offset 0x08c register 23: adc sample sequence fifo 3 status (adcssfstat3), offset 0x0ac this register provides a window into the sample sequencer, providing full/empty status information as well as the positions of the head and tail pointers. the reset value of 0x100 indicates an empty fifo with the head and tail pointers both pointing to index 0. the adcssfstat0 register provides status on fifo0, which has 8 entries; adcssfstat1 on fifo1, which has 4 entries; adcssfstat2 on fifo2, which has 4 entries; and adcssfstat3 on fifo3 which has a single entry. adc sample sequence fifo 0 status (adcssfstat0) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x04c type ro, reset 0x0000.0100 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tptr hptr empty reserved full reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0 ro reserved 31:13 fifo full description value the fifo is currently full. 1 the fifo is not currently full. 0 0 ro full 12 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 11:9 fifo empty description value the fifo is currently empty. 1 the fifo is not currently empty. 0 1 ro empty 8 663 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field fifo head pointer this field contains the current "head" pointer index for the fifo, that is, the next entry to be written. valid values are 0x0-0x7 for fifo0; 0x0-0x3 for fifo1 and fifo2; and 0x0 for fifo3. 0x0 ro hptr 7:4 fifo tail pointer this field contains the current "tail" pointer index for the fifo, that is, the next entry to be read. valid values are 0x0-0x7 for fifo0; 0x0-0x3 for fifo1 and fifo2; and 0x0 for fifo3. 0x0 ro tptr 3:0 july 03, 2014 664 texas instruments-production data analog-to-digital converter (adc) register 24: adc sample sequence 0 operation (adcssop0), offset 0x050 this register determines whether the sample from the given conversion on sample sequence 0 is saved in the sample sequence fifo0 or sent to the digital comparator unit. adc sample sequence 0 operation (adcssop0) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x050 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 s4dcop reserved s5dcop reserved s6dcop reserved s7dcop reserved r/w ro ro ro r/w ro ro ro r/w ro ro ro r/w ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 s0dcop reserved s1dcop reserved s2dcop reserved s3dcop reserved r/w ro ro ro r/w ro ro ro r/w ro ro ro r/w ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 31:29 sample 7 digital comparator operation description value the eighth sample is sent to the digital comparator unit specified by the s7dcsel bit in the adcssdc0 register, and the value is not written to the fifo. 1 the eighth sample is saved in sample sequence fifo0. 0 0 r/w s7dcop 28 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 27:25 sample 6 digital comparator operation same definition as s7dcop but used during the seventh sample. 0 r/w s6dcop 24 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 23:21 sample 5 digital comparator operation same definition as s7dcop but used during the sixth sample. 0 r/w s5dcop 20 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 19:17 sample 4 digital comparator operation same definition as s7dcop but used during the fifth sample. 0 r/w s4dcop 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 15:13 665 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field sample 3 digital comparator operation same definition as s7dcop but used during the fourth sample. 0 r/w s3dcop 12 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 11:9 sample 2 digital comparator operation same definition as s7dcop but used during the third sample. 0 r/w s2dcop 8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 7:5 sample 1 digital comparator operation same definition as s7dcop but used during the second sample. 0 r/w s1dcop 4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 3:1 sample 0 digital comparator operation same definition as s7dcop but used during the first sample. 0 r/w s0dcop 0 july 03, 2014 666 texas instruments-production data analog-to-digital converter (adc) register 25: adc sample sequence 0 digital comparator select (adcssdc0), offset 0x054 this register determines which digital comparator receives the sample from the given conversion on sample sequence 0, if the corresponding sndcop bit in the adcssop0 register is set. adc sample sequence 0 digital comparator select (adcssdc0) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x054 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 s4dcsel s5dcsel s6dcsel s7dcsel r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 s0dcsel s1dcsel s2dcsel s3dcsel r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field sample 7 digital comparator select when the s7dcop bit in the adcssop0 register is set, this field indicates which digital comparator unit (and its associated set of control registers) receives the eighth sample from sample sequencer 0. note: values not listed are reserved. description value digital comparator unit 0 ( adcdccmp0 and adcdcctl0 ) 0x0 digital comparator unit 1 ( adcdccmp1 and adcdcctl1 ) 0x1 digital comparator unit 2 ( adcdccmp2 and adcdcctl2 ) 0x2 digital comparator unit 3 ( adcdccmp3 and adcdcctl3 ) 0x3 digital comparator unit 4 ( adcdccmp4 and adcdcctl4 ) 0x4 digital comparator unit 5 ( adcdccmp5 and adcdcctl5 ) 0x5 digital comparator unit 6 ( adcdccmp6 and adcdcctl6 ) 0x6 digital comparator unit 7 ( adcdccmp7 and adcdcctl7 ) 0x7 0x0 r/w s7dcsel 31:28 sample 6 digital comparator select this field has the same encodings as s7dcsel but is used during the seventh sample. 0x0 r/w s6dcsel 27:24 sample 5 digital comparator select this field has the same encodings as s7dcsel but is used during the sixth sample. 0x0 r/w s5dcsel 23:20 sample 4 digital comparator select this field has the same encodings as s7dcsel but is used during the fifth sample. 0x0 r/w s4dcsel 19:16 sample 3 digital comparator select this field has the same encodings as s7dcsel but is used during the fourth sample. 0x0 r/w s3dcsel 15:12 667 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field sample 2 digital comparator select this field has the same encodings as s7dcsel but is used during the third sample. 0x0 r/w s2dcsel 11:8 sample 1 digital comparator select this field has the same encodings as s7dcsel but is used during the second sample. 0x0 r/w s1dcsel 7:4 sample 0 digital comparator select this field has the same encodings as s7dcsel but is used during the first sample. 0x0 r/w s0dcsel 3:0 july 03, 2014 668 texas instruments-production data analog-to-digital converter (adc) register 26: adc sample sequence input multiplexer select 1 (adcssmux1), offset 0x060 register 27: adc sample sequence input multiplexer select 2 (adcssmux2), offset 0x080 this register defines the analog input configuration for each sample in a sequence executed with sample sequencer 1 or 2. these registers are 16 bits wide and contain information for four possible samples. see the adcssmux0 register on page 657 for detailed bit descriptions. the adcssmux1 register affects sample sequencer 1 and the adcssmux2 register affects sample sequencer 2. adc sample sequence input multiplexer select 1 (adcssmux1) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x060 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mux0 mux1 mux2 mux3 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 4th sample input select 0x0 r/w mux3 15:12 3rd sample input select 0x0 r/w mux2 11:8 2nd sample input select 0x0 r/w mux1 7:4 1st sample input select 0x0 r/w mux0 3:0 669 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 28: adc sample sequence control 1 (adcssctl1), offset 0x064 register 29: adc sample sequence control 2 (adcssctl2), offset 0x084 these registers contain the configuration information for each sample for a sequence executed with sample sequencer 1 or 2. when configuring a sample sequence, the end bit must be set for the final sample, whether it be after the first sample, fourth sample, or any sample in between. these registers are 16-bits wide and contain information for four possible samples. see the adcssctl0 register on page 659 for detailed bit descriptions. the adcssctl1 register configures sample sequencer 1 and the adcssctl2 register configures sample sequencer 2. adc sample sequence control 1 (adcssctl1) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x064 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 d0 end0 ie0 ts0 d1 end1 ie1 ts1 d2 end2 ie2 ts2 d3 end3 ie3 ts3 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 4th sample temp sensor select same definition as ts7 but used during the fourth sample. 0 r/w ts3 15 4th sample interrupt enable same definition as ie7 but used during the fourth sample. 0 r/w ie3 14 4th sample is end of sequence same definition as end7 but used during the fourth sample. 0 r/w end3 13 4th sample diff input select same definition as d7 but used during the fourth sample. 0 r/w d3 12 3rd sample temp sensor select same definition as ts7 but used during the third sample. 0 r/w ts2 11 3rd sample interrupt enable same definition as ie7 but used during the third sample. 0 r/w ie2 10 3rd sample is end of sequence same definition as end7 but used during the third sample. 0 r/w end2 9 3rd sample diff input select same definition as d7 but used during the third sample. 0 r/w d2 8 july 03, 2014 670 texas instruments-production data analog-to-digital converter (adc) description reset type name bit/field 2nd sample temp sensor select same definition as ts7 but used during the second sample. 0 r/w ts1 7 2nd sample interrupt enable same definition as ie7 but used during the second sample. 0 r/w ie1 6 2nd sample is end of sequence same definition as end7 but used during the second sample. 0 r/w end1 5 2nd sample diff input select same definition as d7 but used during the second sample. 0 r/w d1 4 1st sample temp sensor select same definition as ts7 but used during the first sample. 0 r/w ts0 3 1st sample interrupt enable same definition as ie7 but used during the first sample. 0 r/w ie0 2 1st sample is end of sequence same definition as end7 but used during the first sample. 0 r/w end0 1 1st sample diff input select same definition as d7 but used during the first sample. 0 r/w d0 0 671 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 30: adc sample sequence 1 operation (adcssop1), offset 0x070 register 31: adc sample sequence 2 operation (adcssop2), offset 0x090 this register determines whether the sample from the given conversion on sample sequence n is saved in the sample sequence n fifo or sent to the digital comparator unit. the adcssop1 register controls sample sequencer 1 and the adcssop2 register controls sample sequencer 2. adc sample sequence 1 operation (adcssop1) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x070 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 s0dcop reserved s1dcop reserved s2dcop reserved s3dcop reserved r/w ro ro ro r/w ro ro ro r/w ro ro ro r/w ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0 ro reserved 31:13 sample 3 digital comparator operation description value the fourth sample is sent to the digital comparator unit specified by the s3dcsel bit in the adcssdc0n register, and the value is not written to the fifo. 1 the fourth sample is saved in sample sequence fifon. 0 0 r/w s3dcop 12 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 11:9 sample 2 digital comparator operation same definition as s3dcop but used during the third sample. 0 r/w s2dcop 8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 7:5 sample 1 digital comparator operation same definition as s3dcop but used during the second sample. 0 r/w s1dcop 4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 3:1 sample 0 digital comparator operation same definition as s3dcop but used during the first sample. 0 r/w s0dcop 0 july 03, 2014 672 texas instruments-production data analog-to-digital converter (adc) register 32: adc sample sequence 1 digital comparator select (adcssdc1), offset 0x074 register 33: adc sample sequence 2 digital comparator select (adcssdc2), offset 0x094 these registers determine which digital comparator receives the sample from the given conversion on sample sequence n if the corresponding sndcop bit in the adcssopn register is set. the adcssdc1 register controls the selection for sample sequencer 1 and the adcssdc2 register controls the selection for sample sequencer 2. adc sample sequence 1 digital comparator select (adcssdc1) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x074 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 s0dcsel s1dcsel s2dcsel s3dcsel r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 sample 3 digital comparator select when the s3dcop bit in the adcssopn register is set, this field indicates which digital comparator unit (and its associated set of control registers) receives the eighth sample from sample sequencer n. note: values not listed are reserved. description value digital comparator unit 0 ( adcdccmp0 and adccctl0 ) 0x0 digital comparator unit 1 ( adcdccmp1 and adccctl1 ) 0x1 digital comparator unit 2 ( adcdccmp2 and adccctl2 ) 0x2 digital comparator unit 3 ( adcdccmp3 and adccctl3 ) 0x3 digital comparator unit 4 ( adcdccmp4 and adccctl4 ) 0x4 digital comparator unit 5 ( adcdccmp5 and adccctl5 ) 0x5 digital comparator unit 6 ( adcdccmp6 and adccctl6 ) 0x6 digital comparator unit 7 ( adcdccmp7 and adccctl7 ) 0x7 0x0 r/w s3dcsel 15:12 sample 2 digital comparator select this field has the same encodings as s3dcsel but is used during the third sample. 0x0 r/w s2dcsel 11:8 673 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field sample 1 digital comparator select this field has the same encodings as s3dcsel but is used during the second sample. 0x0 r/w s1dcsel 7:4 sample 0 digital comparator select this field has the same encodings as s3dcsel but is used during the first sample. 0x0 r/w s0dcsel 3:0 july 03, 2014 674 texas instruments-production data analog-to-digital converter (adc) register 34: adc sample sequence input multiplexer select 3 (adcssmux3), offset 0x0a0 this register defines the analog input configuration for the sample executed with sample sequencer 3. this register is 4 bits wide and contains information for one possible sample. see the adcssmux0 register on page 657 for detailed bit descriptions. adc sample sequence input multiplexer select 3 (adcssmux3) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x0a0 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mux0 reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:4 1st sample input select 0 r/w mux0 3:0 675 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 35: adc sample sequence control 3 (adcssctl3), offset 0x0a4 this register contains the configuration information for a sample executed with sample sequencer 3. the end0 bit is always set as this sequencer can execute only one sample. this register is 4 bits wide and contains information for one possible sample. see the adcssctl0 register on page 659 for detailed bit descriptions. adc sample sequence control 3 (adcssctl3) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x0a4 type r/w, reset 0x0000.0002 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 d0 end0 ie0 ts0 reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro type 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:4 1st sample temp sensor select same definition as ts7 but used during the first sample. 0 r/w ts0 3 1st sample interrupt enable same definition as ie7 but used during the first sample. 0 r/w ie0 2 1st sample is end of sequence same definition as end7 but used during the first sample. because this sequencer has only one entry, this bit must be set. 1 r/w end0 1 1st sample diff input select same definition as d7 but used during the first sample. 0 r/w d0 0 july 03, 2014 676 texas instruments-production data analog-to-digital converter (adc) register 36: adc sample sequence 3 operation (adcssop3), offset 0x0b0 this register determines whether the sample from the given conversion on sample sequence 3 is saved in the sample sequence 3 fifo or sent to the digital comparator unit. adc sample sequence 3 operation (adcssop3) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x0b0 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 s0dcop reserved r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:1 sample 0 digital comparator operation description value the sample is sent to the digital comparator unit specified by the s0dcsel bit in the adcssdc03 register, and the value is not written to the fifo. 1 the sample is saved in sample sequence fifo3. 0 0 r/w s0dcop 0 677 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 37: adc sample sequence 3 digital comparator select (adcssdc3), offset 0x0b4 this register determines which digital comparator receives the sample from the given conversion on sample sequence 3 if the corresponding sndcop bit in the adcssop3 register is set. adc sample sequence 3 digital comparator select (adcssdc3) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0x0b4 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 s0dcsel reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:4 sample 0 digital comparator select when the s0dcop bit in the adcssop3 register is set, this field indicates which digital comparator unit (and its associated set of control registers) receives the sample from sample sequencer 3. note: values not listed are reserved. description value digital comparator unit 0 ( adcdccmp0 and adccctl0 ) 0x0 digital comparator unit 1 ( adcdccmp1 and adccctl1 ) 0x1 digital comparator unit 2 ( adcdccmp2 and adccctl2 ) 0x2 digital comparator unit 3 ( adcdccmp3 and adccctl3 ) 0x3 digital comparator unit 4 ( adcdccmp4 and adccctl4 ) 0x4 digital comparator unit 5 ( adcdccmp5 and adccctl5 ) 0x5 digital comparator unit 6 ( adcdccmp6 and adccctl6 ) 0x6 digital comparator unit 7 ( adcdccmp7 and adccctl7 ) 0x7 0x0 r/w s0dcsel 3:0 july 03, 2014 678 texas instruments-production data analog-to-digital converter (adc) register 38: adc digital comparator reset initial conditions (adcdcric), offset 0xd00 this register provides the ability to reset any of the digital comparator interrupt or trigger functions back to their initial conditions. resetting these functions ensures that the data that is being used by the interrupt and trigger functions in the digital comparator unit is not stale. adc digital comparator reset initial conditions (adcdcric) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0xd00 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 dctrig0 dctrig1 dctrig2 dctrig3 dctrig4 dctrig5 dctrig6 dctrig7 reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dcint0 dcint1 dcint2 dcint3 dcint4 dcint5 dcint6 dcint7 reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:24 digital comparator trigger 7 description value resets the digital comparator 7 trigger unit to its initial conditions. 1 no effect. 0 when the trigger has been cleared, this bit is automatically cleared. because the digital comparators use the current and previous adc conversion values to determine when to assert the trigger, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. after setting this bit, software should wait until the bit clears before continuing. 0 r/w dctrig7 23 digital comparator trigger 6 description value resets the digital comparator 6 trigger unit to its initial conditions. 1 no effect. 0 when the trigger has been cleared, this bit is automatically cleared. because the digital comparators use the current and previous adc conversion values to determine when to assert the trigger, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 0 r/w dctrig6 22 679 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field digital comparator trigger 5 description value resets the digital comparator 5 trigger unit to its initial conditions. 1 no effect. 0 when the trigger has been cleared, this bit is automatically cleared. because the digital comparators use the current and previous adc conversion values to determine when to assert the trigger, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 0 r/w dctrig5 21 digital comparator trigger 4 description value resets the digital comparator 4 trigger unit to its initial conditions. 1 no effect. 0 when the trigger has been cleared, this bit is automatically cleared. because the digital comparators use the current and previous adc conversion values to determine when to assert the trigger, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 0 r/w dctrig4 20 digital comparator trigger 3 description value resets the digital comparator 3 trigger unit to its initial conditions. 1 no effect. 0 when the trigger has been cleared, this bit is automatically cleared. because the digital comparators use the current and previous adc conversion values to determine when to assert the trigger, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 0 r/w dctrig3 19 digital comparator trigger 2 description value resets the digital comparator 2 trigger unit to its initial conditions. 1 no effect. 0 when the trigger has been cleared, this bit is automatically cleared. because the digital comparators use the current and previous adc conversion values to determine when to assert the trigger, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 0 r/w dctrig2 18 july 03, 2014 680 texas instruments-production data analog-to-digital converter (adc) description reset type name bit/field digital comparator trigger 1 description value resets the digital comparator 1 trigger unit to its initial conditions. 1 no effect. 0 when the trigger has been cleared, this bit is automatically cleared. because the digital comparators use the current and previous adc conversion values to determine when to assert the trigger, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 0 r/w dctrig1 17 digital comparator trigger 0 description value resets the digital comparator 0 trigger unit to its initial conditions. 1 no effect. 0 when the trigger has been cleared, this bit is automatically cleared. because the digital comparators use the current and previous adc conversion values to determine when to assert the trigger, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 0 r/w dctrig0 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 15:8 digital comparator interrupt 7 description value resets the digital comparator 7 interrupt unit to its initial conditions. 1 no effect. 0 when the interrupt has been cleared, this bit is automatically cleared. because the digital comparators use the current and previous adc conversion values to determine when to assert the interrupt, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 0 r/w dcint7 7 digital comparator interrupt 6 description value resets the digital comparator 6 interrupt unit to its initial conditions. 1 no effect. 0 when the interrupt has been cleared, this bit is automatically cleared. because the digital comparators use the current and previous adc conversion values to determine when to assert the interrupt, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 0 r/w dcint6 6 681 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field digital comparator interrupt 5 description value resets the digital comparator 5 interrupt unit to its initial conditions. 1 no effect. 0 when the interrupt has been cleared, this bit is automatically cleared. because the digital comparators use the current and previous adc conversion values to determine when to assert the interrupt, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 0 r/w dcint5 5 digital comparator interrupt 4 description value resets the digital comparator 4 interrupt unit to its initial conditions. 1 no effect. 0 when the interrupt has been cleared, this bit is automatically cleared. because the digital comparators use the current and previous adc conversion values to determine when to assert the interrupt, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 0 r/w dcint4 4 digital comparator interrupt 3 description value resets the digital comparator 3 interrupt unit to its initial conditions. 1 no effect. 0 when the interrupt has been cleared, this bit is automatically cleared. because the digital comparators use the current and previous adc conversion values to determine when to assert the interrupt, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 0 r/w dcint3 3 digital comparator interrupt 2 description value resets the digital comparator 2 interrupt unit to its initial conditions. 1 no effect. 0 when the interrupt has been cleared, this bit is automatically cleared. because the digital comparators use the current and previous adc conversion values to determine when to assert the interrupt, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 0 r/w dcint2 2 july 03, 2014 682 texas instruments-production data analog-to-digital converter (adc) description reset type name bit/field digital comparator interrupt 1 description value resets the digital comparator 1 interrupt unit to its initial conditions. 1 no effect. 0 when the interrupt has been cleared, this bit is automatically cleared. because the digital comparators use the current and previous adc conversion values to determine when to assert the interrupt, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 0 r/w dcint1 1 digital comparator interrupt 0 description value resets the digital comparator 0 interrupt unit to its initial conditions. 1 no effect. 0 when the interrupt has been cleared, this bit is automatically cleared. because the digital comparators use the current and previous adc conversion values to determine when to assert the interrupt, it is important to reset the digital comparator to initial conditions when starting a new sequence so that stale data is not used. 0 r/w dcint0 0 683 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 39: adc digital comparator control 0 (adcdcctl0), offset 0xe00 register 40: adc digital comparator control 1 (adcdcctl1), offset 0xe04 register 41: adc digital comparator control 2 (adcdcctl2), offset 0xe08 register 42: adc digital comparator control 3 (adcdcctl3), offset 0xe0c register 43: adc digital comparator control 4 (adcdcctl4), offset 0xe10 register 44: adc digital comparator control 5 (adcdcctl5), offset 0xe14 register 45: adc digital comparator control 6 (adcdcctl6), offset 0xe18 register 46: adc digital comparator control 7 (adcdcctl7), offset 0xe1c this register provides the comparison encodings that generate an interrupt and/or pwm trigger. see interrupt/adc-trigger selector on page 1118 for more information on using the adc digital comparators to trigger a pwm generator. adc digital comparator control 0 (adcdcctl0) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0xe00 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cim cic cie reserved ctm ctc cte reserved r/w r/w r/w r/w r/w ro ro ro r/w r/w r/w r/w r/w ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0 ro reserved 31:13 comparison trigger enable description value enables the trigger function state machine. the adc conversion data is used to determine if a trigger should be generated according to the programming of the ctc and ctm fields. 1 disables the trigger function state machine. adc conversion data is ignored by the trigger function. 0 0 r/w cte 12 july 03, 2014 684 texas instruments-production data analog-to-digital converter (adc) description reset type name bit/field comparison trigger condition this field specifies the operational region in which a trigger is generated when the adc conversion data is compared against the values of comp0 and comp1 . the comp0 and comp1 fields are defined in the adcdccmpx registers. description value low band adc data < comp0 comp1 0x0 mid band comp0 adc data < comp1 0x1 reserved 0x2 high band comp0 comp1 adc data 0x3 0x0 r/w ctc 11:10 comparison trigger mode this field specifies the mode by which the trigger comparison is made. description value always this mode generates a trigger every time the adc conversion data falls within the selected operational region. 0x0 once this mode generates a trigger the first time that the adc conversion data enters the selected operational region. 0x1 hysteresis always this mode generates a trigger when the adc conversion data falls within the selected operational region and continues to generate the trigger until the hysteresis condition is cleared by entering the opposite operational region. note that the hysteresis modes are only defined for ctc encodings of 0x0 and 0x3. 0x2 hysteresis once this mode generates a trigger the first time that the adc conversion data falls within the selected operational region. no additional triggers are generated until the hysteresis condition is cleared by entering the opposite operational region. note that the hysteresis modes are only defined for ctc encodings of 0x0 and 0x3. 0x3 0x0 r/w ctm 9:8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 7:5 685 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field comparison interrupt enable description value enables the comparison interrupt. the adc conversion data is used to determine if an interrupt should be generated according to the programming of the cic and cim fields. 1 disables the comparison interrupt. adc conversion data has no effect on interrupt generation. 0 0 r/w cie 4 comparison interrupt condition this field specifies the operational region in which an interrupt is generated when the adc conversion data is compared against the values of comp0 and comp1 . the comp0 and comp1 fields are defined in the adcdccmpx registers. description value low band adc data < comp0 comp1 0x0 mid band comp0 adc data < comp1 0x1 reserved 0x2 high band comp0 < comp1 adc data 0x3 0x0 r/w cic 3:2 comparison interrupt mode this field specifies the mode by which the interrupt comparison is made. description value always this mode generates an interrupt every time the adc conversion data falls within the selected operational region. 0x0 once this mode generates an interrupt the first time that the adc conversion data enters the selected operational region. 0x1 hysteresis always this mode generates an interrupt when the adc conversion data falls within the selected operational region and continues to generate the interrupt until the hysteresis condition is cleared by entering the opposite operational region. note that the hysteresis modes are only defined for ctc encodings of 0x0 and 0x3. 0x2 hysteresis once this mode generates an interrupt the first time that the adc conversion data falls within the selected operational region. no additional interrupts are generated until the hysteresis condition is cleared by entering the opposite operational region. note that the hysteresis modes are only defined for ctc encodings of 0x0 and 0x3. 0x3 0x0 r/w cim 1:0 july 03, 2014 686 texas instruments-production data analog-to-digital converter (adc) register 47: adc digital comparator range 0 (adcdccmp0), offset 0xe40 register 48: adc digital comparator range 1 (adcdccmp1), offset 0xe44 register 49: adc digital comparator range 2 (adcdccmp2), offset 0xe48 register 50: adc digital comparator range 3 (adcdccmp3), offset 0xe4c register 51: adc digital comparator range 4 (adcdccmp4), offset 0xe50 register 52: adc digital comparator range 5 (adcdccmp5), offset 0xe54 register 53: adc digital comparator range 6 (adcdccmp6), offset 0xe58 register 54: adc digital comparator range 7 (adcdccmp7), offset 0xe5c this register defines the comparison values that are used to determine if the adc conversion data falls in the appropriate operating region. note: the value in the comp1 field must be greater than or equal to the value in the comp0 field or unexpected results can occur. if the res bit in the adcctl register is clear, selecting 10-bit resolution, use only bits [25:16] in the comp1 field and bits [9:0] in the comp0 field; otherwise unexpected results can occur. adc digital comparator range 0 (adcdccmp0) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 offset 0xe40 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 comp1 reserved r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 comp0 reserved r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 31:28 compare 1 the value in this field is compared against the adc conversion data. the result of the comparison is used to determine if the data lies within the high-band region. note that the value of comp1 must be greater than or equal to the value of comp0. 0x000 r/w comp1 27:16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 15:12 687 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field compare 0 the value in this field is compared against the adc conversion data. the result of the comparison is used to determine if the data lies within the low-band region. 0x000 r/w comp0 11:0 july 03, 2014 688 texas instruments-production data analog-to-digital converter (adc) 13 universal asynchronous receivers/transmitters (uarts) the stellaris ? lm3s9gn5 controller includes three universal asynchronous receiver/transmitter (uart) with the following features: programmable baud-rate generator allowing speeds up to 5 mbps for regular speed (divide by 16) and 10 mbps for high speed (divide by 8) separate 16x8 transmit (tx) and receive (rx) fifos to reduce cpu interrupt service loading programmable fifo length, including 1-byte deep operation providing conventional double-buffered interface fifo trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8 standard asynchronous communication bits for start, stop, and parity line-break generation and detection fully programmable serial interface characteristics C 5, 6, 7, or 8 data bits C even, odd, stick, or no-parity bit generation/detection C 1 or 2 stop bit generation irda serial-ir (sir) encoder/decoder providing C programmable use of irda serial infrared (sir) or uart input/output C support of irda sir encoder/decoder functions for data rates up to 115.2 kbps half-duplex C support of normal 3/16 and low-power (1.41-2.23 s) bit durations C programmable internal clock generator enabling division of reference clock by 1 to 256 for low-power mode bit duration support for communication with iso 7816 smart cards full modem handshake support (on uart1) lin protocol support standard fifo-level and end-of-transmission interrupts efficient transfers using micro direct memory access controller (dma) C separate channels for transmit and receive C receive single request asserted when data is in the fifo; burst request asserted at programmed fifo level 689 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller C transmit single request asserted when there is space in the fifo; burst request asserted at programmed fifo level 13.1 block diagram figure 13-1. uart module block diagram 13.2 signal description the following table lists the external signals of the uart module and describes the function of each. the uart signals are alternate functions for some gpio signals and default to be gpio signals at reset, with the exception of the u0rx and u0tx pins which default to the uart function. the column in the table below titled "pin mux/pin assignment" lists the possible gpio pin placements for these uart signals. the afsel bit in the gpio alternate function select (gpioafsel) register (page 429) should be set to choose the uart function. the number in parentheses is the encoding that must be programmed into the pmcn field in the gpio port control (gpiopctl) register (page 447) to assign the uart signal to the specified gpio port pin. for more information on configuring gpios, see general-purpose input/outputs (gpios) on page 405. july 03, 2014 690 texas instruments-production data universal asynchronous receivers/transmitters (uarts) 7 [ ) , ) 2 [ 5 [ ) , ) 2 [ ' 0 $ & r q w u r o 8 $ 5 7 ' 0 $ & 7 / , g h q w l i l f d w l r q 5 h j l v w h u v 8 $ 5 7 3 & h o o , ' 8 $ 5 7 3 & h o o , ' 8 $ 5 7 3 & h o o , ' 8 $ 5 7 3 & h o o , ' 8 $ 5 7 3 h u l s k , ' 8 $ 5 7 3 h u l s k , ' 8 $ 5 7 3 h u l s k , ' 8 $ 5 7 3 h u l s k , ' 8 $ 5 7 3 h u l s k , ' 8 $ 5 7 3 h u l s k , ' 8 $ 5 7 3 h u l s k , ' 8 $ 5 7 3 h u l s k , ' , q w h u u x s w & r q w u r o 8 $ 5 7 ' 5 & r q w u r o 6 w d w x v 7 u d q v p l w w h u z l w k 6 , 5 7 u d q v p l w ( q f r g h u % d x g 5 d w h * h q h u d w r u 5 h f h l y h u z l w k 6 , 5 5 h f h l y h ' h f r g h u 8 q 7 [ 8 q 5 [ ' 0 $ 5 h t x h v w 6 \ v w h p & o r f n , q w h u u x s w 8 $ 5 7 , ) / 6 8 $ 5 7 , 0 8 $ 5 7 0 , 6 8 $ 5 7 5 , 6 8 $ 5 7 , & 5 8 $ 5 7 , % 5 ' 8 $ 5 7 ) % 5 ' 8 $ 5 7 5 6 5 ( & 5 8 $ 5 7 ) 5 8 $ 5 7 / & 5 + 8 $ 5 7 & 7 / 8 $ 5 7 , / 3 5 8 $ 5 7 / & 7 / 8 $ 5 7 / 6 6 8 $ 5 7 / 7 , 0 table 13-1. uart signals (100lqfp) description buffer type a pin type pin mux / pin assignment pin number pin name uart module 0 receive. when in irda mode, this signal has irda modulation. ttl i pa0 (1) 26 u0rx uart module 0 transmit. when in irda mode, this signal has irda modulation. ttl o pa1 (1) 27 u0tx uart module 1 clear to send modem flow control input signal. ttl i pe6 (9) pd0 (9) pa6 (9) pj3 (9) 2 10 34 50 u1cts uart module 1 data carrier detect modem status input signal. ttl i pe7 (9) pd1 (9) pa7 (9) pj4 (9) 1 11 35 52 u1dcd uart module 1 data set ready modem output control line. ttl i pf0 (9) pj5 (9) 47 53 u1dsr uart module 1 data terminal ready modem status input signal. ttl o pg5 (10) pj7 (9) pd7 (9) 40 55 100 u1dtr uart module 1 ring indicator modem status input signal. ttl i pg6 (10) pg4 (10) pd4 (9) 37 41 97 u1ri uart module 1 request to send modem flow control output line. ttl o pf6 (10) pj6 (9) pf1 (9) 43 54 61 u1rts uart module 1 receive. when in irda mode, this signal has irda modulation. ttl i pd0 (5) pd2 (1) pc6 (5) pa0 (9) pb0 (5) pb4 (7) 10 12 23 26 66 92 u1rx uart module 1 transmit. when in irda mode, this signal has irda modulation. ttl o pd1 (5) pd3 (1) pc7 (5) pa1 (9) pb1 (5) pb5 (7) 11 13 22 27 67 91 u1tx uart module 2 receive. when in irda mode, this signal has irda modulation. ttl i pd0 (4) pg0 (1) pb4 (4) pd5 (9) 10 19 92 98 u2rx uart module 2 transmit. when in irda mode, this signal has irda modulation. ttl o pe4 (5) pd1 (4) pg1 (1) pd6 (9) 6 11 18 99 u2tx a. the ttl designation indicates the pin has ttl-compatible voltage levels. table 13-2. uart signals (108bga) description buffer type a pin type pin mux / pin assignment pin number pin name uart module 0 receive. when in irda mode, this signal has irda modulation. ttl i pa0 (1) l3 u0rx 691 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 13-2. uart signals (108bga) (continued) description buffer type a pin type pin mux / pin assignment pin number pin name uart module 0 transmit. when in irda mode, this signal has irda modulation. ttl o pa1 (1) m3 u0tx uart module 1 clear to send modem flow control input signal. ttl i pe6 (9) pd0 (9) pa6 (9) pj3 (9) a1 g1 l6 m10 u1cts uart module 1 data carrier detect modem status input signal. ttl i pe7 (9) pd1 (9) pa7 (9) pj4 (9) b1 g2 m6 k11 u1dcd uart module 1 data set ready modem output control line. ttl i pf0 (9) pj5 (9) m9 k12 u1dsr uart module 1 data terminal ready modem status input signal. ttl o pg5 (10) pj7 (9) pd7 (9) m7 l12 a2 u1dtr uart module 1 ring indicator modem status input signal. ttl i pg6 (10) pg4 (10) pd4 (9) l7 k3 b5 u1ri uart module 1 request to send modem flow control output line. ttl o pf6 (10) pj6 (9) pf1 (9) m8 l10 h12 u1rts uart module 1 receive. when in irda mode, this signal has irda modulation. ttl i pd0 (5) pd2 (1) pc6 (5) pa0 (9) pb0 (5) pb4 (7) g1 h2 m2 l3 e12 a6 u1rx uart module 1 transmit. when in irda mode, this signal has irda modulation. ttl o pd1 (5) pd3 (1) pc7 (5) pa1 (9) pb1 (5) pb5 (7) g2 h1 l2 m3 d12 b7 u1tx uart module 2 receive. when in irda mode, this signal has irda modulation. ttl i pd0 (4) pg0 (1) pb4 (4) pd5 (9) g1 k1 a6 c6 u2rx uart module 2 transmit. when in irda mode, this signal has irda modulation. ttl o pe4 (5) pd1 (4) pg1 (1) pd6 (9) b2 g2 k2 a3 u2tx a. the ttl designation indicates the pin has ttl-compatible voltage levels. 13.3 functional description each stellaris uart performs the functions of parallel-to-serial and serial-to-parallel conversions. it is similar in functionality to a 16c550 uart, but is not register compatible. the uart is configured for transmit and/or receive via the txe and rxe bits of the uart control (uartctl) register (see page 717). transmit and receive are both enabled out of reset. before any control registers are programmed, the uart must be disabled by clearing the uarten bit in july 03, 2014 692 texas instruments-production data universal asynchronous receivers/transmitters (uarts) uartctl . if the uart is disabled during a tx or rx operation, the current transaction is completed prior to the uart stopping. the uart module also includes a serial ir (sir) encoder/decoder block that can be connected to an infrared transceiver to implement an irda sir physical layer. the sir function is programmed using the uartctl register. 13.3.1 transmit/receive logic the transmit logic performs parallel-to-serial conversion on the data read from the transmit fifo. the control logic outputs the serial bit stream beginning with a start bit and followed by the data bits (lsb first), parity bit, and the stop bits according to the programmed configuration in the control registers. see figure 13-2 on page 693 for details. the receive logic performs serial-to-parallel conversion on the received bit stream after a valid start pulse has been detected. overrun, parity, frame error checking, and line-break detection are also performed, and their status accompanies the data that is written to the receive fifo. figure 13-2. uart character frame 13.3.2 baud-rate generation the baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part. the number formed by these two values is used by the baud-rate generator to determine the bit period. having a fractional baud-rate divisor allows the uart to generate all the standard baud rates. the 16-bit integer is loaded through the uart integer baud-rate divisor (uartibrd) register (see page 713) and the 6-bit fractional part is loaded with the uart fractional baud-rate divisor (uartfbrd) register (see page 714). the baud-rate divisor (brd) has the following relationship to the system clock (where brdi is the integer part of the brd and brdf is the fractional part, separated by a decimal place.) brd = brdi + brdf = uartsysclk / (clkdiv * baud rate) where uartsysclk is the system clock connected to the uart, and clkdiv is either 16 (if hse in uartctl is clear) or 8 (if hse is set). the 6-bit fractional number (that is to be loaded into the divfrac bit field in the uartfbrd register) can be calculated by taking the fractional part of the baud-rate divisor, multiplying it by 64, and adding 0.5 to account for rounding errors: uartfbrd[divfrac] = integer(brdf * 64 + 0.5) the uart generates an internal baud-rate reference clock at 8x or 16x the baud-rate (referred to as baud8 and baud16 , depending on the setting of the hse bit (bit 5) in uartctl ). this reference clock is divided by 8 or 16 to generate the transmit clock, and is used for error detection during receive operations. note that the state of the hse bit has no effect on clock generation in iso 7816 smart card mode (when the smart bit in the uartctl register is set). along with the uart line control, high byte (uartlcrh) register (see page 715), the uartibrd and uartfbrd registers form an internal 30-bit register. this internal register is only updated 693 july 03, 2014 texas instruments-production data stellaris lm3s9gn5 microcontroller g d w d e l w v / 6 % 0 6 % 3 d u l w \ e l w l i h q d e o h g v w r s e l w v 8 q 7 ; q 6 w d u w when a write operation to uartlcrh is performed, so any changes to the baud-rate divisor must be followed by a write to the uartlcrh register for the changes to take effect. to update the baud-rate registers, there are four possible sequences: uartibrd write, uartfbrd write, and uartlcrh write uartfbrd write, uartibrd write, and uartlcrh write uartibrd write and uartlcrh write uartfbrd write and uartlcrh write 13.3.3 data transmission data received or transmitted is stored in two 16-byte fifos, though the receive fifo has an extra four bits per character for status information. for transmission, data is written into the transmit fifo. if the uart is enabled, it causes a data frame to start transmitting with the parameters indicated in the uartlcrh register. data continues to be transmitted until there is no data left in the transmit fifo. the busy bit in the uart flag (uartfr) register (see page 709) is asserted as soon as data is written to the transmit fifo (that is, if the fifo is non-empty) and remains asserted while data is being transmitted. the busy bit is negated only when the transmit fifo is empty, and the last character has been transmitted from the shift register, including the stop bits. the uart can indicate that it is busy even though the uart may no longer be enabled. when the receiver is idle (the unrx signal is continuously 1), and the data input goes low (a start bit has been received), the receive counter begins running and data is sampled on the eighth cycle of baud16 or fourth cycle of baud8 depending on the setting of the hse bit (bit 5) in uartctl (described in transmit/receive logic on page 693). the start bit is valid and recognized if the unrx signal is still low on the eighth cycle of baud16 (hse clear) or the fourth cycle of baud 8 ( hse set), otherwise it is ignored. after a valid start bit is detected, successive data bits are sampled on every 16th cycle of baud16 or 8th cycle of baud8 (that is, one bit period later) according to the programmed length of the data characters and value of the hse bit in uartctl . the parity bit is then checked if parity mode is enabled. data length and parity are defined in the uartlcrh register. lastly, a valid stop bit is confirmed if the unrx signal is high, otherwise a framing error has occurred. when a full word is received, the data is stored in the receive fifo along with any error bits associated with that word. 13.3.4 serial ir (sir) the uart peripheral includes an irda serial-ir (sir) encoder/decoder block. the irda sir block provides functionality that converts between an asynchronous uart data stream and a half-duplex serial sir interface. no analog processing is performed on-chip. the role of the sir block is to provide a digital encoded output and decoded input to the uart. when enabled, the sir block uses the untx and unrx pins for the sir protocol. these signals should be connected to an infrared transceiver to implement an irda sir physical layer link. the sir block can receive and transmit, but it is only half-duplex so it cannot do both at the same time. transmission must be stopped before data can be received. the irda sir physical layer specifies a minimum 10-ms delay between transmission and reception.the sir block has two modes of operation: in normal irda mode, a zero logic level is transmitted as a high pulse of 3/16th duration of the selected baud rate bit period on the output pin, while logic one levels are transmitted as a static low signal. these levels control the driver of an infrared transmitter, sending a pulse of light july 03, 2014 694 texas instruments-production data universal asynchronous receivers/transmitters (uarts) for each zero. on the reception side, the incoming light pulses energize the photo transistor base of the receiver, pulling its output low and driving the uart input pin low. in low-power irda mode, the width of the transmitted infrared pulse is set to three times the period of the internally generated irlpbaud16 signal (1.63 s, assuming a nominal 1.8432 mhz frequency) by changing the appropriate bit in the uartcr register. see page 712 for more information on irda low-power pulse-duration configuration. figure 13-3 on page 695 shows the uart transmit and receive signals, with and without irda modulation. figure 13-3. irda data modulation in both normal and low-power irda modes: during transmission, the uart data bit is used as the base for encoding during reception, the decoded bits are transferred to the uart receive logic the irda sir physical layer specifies a half-duplex communication link, with a minimum 10-ms delay between transmission and reception. this delay must be generated by software because it is not automatically supported by the uart. the delay is required because the infrared receiver electronics might become biased or even saturated from the optical power coupled from the adjacent transmitter led. this delay is known as latency or receiver setup time. 13.3.5 iso 7816 support the uart offers basic support to allow communication with an iso 7816 smartcard. when bit 3 (smart ) of the uartctl register is set, the untx signal is used as a bit clock, and the unrx signal is used as the half-duplex communication line connected to the smartcard. a gpio signal can be used to generate the reset signal to the smartcard. the remaining smartcard signals should be provided by the system design. the maximum clock rate in this mode is system clock / 16. when using iso 7816 mode, the uartlcrh register must be set to transmit 8-bit words ( wlen bits 6:5 configured to 0x3) with even parity ( pen set and eps set). in this mode, the uart automatically uses 2 stop bits, and the stp2 bit of the uartlcrh register is ignored. if a parity error is detected during transmission, unrx is pulled low during the second stop bit. in this case, the uart aborts the transmission, flushes the transmit fifo and discards any data it contains, and raises a parity error interrupt, allowing software to detect the problem and initiate 695 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller ' d w d e l w v ' d w d e l w v 6 w d u w e l w 6 w d u w 6 w r s % l w s h u l r g % l w s h u l r g 8 q 7 [ 8 q 7 [ z l w k , u ' $ 8 q 5 [ z l w k , u ' $ 8 q 5 [ 6 w r s e l w retransmission of the affected data. note that the uart does not support automatic retransmission in this case. 13.3.6 modem handshake support this section describes how to configure and use the modem flow control and status signals for uart1 when connected as a dte (data terminal equipment) or as a dce (data communications equipment). in general, a modem is a dce and a computing device that connects to a modem is the dte. 13.3.6.1 signaling the status signals provided by uart1 differ based on whether the uart is used as a dte or dce. when used as a dte, the modem flow control and status signals are defined as: u1cts is clear to send u1dsr is data set ready u1dcd is data carrier detect u1ri is ring indicator u1rts is request to send u1dtr is data terminal ready when used as a dce, the the modem flow control and status signals are defined as: u1cts is request to send u1dsr is data terminal ready u1rts is clear to send u1dtr is data set ready note that the support for dce functions data carrier detect and ring indicator are not provided. if these signals are required, their function can be emulated by using a general-purpose i/o signal and providing software support. 13.3.6.2 flow control flow control can be accomplished by either hardware or software. the following sections describe the different methods. hardware flow control (rts/cts) hardware flow control between two devices is accomplished by connecting the u1rts output to the clear-to-send input on the receiving device, and connecting the request-to-send output on the receiving device to the u1cts input. the u1cts input controls the transmitter. the transmitter may only transmit data when the u1cts input is asserted. the u1rts output signal indicates the state of the receive fifo. u1cts remains asserted until the preprogrammed watermark level is reached, indicating that the receive fifo has no space to store additional characters. july 03, 2014 696 texas instruments-production data universal asynchronous receivers/transmitters (uarts) the uartctl register bits 15 ( ctsen ) and 14 (rtsen ) specify the flow control mode as shown in table 13-3 on page 697. table 13-3. flow control mode description rtsen ctsen rts and cts flow control enabled 1 1 only cts flow control enabled 0 1 only rts flow control enabled 1 0 both rts and cts flow control disabled 0 0 note that when rtsen is 1, software cannot modify the u1rts output value through the uartctl register request to send ( rts ) bit, and the status of the rts bit should be ignored. software flow control (modem status interrupts) software flow control between two devices is accomplished by using interrupts to indicate the status of the uart. interrupts may be generated for the u1dsr , u1dcd , u1cts , and u1ri signals using bits 3:0 of the uartim register, respectively. the raw and masked interrupt status may be checked using the uartris and uartmis register. these interrupts may be cleared using the uarticr register. 13.3.7 lin support the uart module offers hardware support for the lin protocol as either a master or a slave. the lin mode is enabled by setting the lin bit in the uartctl register. a lin message is identified by the use of a sync break at the beginning of the message. the sync break is a transmission of a series of 0s. the sync break is followed by the sync data field (0x55). figure 13-4 on page 697 illustrates the structure of a lin message. figure 13-4. lin message the uart should be configured as followed to operate in lin mode: 1. configure the uart for 1 start bit, 8 data bits, no parity, and 1 stop bit. enable the transmit fifo. 2. set the lin bit in the uartctl register. 697 july 03, 2014 texas instruments-production data stellaris lm3s9gn5 microcontroller + h d g h u 5 h v s r q v h 0 h v v d j h ) u d p h 6 \ q f k % u h d n 6 \ q f k ) l h o g , g h q w ) l h o g ' d w d ) l h o g v ' d w d ) l h o g & k h f n v x p ) l h o g , q w h u e \ w h 6 s d f h , q ) u d p h 5 h v s r q v h when preparing to send a lin message, the txfifo should contain the sync data (0x55) at fifo location 0 and the identifier data at location 1, followed by the data to be transmitted, and with the checksum in the final fifo entry. 13.3.7.1 lin master the uart is enabled to be the lin master by setting the master bit in the uartlctl register. the length of the sync break is programmable using the blen field in the uartlctl register and can be 13-16 bits (baud clock cycles). 13.3.7.2 lin slave the lin uart slave is required to adjust its baud rate to that of the lin master. in slave mode, the lin uart recognizes the sync break, which must be at least 13 bits in duration. a timer is provided to capture timing data on the 1st and 5th falling edges of the sync field so that the baud rate can be adjusted to match the master. after detecting a sync break, the uart waits for the synchronization field. the first falling edge generates an interrupt using the lme1ris bit in the uartris register, and the timer value is captured and stored in the uartlss register (t1). on the fifth falling edge, a second interrupt is generated using the lme5ris bit in the uartris register, and the timer value is captured again (t2). the actual baud rate can be calculated using (t2-t1)/8, and the local baud rate should be adjusted as needed. figure 13-5 on page 698 illustrates the synchronization field. figure 13-5. lin synchronization field 13.3.8 fifo operation the uart has two 16x8 fifos; one for transmit and one for receive. both fifos are accessed via the uart data (uartdr) register (see page 704). read operations of the uartdr register return a 12-bit value consisting of 8 data bits and 4 error flags while write operations place 8-bit data in the transmit fifo. out of reset, both fifos are disabled and act as 1-byte-deep holding registers. the fifos are enabled by setting the fen bit in uartlcrh (page 715). fifo status can be monitored via the uart flag (uartfr) register (see page 709) and the uart receive status (uartrsr) register. hardware monitors empty, full and overrun conditions. the uartfr register contains empty and full flags ( txfe, txff, rxfe , and rxff bits), and the uartrsr register shows overrun status via the oe bit. if the fifos are disabled, the empty and full flags are set according to the status of the 1-byte-deep holding registers. the trigger points at which the fifos generate interrupts is controlled via the uart interrupt fifo level select (uartifls) register (see page 721). both fifos can be individually configured to trigger interrupts at different levels. available configurations include ?, ?, ?, ?, and ?. for example, july 03, 2014 698 texas instruments-production data universal asynchronous receivers/transmitters (uarts) ( g j h ( g j h 6 \ q f k ) l h o g 7 e l w 6 \ q f % u h d n ' h w h f w 6 \ q f % u h d n if the ? option is selected for the receive fifo, the uart generates a receive interrupt after 4 data bytes are received. out of reset, both fifos are configured to trigger an interrupt at the ? mark. 13.3.9 interrupts the uart can generate interrupts when the following conditions are observed: overrun error break error parity error framing error receive timeout transmit (when condition defined in the txiflsel bit in the uartifls register is met, or if the eot bit in uartctl is set, when the last bit of all transmitted data leaves the serializer) receive (when condition defined in the rxiflsel bit in the uartifls register is met) all of the interrupt events are ored together before being sent to the interrupt controller, so the uart can only generate a single interrupt request to the controller at any given time. software can service multiple interrupt events in a single interrupt service routine by reading the uart masked interrupt status (uartmis) register (see page 731). the interrupt events that can trigger a controller-level interrupt are defined in the uart interrupt mask (uartim) register (see page 723) by setting the corresponding im bits. if interrupts are not used, the raw interrupt status is always visible via the uart raw interrupt status (uartris) register (see page 727). interrupts are always cleared (for both the uartmis and uartris registers) by writing a 1 to the corresponding bit in the uart interrupt clear (uarticr) register (see page 735). the receive timeout interrupt is asserted when the receive fifo is not empty, and no further data is received over a 32-bit period. the receive timeout interrupt is cleared either when the fifo becomes empty through reading all the data (or by reading the holding register), or when a 1 is written to the corresponding bit in the uarticr register. the receive interrupt changes state when one of the following events occurs: if the fifos are enabled and the receive fifo reaches the programmed trigger level, the rxris bit is set. the receive interrupt is cleared by reading data from the receive fifo until it becomes less than the trigger level, or by clearing the interrupt by writing a 1 to the rxic bit. if the fifos are disabled (have a depth of one location) and data is received thereby filling the location, the rxris bit is set. the receive interrupt is cleared by performing a single read of the receive fifo, or by clearing the interrupt by writing a 1 to the rxic bit. the transmit interrupt changes state when one of the following events occurs: if the fifos are enabled and the transmit fifo progresses through the programmed trigger level, the txris bit is set. the transmit interrupt is based on a transition through level, therefore the fifo must be written past the programmed trigger level otherwise no further transmit interrupts will be generated. the transmit interrupt is cleared by writing data to the transmit fifo until it becomes greater than the trigger level, or by clearing the interrupt by writing a 1 to the txic bit. 699 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller if the fifos are disabled (have a depth of one location) and there is no data present in the transmitters single location, the txris bit is set. it is cleared by performing a single write to the transmit fifo, or by clearing the interrupt by writing a 1 to the txic bit. 13.3.10 loopback operation the uart can be placed into an internal loopback mode for diagnostic or debug work by setting the lbe bit in the uartctl register (see page 717). in loopback mode, data transmitted on the untx output is received on the unrx input. note that the lbe bit should be set before the uart is enabled. 13.3.11 dma operation the uart provides an interface to the dma controller with separate channels for transmit and receive. the dma operation of the uart is enabled through the uart dma control (uartdmactl) register. when dma operation is enabled, the uart asserts a dma request on the receive or transmit channel when the associated fifo can transfer data. for the receive channel, a single transfer request is asserted whenever any data is in the receive fifo. a burst transfer request is asserted whenever the amount of data in the receive fifo is at or above the fifo trigger level configured in the uartifls register. for the transmit channel, a single transfer request is asserted whenever there is at least one empty location in the transmit fifo. the burst request is asserted whenever the transmit fifo contains fewer characters than the fifo trigger level. the single and burst dma transfer requests are handled automatically by the dma controller depending on how the dma channel is configured. to enable dma operation for the receive channel, set the rxdmae bit of the dma control (uartdmactl) register. to enable dma operation for the transmit channel, set the txdmae bit of the uartdmactl register. the uart can also be configured to stop using dma for the receive channel if a receive error occurs. if the dmaerr bit of the uartdmacr register is set and a receive error occurs, the dma receive requests are automatically disabled. this error condition can be cleared by clearing the appropriate uart error interrupt. if dma is enabled, then the dma controller triggers an interrupt when a transfer is complete. the interrupt occurs on the uart interrupt vector. therefore, if interrupts are used for uart operation and dma is enabled, the uart interrupt handler must be designed to handle the dma completion interrupt. see micro direct memory access (dma) on page 344 for more details about programming the dma controller. 13.4 initialization and configuration to enable and initialize the uart, the following steps are necessary: 1. the peripheral clock must be enabled by setting the uart0, uart1 , or uart2 bits in the rcgc1 register (see page 270). 2. the clock to the appropriate gpio module must be enabled via the rcgc2 register in the system control module (see page 282). 3. set the gpio afsel bits for the appropriate pins (see page 429). to determine which gpios to configure, see table 24-4 on page 1239. 4. configure the gpio current level and/or slew rate as specified for the mode selected (see page 431 and page 439). july 03, 2014 700 texas instruments-production data universal asynchronous receivers/transmitters (uarts) 5. configure the pmcn fields in the gpiopctl register to assign the uart signals to the appropriate pins (see page 447 and table 24-5 on page 1248). to use the uart, the peripheral clock must be enabled by setting the appropriate bit in the rcgc1 register (page 270). in addition, the clock to the appropriate gpio module must be enabled via the rcgc2 register (page 282) in the system control module. to find out which gpio port to enable, refer to table 24-5 on page 1248. this section discusses the steps that are required to use a uart module. for this example, the uart clock is assumed to be 20 mhz, and the desired uart configuration is: 115200 baud rate data length of 8 bits one stop bit no parity fifos disabled no interrupts the first thing to consider when programming the uart is the baud-rate divisor (brd), because the uartibrd and uartfbrd registers must be written before the uartlcrh register. using the equation described in baud-rate generation on page 693, the brd can be calculated: brd = 20,000,000 / (16 * 115,200) = 10.8507 which means that the divint field of the uartibrd register (see page 713) should be set to 10 decimal or 0xa. the value to be loaded into the uartfbrd register (see page 714) is calculated by the equation: uartfbrd[divfrac] = integer(0.8507 * 64 + 0.5) = 54 with the brd values in hand, the uart configuration is written to the module in the following order: 1. disable the uart by clearing the uarten bit in the uartctl register. 2. write the integer portion of the brd to the uartibrd register. 3. write the fractional portion of the brd to the uartfbrd register. 4. write the desired serial parameters to the uartlcrh register (in this case, a value of 0x0000.0060). 5. optionally, configure the dma channel (see micro direct memory access (dma) on page 344) and enable the dma option(s) in the uartdmactl register. 6. enable the uart by setting the uarten bit in the uartctl register. 13.5 register map table 13-4 on page 702 lists the uart registers. the offset listed is a hexadecimal increment to the registers address, relative to that uarts base address: uart0: 0x4000.c000 701 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller uart1: 0x4000.d000 uart2: 0x4000.e000 note that the uart module clock must be enabled before the registers can be programmed (see page 270). there must be a delay of 3 system clocks after the uart module clock is enabled before any uart module registers are accessed. note: the uart must be disabled (see the uarten bit in the uartctl register on page 717) before any of the control registers are reprogrammed. when the uart is disabled during a tx or rx operation, the current transaction is completed prior to the uart stopping. table 13-4. uart register map see page description reset type name offset 704 uart data 0x0000.0000 r/w uartdr 0x000 706 uart receive status/error clear 0x0000.0000 r/w uartrsr/uartecr 0x004 709 uart flag 0x0000.0090 ro uartfr 0x018 712 uart irda low-power register 0x0000.0000 r/w uartilpr 0x020 713 uart integer baud-rate divisor 0x0000.0000 r/w uartibrd 0x024 714 uart fractional baud-rate divisor 0x0000.0000 r/w uartfbrd 0x028 715 uart line control 0x0000.0000 r/w uartlcrh 0x02c 717 uart control 0x0000.0300 r/w uartctl 0x030 721 uart interrupt fifo level select 0x0000.0012 r/w uartifls 0x034 723 uart interrupt mask 0x0000.0000 r/w uartim 0x038 727 uart raw interrupt status 0x0000.0000 ro uartris 0x03c 731 uart masked interrupt status 0x0000.0000 ro uartmis 0x040 735 uart interrupt clear 0x0000.0000 w1c uarticr 0x044 737 uart dma control 0x0000.0000 r/w uartdmactl 0x048 738 uart lin control 0x0000.0000 r/w uartlctl 0x090 739 uart lin snap shot 0x0000.0000 ro uartlss 0x094 740 uart lin timer 0x0000.0000 ro uartltim 0x098 741 uart peripheral identification 4 0x0000.0000 ro uartperiphid4 0xfd0 742 uart peripheral identification 5 0x0000.0000 ro uartperiphid5 0xfd4 743 uart peripheral identification 6 0x0000.0000 ro uartperiphid6 0xfd8 744 uart peripheral identification 7 0x0000.0000 ro uartperiphid7 0xfdc 745 uart peripheral identification 0 0x0000.0060 ro uartperiphid0 0xfe0 746 uart peripheral identification 1 0x0000.0000 ro uartperiphid1 0xfe4 747 uart peripheral identification 2 0x0000.0018 ro uartperiphid2 0xfe8 748 uart peripheral identification 3 0x0000.0001 ro uartperiphid3 0xfec july 03, 2014 702 texas instruments-production data universal asynchronous receivers/transmitters (uarts) table 13-4. uart register map (continued) see page description reset type name offset 749 uart primecell identification 0 0x0000.000d ro uartpcellid0 0xff0 750 uart primecell identification 1 0x0000.00f0 ro uartpcellid1 0xff4 751 uart primecell identification 2 0x0000.0005 ro uartpcellid2 0xff8 752 uart primecell identification 3 0x0000.00b1 ro uartpcellid3 0xffc 13.6 register descriptions the remainder of this section lists and describes the uart registers, in numerical order by address offset. 703 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 1: uart data (uartdr), offset 0x000 important: this register is read-sensitive. see the register description for details. this register is the data register (the interface to the fifos). for transmitted data, if the fifo is enabled, data written to this location is pushed onto the transmit fifo. if the fifo is disabled, data is stored in the transmitter holding register (the bottom word of the transmit fifo). a write to this register initiates a transmission from the uart. for received data, if the fifo is enabled, the data byte and the 4-bit status (break, frame, parity, and overrun) is pushed onto the 12-bit wide receive fifo. if the fifo is disabled, the data byte and status are stored in the receiving holding register (the bottom word of the receive fifo). the received data can be retrieved by reading this register. uart data (uartdr) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0x000 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 data fe pe be oe reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0 ro reserved 31:12 uart overrun error description value new data was received when the fifo was full, resulting in data loss. 1 no data has been lost due to a fifo overrun. 0 0 ro oe 11 uart break error description value a break condition has been detected, indicating that the receive data input was held low for longer than a full-word transmission time (defined as start, data, parity, and stop bits). 1 no break condition has occurred 0 in fifo mode, this error is associated with the character at the top of the fifo. when a break occurs, only one 0 character is loaded into the fifo. the next character is only enabled after the received data input goes to a 1 (marking state), and the next valid start bit is received. 0 ro be 10 july 03, 2014 704 texas instruments-production data universal asynchronous receivers/transmitters (uarts) description reset type name bit/field uart parity error description value the parity of the received data character does not match the parity defined by bits 2 and 7 of the uartlcrh register. 1 no parity error has occurred 0 in fifo mode, this error is associated with the character at the top of the fifo. 0 ro pe 9 uart framing error description value the received character does not have a valid stop bit (a valid stop bit is 1). 1 no framing error has occurred 0 0 ro fe 8 data transmitted or received data that is to be transmitted via the uart is written to this field. when read, this field contains the data that was received by the uart. 0x00 r/w data 7:0 705 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 2: uart receive status/error clear (uartrsr/uartecr), offset 0x004 the uartrsr/uartecr register is the receive status register/error clear register. in addition to the uartdr register, receive status can also be read from the uartrsr register. if the status is read from this register, then the status information corresponds to the entry read from uartdr prior to reading uartrsr . the status information for overrun is set immediately when an overrun condition occurs. the uartrsr register cannot be written. a write of any value to the uartecr register clears the framing, parity, break, and overrun errors. all the bits are cleared on reset. read-only status register uart receive status/error clear (uartrsr/uartecr) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0x004 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 fe pe be oe reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:4 uart overrun error description value new data was received when the fifo was full, resulting in data loss. 1 no data has been lost due to a fifo overrun. 0 this bit is cleared by a write to uartecr . the fifo contents remain valid because no further data is written when the fifo is full, only the contents of the shift register are overwritten. the cpu must read the data in order to empty the fifo. 0 ro oe 3 july 03, 2014 706 texas instruments-production data universal asynchronous receivers/transmitters (uarts) description reset type name bit/field uart break error description value a break condition has been detected, indicating that the receive data input was held low for longer than a full-word transmission time (defined as start, data, parity, and stop bits). 1 no break condition has occurred 0 this bit is cleared to 0 by a write to uartecr . in fifo mode, this error is associated with the character at the top of the fifo. when a break occurs, only one 0 character is loaded into the fifo. the next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. 0 ro be 2 uart parity error description value the parity of the received data character does not match the parity defined by bits 2 and 7 of the uartlcrh register. 1 no parity error has occurred 0 this bit is cleared to 0 by a write to uartecr . 0 ro pe 1 uart framing error description value the received character does not have a valid stop bit (a valid stop bit is 1). 1 no framing error has occurred 0 this bit is cleared to 0 by a write to uartecr . in fifo mode, this error is associated with the character at the top of the fifo. 0 ro fe 0 write-only error clear register uart receive status/error clear (uartrsr/uartecr) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0x004 type wo, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 data reserved wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 707 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 wo reserved 31:8 error clear a write to this register of any data clears the framing, parity, break, and overrun flags. 0x00 wo data 7:0 july 03, 2014 708 texas instruments-production data universal asynchronous receivers/transmitters (uarts) register 3: uart flag (uartfr), offset 0x018 the uartfr register is the flag register. after reset, the txff, rxff , and busy bits are 0, and txfe and rxfe bits are 1. the ri, dcd, dsr and cts bits indicate the modem flow control and status. note that the modem bits are only implemented on uart1 and are reserved on uart0 and uart2. uart flag (uartfr) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0x018 type ro, reset 0x0000.0090 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cts dsr dcd busy rxfe txff rxff txfe ri reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:9 ring indicator description value the u1ri signal is asserted. 1 the u1ri signal is not asserted. 0 this bit is implemented only on uart1 and is reserved for uart0 and uart2. 0 ro ri 8 uart transmit fifo empty the meaning of this bit depends on the state of the fen bit in the uartlcrh register. description value if the fifo is disabled ( fen is 0), the transmit holding register is empty. if the fifo is enabled ( fen is 1), the transmit fifo is empty. 1 the transmitter has data to transmit. 0 1 ro txfe 7 709 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field uart receive fifo full the meaning of this bit depends on the state of the fen bit in the uartlcrh register. description value if the fifo is disabled ( fen is 0), the receive holding register is full. if the fifo is enabled ( fen is 1), the receive fifo is full. 1 the receiver can receive data. 0 0 ro rxff 6 uart transmit fifo full the meaning of this bit depends on the state of the fen bit in the uartlcrh register. description value if the fifo is disabled ( fen is 0), the transmit holding register is full. if the fifo is enabled ( fen is 1), the transmit fifo is full. 1 the transmitter is not full. 0 0 ro txff 5 uart receive fifo empty the meaning of this bit depends on the state of the fen bit in the uartlcrh register. description value if the fifo is disabled ( fen is 0), the receive holding register is empty. if the fifo is enabled ( fen is 1), the receive fifo is empty. 1 the receiver is not empty. 0 1 ro rxfe 4 uart busy description value the uart is busy transmitting data. this bit remains set until the complete byte, including all stop bits, has been sent from the shift register. 1 the uart is not busy. 0 this bit is set as soon as the transmit fifo becomes non-empty (regardless of whether uart is enabled). 0 ro busy 3 data carrier detect description value the u1dcd signal is asserted. 1 the u1dcd signal is not asserted. 0 this bit is implemented only on uart1 and is reserved for uart0 and uart2. 0 ro dcd 2 july 03, 2014 710 texas instruments-production data universal asynchronous receivers/transmitters (uarts) description reset type name bit/field data set ready description value the u1dsr signal is asserted. 1 the u1dsr signal is not asserted. 0 this bit is implemented only on uart1 and is reserved for uart0 and uart2. 0 ro dsr 1 clear to send description value the u1cts signal is asserted. 1 the u1cts signal is not asserted. 0 this bit is implemented only on uart1 and is reserved for uart0 and uart2. 0 ro cts 0 711 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 4: uart irda low-power register (uartilpr), offset 0x020 the uartilpr register stores the 8-bit low-power counter divisor value used to derive the low-power sir pulse width clock by dividing down the system clock (sysclk). all the bits are cleared when reset. the internal irlpbaud16 clock is generated by dividing down sysclk according to the low-power divisor value written to uartilpr . the duration of sir pulses generated when low-power mode is enabled is three times the period of the irlpbaud16 clock. the low-power divisor value is calculated as follows: ilpdvsr = sysclk / f irlpbaud16 where f irlpbaud16 is nominally 1.8432 mhz. the divisor must be programmed such that 1.42 mhz < f irlpbaud16 < 2.12 mhz, resulting in a low-power pulse duration of 1.41C2.11 s (three times the period of irlpbaud16 ). the minimum frequency of irlpbaud16 ensures that pulses less than one period of irlpbaud16 are rejected, but pulses greater than 1.4 s are accepted as valid pulses. note: zero is an illegal value. programming a zero value results in no irlpbaud16 pulses being generated. uart irda low-power register (uartilpr) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0x020 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ilpdvsr reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 irda low-power divisor this field contains the 8-bit low-power divisor value. 0x00 r/w ilpdvsr 7:0 july 03, 2014 712 texas instruments-production data universal asynchronous receivers/transmitters (uarts) register 5: uart integer baud-rate divisor (uartibrd), offset 0x024 the uartibrd register is the integer part of the baud-rate divisor value. all the bits are cleared on reset. the minimum possible divide ratio is 1 (when uartibrd =0), in which case the uartfbrd register is ignored. when changing the uartibrd register, the new value does not take effect until transmission/reception of the current character is complete. any changes to the baud-rate divisor must be followed by a write to the uartlcrh register. see baud-rate generation on page 693 for configuration details. uart integer baud-rate divisor (uartibrd) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0x024 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 divint r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 integer baud-rate divisor 0x0000 r/w divint 15:0 713 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 6: uart fractional baud-rate divisor (uartfbrd), offset 0x028 the uartfbrd register is the fractional part of the baud-rate divisor value. all the bits are cleared on reset. when changing the uartfbrd register, the new value does not take effect until transmission/reception of the current character is complete. any changes to the baud-rate divisor must be followed by a write to the uartlcrh register. see baud-rate generation on page 693 for configuration details. uart fractional baud-rate divisor (uartfbrd) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0x028 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 divfrac reserved r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:6 fractional baud-rate divisor 0x0 r/w divfrac 5:0 july 03, 2014 714 texas instruments-production data universal asynchronous receivers/transmitters (uarts) register 7: uart line control (uartlcrh), offset 0x02c the uartlcrh register is the line control register. serial parameters such as data length, parity, and stop bit selection are implemented in this register. when updating the baud-rate divisor ( uartibrd and/or uartifrd ), the uartlcrh register must also be written. the write strobe for the baud-rate divisor registers is tied to the uartlcrh register. uart line control (uartlcrh) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0x02c type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 brk pen eps stp2 fen wlen sps reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 uart stick parity select when bits 1, 2, and 7 of uartlcrh are set, the parity bit is transmitted and checked as a 0. when bits 1 and 7 are set and 2 is cleared, the parity bit is transmitted and checked as a 1. when this bit is cleared, stick parity is disabled. 0 r/w sps 7 uart word length the bits indicate the number of data bits transmitted or received in a frame as follows: description value 5 bits (default) 0x0 6 bits 0x1 7 bits 0x2 8 bits 0x3 0x0 r/w wlen 6:5 uart enable fifos description value the transmit and receive fifo buffers are enabled (fifo mode). 1 the fifos are disabled (character mode). the fifos become 1-byte-deep holding registers. 0 0 r/w fen 4 715 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field uart two stop bits select description value two stop bits are transmitted at the end of a frame. the receive logic does not check for two stop bits being received. when in 7816 smartcard mode (the smart bit is set in the uartctl register), the number of stop bits is forced to 2. 1 one stop bit is transmitted at the end of a frame. 0 0 r/w stp2 3 uart even parity select description value even parity generation and checking is performed during transmission and reception, which checks for an even number of 1s in data and parity bits. 1 odd parity is performed, which checks for an odd number of 1s. 0 this bit has no effect when parity is disabled by the pen bit. 0 r/w eps 2 uart parity enable description value parity checking and generation is enabled. 1 parity is disabled and no parity bit is added to the data frame. 0 0 r/w pen 1 uart send break description value a low level is continually output on the untx signal, after completing transmission of the current character. for the proper execution of the break command, software must set this bit for at least two frames (character periods). 1 normal use. 0 0 r/w brk 0 july 03, 2014 716 texas instruments-production data universal asynchronous receivers/transmitters (uarts) register 8: uart control (uartctl), offset 0x030 the uartctl register is the control register. all the bits are cleared on reset except for the transmit enable ( txe ) and receive enable (rxe ) bits, which are set. to enable the uart module, the uarten bit must be set. if software requires a configuration change in the module, the uarten bit must be cleared before the configuration changes are written. if the uart is disabled during a transmit or receive operation, the current transaction is completed prior to the uart stopping. note that bits [15:14,11:10] are only implemented on uart1. these bits are reserved on uart0 and uart2. note: the uartctl register should not be changed while the uart is enabled or else the results are unpredictable. the following sequence is recommended for making changes to the uartctl register. 1. disable the uart. 2. wait for the end of transmission or reception of the current character. 3. flush the transmit fifo by clearing bit 4 ( fen ) in the line control register (uartlcrh ). 4. reprogram the control register. 5. enable the uart. uart control (uartctl) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0x030 type r/w, reset 0x0000.0300 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 uarten siren sirlp smart eot hse lin lbe txe rxe dtr rts reserved rtsen ctsen r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro r/w r/w type 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 717 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field enable clear to send description value cts hardware flow control is enabled. data is only transmitted when the u1cts signal is asserted. 1 cts hardware flow control is disabled. 0 this bit is implemented only on uart1 and is reserved for uart0 and uart2. 0 r/w ctsen 15 enable request to send description value rts hardware flow control is enabled. data is only requested (by asserting u1rts ) when the receive fifo has available entries. 1 rts hardware flow control is disabled. 0 this bit is implemented only on uart1 and is reserved for uart0 and uart2. 0 r/w rtsen 14 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 13:12 request to send when rtsen is clear, the status of this bit is reflected on the u1rts signal. if rtsen is set, this bit is ignored on a write and should be ignored on read. this bit is implemented only on uart1 and is reserved for uart0 and uart2. 0 r/w rts 11 data terminal ready this bit sets the state of the u1dtr output. this bit is implemented only on uart1 and is reserved for uart0 and uart2. 0 r/w dtr 10 uart receive enable description value the receive section of the uart is enabled. 1 the receive section of the uart is disabled. 0 if the uart is disabled in the middle of a receive, it completes the current character before stopping. note: to enable reception, the uarten bit must also be set. 1 r/w rxe 9 july 03, 2014 718 texas instruments-production data universal asynchronous receivers/transmitters (uarts) description reset type name bit/field uart transmit enable description value the transmit section of the uart is enabled. 1 the transmit section of the uart is disabled. 0 if the uart is disabled in the middle of a transmission, it completes the current character before stopping. note: to enable transmission, the uarten bit must also be set. 1 r/w txe 8 uart loop back enable description value the untx path is fed through the unrx path. 1 normal operation. 0 0 r/w lbe 7 lin mode enable description value the uart operates in lin mode. 1 normal operation. 0 0 r/w lin 6 high-speed enable description value the uart is clocked using the system clock divided by 16. 0 the uart is clocked using the system clock divided by 8. 1 note: system clock used is also dependent on the baud-rate divisor configuration (see page 713) and page 714). the state of this bit has no effect on clock generation in iso 7816 smart card mode (the smart bit is set). 0 r/w hse 5 end of transmission this bit determines the behavior of the txris bit in the uartris register. description value the txris bit is set only after all transmitted data, including stop bits, have cleared the serializer. 1 the txris bit is set when the transmit fifo condition specified in uartifls is met. 0 0 r/w eot 4 719 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field iso 7816 smart card support description value the uart operates in smart card mode. 1 normal operation. 0 the application must ensure that it sets 8-bit word length ( wlen set to 0x3) and even parity ( pen set to 1, eps set to 1, sps set to 0) in uartlcrh when using iso 7816 mode. in this mode, the value of the stp2 bit in uartlcrh is ignored and the number of stop bits is forced to 2. note that the uart does not support automatic retransmission on parity errors. if a parity error is detected on transmission, all further transmit operations are aborted and software must handle retransmission of the affected byte or message. 0 r/w smart 3 uart sir low-power mode this bit selects the irda encoding mode. description value the uart operates in sir low-power mode. low-level bits are transmitted with a pulse width which is 3 times the period of the irlpbaud16 input signal, regardless of the selected bit rate. 1 low-level bits are transmitted as an active high pulse with a width of 3/16th of the bit period. 0 setting this bit uses less power, but might reduce transmission distances. see page 712 for more information. 0 r/w sirlp 2 uart sir enable description value the irda sir block is enabled, and the uart will transmit and receive data using sir protocol. 1 normal operation. 0 0 r/w siren 1 uart enable description value the uart is enabled. 1 the uart is disabled. 0 if the uart is disabled in the middle of transmission or reception, it completes the current character before stopping. 0 r/w uarten 0 july 03, 2014 720 texas instruments-production data universal asynchronous receivers/transmitters (uarts) register 9: uart interrupt fifo level select (uartifls), offset 0x034 the uartifls register is the interrupt fifo level select register. you can use this register to define the fifo level at which the txris and rxris bits in the uartris register are triggered. the interrupts are generated based on a transition through a level rather than being based on the level. that is, the interrupts are generated when the fill level progresses through the trigger level. for example, if the receive trigger level is set to the half-way mark, the interrupt is triggered as the module is receiving the 9th character. out of reset, the txiflsel and rxiflsel bits are configured so that the fifos trigger an interrupt at the half-way mark. uart interrupt fifo level select (uartifls) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0x034 type r/w, reset 0x0000.0012 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 txiflsel rxiflsel reserved r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro type 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:6 uart receive interrupt fifo level select the trigger points for the receive interrupt are as follows: description value rx fifo ? full 0x0 rx fifo ? full 0x1 rx fifo ? full (default) 0x2 rx fifo ? full 0x3 rx fifo ? full 0x4 reserved 0x5-0x7 0x2 r/w rxiflsel 5:3 721 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field uart transmit interrupt fifo level select the trigger points for the transmit interrupt are as follows: description value tx fifo ? empty 0x0 tx fifo ? empty 0x1 tx fifo ? empty (default) 0x2 tx fifo ? empty 0x3 tx fifo ? empty 0x4 reserved 0x5-0x7 note: if the eot bit in uartctl is set (see page 717), the transmit interrupt is generated once the fifo is completely empty and all data including stop bits have left the transmit serializer. in this case, the setting of txiflsel is ignored. 0x2 r/w txiflsel 2:0 july 03, 2014 722 texas instruments-production data universal asynchronous receivers/transmitters (uarts) register 10: uart interrupt mask (uartim), offset 0x038 the uartim register is the interrupt mask set/clear register. on a read, this register gives the current value of the mask on the relevant interrupt. setting a bit allows the corresponding raw interrupt signal to be routed to the interrupt controller. clearing a bit prevents the raw interrupt signal from being sent to the interrupt controller. note that bits [3:0] are only implemented on uart1. these bits are reserved on uart0 and uart2. uart interrupt mask (uartim) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0x038 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 riim ctsim dcdim dsrim rxim txim rtim feim peim beim oeim reserved lmsbim lme1im lme5im r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:16 lin mode edge 5 interrupt mask description value an interrupt is sent to the interrupt controller when the lme5ris bit in the uartris register is set. 1 the lme5ris interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w lme5im 15 lin mode edge 1 interrupt mask description value an interrupt is sent to the interrupt controller when the lme1ris bit in the uartris register is set. 1 the lme1ris interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w lme1im 14 lin mode sync break interrupt mask description value an interrupt is sent to the interrupt controller when the lmsbris bit in the uartris register is set. 1 the lmsbris interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w lmsbim 13 723 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 12:11 uart overrun error interrupt mask description value an interrupt is sent to the interrupt controller when the oeris bit in the uartris register is set. 1 the oeris interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w oeim 10 uart break error interrupt mask description value an interrupt is sent to the interrupt controller when the beris bit in the uartris register is set. 1 the beris interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w beim 9 uart parity error interrupt mask description value an interrupt is sent to the interrupt controller when the peris bit in the uartris register is set. 1 the peris interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w peim 8 uart framing error interrupt mask description value an interrupt is sent to the interrupt controller when the feris bit in the uartris register is set. 1 the feris interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w feim 7 uart receive time-out interrupt mask description value an interrupt is sent to the interrupt controller when the rtris bit in the uartris register is set. 1 the rtris interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w rtim 6 july 03, 2014 724 texas instruments-production data universal asynchronous receivers/transmitters (uarts) description reset type name bit/field uart transmit interrupt mask description value an interrupt is sent to the interrupt controller when the txris bit in the uartris register is set. 1 the txris interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w txim 5 uart receive interrupt mask description value an interrupt is sent to the interrupt controller when the rxris bit in the uartris register is set. 1 the rxris interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w rxim 4 uart data set ready modem interrupt mask description value an interrupt is sent to the interrupt controller when the dsrris bit in the uartris register is set. 1 the dsrris interrupt is suppressed and not sent to the interrupt controller. 0 this bit is implemented only on uart1 and is reserved for uart0 and uart2. 0 r/w dsrim 3 uart data carrier detect modem interrupt mask description value an interrupt is sent to the interrupt controller when the dcdris bit in the uartris register is set. 1 the dcdris interrupt is suppressed and not sent to the interrupt controller. 0 this bit is implemented only on uart1 and is reserved for uart0 and uart2. 0 r/w dcdim 2 uart clear to send modem interrupt mask description value an interrupt is sent to the interrupt controller when the ctsris bit in the uartris register is set. 1 the ctsris interrupt is suppressed and not sent to the interrupt controller. 0 this bit is implemented only on uart1 and is reserved for uart0 and uart2. 0 r/w ctsim 1 725 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field uart ring indicator modem interrupt mask description value an interrupt is sent to the interrupt controller when the riris bit in the uartris register is set. 1 the riris interrupt is suppressed and not sent to the interrupt controller. 0 this bit is implemented only on uart1 and is reserved for uart0 and uart2. 0 r/w riim 0 july 03, 2014 726 texas instruments-production data universal asynchronous receivers/transmitters (uarts) register 11: uart raw interrupt status (uartris), offset 0x03c the uartris register is the raw interrupt status register. on a read, this register gives the current raw status value of the corresponding interrupt. a write has no effect. note that bits [3:0] are only implemented on uart1. these bits are reserved on uart0 and uart2. uart raw interrupt status (uartris) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0x03c type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 riris ctsris dcdris dsrris rxris txris rtris feris peris beris oeris reserved lmsbris lme1ris lme5ris ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:16 lin mode edge 5 raw interrupt status description value the timer value at the 5th falling edge of the lin sync field has been captured. 1 no interrupt 0 this bit is cleared by writing a 1 to the lme5ic bit in the uarticr register. 0 ro lme5ris 15 lin mode edge 1 raw interrupt status description value the timer value at the 1st falling edge of the lin sync field has been captured. 1 no interrupt 0 this bit is cleared by writing a 1 to the lme1ic bit in the uarticr register. 0 ro lme1ris 14 lin mode sync break raw interrupt status description value a lin sync break has been detected. 1 no interrupt 0 this bit is cleared by writing a 1 to the lmsbic bit in the uarticr register. 0 ro lmsbris 13 727 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 12:11 uart overrun error raw interrupt status description value an overrun error has occurred. 1 no interrupt 0 this bit is cleared by writing a 1 to the oeic bit in the uarticr register. 0 ro oeris 10 uart break error raw interrupt status description value a break error has occurred. 1 no interrupt 0 this bit is cleared by writing a 1 to the beic bit in the uarticr register. 0 ro beris 9 uart parity error raw interrupt status description value a parity error has occurred. 1 no interrupt 0 this bit is cleared by writing a 1 to the peic bit in the uarticr register. 0 ro peris 8 uart framing error raw interrupt status description value a framing error has occurred. 1 no interrupt 0 this bit is cleared by writing a 1 to the feic bit in the uarticr register. 0 ro feris 7 uart receive time-out raw interrupt status description value a receive time out has occurred. 1 no interrupt 0 this bit is cleared by writing a 1 to the rtic bit in the uarticr register. 0 ro rtris 6 july 03, 2014 728 texas instruments-production data universal asynchronous receivers/transmitters (uarts) description reset type name bit/field uart transmit raw interrupt status description value if the eot bit in the uartctl register is clear, the transmit fifo level has passed through the condition defined in the uartifls register. if the eot bit is set, the last bit of all transmitted data and flags has left the serializer. 1 no interrupt 0 this bit is cleared by writing a 1 to the txic bit in the uarticr register or by writing data to the transmit fifo until it becomes greater than the trigger level, if the fifo is enabled, or by writing a single byte if the fifo is disabled. 0 ro txris 5 uart receive raw interrupt status description value the receive fifo level has passed through the condition defined in the uartifls register. 1 no interrupt 0 this bit is cleared by writing a 1 to the rxic bit in the uarticr register or by reading data from the receive fifo until it becomes less than the trigger level, if the fifo is enabled, or by reading a single byte if the fifo is disabled. 0 ro rxris 4 uart data set ready modem raw interrupt status description value data set ready used for software flow control. 1 no interrupt 0 this bit is cleared by writing a 1 to the dsric bit in the uarticr register. this bit is implemented only on uart1 and is reserved for uart0 and uart2. 0 ro dsrris 3 uart data carrier detect modem raw interrupt status description value data carrier detect used for software flow control. 1 no interrupt 0 this bit is cleared by writing a 1 to the dcdic bit in the uarticr register. this bit is implemented only on uart1 and is reserved for uart0 and uart2. 0 ro dcdris 2 729 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field uart clear to send modem raw interrupt status description value clear to send used for software flow control. 1 no interrupt 0 this bit is cleared by writing a 1 to the ctsic bit in the uarticr register. this bit is implemented only on uart1 and is reserved for uart0 and uart2. 0 ro ctsris 1 uart ring indicator modem raw interrupt status description value ring indicator used for software flow control. 1 no interrupt 0 this bit is cleared by writing a 1 to the riic bit in the uarticr register. this bit is implemented only on uart1 and is reserved for uart0 and uart2. 0 ro riris 0 july 03, 2014 730 texas instruments-production data universal asynchronous receivers/transmitters (uarts) register 12: uart masked interrupt status (uartmis), offset 0x040 the uartmis register is the masked interrupt status register. on a read, this register gives the current masked status value of the corresponding interrupt. a write has no effect. note that bits [3:0] are only implemented on uart1. these bits are reserved on uart0 and uart2. uart masked interrupt status (uartmis) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0x040 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rimis ctsmis dcdmis dsrmis rxmis txmis rtmis femis pemis bemis oemis reserved lmsbmis lme1mis lme5mis ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:16 lin mode edge 5 masked interrupt status description value an unmasked interrupt was signaled due to the 5th falling edge of the lin sync field. 1 an interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the lme5ic bit in the uarticr register. 0 ro lme5mis 15 lin mode edge 1 masked interrupt status description value an unmasked interrupt was signaled due to the 1st falling edge of the lin sync field. 1 an interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the lme1ic bit in the uarticr register. 0 ro lme1mis 14 lin mode sync break masked interrupt status description value an unmasked interrupt was signaled due to the receipt of a lin sync break. 1 an interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the lmsbic bit in the uarticr register. 0 ro lmsbmis 13 731 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 12:11 uart overrun error masked interrupt status description value an unmasked interrupt was signaled due to an overrun error. 1 an interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the oeic bit in the uarticr register. 0 ro oemis 10 uart break error masked interrupt status description value an unmasked interrupt was signaled due to a break error. 1 an interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the beic bit in the uarticr register. 0 ro bemis 9 uart parity error masked interrupt status description value an unmasked interrupt was signaled due to a parity error. 1 an interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the peic bit in the uarticr register. 0 ro pemis 8 uart framing error masked interrupt status description value an unmasked interrupt was signaled due to a framing error. 1 an interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the feic bit in the uarticr register. 0 ro femis 7 uart receive time-out masked interrupt status description value an unmasked interrupt was signaled due to a receive time out. 1 an interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the rtic bit in the uarticr register. 0 ro rtmis 6 july 03, 2014 732 texas instruments-production data universal asynchronous receivers/transmitters (uarts) description reset type name bit/field uart transmit masked interrupt status description value an unmasked interrupt was signaled due to passing through the specified transmit fifo level (if the eot bit is clear) or due to the transmission of the last data bit (if the eot bit is set). 1 an interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the txic bit in the uarticr register or by writing data to the transmit fifo until it becomes greater than the trigger level, if the fifo is enabled, or by writing a single byte if the fifo is disabled. 0 ro txmis 5 uart receive masked interrupt status description value an unmasked interrupt was signaled due to passing through the specified receive fifo level. 1 an interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the rxic bit in the uarticr register or by reading data from the receive fifo until it becomes less than the trigger level, if the fifo is enabled, or by reading a single byte if the fifo is disabled. 0 ro rxmis 4 uart data set ready modem masked interrupt status description value an unmasked interrupt was signaled due to data set ready. 1 an interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the dsric bit in the uarticr register. this bit is implemented only on uart1 and is reserved for uart0 and uart2. 0 ro dsrmis 3 uart data carrier detect modem masked interrupt status description value an unmasked interrupt was signaled due to data carrier detect. 1 an interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the dcdic bit in the uarticr register. this bit is implemented only on uart1 and is reserved for uart0 and uart2. 0 ro dcdmis 2 733 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field uart clear to send modem masked interrupt status description value an unmasked interrupt was signaled due to clear to send. 1 an interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the ctsic bit in the uarticr register. this bit is implemented only on uart1 and is reserved for uart0 and uart2. 0 ro ctsmis 1 uart ring indicator modem masked interrupt status description value an unmasked interrupt was signaled due to ring indicator. 1 an interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the riic bit in the uarticr register. this bit is implemented only on uart1 and is reserved for uart0 and uart2. 0 ro rimis 0 july 03, 2014 734 texas instruments-production data universal asynchronous receivers/transmitters (uarts) register 13: uart interrupt clear (uarticr), offset 0x044 the uarticr register is the interrupt clear register. on a write of 1, the corresponding interrupt (both raw interrupt and masked interrupt, if enabled) is cleared. a write of 0 has no effect. note that bits [3:0] are only implemented on uart1. these bits are reserved on uart0 and uart2. uart interrupt clear (uarticr) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0x044 type w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rimic ctsmic dcdmic dsrmic rxic txic rtic feic peic beic oeic reserved lmsbic lme1ic lme5ic w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c ro ro w1c w1c w1c type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:16 lin mode edge 5 interrupt clear writing a 1 to this bit clears the lme5ris bit in the uartris register and the lme5mis bit in the uartmis register. 0 w1c lme5ic 15 lin mode edge 1 interrupt clear writing a 1 to this bit clears the lme1ris bit in the uartris register and the lme1mis bit in the uartmis register. 0 w1c lme1ic 14 lin mode sync break interrupt clear writing a 1 to this bit clears the lmsbris bit in the uartris register and the lmsbmis bit in the uartmis register. 0 w1c lmsbic 13 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 12:11 overrun error interrupt clear writing a 1 to this bit clears the oeris bit in the uartris register and the oemis bit in the uartmis register. 0 w1c oeic 10 break error interrupt clear writing a 1 to this bit clears the beris bit in the uartris register and the bemis bit in the uartmis register. 0 w1c beic 9 parity error interrupt clear writing a 1 to this bit clears the peris bit in the uartris register and the pemis bit in the uartmis register. 0 w1c peic 8 735 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field framing error interrupt clear writing a 1 to this bit clears the feris bit in the uartris register and the femis bit in the uartmis register. 0 w1c feic 7 receive time-out interrupt clear writing a 1 to this bit clears the rtris bit in the uartris register and the rtmis bit in the uartmis register. 0 w1c rtic 6 transmit interrupt clear writing a 1 to this bit clears the txris bit in the uartris register and the txmis bit in the uartmis register. 0 w1c txic 5 receive interrupt clear writing a 1 to this bit clears the rxris bit in the uartris register and the rxmis bit in the uartmis register. 0 w1c rxic 4 uart data set ready modem interrupt clear writing a 1 to this bit clears the dsrris bit in the uartris register and the dsrmis bit in the uartmis register. this bit is implemented only on uart1 and is reserved for uart0 and uart2. 0 w1c dsrmic 3 uart data carrier detect modem interrupt clear writing a 1 to this bit clears the dcdris bit in the uartris register and the dcdmis bit in the uartmis register. this bit is implemented only on uart1 and is reserved for uart0 and uart2. 0 w1c dcdmic 2 uart clear to send modem interrupt clear writing a 1 to this bit clears the ctsris bit in the uartris register and the ctsmis bit in the uartmis register. this bit is implemented only on uart1 and is reserved for uart0 and uart2. 0 w1c ctsmic 1 uart ring indicator modem interrupt clear writing a 1 to this bit clears the riris bit in the uartris register and the rimis bit in the uartmis register. this bit is implemented only on uart1 and is reserved for uart0 and uart2. 0 w1c rimic 0 july 03, 2014 736 texas instruments-production data universal asynchronous receivers/transmitters (uarts) register 14: uart dma control (uartdmactl), offset 0x048 the uartdmactl register is the dma control register. uart dma control (uartdmactl) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0x048 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rxdmae txdmae dmaerr reserved r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00000.000 ro reserved 31:3 dma on error description value dma receive requests are automatically disabled when a receive error occurs. 1 dma receive requests are unaffected when a receive error occurs. 0 0 r/w dmaerr 2 transmit dma enable description value dma for the transmit fifo is enabled. 1 dma for the transmit fifo is disabled. 0 0 r/w txdmae 1 receive dma enable description value dma for the receive fifo is enabled. 1 dma for the receive fifo is disabled. 0 0 r/w rxdmae 0 737 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 15: uart lin control (uartlctl), offset 0x090 the uartlctl register is the configures the operation of the uart when in lin mode. uart lin control (uartlctl) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0x090 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 master reserved blen reserved r/w ro ro ro r/w r/w ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:6 sync break length description value sync break length is 16t bits 0x3 sync break length is 15t bits 0x2 sync break length is 14t bits 0x1 sync break length is 13t bits (default) 0x0 0x0 r/w blen 5:4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 3:1 lin master enable description value the uart operates as a lin master. 1 the uart operates as a lin slave. 0 0 r/w master 0 july 03, 2014 738 texas instruments-production data universal asynchronous receivers/transmitters (uarts) register 16: uart lin snap shot (uartlss), offset 0x094 the uartlss register captures the free-running timer value when either the sync edge 1 or the sync edge 5 is detected in lin mode. uart lin snap shot (uartlss) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0x094 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tss ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 timer snap shot this field contains the value of the free-running timer when either the sync edge 5 or the sync edge 1 was detected. 0x0000 ro tss 15:0 739 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 17: uart lin timer (uartltim), offset 0x098 the uartltim register contains the current timer value for the free-running timer that is used to calculate the baud rate when in lin slave mode. the value in this register is used along with the value in the uart lin snap shot (uartlss) register to adjust the baud rate to match that of the master. uart lin timer (uartltim) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0x098 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 timer ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 timer value this field contains the value of the free-running timer. 0x0000 ro timer 15:0 july 03, 2014 740 texas instruments-production data universal asynchronous receivers/transmitters (uarts) register 18: uart peripheral identification 4 (uartperiphid4), offset 0xfd0 the uartperiphidn registers are hard-coded and the fields within the registers determine the reset values. uart peripheral identification 4 (uartperiphid4) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0xfd0 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid4 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 uart peripheral id register [7:0] can be used by software to identify the presence of this peripheral. 0x00 ro pid4 7:0 741 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 19: uart peripheral identification 5 (uartperiphid5), offset 0xfd4 the uartperiphidn registers are hard-coded and the fields within the registers determine the reset values. uart peripheral identification 5 (uartperiphid5) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0xfd4 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid5 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 uart peripheral id register [15:8] can be used by software to identify the presence of this peripheral. 0x00 ro pid5 7:0 july 03, 2014 742 texas instruments-production data universal asynchronous receivers/transmitters (uarts) register 20: uart peripheral identification 6 (uartperiphid6), offset 0xfd8 the uartperiphidn registers are hard-coded and the fields within the registers determine the reset values. uart peripheral identification 6 (uartperiphid6) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0xfd8 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid6 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 uart peripheral id register [23:16] can be used by software to identify the presence of this peripheral. 0x00 ro pid6 7:0 743 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 21: uart peripheral identification 7 (uartperiphid7), offset 0xfdc the uartperiphidn registers are hard-coded and the fields within the registers determine the reset values. uart peripheral identification 7 (uartperiphid7) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0xfdc type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid7 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 uart peripheral id register [31:24] can be used by software to identify the presence of this peripheral. 0x00 ro pid7 7:0 july 03, 2014 744 texas instruments-production data universal asynchronous receivers/transmitters (uarts) register 22: uart peripheral identification 0 (uartperiphid0), offset 0xfe0 the uartperiphidn registers are hard-coded and the fields within the registers determine the reset values. uart peripheral identification 0 (uartperiphid0) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0xfe0 type ro, reset 0x0000.0060 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid0 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 uart peripheral id register [7:0] can be used by software to identify the presence of this peripheral. 0x60 ro pid0 7:0 745 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 23: uart peripheral identification 1 (uartperiphid1), offset 0xfe4 the uartperiphidn registers are hard-coded and the fields within the registers determine the reset values. uart peripheral identification 1 (uartperiphid1) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0xfe4 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid1 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 uart peripheral id register [15:8] can be used by software to identify the presence of this peripheral. 0x00 ro pid1 7:0 july 03, 2014 746 texas instruments-production data universal asynchronous receivers/transmitters (uarts) register 24: uart peripheral identification 2 (uartperiphid2), offset 0xfe8 the uartperiphidn registers are hard-coded and the fields within the registers determine the reset values. uart peripheral identification 2 (uartperiphid2) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0xfe8 type ro, reset 0x0000.0018 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid2 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 uart peripheral id register [23:16] can be used by software to identify the presence of this peripheral. 0x18 ro pid2 7:0 747 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 25: uart peripheral identification 3 (uartperiphid3), offset 0xfec the uartperiphidn registers are hard-coded and the fields within the registers determine the reset values. uart peripheral identification 3 (uartperiphid3) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0xfec type ro, reset 0x0000.0001 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 uart peripheral id register [31:24] can be used by software to identify the presence of this peripheral. 0x01 ro pid3 7:0 july 03, 2014 748 texas instruments-production data universal asynchronous receivers/transmitters (uarts) register 26: uart primecell identification 0 (uartpcellid0), offset 0xff0 the uartpcellidn registers are hard-coded and the fields within the registers determine the reset values. uart primecell identification 0 (uartpcellid0) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0xff0 type ro, reset 0x0000.000d 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cid0 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 uart primecell id register [7:0] provides software a standard cross-peripheral identification system. 0x0d ro cid0 7:0 749 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 27: uart primecell identification 1 (uartpcellid1), offset 0xff4 the uartpcellidn registers are hard-coded and the fields within the registers determine the reset values. uart primecell identification 1 (uartpcellid1) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0xff4 type ro, reset 0x0000.00f0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cid1 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 uart primecell id register [15:8] provides software a standard cross-peripheral identification system. 0xf0 ro cid1 7:0 july 03, 2014 750 texas instruments-production data universal asynchronous receivers/transmitters (uarts) register 28: uart primecell identification 2 (uartpcellid2), offset 0xff8 the uartpcellidn registers are hard-coded and the fields within the registers determine the reset values. uart primecell identification 2 (uartpcellid2) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0xff8 type ro, reset 0x0000.0005 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cid2 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 uart primecell id register [23:16] provides software a standard cross-peripheral identification system. 0x05 ro cid2 7:0 751 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 29: uart primecell identification 3 (uartpcellid3), offset 0xffc the uartpcellidn registers are hard-coded and the fields within the registers determine the reset values. uart primecell identification 3 (uartpcellid3) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 offset 0xffc type ro, reset 0x0000.00b1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cid3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 uart primecell id register [31:24] provides software a standard cross-peripheral identification system. 0xb1 ro cid3 7:0 july 03, 2014 752 texas instruments-production data universal asynchronous receivers/transmitters (uarts) 14 synchronous serial interface (ssi) the stellaris ? microcontroller includes two synchronous serial interface (ssi) modules. each ssi is a master or slave interface for synchronous serial communication with peripheral devices that have either freescale spi, microwire, or texas instruments synchronous serial interfaces. the stellaris lm3s9gn5 controller includes two ssi modules with the following features: programmable interface operation for freescale spi, microwire, or texas instruments synchronous serial interfaces master or slave operation programmable clock bit rate and prescaler separate transmit and receive fifos, each 16 bits wide and 8 locations deep programmable data frame size from 4 to 16 bits internal loopback test mode for diagnostic/debug testing standard fifo-based interrupts and end-of-transmission interrupt efficient transfers using micro direct memory access controller (dma) C separate channels for transmit and receive C receive single request asserted when data is in the fifo; burst request asserted when fifo contains 4 entries C transmit single request asserted when there is space in the fifo; burst request asserted when fifo contains 4 entries 753 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 14.1 block diagram figure 14-1. ssi module block diagram 14.2 signal description the following table lists the external signals of the ssi module and describes the function of each. the ssi signals are alternate functions for some gpio signals and default to be gpio signals at reset., with the exception of the ssi0clk, ssi0fss, ssi0rx , and ssi0tx pins which default to the ssi function. the column in the table below titled "pin mux/pin assignment" lists the possible gpio pin placements for the ssi signals. the afsel bit in the gpio alternate function select (gpioafsel) register (page 429) should be set to choose the ssi function. the number in july 03, 2014 754 texas instruments-production data synchronous serial interface (ssi) , g h q w l i l f d w l r q 5 h j l v w h u v 6 6 , 3 & h o o , ' 6 6 , 3 & h o o , ' 6 6 , 3 & h o o , ' 6 6 , 3 & h o o , ' 6 6 , 3 h u l s k , ' 6 6 , 3 h u l s k , ' 6 6 , 3 h u l s k , ' 6 6 , 3 h u l s k , ' 6 6 , 3 h u l s k , ' 6 6 , 3 h u l s k , ' 6 6 , 3 h u l s k , ' 6 6 , 3 h u l s k , ' & o r f n 3 u h v f d o h u 6 6 , & 3 6 5 & r q w u r o 6 w d w x v , q w h u u x s w & r q w u r o 6 6 , ' 5 7 [ ) , ) 2 [ 5 [ ) , ) 2 [ 7 u d q v p l w 5 h f h l y h / r j l f 6 6 , 7 [ 6 6 , 5 [ 6 6 , & o n 6 6 , ) v v ' 0 $ & r q w u r o 6 6 , ' 0 $ & 7 / ' 0 $ 5 h t x h v w , q w h u u x s w 6 \ v w h p & o r f n 6 6 , 6 5 6 6 , & 5 6 6 , & 5 6 6 , 5 , 6 6 6 , 0 , 6 6 6 , , 0 6 6 , , & 5 parentheses is the encoding that must be programmed into the pmcn field in the gpio port control (gpiopctl) register (page 447) to assign the ssi signal to the specified gpio port pin. for more information on configuring gpios, see general-purpose input/outputs (gpios) on page 405. table 14-1. ssi signals (100lqfp) description buffer type a pin type pin mux / pin assignment pin number pin name ssi module 0 clock. ttl i/o pa2 (1) 28 ssi0clk ssi module 0 frame signal. ttl i/o pa3 (1) 29 ssi0fss ssi module 0 receive. ttl i pa4 (1) 30 ssi0rx ssi module 0 transmit. ttl o pa5 (1) 31 ssi0tx ssi module 1 clock. ttl i/o pf2 (9) pe0 (2) ph4 (11) 60 74 76 ssi1clk ssi module 1 frame signal. ttl i/o pf3 (9) ph5 (11) pe1 (2) 59 63 75 ssi1fss ssi module 1 receive. ttl i pf4 (9) ph6 (11) pe2 (2) 58 62 95 ssi1rx ssi module 1 transmit. ttl o ph7 (11) pf5 (9) pe3 (2) 15 46 96 ssi1tx a. the ttl designation indicates the pin has ttl-compatible voltage levels. table 14-2. ssi signals (108bga) description buffer type a pin type pin mux / pin assignment pin number pin name ssi module 0 clock. ttl i/o pa2 (1) m4 ssi0clk ssi module 0 frame signal. ttl i/o pa3 (1) l4 ssi0fss ssi module 0 receive. ttl i pa4 (1) l5 ssi0rx ssi module 0 transmit. ttl o pa5 (1) m5 ssi0tx ssi module 1 clock. ttl i/o pf2 (9) pe0 (2) ph4 (11) j11 b11 b10 ssi1clk ssi module 1 frame signal. ttl i/o pf3 (9) ph5 (11) pe1 (2) j12 f10 a12 ssi1fss ssi module 1 receive. ttl i pf4 (9) ph6 (11) pe2 (2) l9 g3 a4 ssi1rx ssi module 1 transmit. ttl o ph7 (11) pf5 (9) pe3 (2) h3 l8 b4 ssi1tx a. the ttl designation indicates the pin has ttl-compatible voltage levels. 14.3 functional description the ssi performs serial-to-parallel conversion on data received from a peripheral device. the cpu accesses data, control, and status information. the transmit and receive paths are buffered with internal fifo memories allowing up to eight 16-bit values to be stored independently in both transmit 755 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller and receive modes. the ssi also supports the dma interface. the transmit and receive fifos can be programmed as destination/source addresses in the dma module. dma operation is enabled by setting the appropriate bit(s) in the ssidmactl register (see page 782). 14.3.1 bit rate generation the ssi includes a programmable bit rate clock divider and prescaler to generate the serial output clock. bit rates are supported to 2 mhz and higher, although maximum bit rate is determined by peripheral devices. the serial bit rate is derived by dividing down the input clock (sysclk). the clock is first divided by an even prescale value cpsdvsr from 2 to 254, which is programmed in the ssi clock prescale (ssicpsr) register (see page 775). the clock is further divided by a value from 1 to 256, which is 1 + scr , where scr is the value programmed in the ssi control 0 (ssicr0) register (see page 768). the frequency of the output clock ssiclk is defined by: ssiclk = sysclk / (cpsdvsr * (1 + scr)) note: for master mode, the system clock must be at least two times faster than the ssiclk , with the restriction that ssiclk cannot be faster than 25 mhz. for slave mode, the system clock must be at least 12 times faster than the ssiclk. see synchronous serial interface (ssi) on page 1314 to view ssi timing parameters. 14.3.2 fifo operation 14.3.2.1 transmit fifo the common transmit fifo is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. the cpu writes data to the fifo by writing the ssi data (ssidr) register (see page 772), and data is stored in the fifo until it is read out by the transmission logic. when configured as a master or a slave, parallel data is written into the transmit fifo prior to serial conversion and transmission to the attached slave or master, respectively, through the ssitx pin. in slave mode, the ssi transmits data each time the master initiates a transaction. if the transmit fifo is empty and the master initiates, the slave transmits the 8th most recent value in the transmit fifo. if less than 8 values have been written to the transmit fifo since the ssi module clock was enabled using the ssi bit in the rgcg1 register, then 0 is transmitted. care should be taken to ensure that valid data is in the fifo as needed. the ssi can be configured to generate an interrupt or a dma request when the fifo is empty. 14.3.2.2 receive fifo the common receive fifo is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. received data from the serial interface is stored in the buffer until read out by the cpu, which accesses the read fifo by reading the ssidr register. when configured as a master or slave, serial data received through the ssirx pin is registered prior to parallel loading into the attached slave or master receive fifo, respectively. 14.3.3 interrupts the ssi can generate interrupts when the following conditions are observed: transmit fifo service (when the transmit fifo is half full or less) receive fifo service (when the receive fifo is half full or more) july 03, 2014 756 texas instruments-production data synchronous serial interface (ssi) receive fifo time-out receive fifo overrun end of transmission all of the interrupt events are ored together before being sent to the interrupt controller, so the ssi generates a single interrupt request to the controller regardless of the number of active interrupts. each of the four individual maskable interrupts can be masked by clearing the appropriate bit in the ssi interrupt mask (ssiim) register (see page 776). setting the appropriate mask bit enables the interrupt. the individual outputs, along with a combined interrupt output, allow use of either a global interrupt service routine or modular device drivers to handle interrupts. the transmit and receive dynamic dataflow interrupts have been separated from the status interrupts so that data can be read or written in response to the fifo trigger levels. the status of the individual interrupt sources can be read from the ssi raw interrupt status (ssiris) and ssi masked interrupt status (ssimis) registers (see page 777 and page 779, respectively). the receive fifo has a time-out period that is 32 periods at the rate of ssiclk (whether or not ssiclk is currently active) and is started when the rx fifo goes from empty to not-empty. if the rx fifo is emptied before 32 clocks have passed, the time-out period is reset. as a result, the isr should clear the receive fifo time-out interrupt just after reading out the rx fifo by writing a 1 to the rtic bit in the ssi interrupt clear (ssiicr) register. the interrupt should not be cleared so late that the isr returns before the interrupt is actually cleared, or the isr may be re-activated unnecessarily. the end-of-transmission (eot) interrupt indicates that the data has been transmitted completely. this interrupt can be used to indicate when it is safe to turn off the ssi module clock or enter sleep mode. in addition, because transmitted data and received data complete at exactly the same time, the interrupt can also indicate that read data is ready immediately, without waiting for the receive fifo time-out period to complete. 14.3.4 frame formats each data frame is between 4 and 16 bits long, depending on the size of data programmed, and is transmitted starting with the msb. there are three basic frame types that can be selected: texas instruments synchronous serial freescale spi microwire for all three formats, the serial clock ( ssiclk ) is held inactive while the ssi is idle, and ssiclk transitions at the programmed frequency only during active transmission or reception of data. the idle state of ssiclk is utilized to provide a receive timeout indication that occurs when the receive fifo still contains data after a timeout period. for freescale spi and microwire frame formats, the serial frame ( ssifss ) pin is active low, and is asserted (pulled down) during the entire transmission of the frame. for texas instruments synchronous serial frame format, the ssifss pin is pulsed for one serial clock period starting at its rising edge, prior to the transmission of each frame. for this frame format, both the ssi and the off-chip slave device drive their output data on the rising edge of ssiclk and latch data from the other device on the falling edge. 757 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller unlike the full-duplex transmission of the other two frame formats, the microwire format uses a special master-slave messaging technique which operates at half-duplex. in this mode, when a frame begins, an 8-bit control message is transmitted to the off-chip slave. during this transmit, no incoming data is received by the ssi. after the message has been sent, the off-chip slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent, responds with the requested data. the returned data can be 4 to 16 bits in length, making the total frame length anywhere from 13 to 25 bits. 14.3.4.1 texas instruments synchronous serial frame format figure 14-2 on page 758 shows the texas instruments synchronous serial frame format for a single transmitted frame. figure 14-2. ti synchronous serial frame format (single transfer) in this mode, ssiclk and ssifss are forced low, and the transmit data line ssitx is tristated whenever the ssi is idle. once the bottom entry of the transmit fifo contains data, ssifss is pulsed high for one ssiclk period. the value to be transmitted is also transferred from the transmit fifo to the serial shift register of the transmit logic. on the next rising edge of ssiclk , the msb of the 4 to 16-bit data frame is shifted out on the ssitx pin. likewise, the msb of the received data is shifted onto the ssirx pin by the off-chip serial slave device. both the ssi and the off-chip serial slave device then clock each data bit into their serial shifter on each falling edge of ssiclk . the received data is transferred from the serial shifter to the receive fifo on the first rising edge of ssiclk after the lsb has been latched. figure 14-3 on page 758 shows the texas instruments synchronous serial frame format when back-to-back frames are transmitted. figure 14-3. ti synchronous serial frame format (continuous transfer) july 03, 2014 758 texas instruments-production data synchronous serial interface (ssi) 6 6 , & o n 6 6 , ) v v 6 6 , 7 [ 6 6 , 5 [ 0 6 % / 6 % w r e l w v 0 6 % / 6 % 6 6 , & o n 6 6 , ) v v 6 6 , 7 [ 6 6 , 5 [ w r e l w v 14.3.4.2 freescale spi frame format the freescale spi interface is a four-wire interface where the ssifss signal behaves as a slave select. the main feature of the freescale spi format is that the inactive state and phase of the ssiclk signal are programmable through the spo and sph bits in the ssiscr0 control register. spo clock polarity bit when the spo clock polarity control bit is clear, it produces a steady state low value on the ssiclk pin. if the spo bit is set, a steady state high value is placed on the ssiclk pin when data is not being transferred. sph phase control bit the sph phase control bit selects the clock edge that captures data and allows it to change state. the state of this bit has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge. when the sph phase control bit is clear, data is captured on the first clock edge transition. if the sph bit is set, data is captured on the second clock edge transition. 14.3.4.3 freescale spi frame format with spo=0 and sph=0 single and continuous transmission signal sequences for freescale spi format with spo =0 and sph =0 are shown in figure 14-4 on page 759 and figure 14-5 on page 759. figure 14-4. freescale spi format (single transfer) with spo=0 and sph=0 note: q is undefined. figure 14-5. freescale spi format (continuous transfer) with spo=0 and sph=0 in this configuration, during idle periods: ssiclk is forced low 759 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 6 6 , & o n 6 6 , ) v v 6 6 , 5 [ 4 6 6 , 7 [ 0 6 % 0 6 % / 6 % / 6 % w r e l w v 6 6 , & o n 6 6 , ) v v 6 6 , 5 [ / 6 % 6 6 , 7 [ 0 6 % / 6 % / 6 % 0 6 % 0 6 % 0 6 % / 6 % w r e l w v ssifss is forced high the transmit data line ssitx is arbitrarily forced low when the ssi is configured as a master, it enables the ssiclk pad when the ssi is configured as a slave, it disables the ssiclk pad if the ssi is enabled and valid data is in the transmit fifo, the start of transmission is signified by the ssifss master signal being driven low, causing slave data to be enabled onto the ssirx input line of the master. the master ssitx output pad is enabled. one half ssiclk period later, valid master data is transferred to the ssitx pin. once both the master and slave data have been set, the ssiclk master clock pin goes high after one additional half ssiclk period. the data is now captured on the rising and propagated on the falling edges of the ssiclk signal. in the case of a single word transmission, after all bits of the data word have been transferred, the ssifss line is returned to its idle high state one ssiclk period after the last bit has been captured. however, in the case of continuous back-to-back transmissions, the ssifss signal must be pulsed high between each data word transfer because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the sph bit is clear. therefore, the master device must raise the ssifss pin of the slave device between each data transfer to enable the serial peripheral data write. on completion of the continuous transfer, the ssifss pin is returned to its idle state one ssiclk period after the last bit has been captured. 14.3.4.4 freescale spi frame format with spo=0 and sph=1 the transfer signal sequence for freescale spi format with spo =0 and sph =1 is shown in figure 14-6 on page 760, which covers both single and continuous transfers. figure 14-6. freescale spi frame format with spo=0 and sph=1 note: q is undefined. in this configuration, during idle periods: ssiclk is forced low ssifss is forced high the transmit data line ssitx is arbitrarily forced low when the ssi is configured as a master, it enables the ssiclk pad july 03, 2014 760 texas instruments-production data synchronous serial interface (ssi) 6 6 , & o n 6 6 , ) v v 6 6 , 5 [ 6 6 , 7 [ 4 0 6 % 4 0 6 % / 6 % / 6 % w r e l w v 4 when the ssi is configured as a slave, it disables the ssiclk pad if the ssi is enabled and valid data is in the transmit fifo, the start of transmission is signified by the ssifss master signal being driven low. the master ssitx output is enabled. after an additional one-half ssiclk period, both master and slave valid data are enabled onto their respective transmission lines. at the same time, the ssiclk is enabled with a rising edge transition. data is then captured on the falling edges and propagated on the rising edges of the ssiclk signal. in the case of a single word transfer, after all bits have been transferred, the ssifss line is returned to its idle high state one ssiclk period after the last bit has been captured. for continuous back-to-back transfers, the ssifss pin is held low between successive data words, and termination is the same as that of the single word transfer. 14.3.4.5 freescale spi frame format with spo=1 and sph=0 single and continuous transmission signal sequences for freescale spi format with spo =1 and sph =0 are shown in figure 14-7 on page 761 and figure 14-8 on page 761. figure 14-7. freescale spi frame format (single transfer) with spo=1 and sph=0 note: q is undefined. figure 14-8. freescale spi frame format (continuous transfer) with spo=1 and sph=0 in this configuration, during idle periods: ssiclk is forced high ssifss is forced high the transmit data line ssitx is arbitrarily forced low when the ssi is configured as a master, it enables the ssiclk pad when the ssi is configured as a slave, it disables the ssiclk pad 761 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 6 6 , & o n 6 6 , ) v v 6 6 , 5 [ 6 6 , 7 [ 4 0 6 % 0 6 % / 6 % / 6 % w r e l w v 6 6 , & o n 6 6 , ) v v 6 6 , 7 [ 6 6 , 5 [ 0 6 % / 6 % / 6 % 0 6 % w r e l w v if the ssi is enabled and valid data is in the transmit fifo, the start of transmission is signified by the ssifss master signal being driven low, causing slave data to be immediately transferred onto the ssirx line of the master. the master ssitx output pad is enabled. one-half period later, valid master data is transferred to the ssitx line. once both the master and slave data have been set, the ssiclk master clock pin becomes low after one additional half ssiclk period, meaning that data is captured on the falling edges and propagated on the rising edges of the ssiclk signal. in the case of a single word transmission, after all bits of the data word are transferred, the ssifss line is returned to its idle high state one ssiclk period after the last bit has been captured. however, in the case of continuous back-to-back transmissions, the ssifss signal must be pulsed high between each data word transfer because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the sph bit is clear. therefore, the master device must raise the ssifss pin of the slave device between each data transfer to enable the serial peripheral data write. on completion of the continuous transfer, the ssifss pin is returned to its idle state one ssiclk period after the last bit has been captured. 14.3.4.6 freescale spi frame format with spo=1 and sph=1 the transfer signal sequence for freescale spi format with spo =1 and sph =1 is shown in figure 14-9 on page 762, which covers both single and continuous transfers. figure 14-9. freescale spi frame format with spo=1 and sph=1 note: q is undefined. in this configuration, during idle periods: ssiclk is forced high ssifss is forced high the transmit data line ssitx is arbitrarily forced low when the ssi is configured as a master, it enables the ssiclk pad when the ssi is configured as a slave, it disables the ssiclk pad if the ssi is enabled and valid data is in the transmit fifo, the start of transmission is signified by the ssifss master signal being driven low. the master ssitx output pad is enabled. after an additional one-half ssiclk period, both master and slave data are enabled onto their respective transmission lines. at the same time, ssiclk is enabled with a falling edge transition. data is then captured on the rising edges and propagated on the falling edges of the ssiclk signal. july 03, 2014 762 texas instruments-production data synchronous serial interface (ssi) 6 6 , & o n 6 6 , ) v v 6 6 , 5 [ 6 6 , 7 [ 4 0 6 % 0 6 % / 6 % / 6 % w r e l w v 4 after all bits have been transferred, in the case of a single word transmission, the ssifss line is returned to its idle high state one ssiclk period after the last bit has been captured. for continuous back-to-back transmissions, the ssifss pin remains in its active low state until the final bit of the last word has been captured and then returns to its idle state as described above. for continuous back-to-back transfers, the ssifss pin is held low between successive data words and termination is the same as that of the single word transfer. 14.3.4.7 microwire frame format figure 14-10 on page 763 shows the microwire frame format for a single frame. figure 14-11 on page 764 shows the same format when back-to-back frames are transmitted. figure 14-10. microwire frame format (single frame) microwire format is very similar to spi format, except that transmission is half-duplex instead of full-duplex and uses a master-slave message passing technique. each serial transmission begins with an 8-bit control word that is transmitted from the ssi to the off-chip slave device. during this transmission, no incoming data is received by the ssi. after the message has been sent, the off-chip slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent, responds with the required data. the returned data is 4 to 16 bits in length, making the total frame length anywhere from 13 to 25 bits. in this configuration, during idle periods: ssiclk is forced low ssifss is forced high the transmit data line ssitx is arbitrarily forced low a transmission is triggered by writing a control byte to the transmit fifo. the falling edge of ssifss causes the value contained in the bottom entry of the transmit fifo to be transferred to the serial shift register of the transmit logic and the msb of the 8-bit control frame to be shifted out onto the ssitx pin. ssifss remains low for the duration of the frame transmission. the ssirx pin remains tristated during this transmission. the off-chip serial slave device latches each control bit into its serial shifter on each rising edge of ssiclk . after the last bit is latched by the slave device, the control byte is decoded during a one clock wait-state, and the slave responds by transmitting data back to the ssi. each bit is driven onto the ssirx line on the falling edge of ssiclk . the ssi in turn latches each bit on the rising edge of ssiclk . at the end of the frame, for single transfers, the ssifss signal is pulled high one clock period after the last bit has been latched in the receive serial shifter, causing the data to be transferred to the receive fifo. 763 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 6 6 , & o n 6 6 , ) v v 6 6 , 5 [ 6 6 , 7 [ e l w f r q w u r o w r e l w v r x w s x w g d w d / 6 % 0 6 % 0 6 % / 6 % note: the off-chip slave device can tristate the receive line either on the falling edge of ssiclk after the lsb has been latched by the receive shifter or when the ssifss pin goes high. for continuous transfers, data transmission begins and ends in the same manner as a single transfer. however, the ssifss line is continuously asserted (held low) and transmission of data occurs back-to-back. the control byte of the next frame follows directly after the lsb of the received data from the current frame. each of the received values is transferred from the receive shifter on the falling edge of ssiclk , after the lsb of the frame has been latched into the ssi. figure 14-11. microwire frame format (continuous transfer) in the microwire mode, the ssi slave samples the first bit of receive data on the rising edge of ssiclk after ssifss has gone low. masters that drive a free-running ssiclk must ensure that the ssifss signal has sufficient setup and hold margins with respect to the rising edge of ssiclk. figure 14-12 on page 764 illustrates these setup and hold time requirements. with respect to the ssiclk rising edge on which the first bit of receive data is to be sampled by the ssi slave, ssifss must have a setup of at least two times the period of ssiclk on which the ssi operates. with respect to the ssiclk rising edge previous to this edge, ssifss must have a hold of at least one ssiclk period. figure 14-12. microwire frame format, ssifss input setup and hold requirements 14.3.5 dma operation the ssi peripheral provides an interface to the dma controller with separate channels for transmit and receive. the dma operation of the ssi is enabled through the ssi dma control (ssidmactl) register. when dma operation is enabled, the ssi asserts a dma request on the receive or transmit channel when the associated fifo can transfer data. for the receive channel, a single transfer request is asserted whenever any data is in the receive fifo. a burst transfer request is asserted whenever the amount of data in the receive fifo is 4 or more items. for the transmit channel, a single transfer request is asserted whenever at least one empty location is in the transmit july 03, 2014 764 texas instruments-production data synchronous serial interface (ssi) 6 6 , & o n 6 6 , ) v v / 6 % 0 6 % 6 6 , 5 [ 6 6 , 7 [ / 6 % / 6 % 0 6 % w r e l w v r x w s x w g d w d e l w f r q w u r o 0 6 % 6 6 , & o n 6 6 , ) v v 6 6 , 5 [ ) l u v w 5 ; g d w d w r e h v d p s o h g e \ 6 6 , v o d y h w + r o g w 6 6 , & o n w 6 h w x s w 6 6 , & o n fifo. the burst request is asserted whenever the transmit fifo has 4 or more empty slots. the single and burst dma transfer requests are handled automatically by the dma controller depending how the dma channel is configured. to enable dma operation for the receive channel, the rxdmae bit of the dma control (ssidmactl) register should be set. to enable dma operation for the transmit channel, the txdmae bit of ssidmactl should be set. if dma is enabled, then the dma controller triggers an interrupt when a transfer is complete. the interrupt occurs on the ssi interrupt vector. therefore, if interrupts are used for ssi operation and dma is enabled, the ssi interrupt handler must be designed to handle the dma completion interrupt. see micro direct memory access (dma) on page 344 for more details about programming the dma controller. 14.4 initialization and configuration to enable and initialize the ssi, the following steps are necessary: 1. enable the ssi module by setting the ssi bit in the rcgc1 register (see page 270). 2. enable the clock to the appropriate gpio module via the rcgc2 register (see page 282). to find out which gpio port to enable, refer to table 24-5 on page 1248. 3. set the gpio afsel bits for the appropriate pins (see page 429). to determine which gpios to configure, see table 24-4 on page 1239. 4. configure the pmcn fields in the gpiopctl register to assign the ssi signals to the appropriate pins. see page 447 and table 24-5 on page 1248. for each of the frame formats, the ssi is configured using the following steps: 1. ensure that the sse bit in the ssicr1 register is clear before making any configuration changes. 2. select whether the ssi is a master or slave: a. for master operations, set the ssicr1 register to 0x0000.0000. b. for slave mode (output enabled), set the ssicr1 register to 0x0000.0004. c. for slave mode (output disabled), set the ssicr1 register to 0x0000.000c. 3. configure the clock prescale divisor by writing the ssicpsr register. 4. write the ssicr0 register with the following configuration: serial clock rate ( scr) desired clock phase/polarity, if using freescale spi mode ( sph and spo) the protocol mode: freescale spi, ti ssf, microwire ( frf) the data size ( dss) 5. optionally, configure the dma channel (see micro direct memory access (dma) on page 344) and enable the dma option(s) in the ssidmactl register. 6. enable the ssi by setting the sse bit in the ssicr1 register. 765 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller as an example, assume the ssi must be configured to operate with the following parameters: master operation freescale spi mode (spo=1, sph=1) 1 mbps bit rate 8 data bits assuming the system clock is 20 mhz, the bit rate calculation would be: ssiclk = sysclk / (cpsdvsr * (1 + scr)) 1x10 6 = 20x10 6 / (cpsdvsr * (1 + scr)) in this case, if cpsdvsr=0x2, scr must be 0x9. the configuration sequence would be as follows: 1. ensure that the sse bit in the ssicr1 register is clear. 2. write the ssicr1 register with a value of 0x0000.0000. 3. write the ssicpsr register with a value of 0x0000.0002. 4. write the ssicr0 register with a value of 0x0000.09c7. 5. the ssi is then enabled by setting the sse bit in the ssicr1 register. 14.5 register map table 14-3 on page 766 lists the ssi registers. the offset listed is a hexadecimal increment to the registers address, relative to that ssi modules base address: ssi0: 0x4000.8000 ssi1: 0x4000.9000 note that the ssi module clock must be enabled before the registers can be programmed (see page 270). there must be a delay of 3 system clocks after the ssi module clock is enabled before any ssi module registers are accessed. note: the ssi must be disabled (see the sse bit in the ssicr1 register) before any of the control registers are reprogrammed. table 14-3. ssi register map see page description reset type name offset 768 ssi control 0 0x0000.0000 r/w ssicr0 0x000 770 ssi control 1 0x0000.0000 r/w ssicr1 0x004 772 ssi data 0x0000.0000 r/w ssidr 0x008 773 ssi status 0x0000.0003 ro ssisr 0x00c 775 ssi clock prescale 0x0000.0000 r/w ssicpsr 0x010 july 03, 2014 766 texas instruments-production data synchronous serial interface (ssi) table 14-3. ssi register map (continued) see page description reset type name offset 776 ssi interrupt mask 0x0000.0000 r/w ssiim 0x014 777 ssi raw interrupt status 0x0000.0008 ro ssiris 0x018 779 ssi masked interrupt status 0x0000.0000 ro ssimis 0x01c 781 ssi interrupt clear 0x0000.0000 w1c ssiicr 0x020 782 ssi dma control 0x0000.0000 r/w ssidmactl 0x024 783 ssi peripheral identification 4 0x0000.0000 ro ssiperiphid4 0xfd0 784 ssi peripheral identification 5 0x0000.0000 ro ssiperiphid5 0xfd4 785 ssi peripheral identification 6 0x0000.0000 ro ssiperiphid6 0xfd8 786 ssi peripheral identification 7 0x0000.0000 ro ssiperiphid7 0xfdc 787 ssi peripheral identification 0 0x0000.0022 ro ssiperiphid0 0xfe0 788 ssi peripheral identification 1 0x0000.0000 ro ssiperiphid1 0xfe4 789 ssi peripheral identification 2 0x0000.0018 ro ssiperiphid2 0xfe8 790 ssi peripheral identification 3 0x0000.0001 ro ssiperiphid3 0xfec 791 ssi primecell identification 0 0x0000.000d ro ssipcellid0 0xff0 792 ssi primecell identification 1 0x0000.00f0 ro ssipcellid1 0xff4 793 ssi primecell identification 2 0x0000.0005 ro ssipcellid2 0xff8 794 ssi primecell identification 3 0x0000.00b1 ro ssipcellid3 0xffc 14.6 register descriptions the remainder of this section lists and describes the ssi registers, in numerical order by address offset. 767 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 1: ssi control 0 (ssicr0), offset 0x000 the ssicr0 register contains bit fields that control various functions within the ssi module. functionality such as protocol mode, clock rate, and data size are configured in this register. ssi control 0 (ssicr0) ssi0 base: 0x4000.8000 ssi1 base: 0x4000.9000 offset 0x000 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dss frf spo sph scr r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 ssi serial clock rate this bit field is used to generate the transmit and receive bit rate of the ssi. the bit rate is: br=sysclk/(cpsdvsr * (1 + scr)) where cpsdvsr is an even value from 2-254 programmed in the ssicpsr register, and scr is a value from 0-255. 0x00 r/w scr 15:8 ssi serial clock phase this bit is only applicable to the freescale spi format. the sph control bit selects the clock edge that captures data and allows it to change state. this bit has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge. description value data is captured on the first clock edge transition. 0 data is captured on the second clock edge transition. 1 0 r/w sph 7 ssi serial clock polarity description value a steady state low value is placed on the ssiclk pin. 0 a steady state high value is placed on the ssiclk pin when data is not being transferred. 1 0 r/w spo 6 july 03, 2014 768 texas instruments-production data synchronous serial interface (ssi) description reset type name bit/field ssi frame format select frame format value freescale spi frame format 0x0 texas instruments synchronous serial frame format 0x1 microwire frame format 0x2 reserved 0x3 0x0 r/w frf 5:4 ssi data size select data size value reserved 0x0-0x2 4-bit data 0x3 5-bit data 0x4 6-bit data 0x5 7-bit data 0x6 8-bit data 0x7 9-bit data 0x8 10-bit data 0x9 11-bit data 0xa 12-bit data 0xb 13-bit data 0xc 14-bit data 0xd 15-bit data 0xe 16-bit data 0xf 0x0 r/w dss 3:0 769 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 2: ssi control 1 (ssicr1), offset 0x004 the ssicr1 register contains bit fields that control various functions within the ssi module. master and slave mode functionality is controlled by this register. ssi control 1 (ssicr1) ssi0 base: 0x4000.8000 ssi1 base: 0x4000.9000 offset 0x004 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 lbm sse ms sod eot reserved r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0 ro reserved 31:5 end of transmission description value the txris interrupt indicates that the transmit fifo is half full or less. 0 the end of transmit interrupt mode for the txris interrupt is enabled. 1 0 r/w eot 4 ssi slave mode output disable this bit is relevant only in the slave mode ( ms =1). in multiple-slave systems, it is possible for the ssi master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto the serial output line. in such systems, the txd lines from multiple slaves could be tied together. to operate in such a system, the sod bit can be configured so that the ssi slave does not drive the ssitx pin. description value ssi can drive the ssitx output in slave mode. 0 ssi must not drive the ssitx output in slave mode. 1 0 r/w sod 3 ssi master/slave select this bit selects master or slave mode and can be modified only when the ssi is disabled ( sse=0). description value the ssi is configured as a master. 0 the ssi is configured as a slave. 1 0 r/w ms 2 july 03, 2014 770 texas instruments-production data synchronous serial interface (ssi) description reset type name bit/field ssi synchronous serial port enable description value ssi operation is disabled. 0 ssi operation is enabled. 1 note: this bit must be cleared before any control registers are reprogrammed. 0 r/w sse 1 ssi loopback mode description value normal serial port operation enabled. 0 output of the transmit serial shift register is connected internally to the input of the receive serial shift register. 1 0 r/w lbm 0 771 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 3: ssi data (ssidr), offset 0x008 important: this register is read-sensitive. see the register description for details. the ssidr register is 16-bits wide. when the ssidr register is read, the entry in the receive fifo that is pointed to by the current fifo read pointer is accessed. when a data value is removed by the ssi receive logic from the incoming data frame, it is placed into the entry in the receive fifo pointed to by the current fifo write pointer. when the ssidr register is written to, the entry in the transmit fifo that is pointed to by the write pointer is written to. data values are removed from the transmit fifo one value at a time by the transmit logic. each data value is loaded into the transmit serial shifter, then serially shifted out onto the ssitx pin at the programmed bit rate. when a data size of less than 16 bits is selected, the user must right-justify data written to the transmit fifo. the transmit logic ignores the unused bits. received data less than 16 bits is automatically right-justified in the receive buffer. when the ssi is programmed for microwire frame format, the default size for transmit data is eight bits (the most significant byte is ignored). the receive data size is controlled by the programmer. the transmit fifo and the receive fifo are not cleared even when the sse bit in the ssicr1 register is cleared, allowing the software to fill the transmit fifo before enabling the ssi. ssi data (ssidr) ssi0 base: 0x4000.8000 ssi1 base: 0x4000.9000 offset 0x008 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 data r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 ssi receive/transmit data a read operation reads the receive fifo. a write operation writes the transmit fifo. software must right-justify data when the ssi is programmed for a data size that is less than 16 bits. unused bits at the top are ignored by the transmit logic. the receive logic automatically right-justifies the data. 0x0000 r/w data 15:0 july 03, 2014 772 texas instruments-production data synchronous serial interface (ssi) register 4: ssi status (ssisr), offset 0x00c the ssisr register contains bits that indicate the fifo fill status and the ssi busy status. ssi status (ssisr) ssi0 base: 0x4000.8000 ssi1 base: 0x4000.9000 offset 0x00c type ro, reset 0x0000.0003 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tfe tnf rne rff bsy reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:5 ssi busy bit description value the ssi is idle. 0 the ssi is currently transmitting and/or receiving a frame, or the transmit fifo is not empty. 1 0 ro bsy 4 ssi receive fifo full description value the receive fifo is not full. 0 the receive fifo is full. 1 0 ro rff 3 ssi receive fifo not empty description value the receive fifo is empty. 0 the receive fifo is not empty. 1 0 ro rne 2 ssi transmit fifo not full description value the transmit fifo is full. 0 the transmit fifo is not full. 1 1 ro tnf 1 773 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field ssi transmit fifo empty description value the transmit fifo is not empty. 0 the transmit fifo is empty. 1 1 ro tfe 0 july 03, 2014 774 texas instruments-production data synchronous serial interface (ssi) register 5: ssi clock prescale (ssicpsr), offset 0x010 the ssicpsr register specifies the division factor which is used to derive the ssiclk from the system clock. the clock is further divided by a value from 1 to 256, which is 1 + scr. scr is programmed in the ssicr0 register. the frequency of the ssiclk is defined by: ssiclk = sysclk / (cpsdvsr * (1 + scr)) the value programmed into this register must be an even number between 2 and 254. the least-significant bit of the programmed number is hard-coded to zero. if an odd number is written to this register, data read back from this register has the least-significant bit as zero. ssi clock prescale (ssicpsr) ssi0 base: 0x4000.8000 ssi1 base: 0x4000.9000 offset 0x010 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cpsdvsr reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 ssi clock prescale divisor this value must be an even number from 2 to 254, depending on the frequency of ssiclk . the lsb always returns 0 on reads. 0x00 r/w cpsdvsr 7:0 775 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 6: ssi interrupt mask (ssiim), offset 0x014 the ssiim register is the interrupt mask set or clear register. it is a read/write register and all bits are cleared on reset. on a read, this register gives the current value of the mask on the corresponding interrupt. setting a bit sets the mask, preventing the interrupt from being signaled to the interrupt controller. clearing a bit clears the corresponding mask, enabling the interrupt to be sent to the interrupt controller. ssi interrupt mask (ssiim) ssi0 base: 0x4000.8000 ssi1 base: 0x4000.9000 offset 0x014 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rorim rtim rxim txim reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:4 ssi transmit fifo interrupt mask description value the transmit fifo interrupt is masked. 0 the transmit fifo interrupt is not masked. 1 0 r/w txim 3 ssi receive fifo interrupt mask description value the receive fifo interrupt is masked. 0 the receive fifo interrupt is not masked. 1 0 r/w rxim 2 ssi receive time-out interrupt mask description value the receive fifo time-out interrupt is masked. 0 the receive fifo time-out interrupt is not masked. 1 0 r/w rtim 1 ssi receive overrun interrupt mask description value the receive fifo overrun interrupt is masked. 0 the receive fifo overrun interrupt is not masked. 1 0 r/w rorim 0 july 03, 2014 776 texas instruments-production data synchronous serial interface (ssi) register 7: ssi raw interrupt status (ssiris), offset 0x018 the ssiris register is the raw interrupt status register. on a read, this register gives the current raw status value of the corresponding interrupt prior to masking. a write has no effect. ssi raw interrupt status (ssiris) ssi0 base: 0x4000.8000 ssi1 base: 0x4000.9000 offset 0x018 type ro, reset 0x0000.0008 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rorris rtris rxris txris reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:4 ssi transmit fifo raw interrupt status description value no interrupt. 0 if the eot bit in the ssicr1 register is clear, the transmit fifo is half empty or less. if the eot bit is set, the transmit fifo is empty, and the last bit has been transmitted out of the serializer. 1 this bit is cleared when the transmit fifo is more than half full (if the eot bit is clear) or when it has any data in it (if the eot bit is set). 1 ro txris 3 ssi receive fifo raw interrupt status description value no interrupt. 0 the receive fifo is half full or more. 1 this bit is cleared when the receive fifo is less than half full. 0 ro rxris 2 ssi receive time-out raw interrupt status description value no interrupt. 0 the receive time-out has occurred. 1 this bit is cleared when a 1 is written to the rtic bit in the ssi interrupt clear (ssiicr) register. 0 ro rtris 1 777 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field ssi receive overrun raw interrupt status description value no interrupt. 0 the receive fifo has overflowed 1 this bit is cleared when a 1 is written to the roric bit in the ssi interrupt clear (ssiicr) register. 0 ro rorris 0 july 03, 2014 778 texas instruments-production data synchronous serial interface (ssi) register 8: ssi masked interrupt status (ssimis), offset 0x01c the ssimis register is the masked interrupt status register. on a read, this register gives the current masked status value of the corresponding interrupt. a write has no effect. ssi masked interrupt status (ssimis) ssi0 base: 0x4000.8000 ssi1 base: 0x4000.9000 offset 0x01c type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rormis rtmis rxmis txmis reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:4 ssi transmit fifo masked interrupt status description value an interrupt has not occurred or is masked. 0 an unmasked interrupt was signaled due to the transmit fifo being half empty or less (if the eot bit is clear) or due to the transmission of the last data bit (if the eot bit is set). 1 this bit is cleared when the transmit fifo is more than half empty (if the eot bit is clear) or when it has any data in it (if the eot bit is set). 0 ro txmis 3 ssi receive fifo masked interrupt status description value an interrupt has not occurred or is masked. 0 an unmasked interrupt was signaled due to the receive fifo being half full or more. 1 this bit is cleared when the receive fifo is less than half full. 0 ro rxmis 2 ssi receive time-out masked interrupt status description value an interrupt has not occurred or is masked. 0 an unmasked interrupt was signaled due to the receive time out. 1 this bit is cleared when a 1 is written to the rtic bit in the ssi interrupt clear (ssiicr) register. 0 ro rtmis 1 779 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field ssi receive overrun masked interrupt status description value an interrupt has not occurred or is masked. 0 an unmasked interrupt was signaled due to the receive fifo overflowing. 1 this bit is cleared when a 1 is written to the roric bit in the ssi interrupt clear (ssiicr) register. 0 ro rormis 0 july 03, 2014 780 texas instruments-production data synchronous serial interface (ssi) register 9: ssi interrupt clear (ssiicr), offset 0x020 the ssiicr register is the interrupt clear register. on a write of 1, the corresponding interrupt is cleared. a write of 0 has no effect. ssi interrupt clear (ssiicr) ssi0 base: 0x4000.8000 ssi1 base: 0x4000.9000 offset 0x020 type w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 roric rtic reserved w1c w1c ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:2 ssi receive time-out interrupt clear writing a 1 to this bit clears the rtris bit in the ssiris register and the rtmis bit in the ssimis register. 0 w1c rtic 1 ssi receive overrun interrupt clear writing a 1 to this bit clears the rorris bit in the ssiris register and the rormis bit in the ssimis register. 0 w1c roric 0 781 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 10: ssi dma control (ssidmactl), offset 0x024 the ssidmactl register is the dma control register. ssi dma control (ssidmactl) ssi0 base: 0x4000.8000 ssi1 base: 0x4000.9000 offset 0x024 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rxdmae txdmae reserved r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:2 transmit dma enable description value dma for the transmit fifo is disabled. 0 dma for the transmit fifo is enabled. 1 0 r/w txdmae 1 receive dma enable description value dma for the receive fifo is disabled. 0 dma for the receive fifo is enabled. 1 0 r/w rxdmae 0 july 03, 2014 782 texas instruments-production data synchronous serial interface (ssi) register 11: ssi peripheral identification 4 (ssiperiphid4), offset 0xfd0 the ssiperiphidn registers are hard-coded and the fields within the register determine the reset value. ssi peripheral identification 4 (ssiperiphid4) ssi0 base: 0x4000.8000 ssi1 base: 0x4000.9000 offset 0xfd0 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid4 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 ssi peripheral id register [7:0] can be used by software to identify the presence of this peripheral. 0x00 ro pid4 7:0 783 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 12: ssi peripheral identification 5 (ssiperiphid5), offset 0xfd4 the ssiperiphidn registers are hard-coded and the fields within the register determine the reset value. ssi peripheral identification 5 (ssiperiphid5) ssi0 base: 0x4000.8000 ssi1 base: 0x4000.9000 offset 0xfd4 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid5 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 ssi peripheral id register [15:8] can be used by software to identify the presence of this peripheral. 0x00 ro pid5 7:0 july 03, 2014 784 texas instruments-production data synchronous serial interface (ssi) register 13: ssi peripheral identification 6 (ssiperiphid6), offset 0xfd8 the ssiperiphidn registers are hard-coded and the fields within the register determine the reset value. ssi peripheral identification 6 (ssiperiphid6) ssi0 base: 0x4000.8000 ssi1 base: 0x4000.9000 offset 0xfd8 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid6 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 ssi peripheral id register [23:16] can be used by software to identify the presence of this peripheral. 0x00 ro pid6 7:0 785 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 14: ssi peripheral identification 7 (ssiperiphid7), offset 0xfdc the ssiperiphidn registers are hard-coded and the fields within the register determine the reset value. ssi peripheral identification 7 (ssiperiphid7) ssi0 base: 0x4000.8000 ssi1 base: 0x4000.9000 offset 0xfdc type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid7 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 ssi peripheral id register [31:24] can be used by software to identify the presence of this peripheral. 0x00 ro pid7 7:0 july 03, 2014 786 texas instruments-production data synchronous serial interface (ssi) register 15: ssi peripheral identification 0 (ssiperiphid0), offset 0xfe0 the ssiperiphidn registers are hard-coded and the fields within the register determine the reset value. ssi peripheral identification 0 (ssiperiphid0) ssi0 base: 0x4000.8000 ssi1 base: 0x4000.9000 offset 0xfe0 type ro, reset 0x0000.0022 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid0 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 ssi peripheral id register [7:0] can be used by software to identify the presence of this peripheral. 0x22 ro pid0 7:0 787 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 16: ssi peripheral identification 1 (ssiperiphid1), offset 0xfe4 the ssiperiphidn registers are hard-coded and the fields within the register determine the reset value. ssi peripheral identification 1 (ssiperiphid1) ssi0 base: 0x4000.8000 ssi1 base: 0x4000.9000 offset 0xfe4 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid1 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 ssi peripheral id register [15:8] can be used by software to identify the presence of this peripheral. 0x00 ro pid1 7:0 july 03, 2014 788 texas instruments-production data synchronous serial interface (ssi) register 17: ssi peripheral identification 2 (ssiperiphid2), offset 0xfe8 the ssiperiphidn registers are hard-coded and the fields within the register determine the reset value. ssi peripheral identification 2 (ssiperiphid2) ssi0 base: 0x4000.8000 ssi1 base: 0x4000.9000 offset 0xfe8 type ro, reset 0x0000.0018 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid2 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 ssi peripheral id register [23:16] can be used by software to identify the presence of this peripheral. 0x18 ro pid2 7:0 789 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 18: ssi peripheral identification 3 (ssiperiphid3), offset 0xfec the ssiperiphidn registers are hard-coded and the fields within the register determine the reset value. ssi peripheral identification 3 (ssiperiphid3) ssi0 base: 0x4000.8000 ssi1 base: 0x4000.9000 offset 0xfec type ro, reset 0x0000.0001 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pid3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 ssi peripheral id register [31:24] can be used by software to identify the presence of this peripheral. 0x01 ro pid3 7:0 july 03, 2014 790 texas instruments-production data synchronous serial interface (ssi) register 19: ssi primecell identification 0 (ssipcellid0), offset 0xff0 the ssipcellidn registers are hard-coded, and the fields within the register determine the reset value. ssi primecell identification 0 (ssipcellid0) ssi0 base: 0x4000.8000 ssi1 base: 0x4000.9000 offset 0xff0 type ro, reset 0x0000.000d 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cid0 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 ssi primecell id register [7:0] provides software a standard cross-peripheral identification system. 0x0d ro cid0 7:0 791 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 20: ssi primecell identification 1 (ssipcellid1), offset 0xff4 the ssipcellidn registers are hard-coded, and the fields within the register determine the reset value. ssi primecell identification 1 (ssipcellid1) ssi0 base: 0x4000.8000 ssi1 base: 0x4000.9000 offset 0xff4 type ro, reset 0x0000.00f0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cid1 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 ssi primecell id register [15:8] provides software a standard cross-peripheral identification system. 0xf0 ro cid1 7:0 july 03, 2014 792 texas instruments-production data synchronous serial interface (ssi) register 21: ssi primecell identification 2 (ssipcellid2), offset 0xff8 the ssipcellidn registers are hard-coded, and the fields within the register determine the reset value. ssi primecell identification 2 (ssipcellid2) ssi0 base: 0x4000.8000 ssi1 base: 0x4000.9000 offset 0xff8 type ro, reset 0x0000.0005 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cid2 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 ssi primecell id register [23:16] provides software a standard cross-peripheral identification system. 0x05 ro cid2 7:0 793 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 22: ssi primecell identification 3 (ssipcellid3), offset 0xffc the ssipcellidn registers are hard-coded, and the fields within the register determine the reset value. ssi primecell identification 3 (ssipcellid3) ssi0 base: 0x4000.8000 ssi1 base: 0x4000.9000 offset 0xffc type ro, reset 0x0000.00b1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cid3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 ssi primecell id register [31:24] provides software a standard cross-peripheral identification system. 0xb1 ro cid3 7:0 july 03, 2014 794 texas instruments-production data synchronous serial interface (ssi) 15 inter-integrated circuit (i 2 c) interface the inter-integrated circuit (i 2 c) bus provides bi-directional data transfer through a two-wire design (a serial data line sda and a serial clock line scl), and interfaces to external i 2 c devices such as serial memory (rams and roms), networking devices, lcds, tone generators, and so on. the i 2 c bus may also be used for system testing and diagnostic purposes in product development and manufacture. the lm3s9gn5 microcontroller includes two i 2 c modules, providing the ability to interact (both transmit and receive) with other i 2 c devices on the bus. the stellaris ? lm3s9gn5 controller includes two i 2 c modules with the following features: devices on the i 2 c bus can be designated as either a master or a slave C supports both transmitting and receiving data as either a master or a slave C supports simultaneous master and slave operation four i 2 c modes C master transmit C master receive C slave transmit C slave receive two transmission speeds: standard (100 kbps) and fast (400 kbps) master and slave interrupt generation C master generates interrupts when a transmit or receive operation completes (or aborts due to an error) C slave generates interrupts when data has been transferred or requested by a master or when a start or stop condition is detected master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode 795 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 15.1 block diagram figure 15-1. i 2 c block diagram 15.2 signal description the following table lists the external signals of the i 2 c interface and describes the function of each. the i 2 c interface signals are alternate functions for some gpio signals and default to be gpio signals at reset., with the exception of the i2c0scl and i2csda pins which default to the i 2 c function. the column in the table below titled "pin mux/pin assignment" lists the possible gpio pin placements for the i 2 c signals. the afsel bit in the gpio alternate function select (gpioafsel) register (page 429) should be set to choose the i 2 c function. the number in parentheses is the encoding that must be programmed into the pmcn field in the gpio port control (gpiopctl) register (page 447) to assign the i 2 c signal to the specified gpio port pin. note that the i 2 c pins should be set to open drain using the gpio open drain select (gpioodr) register. for more information on configuring gpios, see general-purpose input/outputs (gpios) on page 405. table 15-1. i2c signals (100lqfp) description buffer type a pin type pin mux / pin assignment pin number pin name i 2 c module 0 clock. od i/o pb2 (1) 72 i2c0scl i 2 c module 0 data. od i/o pb3 (1) 65 i2c0sda i 2 c module 1 clock. od i/o pj0 (11) pg0 (3) pa0 (8) pa6 (1) 14 19 26 34 i2c1scl i 2 c module 1 data. od i/o pg1 (3) pa1 (8) pa7 (1) pj1 (11) 18 27 35 87 i2c1sda a. the ttl designation indicates the pin has ttl-compatible voltage levels. table 15-2. i2c signals (108bga) description buffer type a pin type pin mux / pin assignment pin number pin name i 2 c module 0 clock. od i/o pb2 (1) a11 i2c0scl july 03, 2014 796 texas instruments-production data inter-integrated circuit (i 2 c) interface , & , 2 6 h o h f w , & 0 d v w h u & r u h , q w h u u x s w , & 6 o d y h & r u h , & 6 & / , & 6 ' $ , & 6 ' $ , & 6 & / , & 6 ' $ , & 6 & / , & 0 6 $ , & 0 & 6 , & 0 ' 5 , & 0 7 3 5 , & 0 , 0 5 , & 0 5 , 6 , & 0 , & 5 , & 0 & 5 , & 6 2 $ 5 , & 6 & 6 5 , & 6 ' 5 , & 6 , 0 5 , & 6 5 , 6 , & 6 0 , 6 , & 6 , & 5 , & 0 0 , 6 , & & r q w u r o table 15-2. i2c signals (108bga) (continued) description buffer type a pin type pin mux / pin assignment pin number pin name i 2 c module 0 data. od i/o pb3 (1) e11 i2c0sda i 2 c module 1 clock. od i/o pj0 (11) pg0 (3) pa0 (8) pa6 (1) f3 k1 l3 l6 i2c1scl i 2 c module 1 data. od i/o pg1 (3) pa1 (8) pa7 (1) pj1 (11) k2 m3 m6 b6 i2c1sda a. the ttl designation indicates the pin has ttl-compatible voltage levels. 15.3 functional description each i 2 c module is comprised of both master and slave functions. for proper operation, the sda and scl pins must be configured as open-drain signals. a typical i 2 c bus configuration is shown in figure 15-2. see inter-integrated circuit (i 2 c) interface on page 1316 for i 2 c timing diagrams. figure 15-2. i 2 c bus configuration 15.3.1 i 2 c bus functional overview the i 2 c bus uses only two signals: sda and scl, named i2csda and i2cscl on stellaris microcontrollers. sda is the bi-directional serial data line and scl is the bi-directional serial clock line. the bus is considered idle when both lines are high. every transaction on the i 2 c bus is nine bits long, consisting of eight data bits and a single acknowledge bit. the number of bytes per transfer (defined as the time between a valid start and stop condition, described in start and stop conditions on page 797) is unrestricted, but each byte has to be followed by an acknowledge bit, and data must be transferred msb first. when a receiver cannot receive another complete byte, it can hold the clock line scl low and force the transmitter into a wait state. the data transfer continues when the receiver releases the clock scl. 15.3.1.1 start and stop conditions the protocol of the i 2 c bus defines two states to begin and end a transaction: start and stop. a high-to-low transition on the sda line while the scl is high is defined as a start condition, and a low-to-high transition on the sda line while scl is high is defined as a stop condition. the bus is considered busy after a start condition and free after a stop condition. see figure 15-3. 797 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 5 3 8 3 6 w h o o d u l v ? , & 6 & / , & 6 ' $ 5 3 8 3 u g 3 d u w \ ' h y l f h z l w k , & , q w h u i d f h 6 & / 6 ' $ , & % x v 6 & / 6 ' $ 6 & / 6 ' $ u g 3 d u w \ ' h y l f h z l w k , & , q w h u i d f h figure 15-3. start and stop conditions the stop bit determines if the cycle stops at the end of the data cycle or continues on to a repeated start condition. to generate a single transmit cycle, the i 2 c master slave address (i2cmsa) register is written with the desired address, the r/s bit is cleared, and the control register is written with ack =x (0 or 1), stop=1, start =1, and run =1 to perform the operation and stop. when the operation is completed (or aborted due an error), the interrupt pin becomes active and the data may be read from the i 2 c master data (i2cmdr) register. when the i 2 c module operates in master receiver mode, the ack bit is normally set causing the i 2 c bus controller to transmit an acknowledge automatically after each byte. this bit must be cleared when the i 2 c bus controller requires no further data to be transmitted from the slave transmitter. when operating in slave mode, two bits in the i 2 c slave raw interrupt status (i2csris) register indicate detection of start and stop conditions on the bus; while two bits in the i 2 c slave masked interrupt status (i2csmis) register allow start and stop conditions to be promoted to controller interrupts (when interrupts are enabled). 15.3.1.2 data format with 7-bit address data transfers follow the format shown in figure 15-4. after the start condition, a slave address is transmitted. this address is 7-bits long followed by an eighth bit, which is a data direction bit ( r/s bit in the i2cmsa register). if the r/s bit is clear, it indicates a transmit operation (send), and if it is set, it indicates a request for data (receive). a data transfer is always terminated by a stop condition generated by the master, however, a master can initiate communications with another device on the bus by generating a repeated start condition and addressing another slave without first generating a stop condition. various combinations of receive/transmit formats are then possible within a single transfer. figure 15-4. complete data transfer with a 7-bit address the first seven bits of the first byte make up the slave address (see figure 15-5). the eighth bit determines the direction of the message. a zero in the r/s position of the first byte means that the master transmits (sends) data to the selected slave, and a one in this position means that the master receives data from the slave. july 03, 2014 798 texas instruments-production data inter-integrated circuit (i 2 c) interface 6 7 $ 5 7 f r q g l w l r q 6 ' $ 6 & / 6 7 2 3 f r q g l w l r q 6 ' $ 6 & / ' d w d 6 o d y h d g g u h v v $ & . / 6 % 0 6 % $ & . 5 6 / 6 % 0 6 % 6 ' $ 6 & / 6 w r s 6 w d u w figure 15-5. r/s bit in first byte 15.3.1.3 data validity the data on the sda line must be stable during the high period of the clock, and the data line can only change when scl is low (see figure 15-6). figure 15-6. data validity during bit transfer on the i 2 c bus 15.3.1.4 acknowledge all bus transactions have a required acknowledge clock cycle that is generated by the master. during the acknowledge cycle, the transmitter (which can be the master or slave) releases the sda line. to acknowledge the transaction, the receiver must pull down sda during the acknowledge clock cycle. the data transmitted out by the receiver during the acknowledge cycle must comply with the data validity requirements described in data validity on page 799. when a slave receiver does not acknowledge the slave address, sda must be left high by the slave so that the master can generate a stop condition and abort the current transfer. if the master device is acting as a receiver during a transfer, it is responsible for acknowledging each transfer made by the slave. because the master controls the number of bytes in the transfer, it signals the end of data to the slave transmitter by not generating an acknowledge on the last data byte. the slave transmitter must then release sda to allow the master to generate the stop or a repeated start condition. 15.3.1.5 arbitration a master may start a transfer only if the bus is idle. it's possible for two or more masters to generate a start condition within minimum hold time of the start condition. in these situations, an arbitration scheme takes place on the sda line, while scl is high. during arbitration, the first of the competing master devices to place a '1' (high) on sda while another master transmits a '0' (low) switches off its data output stage and retires until the bus is idle again. arbitration can take place over several bits. its first stage is a comparison of address bits, and if both masters are trying to address the same device, arbitration continues on to the comparison of data bits. 15.3.2 available speed modes the i 2 c bus can run in either standard mode (100 kbps) or fast mode (400 kbps). the selected mode should match the speed of the other i 2 c devices on the bus. 799 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 5 6 / 6 % 6 o d y h d g g u h v v 0 6 % & k d q j h r i g d w d d o o r z h g ' d w d o l q h v w d e o h 6 ' $ 6 & / 15.3.2.1 standard and fast modes standard and fast modes are selected using a value in the i 2 c master timer period (i2cmtpr) register that results in an scl frequency of 100 kbps for standard mode. the i 2 c clock rate is determined by the parameters clk_prd, timer_prd, scl_lp , and scl_hp where: clk_prd is the system clock period scl_lp is the low phase of scl (fixed at 6) scl_hp is the high phase of scl (fixed at 4) timer_prd is the programmed value in the i2cmtpr register (see page 819). the i 2 c clock period is calculated as follows: scl_period = 2 (1 + timer_prd ) (scl_lp + scl_hp ) clk_prd for example: clk_prd = 50 ns timer_prd = 2 scl_lp=6 scl_hp=4 yields a scl frequency of: 1/scl_period = 333 khz table 15-3 gives examples of the timer periods that should be used to generate scl frequencies based on various system clock frequencies. table 15-3. examples of i 2 c master timer period versus speed mode fast mode timer period standard mode timer period system clock - - 100 kbps 0x01 4 mhz - - 100 kbps 0x02 6 mhz 312 kbps 0x01 89 kbps 0x06 12.5 mhz 278 kbps 0x02 93 kbps 0x08 16.7 mhz 333 kbps 0x02 100 kbps 0x09 20 mhz 312 kbps 0x03 96.2 kbps 0x0c 25 mhz 330 kbps 0x04 97.1 kbps 0x10 33 mhz 400 kbps 0x04 100 kbps 0x13 40 mhz 357 kbps 0x06 100 kbps 0x18 50 mhz 400 kbps 0x09 100 kbps 0x27 80 mhz 15.3.3 interrupts the i 2 c can generate interrupts when the following conditions are observed: master transaction completed master arbitration lost july 03, 2014 800 texas instruments-production data inter-integrated circuit (i 2 c) interface master transaction error slave transaction received slave transaction requested stop condition on bus detected start condition on bus detected the i 2 c master and i 2 c slave modules have separate interrupt signals. while both modules can generate interrupts for multiple conditions, only a single interrupt signal is sent to the interrupt controller. 15.3.3.1 i 2 c master interrupts the i 2 c master module generates an interrupt when a transaction completes (either transmit or receive), when arbitration is lost, or when an error occurs during a transaction. to enable the i 2 c master interrupt, software must set the im bit in the i 2 c master interrupt mask (i2cmimr) register. when an interrupt condition is met, software must check the error and arblst bits in the i 2 c master control/status (i2cmcs) register to verify that an error didn't occur during the last transaction and to ensure that arbitration has not been lost. an error condition is asserted if the last transaction wasn't acknowledged by the slave. if an error is not detected and the master has not lost arbitration, the application can proceed with the transfer. the interrupt is cleared by writing a 1 to the ic bit in the i 2 c master interrupt clear (i2cmicr) register. if the application doesn't require the use of interrupts, the raw interrupt status is always visible via the i 2 c master raw interrupt status (i2cmris) register. 15.3.3.2 i 2 c slave interrupts the slave module can generate an interrupt when data has been received or requested. this interrupt is enabled by setting the dataim bit in the i 2 c slave interrupt mask (i2csimr) register. software determines whether the module should write (transmit) or read (receive) data from the i 2 c slave data (i2csdr) register, by checking the rreq and treq bits of the i 2 c slave control/status (i2cscsr) register. if the slave module is in receive mode and the first byte of a transfer is received, the fbr bit is set along with the rreq bit. the interrupt is cleared by setting the dataic bit in the i 2 c slave interrupt clear (i2csicr) register. in addition, the slave module can generate an interrupt when a start and stop condition is detected. these interrupts are enabled by setting the startim and stopim bits of the i 2 c slave interrupt mask (i2csimr) register and cleared by writing a 1 to the stopic and startic bits of the i 2 c slave interrupt clear (i2csicr) register. if the application doesn't require the use of interrupts, the raw interrupt status is always visible via the i 2 c slave raw interrupt status (i2csris) register. 15.3.4 loopback operation the i 2 c modules can be placed into an internal loopback mode for diagnostic or debug work by setting the lpbk bit in the i 2 c master configuration (i2cmcr) register. in loopback mode, the sda and scl signals from the master and slave modules are tied together. 801 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 15.3.5 command sequence flow charts this section details the steps required to perform the various i 2 c transfer types in both master and slave mode. 15.3.5.1 i 2 c master command sequences the figures that follow show the command sequences available for the i 2 c master. july 03, 2014 802 texas instruments-production data inter-integrated circuit (i 2 c) interface figure 15-7. master single transmit 803 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller , g o h : u l w h 6 o d y h $ g g u h v v w r , & 0 6 $ : u l w h g d w d w r , & 0 ' 5 5 h d g , & 0 & 6 6 h t x h q f h p d \ e h r p l w w h g l q d 6 l q j o h 0 d v w h u v \ v w h p % 8 6 % 6 < e l w " 1 2 : u l w h --- 0 - 111 0 0 figure 15-8. master single receive july 03, 2014 804 texas instruments-production data inter-integrated circuit (i 2 c) interface , g o h : u l w h 6 o d y h $ g g u h v v w r , & 0 6 $ 5 h d g , & 0 & 6 6 h t x h q f h p d \ e h r p l w w h g l q d 6 l q j o h 0 d v w h u v \ v w h p % 8 6 % 6 < e l w " 1 2 : u l w h --- 00111 0 0 figure 15-9. master transmit with repeated start 805 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller , g o h : u l w h 6 o d y h $ g g u h v v w r , & 0 6 $ : u l w h g d w d w r , & 0 ' 5 5 h d g , & 0 & 6 % 8 6 % 6 < e l w " < ( 6 : u l w h --- 0 - 011 0 0 1 --- 0 - 100 --- 0 - 001 --- 0 - 101 0 0 figure 15-10. master receive with repeated start july 03, 2014 806 texas instruments-production data inter-integrated circuit (i 2 c) interface , g o h : u l w h 6 o d y h $ g g u h v v w r , & 0 6 $ 5 h d g , & 0 & 6 % 8 6 % 6 < e l w " 1 2 : u l w h --- 01011 0 0 1 --- 0 - 100 -1 --- 00101 0 --- 01001 0 figure 15-11. master receive with repeated start after transmit with repeated start 807 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller , g o h 0 d v w h u r s h u d w h v l q 0 d v w h u 7 u d q v p l w p r g h 6 7 2 3 f r q g l w l r q l v q r w j h q h u d w h g : u l w h 6 o d y h $ g g u h v v w r , & 0 6 $ : u l w h --- 01011 figure 15-12. master transmit with repeated start after receive with repeated start 15.3.5.2 i 2 c slave command sequences figure 15-13 on page 809 presents the command sequence available for the i 2 c slave. july 03, 2014 808 texas instruments-production data inter-integrated circuit (i 2 c) interface , g o h 0 d v w h u r s h u d w h v l q 0 d v w h u 5 h f h l y h p r g h 6 7 2 3 f r q g l w l r q l v q r w j h q h u d w h g : u l w h 6 o d y h $ g g u h v v w r , & 0 6 $ : u l w h --- 0 - 011 figure 15-13. slave command sequence 15.4 initialization and configuration the following example shows how to configure the i 2 c module to transmit a single byte as a master. this assumes the system clock is 20 mhz. 1. enable the i 2 c clock by writing a value of 0x0000.1000 to the rcgc1 register in the system control module (see page 270). 2. enable the clock to the appropriate gpio module via the rcgc2 register in the system control module (see page 282). to find out which gpio port to enable, refer to table 24-5 on page 1248. 3. in the gpio module, enable the appropriate pins for their alternate function using the gpioafsel register (see page 429). to determine which gpios to configure, see table 24-4 on page 1239. 4. enable the i 2 c pins for open-drain operation. see page 434. 5. configure the pmcn fields in the gpiopctl register to assign the i 2 c signals to the appropriate pins. see page 447 and table 24-5 on page 1248. 6. initialize the i 2 c master by writing the i2cmcr register with a value of 0x0000.0010. 809 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller , g o h : u l w h 2 : 1 6 o d y h $ g g u h v v w r , & 6 2 $ 5 : u l w h ------- 1 1 1 7. set the desired scl clock speed of 100 kbps by writing the i2cmtpr register with the correct value. the value written to the i2cmtpr register represents the number of system clock periods in one scl clock period. the tpr value is determined by the following equation: tpr = (system clock/(2*(scl_lp + scl_hp)*scl_clk))-1; tpr = (20mhz/(2*(6+4)*100000))-1; tpr = 9 write the i2cmtpr register with the value of 0x0000.0009. 8. specify the slave address of the master and that the next operation is a transmit by writing the i2cmsa register with a value of 0x0000.0076. this sets the slave address to 0x3b. 9. place data (byte) to be transmitted in the data register by writing the i2cmdr register with the desired data. 10. initiate a single byte transmit of the data from master to slave by writing the i2cmcs register with a value of 0x0000.0007 (stop, start, run). 11. wait until the transmission completes by polling the i2cmcs registers busbsy bit until it has been cleared. 12. check the error bit in the i2cmcs register to confirm the transmit was acknowledged. 15.5 register map table 15-4 on page 810 lists the i 2 c registers. all addresses given are relative to the i 2 c base address: i 2 c 0: 0x4002.0000 i 2 c 1: 0x4002.1000 note that the i 2 c module clock must be enabled before the registers can be programmed (see page 270). there must be a delay of 3 system clocks after the i 2 c module clock is enabled before any i 2 c module registers are accessed. the hw_i2c.h file in the stellarisware ? driver library uses a base address of 0x800 for the i 2 c slave registers. be aware when using registers with offsets between 0x800 and 0x818 that stellarisware uses an offset between 0x000 and 0x018 with the slave base address. table 15-4. inter-integrated circuit (i 2 c) interface register map see page description reset type name offset i 2 c master 812 i2c master slave address 0x0000.0000 r/w i2cmsa 0x000 813 i2c master control/status 0x0000.0020 r/w i2cmcs 0x004 818 i2c master data 0x0000.0000 r/w i2cmdr 0x008 819 i2c master timer period 0x0000.0001 r/w i2cmtpr 0x00c 820 i2c master interrupt mask 0x0000.0000 r/w i2cmimr 0x010 821 i2c master raw interrupt status 0x0000.0000 ro i2cmris 0x014 july 03, 2014 810 texas instruments-production data inter-integrated circuit (i 2 c) interface table 15-4. inter-integrated circuit (i 2 c) interface register map (continued) see page description reset type name offset 822 i2c master masked interrupt status 0x0000.0000 ro i2cmmis 0x018 823 i2c master interrupt clear 0x0000.0000 wo i2cmicr 0x01c 824 i2c master configuration 0x0000.0000 r/w i2cmcr 0x020 i 2 c slave 825 i2c slave own address 0x0000.0000 r/w i2csoar 0x800 826 i2c slave control/status 0x0000.0000 ro i2cscsr 0x804 828 i2c slave data 0x0000.0000 r/w i2csdr 0x808 829 i2c slave interrupt mask 0x0000.0000 r/w i2csimr 0x80c 830 i2c slave raw interrupt status 0x0000.0000 ro i2csris 0x810 831 i2c slave masked interrupt status 0x0000.0000 ro i2csmis 0x814 832 i2c slave interrupt clear 0x0000.0000 wo i2csicr 0x818 15.6 register descriptions (i 2 c master) the remainder of this section lists and describes the i 2 c master registers, in numerical order by address offset. 811 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 1: i 2 c master slave address (i2cmsa), offset 0x000 this register consists of eight bits: seven address bits (a6-a0), and a receive/send bit, which determines if the next operation is a receive (high), or transmit (low). i2c master slave address (i2cmsa) i2c 0 base: 0x4002.0000 i2c 1 base: 0x4002.1000 offset 0x000 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r/s sa reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 i 2 c slave address this field specifies bits a6 through a0 of the slave address. 0x00 r/w sa 7:1 receive/send the r/s bit specifies if the next operation is a receive (high) or transmit (low). description value transmit 0 receive 1 0 r/w r/s 0 july 03, 2014 812 texas instruments-production data inter-integrated circuit (i 2 c) interface register 2: i 2 c master control/status (i2cmcs), offset 0x004 this register accesses status bits when read and control bits when written. when read, the status register indicates the state of the i 2 c bus controller. when written, the control register configures the i 2 c controller operation. the start bit generates the start or repeated start condition. the stop bit determines if the cycle stops at the end of the data cycle or continues on to a repeated start condition. to generate a single transmit cycle, the i 2 c master slave address (i2cmsa) register is written with the desired address, the r/s bit is cleared, and this register is written with ack =x (0 or 1), stop=1, start =1, and run =1 to perform the operation and stop. when the operation is completed (or aborted due an error), an interrupt becomes active and the data may be read from the i2cmdr register. when the i 2 c module operates in master receiver mode, the ack bit is normally set, causing the i 2 c bus controller to transmit an acknowledge automatically after each byte. this bit must be cleared when the i 2 c bus controller requires no further data to be transmitted from the slave transmitter. read-only status register i2c master control/status (i2cmcs) i2c 0 base: 0x4002.0000 i2c 1 base: 0x4002.1000 offset 0x004 type ro, reset 0x0000.0020 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 busy error adrack datack arblst idle busbsy reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:7 bus busy description value the i 2 c bus is idle. 0 the i 2 c bus is busy. 1 the bit changes based on the start and stop conditions. 0 ro busbsy 6 i 2 c idle description value the i 2 c controller is not idle. 0 the i 2 c controller is idle. 1 1 ro idle 5 813 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field arbitration lost description value the i 2 c controller won arbitration. 0 the i 2 c controller lost arbitration. 1 0 ro arblst 4 acknowledge data description value the transmitted data was acknowledged 0 the transmitted data was not acknowledged. 1 0 ro datack 3 acknowledge address description value the transmitted address was acknowledged 0 the transmitted address was not acknowledged. 1 0 ro adrack 2 error description value no error was detected on the last operation. 0 an error occurred on the last operation. 1 the error can be from the slave address not being acknowledged or the transmit data not being acknowledged. 0 ro error 1 i 2 c busy description value the controller is idle. 0 the controller is busy. 1 when the busy bit is set, the other status bits are not valid. 0 ro busy 0 write-only control register i2c master control/status (i2cmcs) i2c 0 base: 0x4002.0000 i2c 1 base: 0x4002.1000 offset 0x004 type wo, reset 0x0000.0020 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 run start stop ack reserved reserved reserved wo wo wo wo ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 reset july 03, 2014 814 texas instruments-production data inter-integrated circuit (i 2 c) interface description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:6 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 ro reserved 5 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 4 data acknowledge enable description value the received data byte is not acknowledged automatically by the master. 0 the received data byte is acknowledged automatically by the master. see field decoding in table 15-5 on page 816. 1 0 wo ack 3 generate stop description value the controller does not generate the stop condition. 0 the controller generates the stop condition. see field decoding in table 15-5 on page 816. 1 0 wo stop 2 generate start description value the controller does not generate the start condition. 0 the controller generates the start or repeated start condition. see field decoding in . 1 0 wo start 1 i 2 c master enable description value the master is disabled. 0 the master is enabled to transmit or receive data. see field decoding in table 15-5 on page 816. 1 0 wo run 0 815 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 15-5. write field decoding for i2cmcs[3:0] field description i2cmcs[3:0] i2cmsa[0] current state run start stop ack r/s start condition followed by transmit (master goes to the master transmit state). 1 1 0 x a 0 idle start condition followed by a transmit and stop condition (master remains in idle state). 1 1 1 x 0 start condition followed by receive operation with negative ack (master goes to the master receive state). 1 1 0 0 1 start condition followed by receive and stop condition (master remains in idle state). 1 1 1 0 1 start condition followed by receive (master goes to the master receive state). 1 1 0 1 1 illegal 1 1 1 1 1 nop all other combinations not listed are non-operations. transmit operation (master remains in master transmit state). 1 0 0 x x master transmit stop condition (master goes to idle state). 0 0 1 x x transmit followed by stop condition (master goes to idle state). 1 0 1 x x repeated start condition followed by a transmit (master remains in master transmit state). 1 1 0 x 0 repeated start condition followed by transmit and stop condition (master goes to idle state). 1 1 1 x 0 repeated start condition followed by a receive operation with a negative ack (master goes to master receive state). 1 1 0 0 1 repeated start condition followed by a transmit and stop condition (master goes to idle state). 1 1 1 0 1 repeated start condition followed by receive (master goes to master receive state). 1 1 0 1 1 illegal. 1 1 1 1 1 nop. all other combinations not listed are non-operations. july 03, 2014 816 texas instruments-production data inter-integrated circuit (i 2 c) interface table 15-5. write field decoding for i2cmcs[3:0] field (continued) description i2cmcs[3:0] i2cmsa[0] current state run start stop ack r/s receive operation with negative ack (master remains in master receive state). 1 0 0 0 x master receive stop condition (master goes to idle state). b 0 0 1 x x receive followed by stop condition (master goes to idle state). 1 0 1 0 x receive operation (master remains in master receive state). 1 0 0 1 x illegal. 1 0 1 1 x repeated start condition followed by receive operation with a negative ack (master remains in master receive state). 1 1 0 0 1 repeated start condition followed by receive and stop condition (master goes to idle state). 1 1 1 0 1 repeated start condition followed by receive (master remains in master receive state). 1 1 0 1 1 repeated start condition followed by transmit (master goes to master transmit state). 1 1 0 x 0 repeated start condition followed by transmit and stop condition (master goes to idle state). 1 1 1 x 0 nop. all other combinations not listed are non-operations. a. an x in a table cell indicates the bit can be 0 or 1. b. in master receive mode, a stop condition should be generated only after a data negative acknowledge executed by the master or an address negative acknowledge executed by the slave. 817 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 3: i 2 c master data (i2cmdr), offset 0x008 important: this register is read-sensitive. see the register description for details. this register contains the data to be transmitted when in the master transmit state and the data received when in the master receive state. i2c master data (i2cmdr) i2c 0 base: 0x4002.0000 i2c 1 base: 0x4002.1000 offset 0x008 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 data reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 data transferred data transferred during transaction. 0x00 r/w data 7:0 july 03, 2014 818 texas instruments-production data inter-integrated circuit (i 2 c) interface register 4: i 2 c master timer period (i2cmtpr), offset 0x00c this register specifies the period of the scl clock. i2c master timer period (i2cmtpr) i2c 0 base: 0x4002.0000 i2c 1 base: 0x4002.1000 offset 0x00c type r/w, reset 0x0000.0001 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tpr reserved r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro type 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:7 scl clock period this field specifies the period of the scl clock. scl_prd = 2(1 + tpr)(scl_lp + scl_hp)clk_prd where: scl_prd is the scl line period (i 2 c clock). tpr is the timer period register value (range of 1 to 127). scl_lp is the scl low period (fixed at 6). scl_hp is the scl high period (fixed at 4). clk_prd is the system clock period in ns. 0x1 r/w tpr 6:0 819 july 03, 2014 texas instruments-production data stellaris lm3s9gn5 microcontroller register 5: i 2 c master interrupt mask (i2cmimr), offset 0x010 this register controls whether a raw interrupt is promoted to a controller interrupt. i2c master interrupt mask (i2cmimr) i2c 0 base: 0x4002.0000 i2c 1 base: 0x4002.1000 offset 0x010 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 im reserved r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:1 interrupt mask description value the master interrupt is sent to the interrupt controller when the ris bit in the i2cmris register is set. 1 the ris interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w im 0 july 03, 2014 820 texas instruments-production data inter-integrated circuit (i 2 c) interface register 6: i 2 c master raw interrupt status (i2cmris), offset 0x014 this register specifies whether an interrupt is pending. i2c master raw interrupt status (i2cmris) i2c 0 base: 0x4002.0000 i2c 1 base: 0x4002.1000 offset 0x014 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ris reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:1 raw interrupt status description value a master interrupt is pending. 1 no interrupt. 0 this bit is cleared by writing a 1 to the ic bit in the i2cmicr register. 0 ro ris 0 821 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 7: i 2 c master masked interrupt status (i2cmmis), offset 0x018 this register specifies whether an interrupt was signaled. i2c master masked interrupt status (i2cmmis) i2c 0 base: 0x4002.0000 i2c 1 base: 0x4002.1000 offset 0x018 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mis reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:1 masked interrupt status description value an unmasked master interrupt was signaled and is pending. 1 an interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the ic bit in the i2cmicr register. 0 ro mis 0 july 03, 2014 822 texas instruments-production data inter-integrated circuit (i 2 c) interface register 8: i 2 c master interrupt clear (i2cmicr), offset 0x01c this register clears the raw and masked interrupts. i2c master interrupt clear (i2cmicr) i2c 0 base: 0x4002.0000 i2c 1 base: 0x4002.1000 offset 0x01c type wo, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ic reserved wo ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:1 interrupt clear writing a 1 to this bit clears the ris bit in the i2cmris register and the mis bit in the i2cmmis register. a read of this register returns no meaningful data. 0 wo ic 0 823 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 9: i 2 c master configuration (i2cmcr), offset 0x020 this register configures the mode (master or slave) and sets the interface for test mode loopback. i2c master configuration (i2cmcr) i2c 0 base: 0x4002.0000 i2c 1 base: 0x4002.1000 offset 0x020 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 lpbk reserved mfe sfe reserved r/w ro ro ro r/w r/w ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:6 i 2 c slave function enable description value slave mode is enabled. 1 slave mode is disabled. 0 0 r/w sfe 5 i 2 c master function enable description value master mode is enabled. 1 master mode is disabled. 0 0 r/w mfe 4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 3:1 i 2 c loopback description value the controller in a test mode loopback configuration. 1 normal operation. 0 0 r/w lpbk 0 15.7 register descriptions (i 2 c slave) the remainder of this section lists and describes the i 2 c slave registers, in numerical order by address offset. july 03, 2014 824 texas instruments-production data inter-integrated circuit (i 2 c) interface register 10: i 2 c slave own address (i2csoar), offset 0x800 this register consists of seven address bits that identify the stellaris i 2 c device on the i 2 c bus. i2c slave own address (i2csoar) i2c 0 base: 0x4002.0000 i2c 1 base: 0x4002.1000 offset 0x800 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 oar reserved r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:7 i 2 c slave own address this field specifies bits a6 through a0 of the slave address. 0x00 r/w oar 6:0 825 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 11: i 2 c slave control/status (i2cscsr), offset 0x804 this register functions as a control register when written, and a status register when read. read-only status register i2c slave control/status (i2cscsr) i2c 0 base: 0x4002.0000 i2c 1 base: 0x4002.1000 offset 0x804 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rreq treq fbr reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:3 first byte received description value the first byte following the slaves own address has been received. 1 the first byte has not been received. 0 this bit is only valid when the rreq bit is set and is automatically cleared when data has been read from the i2csdr register. note: this bit is not used for slave transmit operations. 0 ro fbr 2 transmit request description value the i 2 c controller has been addressed as a slave transmitter and is using clock stretching to delay the master until data has been written to the i2csdr register. 1 no outstanding transmit request. 0 0 ro treq 1 receive request description value the i 2 c controller has outstanding receive data from the i 2 c master and is using clock stretching to delay the master until the data has been read from the i2csdr register. 1 no outstanding receive data. 0 0 ro rreq 0 july 03, 2014 826 texas instruments-production data inter-integrated circuit (i 2 c) interface write-only control register i2c slave control/status (i2cscsr) i2c 0 base: 0x4002.0000 i2c 1 base: 0x4002.1000 offset 0x804 type wo, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 da reserved wo ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:1 device active description value disables the i 2 c slave operation. 0 enables the i 2 c slave operation. 1 once this bit has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur. 0 wo da 0 827 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 12: i 2 c slave data (i2csdr), offset 0x808 important: this register is read-sensitive. see the register description for details. this register contains the data to be transmitted when in the slave transmit state, and the data received when in the slave receive state. i2c slave data (i2csdr) i2c 0 base: 0x4002.0000 i2c 1 base: 0x4002.1000 offset 0x808 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 data reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 data for transfer this field contains the data for transfer during a slave receive or transmit operation. 0x00 r/w data 7:0 july 03, 2014 828 texas instruments-production data inter-integrated circuit (i 2 c) interface register 13: i 2 c slave interrupt mask (i2csimr), offset 0x80c this register controls whether a raw interrupt is promoted to a controller interrupt. i2c slave interrupt mask (i2csimr) i2c 0 base: 0x4002.0000 i2c 1 base: 0x4002.1000 offset 0x80c type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dataim startim stopim reserved r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:3 stop condition interrupt mask description value the stop condition interrupt is sent to the interrupt controller when the stopris bit in the i2csris register is set. 1 the stopris interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w stopim 2 start condition interrupt mask description value the start condition interrupt is sent to the interrupt controller when the startris bit in the i2csris register is set. 1 the startris interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w startim 1 data interrupt mask description value the data received or data requested interrupt is sent to the interrupt controller when the dataris bit in the i2csris register is set. 1 the dataris interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w dataim 0 829 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 14: i 2 c slave raw interrupt status (i2csris), offset 0x810 this register specifies whether an interrupt is pending. i2c slave raw interrupt status (i2csris) i2c 0 base: 0x4002.0000 i2c 1 base: 0x4002.1000 offset 0x810 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dataris startris stopris reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:3 stop condition raw interrupt status description value a stop condition interrupt is pending. 1 no interrupt. 0 this bit is cleared by writing a 1 to the stopic bit in the i2csicr register. 0 ro stopris 2 start condition raw interrupt status description value a start condition interrupt is pending. 1 no interrupt. 0 this bit is cleared by writing a 1 to the startic bit in the i2csicr register. 0 ro startris 1 data raw interrupt status description value a data received or data requested interrupt is pending. 1 no interrupt. 0 this bit is cleared by writing a 1 to the dataic bit in the i2csicr register. 0 ro dataris 0 july 03, 2014 830 texas instruments-production data inter-integrated circuit (i 2 c) interface register 15: i 2 c slave masked interrupt status (i2csmis), offset 0x814 this register specifies whether an interrupt was signaled. i2c slave masked interrupt status (i2csmis) i2c 0 base: 0x4002.0000 i2c 1 base: 0x4002.1000 offset 0x814 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 datamis startmis stopmis reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:3 stop condition masked interrupt status description value an unmasked stop condition interrupt was signaled is pending. 1 an interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the stopic bit in the i2csicr register. 0 ro stopmis 2 start condition masked interrupt status description value an unmasked start condition interrupt was signaled is pending. 1 an interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the startic bit in the i2csicr register. 0 ro startmis 1 data masked interrupt status description value an unmasked data received or data requested interrupt was signaled is pending. 1 an interrupt has not occurred or is masked. 0 this bit is cleared by writing a 1 to the dataic bit in the i2csicr register. 0 ro datamis 0 831 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 16: i 2 c slave interrupt clear (i2csicr), offset 0x818 this register clears the raw interrupt. a read of this register returns no meaningful data. i2c slave interrupt clear (i2csicr) i2c 0 base: 0x4002.0000 i2c 1 base: 0x4002.1000 offset 0x818 type wo, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dataic startic stopic reserved wo wo wo ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:3 stop condition interrupt clear writing a 1 to this bit clears the stopris bit in the i2csris register and the stopmis bit in the i2csmis register. a read of this register returns no meaningful data. 0 wo stopic 2 start condition interrupt clear writing a 1 to this bit clears the stopris bit in the i2csris register and the stopmis bit in the i2csmis register. a read of this register returns no meaningful data. 0 wo startic 1 data interrupt clear writing a 1 to this bit clears the stopris bit in the i2csris register and the stopmis bit in the i2csmis register. a read of this register returns no meaningful data. 0 wo dataic 0 july 03, 2014 832 texas instruments-production data inter-integrated circuit (i 2 c) interface 16 inter-integrated circuit sound (i 2 s) interface the i 2 s module is a configurable serial audio core that contains a transmit module and a receive module. the module is configurable for the i 2 s as well as left-justified and right-justified serial audio formats. data can be in one of four modes: stereo, mono, compact 16-bit stereo and compact 8-bit stereo. the transmit and receive modules each have an 8-entry audio-sample fifo. an audio sample can consist of a left and right stereo sample, a mono sample, or a left and right compact stereo sample. in compact 16-bit stereo, each fifo entry contains both the 16-bit left and 16-bit right samples, allowing efficient data transfers and requiring less memory space. in compact 8-bit stereo, each fifo entry contains an 8-bit left and an 8-bit right sample, reducing memory requirements further. both the transmitter and receiver are capable of being a master or a slave. the stellaris ? i 2 s module has the following features: configurable audio format supporting i 2 s, left-justification, and right-justification configurable sample size from 8 to 32 bits mono and stereo support 8-, 16-, and 32-bit fifo interface for packing memory independent transmit and receive 8-entry fifos configurable fifo-level interrupt and dma requests independent transmit and receive mclk direction control transmit and receive internal mclk sources independent transmit and receive control for serial clock and word select mclk and sclk can be independently set to master or slave configurable transmit zero or last sample when fifo empty efficient transfers using micro direct memory access controller (dma) C separate channels for transmit and receive C burst requests C channel requests asserted when fifo contains required amount of data 833 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 16.1 block diagram figure 16-1. i 2 s block diagram 16.2 signal description the following table lists the external signals of the i 2 s module and describes the function of each. the i 2 s module signals are alternate functions for some gpio signals and default to be gpio signals at reset. the column in the table below titled "pin mux/pin assignment" lists the possible gpio pin placements for the i 2 s signals. the afsel bit in the gpio alternate function select (gpioafsel) register (page 429) should be set to choose the i 2 s function. the number in parentheses is the encoding that must be programmed into the pmcn field in the gpio port control (gpiopctl) register (page 447) to assign the i 2 s signal to the specified gpio port pin. for more information on configuring gpios, see general-purpose input/outputs (gpios) on page 405. july 03, 2014 834 texas instruments-production data inter-integrated circuit sound (i 2 s) interface , 6 7 ; 0 & / . 6 \ v w h p $ + % % x v 6 \ v & o n , 6 5 ; & ) * 5 h f h l y h ) , ) 2 5 h f h l y h ) , ) 2 h q w u \ , 6 5 ; 6 & . , 6 5 ; 6 ' , 6 5 ; : 6 , 6 5 ; 0 & / . , 6 5 ; ) , ) 2 , 6 5 ; ) , ) 2 & ) * , 6 5 ; / , 0 , 7 , 6 5 ; / ( 9 6 h u l d o ' h f r g h u % l w & o n : g 6 h o * h q h u d w l r q , 6 5 ; , 6 0 , q w h u u x s w v ' 0 $ 5 h j l v w h u v , 6 , & , 6 , 0 , 6 5 , 6 , 6 0 , 6 , 6 & ) * , 6 7 ; , 6 0 7 u d q v p l w ) , ) 2 7 u d q v p l w ) , ) 2 h q w u \ 6 h u l d o ( q f r g h u , 6 7 ; 6 ' , 6 7 ; 6 & . % l w & o n : g 6 h o * h q h u d w l r q , 6 7 ; : 6 , 6 7 ; ) , ) 2 , 6 7 ; ) , ) 2 & ) * , 6 7 ; / , 0 , 7 , 6 7 ; / ( 9 , 6 7 ; & ) * table 16-1. i2s signals (100lqfp) description buffer type a pin type pin mux / pin assignment pin number pin name i 2 s module 0 receive master clock. ttl i/o pg3 (9) pa3 (9) pd5 (8) 16 29 98 i2s0rxmclk i 2 s module 0 receive clock. ttl i/o pd0 (8) pg5 (9) 10 40 i2s0rxsck i 2 s module 0 receive data. ttl i/o pg2 (9) pa2 (9) pd4 (8) 17 28 97 i2s0rxsd i 2 s module 0 receive word select. ttl i/o pd1 (8) pg6 (9) 11 37 i2s0rxws i 2 s module 0 transmit master clock. ttl i/o pf6 (9) pf1 (8) 43 61 i2s0txmclk i 2 s module 0 transmit clock. ttl i/o pa4 (9) pb6 (9) pd6 (8) 30 90 99 i2s0txsck i 2 s module 0 transmit data. ttl i/o pe5 (9) pf0 (8) 5 47 i2s0txsd i 2 s module 0 transmit word select. ttl i/o pe4 (9) pa5 (9) pd7 (8) 6 31 100 i2s0txws a. the ttl designation indicates the pin has ttl-compatible voltage levels. table 16-2. i2s signals (108bga) description buffer type a pin type pin mux / pin assignment pin number pin name i 2 s module 0 receive master clock. ttl i/o pg3 (9) pa3 (9) pd5 (8) j2 l4 c6 i2s0rxmclk i 2 s module 0 receive clock. ttl i/o pd0 (8) pg5 (9) g1 m7 i2s0rxsck i 2 s module 0 receive data. ttl i/o pg2 (9) pa2 (9) pd4 (8) j1 m4 b5 i2s0rxsd i 2 s module 0 receive word select. ttl i/o pd1 (8) pg6 (9) g2 l7 i2s0rxws i 2 s module 0 transmit master clock. ttl i/o pf6 (9) pf1 (8) m8 h12 i2s0txmclk i 2 s module 0 transmit clock. ttl i/o pa4 (9) pb6 (9) pd6 (8) l5 a7 a3 i2s0txsck i 2 s module 0 transmit data. ttl i/o pe5 (9) pf0 (8) b3 m9 i2s0txsd i 2 s module 0 transmit word select. ttl i/o pe4 (9) pa5 (9) pd7 (8) b2 m5 a2 i2s0txws a. the ttl designation indicates the pin has ttl-compatible voltage levels. 835 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 16.3 functional description the inter-integrated circuit sound (i 2 s) module contains separate transmit and receive engines. each engine consists of the following: serial encoder for the transmitter; serial decoder for the receiver 8-entry fifo to store sample data independent configuration of all programmable settings the basic programming model of the i 2 s block is as follows: configuration C overall i 2 s module configuration in the i 2 s module configuration (i2scfg) register. this register is used to select the mclk source and enable the receiver and transmitter. C transmit and receive configuration in the i 2 s transmit module configuration (i2stxcfg) and i 2 s receive module configuration (i2srxcfg) registers. these registers set the basic parameters for the receiver and transmitter such as data configuration (justification, delay, read mode, sample size, and system data size); sclk (polarity and source); and word select polarity. C transmit and receive fifo configuration in the i 2 s transmit fifo configuration (i2stxfifocfg) and i 2 s receive fifo configuration (i2srxfifocfg) registers. these registers select the compact stereo mode size (16-bit or 8-bit), provide indication of whether the next sample is left or right, and select mono mode for the receiver. fifo C transmit and receive fifo data in the i 2 s transmit fifo data (i2stxfifo) and i 2 s receive fifo data (i2srxfifo) registers C information on fifo data levels in the i 2 s transmit fifo level (i2stxlev) and i 2 s receive fifo level (i2srxlev) registers C configuration for fifo service requests based on fifo levels in the i 2 s transmit fifo limit (i2stxlimit) and i 2 s receive fifo limit (i2srxlim) registers interrupt control C interrupt masking configuration in the i 2 s interrupt mask (i2sim) register C raw and masked interrupt status in the i 2 s raw interrupt status (i2sris) and i 2 s masked interrupt status (i2smis ) registers C interrupt clearing through the i 2 s interrupt clear (i2sic) register C configuration for fifo service requests interrupts and transmit/receive error interrupts in the i 2 s transmit interrupt status and mask (i2stxism) and i 2 s receive interrupt status and mask (i2srxism) registers july 03, 2014 836 texas instruments-production data inter-integrated circuit sound (i 2 s) interface figure 16-2 on page 837 provides an example of an i 2 s data transfer. figure 16-3 on page 837 provides an example of an left-justified data transfer. figure 16-4 on page 837 provides an example of an right-justified data transfer. figure 16-2. i 2 s data transfer figure 16-3. left-justified data transfer figure 16-4. right-justified data transfer 16.3.1 transmit the transmitter consists of a serial encoder, an 8-entry fifo, and control logic. the transmitter has independent mclk ( i2s0txmclk ), sclk (i2s0txsck ), and word-select (i2s0txws ) signals. 16.3.1.1 serial encoder the serial encoder reads audio samples from the receive fifo and converts them into an audio stream. by configuring the serial encoder, common audio formats i 2 s, left-justified, and right-justified are supported. the msb is transmitted first. the sample size and system data size 837 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 6 & . : r u g 6 h o h f w 6 h u l d o ' d w d 0 6 % / 6 % : 2 5 ' q 5 , * + 7 & + $ 1 1 ( / : 2 5 ' q / ( ) 7 & + $ 1 1 ( / : 2 5 ' q 5 , * + 7 & + $ 1 1 ( / 0 6 % 0 6 % / 6 % 6 \ v w h p ' d w d 6 l ] h / h i w & k d q q h o 6 d p s o h 6 l ] h : r u g 6 h o h f w 6 h u l d o ' d w d 6 & / . 0 6 % / 6 % 5 l j k w & k d q q h o 6 \ v w h p ' d w d 6 l ] h / h i w & k d q q h o 5 l j k w & k d q q h o 0 6 % / 6 % 0 6 % / 6 % 6 d p s o h 6 l ] h 6 h u l d o ' d w d : r u g 6 h o h f w 6 & / . are configurable with the ssz and sdsz bits in the i 2 s transmit module configuration (i2stxcfg) register. the sample size is the number of bits of data being transmitted, and the system data size is the number of i2s0txsck transitions between the word select transitions. the system data size must be large enough to accommodate the maximum sample size. in mono mode, the sample data is repeated in both the left and right channels. when the fifo is empty, the user may select either transmission of zeros or of the last sample. the serial encoder is enabled using the txen bit in the i 2 s module configuration (i2scfg) register. 16.3.1.2 fifo operation the transmit fifo stores eight mono samples or eight stereo sample-pairs of data and is accessed through the i 2 s transmit fifo data (i2stxfifo) register. the fifo interface for the audio data is different based on the write mode, defined by the i 2 s transmit fifo configuration (i2stxfifocfg) compact stereo sample size bit ( css ) and the i2stxcfg write mode field ( wm). all data samples are msb-aligned. table 16-3 on page 838 defines the interface for each write mode. stereo samples are written first left then right. the next sample (right or left) to be written is indicated by the lrs bit in the i2stxfifocfg register. table 16-3. i 2 s transmit fifo interface data alignment samples per fifo write sample width write mode css bit in i2stxfifocfg wm field in i2stxcfg msb 1 8-32 bits stereo don't care 0x0 msb right [31:16], left [15:0] 2 8-16 bits compact stereo - 16 bit 0 0x1 right [15:8], left[7:0] 2 8 bits compact stereo - 8 bit 1 0x1 msb 1 8-32 bits mono don't care 0x2 the number of samples in the transmit fifo can be read using the i 2 s transmit fifo level (i2stxlev) register. the value ranges from 0 to 16. stereo and compact stereo sample pairs are counted as two. the mono samples also increment the count by two, therefore, four mono samples will have a count of eight. 16.3.1.3 clock control the transmitter mclk and sclk can be independently programmed to be the master or slave. the transmitter is programmed to be the master or slave of the sclk using the msl bit in the i2stxcfg register. when the transmitter is the master, the i2s0txsck frequency is the specified i2s0txmclk divided by four. the i2s0txsck may be inverted using the scp bit in the i2stxcfg register. the transmitter can also be the master or slave of the mclk. when the transmitter is the master, the pll must be active and a fractional clock divider must be programmed. see page 234 for the setup for the master i2s0txmclk source. an external transmit i2s0txmclk does not require the use of the pll and is selected using the txslv bit in the i2scfg register. the following tables show combinations of the txint and txfrac bits in the i 2 s mclk configuration (i2smclkcfg) register that provide mclk frequencies within acceptable error limits. in the table, fs is the sampling frequency in khz and possible crystal frequencies are shown in mhz across the top row of the table. the words "not supported" in the table mean that it is not possible to obtain the specified sampling frequencies with the specified crystal frequency within the error tolerance of 0.3%. the values in the table are based on the following values: mclk = fs 256 pll = 400 mhz july 03, 2014 838 texas instruments-production data inter-integrated circuit sound (i 2 s) interface the integer value is taken from the result of the following calculation: round(pll/mclk) the remaining fractional component is converted to binary, and the first four bits are the fractional value. table 16-4. crystal frequency (values from 3.5795 mhz to 5 mhz) crystal frequency (mhz) sampling frequency fs (khz) 5 4.9152 4.096 4 3.6864 3.5795 fractional integer fractional integer fractional integer fractional integer fractional integer fractional integer 5 195 6 194 0 196 5 195 6 194 12 195 8 12 141 1 141 4 142 12 141 1 141 1 142 11.025 3 130 10 129 11 130 3 130 10 129 8 130 12 10 97 3 97 0 98 10 97 3 97 14 97 16 14 70 8 70 2 71 14 70 8 70 0 71 22.05 2 65 13 64 5 65 2 65 13 64 4 65 24 13 48 10 48 0 49 13 48 10 48 15 48 32 7 35 4 35 9 35 7 35 4 35 8 35 44.1 9 32 6 32 11 32 9 32 6 32 10 32 48 7 24 5 24 8 24 7 24 5 24 8 24 64 11 17 10 17 12 17 11 17 10 17 12 17 88.2 4 16 3 16 5 16 4 16 3 16 5 16 96 3 12 2 12 4 12 3 12 2 12 4 12 128 14 8 13 8 14 8 14 8 13 8 14 8 176.4 2 8 not supported 3 8 2 8 not supported not supported 192 table 16-5. crystal frequency (values from 5.12 mhz to 8.192 mhz) crystal frequency (mhz) sampling frequency fs (khz) 8.192 8 7.3728 6.144 6 5.12 fractional integer fractional integer fractional integer fractional integer fractional integer fractional integer 11 194 5 195 6 194 0 195 5 195 0 195 8 4 141 12 141 1 141 8 141 12 141 8 141 11.025 12 129 3 130 10 129 0 130 3 130 0 130 12 5 97 10 97 3 97 8 97 10 97 8 97 16 10 70 14 70 8 70 12 70 14 70 12 70 22.05 14 64 2 65 13 64 0 65 2 65 0 65 24 11 48 13 48 10 48 12 48 13 48 12 48 32 5 35 7 35 4 35 6 35 7 35 6 35 44.1 7 32 9 32 6 32 8 32 9 32 8 32 48 5 24 7 24 5 24 6 24 7 24 6 24 64 11 17 11 17 10 17 11 17 11 17 11 17 88.2 4 16 4 16 3 16 4 16 4 16 4 16 96 3 12 3 12 2 12 3 12 3 12 3 12 128 13 8 14 8 13 8 not supported 14 8 not supported 176.4 2 8 2 8 not supported 2 8 2 8 2 8 192 839 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 16-6. crystal frequency (values from 10 mhz to 14.3181 mhz) crystal frequency (mhz) sampling frequency fs (khz) 14.3181 13.56 12.288 12 10 fractional integer fractional integer fractional integer fractional integer fractional integer 12 195 3 194 0 196 5 195 5 195 8 1 142 15 140 4 142 12 141 12 141 11.025 8 130 8 129 11 130 3 130 3 130 12 14 97 2 97 0 98 10 97 10 97 16 0 71 7 70f 2 71 14 70 14 70 22.05 4 65 12 64 5 65 2 65 2 65 24 15 48 9 48 0 49 13 48 13 48 32 8 35 4 35 9 35 7 35 7 35 44.1 10 32 6 32 11 32 9 32 9 32 48 8 24 4 24 8 24 7 24 7 24 64 12 17 10 17 12 17 11 17 11 17 88.2 5 16 3 16 5 16 4 16 4 16 96 4 12 2 12 4 12 3 12 3 12 128 14 8 13 8 14 8 14 8 14 8 176.4 not supported not supported 3 8 2 8 2 8 192 table 16-7. crystal frequency (values from 16 mhz to 16.384 mhz) crystal frequency (mhz) sampling frequency fs (khz) 16.384 16 fractional integer fractional integer 0 192 5 195 8 5 139 12 141 11.025 0 128 3 130 12 0 96 10 97 16 11 69 14 70 22.05 0 64 2 65 24 0 48 13 48 32 13 34 7 35 44.1 0 32 9 32 48 0 24 7 24 64 7 17 11 17 88.2 0 16 4 16 96 0 12 3 12 128 11 8 14 8 176.4 0 8 2 8 192 16.3.1.4 interrupt control a single interrupt is asserted to the cpu whenever any of the transmit or receive sources is asserted. the transmit module has two interrupt sources: the fifo service request and write error. the interrupts may be masked using the txsrim and txweim bits in the i 2 s interrupt mask (i2sim) july 03, 2014 840 texas instruments-production data inter-integrated circuit sound (i 2 s) interface register. the status of the interrupt source is indicated by the i 2 s raw interrupt status (i2sris) register. the status of enabled interrupts is indicated by the i 2 s masked interrupt status (i2smis) register. the fifo level interrupt has a second level of masking using the ffm bit in the i 2 s transmit interrupt status and mask (i2stxism) register. the fifo service request interrupt is asserted when the fifo level (indicated by the level field in the i 2 s transmit fifo level (i2stxlev) register) is below the fifo limit (programmed using the i 2 s transmit fifo limit (i2stxlimit) register) and both the txsrim and ffm bits are set. if software attempts to write to a full fifo, a transmit fifo write error occurs (indicated by the txweris bit in the i 2 s raw interrupt status (i2sris) register). the txweris bit in the i2sris register and the txwemis bit in the i2smis register are cleared by setting the txweic bit in the i 2 s interrupt clear (i2sic) register. 16.3.1.5 dma support the dma can be used to more efficiently stream data to and from the i 2 s bus. the i 2 s tranmit and receive modules have separate dma channels. the fifo interrupt mask bit ( ffm ) in the i2stxism register must be set for the request signaling to propagate to the dma module. see micro direct memory access (dma) on page 344 for channel configuration. the i 2 s module uses the dma burst request signal, not the single request. thus each time a dma request is made, the dma controller transfers the number of items specified as the burst size for the dma channel. therefore, the dma channel burst size and the i 2 s fifo service request limit must be set to the same value (using the limit field in the i2stxlimit register). 16.3.2 receive the receiver consists of a serial decoder, an 8-entry fifo, and control logic. the receiver has independent mclk ( i2s0rxmclk ), sclk (i2s0rxsck ), and word-select (i2s0rxws ) signals. 16.3.2.1 serial decoder the serial decoder accepts incoming audio stream data and places the sample data in the receive fifo. by configuring the serial decoder, common audio formats i 2 s, left-justified, and right-justified are supported. the msb is transmitted first. the sample size and system data size are configurable with the ssz and sdsz bits in the i 2 s receive module configuration (i2srxcfg) register. the sample size is the number of bits of data being received, and the system data size is the number of i2s0rxsck transitions between the word select transitions. the system data size must be large enough to accommodate the maximum sample size. any bits received after the lsb are 0s. if the fifo is full, the incoming sample (in mono) or sample-pairs (stereo) are dropped until the fifo has space. the serial decoder is enabled using the rxen bit in the i2scfg register. 16.3.2.2 fifo operation the receive fifo stores eight mono samples or eight stereo sample-pairs of data and is accessed through the i 2 s receive fifo data (i2srxfifo) register. table 16-8 on page 842 defines the interface for each read mode. all data is stored msb-aligned. the stereo data is read left sample then right. in mono mode, the fifo interface can be configured to read the right or left channel by setting the fifo mono mode bit ( fmm ) in the i 2 s receive fifo configuration (i2srxfifocfg) register. this enables reads from a single channel, where the channel selected can be either the right or left as determined by the lrp bit in the i2srxcfg register. 841 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 16-8. i 2 s receive fifo interface data alignment samples per fifo read sample width read mode css bit in i2srxfifocfg rm bit in i2rxcfg msb 1 8-32 bits stereo don't care 0 msb right [31:15], left [15:0] 2 8-16 bits compact stereo - 16 bit 0 1 right [15:8] left[7:0] 2 8 bits compact stereo - 8 bit 1 1 msb 1 8-32 bits mono ( fmm bit in the i2srxfifocfg register must be set.) don't care 0 the number of samples in the receive fifo can be read using the i 2 s receive fifo level (i2srxlev) register. the value ranges from 0 to 16. stereo and compact stereo sample pairs are counted as two. the mono samples also increment the count by two, therefore four mono samples will have a count of eight. 16.3.2.3 clock control the receiver mclk and sclk can be independently programmed to be the master or slave. the receiver is programmed to be the master or slave of the sclk using the msl bit in the i2srxcfg register. when the receiver is the master, the i2s0rxsck frequency is the specified i2s0rxmclk divided by four. the i2s0rxsck may be inverted using the scp bit in the i2srxcfg register. the receiver can also be the master or slave of the mclk. when the receiver is the master, the pll must be active and a fractional clock divider must be programmed. see page 234 for the setup for the master i2s0rxmclk source. an external transmit i2s0rxmclk does not require the use of the pll and is selected using the rxslv bit in the i2scfg register. refer to clock control on page 838 for combinations of the rxint and rxfrac bits in the i 2 s mclk configuration (i2smclkcfg) register that provide mclk frequencies within acceptable error limits. in the table, fs is the sampling frequency in khz and possible crystal frequencies are shown in mhz across the top row of the table. the words "not supported" in the table mean that it is not possible to obtain the specified sampling frequencies with the specified crystal frequency within the error tolerance of 0.3%. 16.3.2.4 interrupt control a single interrupt is asserted to the cpu whenever any of the transmit or receive sources is asserted. the receive module has two interrupt sources: the fifo service request and read error. the interrupts may be masked using the rxsrim and rxreim bits in the i2sim register. the status of the interrupt source is indicated by the i2sris register. the status of enabled interrupts is indicated by the i2smis register. the fifo service request interrupt has a second level of masking using the ffm bit in the i 2 s receive interrupt status and mask (i2srxism) register. the sources may be masked using the i2sim register. the fifo service request interrupt is asserted when the fifo level (indicated by the level field in the i 2 s receive fifo level (i2srxlev) register) is above the fifo limit (programmed using the i 2 s receive fifo limit (i2srxlimit) register) and both the rxsrim and ffm bits are set. an error occurs when reading an empty fifo or if a stereo sample pair is not read left then right. to clear an interrupt, write a 1 to the appropriate bit in the i2sic register. if software attempts to read an empty fifo or if a stereo sample pair is not read left then right, a receive fifo read error occurs (indicated by the rxreris bit in the i2sris register). the rxreris bit in the i2sris register and the rxremis bit in the i2smis register are cleared by setting the rxreic bit in the i2sic register. july 03, 2014 842 texas instruments-production data inter-integrated circuit sound (i 2 s) interface 16.3.2.5 dma support the dma can be used to more efficiently stream data to and from the i 2 s bus. the i 2 s transmit and receive modules have separate dma channels. the fifo interrupt mask bit ( ffm ) in the i2srxism register must be set for the request signaling to propagate to the dma module. see micro direct memory access (dma) on page 344 for channel configuration. the i 2 s module uses the dma burst request signal, not the single request. thus each time a dma request is made, the dma controller transfers the number of items specified as the burst size for the dma channel. therefore, the dma channel burst size and the i 2 s fifo service request limit must be set to the same value (using the limit field in the i2srxlimit register). 16.4 initialization and configuration the default setup for the i 2 s transmit and receive is to use external mclk, external sclk, stereo, i 2 s audio format, and 32-bit data samples. the following example shows how to configure a system using the internal mclk, internal sclk, compact stereo, and left-justified audio format with 16-bit data samples. 1. enable the i 2 s peripheral clock by writing a value of 0x1000.0000 to the rcgc1 register in the system control module (see page 270). 2. enable the clock to the appropriate gpio module via the rcgc2 register in the system control module (see page 282). to find out which gpio port to enable, refer to table 24-5 on page 1248. 3. in the gpio module, enable the appropriate pins for their alternate function using the gpioafsel register (see page 429). to determine which gpios to configure, see table 24-4 on page 1239. 4. configure the pmcn fields in the gpiopctl register to assign the i 2 s signals to the appropriate pins (see page 447 and table 24-5 on page 1248). 5. set up the mclk sources for a 48-khz sample rate. the input crystal is assumed to be 6 mhz for this example (internal source). enable the pll by clearing the pwrdwn bit in the rcc register in the system control module (see page 219). set the mclk dividers and enable them by writing 0x0208.0208 to the i2smclkcfg register in the system control module (see page 234). enable the mclk internal sources by writing 0x8208.8208 to the i2smclkcfg register in the system control module. to allow an external mclk to be used, set bits 4 and 5 of the i2scfg register. starting up the pll and enabling the mclk sources is not required. 6. set up the serial bit clock sclk source. by default, the sclk is externally sourced. receiver: masters the i2s0rxsck by oring 0x0040.0000 into the i2srxcfg register. transmitter: masters the i2s0txsck by oring 0x0040.0000 into the i2stxcfg register. 7. configure the serial encoder/decoder (left-justified, compact stereo, 16-bit samples, 32-bit system data size). 843 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller set the audio format using the justification ( jst ), data delay (dly ), sclk polarity (scp), and left-right polarity ( lrp ) bits written to the i2stxcfg and i2srxcfg registers. the settings are shown in the table below. table 16-9. audio formats configuration i2stxcfg/i2srxcfg register bit audio format lrp scp dly jst 1 0 1 0 i 2 s 0 0 0 0 left-justified 0 0 0 1 right-justified write 0x0140.3df0 to both the i2stxcfg and i2srxcfg registers to program the following configurations: C set the sample size to 16 bits using the ssz field of the i2stxcfg and i2srxcfg registers. C set the system data size to 32 bits using the sdsz field of the i2stxcfg and i2srxcfg registers. C set the write and read modes using the wm and rm fields in the i2stxcfg and i2srxcfg registers, respectively. 8. set up the fifo limits for triggering interrupts (also used for dma) set up the transmit fifo to trigger when it has less than four sample pairs by writing a 0x0000.0008 to the i2stxlimit register. set up the receive fifo to trigger when there are more than four sample pairs by writing a 0x0000.00008 to the i2srxlimit register. 9. enable interrupts. enable the transmit fifo interrupt by setting the ffm bit in the i2stxism register (write 0x0000.0001). set up the receive fifo interrupts by setting the ffm bit in the i2srxism register (write 0x0000.0001). enable the tx fifo service request, the tx error, the rx fifo service request, and the rx error interrupts to be sent to the cpu by writing a 0x0000.0033 to the i2ssim register. 10. enable the serial encoder and serial decoders by writing a 0x0000.0003 to the i2scfg register. 16.5 register map table 16-10 on page 845 lists the i 2 s registers. the offset listed is a hexadecimal increment to the registers address, relative to the i 2 s interface base address of 0x4005.4000. note that the i 2 s module clock must be enabled before the registers can be programmed (see page 270). there must be a delay of 3 system clocks after the i 2 s module clock is enabled before any i 2 s module registers are accessed. july 03, 2014 844 texas instruments-production data inter-integrated circuit sound (i 2 s) interface table 16-10. inter-integrated circuit sound (i 2 s) interface register map see page description reset type name offset 846 i2s transmit fifo data 0x0000.0000 wo i2stxfifo 0x000 847 i2s transmit fifo configuration 0x0000.0000 r/w i2stxfifocfg 0x004 848 i2s transmit module configuration 0x1400.7df0 r/w i2stxcfg 0x008 850 i2s transmit fifo limit 0x0000.0000 r/w i2stxlimit 0x00c 851 i2s transmit interrupt status and mask 0x0000.0000 r/w i2stxism 0x010 852 i2s transmit fifo level 0x0000.0000 ro i2stxlev 0x018 853 i2s receive fifo data 0x0000.0000 ro i2srxfifo 0x800 854 i2s receive fifo configuration 0x0000.0000 r/w i2srxfifocfg 0x804 855 i2s receive module configuration 0x1400.7df0 r/w i2srxcfg 0x808 858 i2s receive fifo limit 0x0000.7fff r/w i2srxlimit 0x80c 859 i2s receive interrupt status and mask 0x0000.0000 r/w i2srxism 0x810 860 i2s receive fifo level 0x0000.0000 ro i2srxlev 0x818 861 i2s module configuration 0x0000.0000 r/w i2scfg 0xc00 863 i2s interrupt mask 0x0000.0000 r/w i2sim 0xc10 865 i2s raw interrupt status 0x0000.0000 ro i2sris 0xc14 867 i2s masked interrupt status 0x0000.0000 ro i2smis 0xc18 869 i2s interrupt clear 0x0000.0000 wo i2sic 0xc1c 16.6 register descriptions the remainder of this section lists and describes the i 2 s registers, in numerical order by address offset. 845 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 1: i 2 s transmit fifo data (i2stxfifo), offset 0x000 this register is the 32-bit serial audio transmit data register. in stereo mode, the data is written left, right, left, right, and so on. the lrs bit in the i 2 s transmit fifo configuration (i2stxfifocfg) register can be read to verify the next position expected. in compact 16-bit mode, bits [31:16] contain the right sample, and bits [15:0] contain the left sample. in compact 8-bit mode, bits [15:8] contain the right sample, and bits [7:0] contain the left sample. in mono mode, each 32-bit entry is a single sample. note that if the fifo is full and a write is attempted, a transmit fifo write error is generated. i2s transmit fifo data (i2stxfifo) base 0x4005.4000 offset 0x000 type wo, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 txfifo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 txfifo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field tx data serial audio sample data to be transmitted. 0x0000.0000 wo txfifo 31:0 july 03, 2014 846 texas instruments-production data inter-integrated circuit sound (i 2 s) interface register 2: i 2 s transmit fifo configuration (i2stxfifocfg), offset 0x004 this register configures the sample for dual-channel operation. in stereo mode, the lrs bit toggles between left and right samples as the transmit fifo is written. the left sample is written first, followed by the right. i2s transmit fifo configuration (i2stxfifocfg) base 0x4005.4000 offset 0x004 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 lrs css reserved r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:2 compact stereo sample size description value the transmitter is in compact 16-bit stereo mode with a 16-bit sample size. 0 the transmitter is in compact 8-bit stereo mode with an 8-bit sample size. 1 0 r/w css 1 left-right sample indicator description value the left sample is the next position. 0 the right sample is the next position. 1 in mono mode and compact stereo mode, this bit toggles as if it were in stereo mode, but it has no meaning and should be ignored. 0 r/w lrs 0 847 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 3: i 2 s transmit module configuration (i2stxcfg), offset 0x008 this register controls the configuration of the transmit module. i2s transmit module configuration (i2stxcfg) base 0x4005.4000 offset 0x008 type r/w, reset 0x1400.7df0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved msl fmt wm lrp scp dly jst reserved ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w ro ro type 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved sdsz ssz ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 1 1 1 1 1 0 1 1 1 1 1 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 31:30 justification of output data description value the data is left-justified. 0 the data is right-justified. 1 0 r/w jst 29 data delay description value data is latched on the next latching edge of i2s0txsck as defined by the scp bit. this bit should be clear in left-justified or right-justified mode. 0 a one- i2s0txsck delay from the edge of i2s0txws is inserted before data is latched. this bit should be set in i 2 s mode. 1 1 r/w dly 28 sclk polarity description value data and the i2s0txws signal (when the msl bit is set) are launched on the falling edge of i2s0txsck. 0 data and the i2s0txws signal (when the msl bit is set) are launched on the rising edge of i2s0txsck. 1 0 r/w scp 27 left/right clock polarity description value i2s0txws is high during the transmission of the left channel data. 0 i2s0txws is high during the transmission of the right channel data. 1 1 r/w lrp 26 july 03, 2014 848 texas instruments-production data inter-integrated circuit sound (i 2 s) interface description reset type name bit/field write mode this bit field selects the mode in which the transmit data is stored in the fifo and transmitted. description value stereo mode 0x0 compact stereo mode left/right sample packed. refer to i2stxfifocfg for 8/16-bit sample size selection. 0x1 mono mode 0x2 reserved 0x3 0x0 r/w wm 25:24 fifo empty description value all zeroes are transmitted if the fifo is empty. 0 the last sample is transmitted if the fifo is empty. 1 0 r/w fmt 23 sclk master/slave source of serial bit clock ( i2s0txsck ) and word select (i2s0txws). description value the transmitter is a slave using the externally driven i2s0txsck and i2s0txws signals. 0 the transmitter is a master using the internally generated i2s0txsck and i2s0txws signals. 1 0 r/w msl 22 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 21:16 sample size this field contains the number of bits minus one in the sample. note: this field is only used in right-justified mode. unused bits are not masked. 0x1f r/w ssz 15:10 system data size this field contains the number of bits minus one during the high or low phase of the i2s0txws signal. 0x1f r/w sdsz 9:4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 3:0 849 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 4: i 2 s transmit fifo limit (i2stxlimit), offset 0x00c this register sets the lower fifo limit at which a fifo service request is issued. i2s transmit fifo limit (i2stxlimit) base 0x4005.4000 offset 0x00c type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 limit reserved r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:5 fifo limit this field sets the fifo level at which a fifo service request is issued, generating an interrupt or a dma transfer request. the transmit fifo generates a service request when the number of items in the fifo is less than the level specified by the limit field. for example, if the limit field is set to 8, then a service request is generated when there are less than 8 samples remaining in the transmit fifo. 0x00 r/w limit 4:0 july 03, 2014 850 texas instruments-production data inter-integrated circuit sound (i 2 s) interface register 5: i 2 s transmit interrupt status and mask (i2stxism), offset 0x010 this register indicates the transmit interrupt status and interrupt masking control. i2s transmit interrupt status and mask (i2stxism) base 0x4005.4000 offset 0x010 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ffi reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ffm reserved r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 31:17 transmit fifo service request interrupt description value the fifo level is equal to or above the fifo limit. 0 the fifo level is below the fifo limit. 1 0 ro ffi 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 15:1 fifo interrupt mask description value the fifo interrupt is masked and not sent to the cpu. 0 the fifo interrupt is enabled to be sent to the interrupt controller. 1 0 r/w ffm 0 851 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 6: i 2 s transmit fifo level (i2stxlev), offset 0x018 the number of samples in the transmit fifo can be read using the i2stxlev register. the value ranges from 0 to 16. stereo and compact stereo sample-pairs are counted as two. mono samples also increment the count by two. for example, the level field is set to eight if there are four mono samples. i2s transmit fifo level (i2stxlev) base 0x4005.4000 offset 0x018 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 level reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:5 number of audio samples this field contains the number of samples in the fifo. 0x00 ro level 4:0 july 03, 2014 852 texas instruments-production data inter-integrated circuit sound (i 2 s) interface register 7: i 2 s receive fifo data (i2srxfifo), offset 0x800 important: this register is read-sensitive. see the register description for details. this register is the 32-bit serial audio receive data register. in stereo mode, the data is read left, right, left, right, and so on. the lrs bit in the i 2 s receive fifo configuration (i2srxfifocfg) register can be read to verify the next position expected. in compact 16-bit mode, bits [31:16] contain the right sample, and bits [15:0] contain the left sample. in compact 8-bit mode, bits [15:8] contain the right sample, and bits [7:0] contain the left sample. in mono mode, each 32-bit entry is a single sample. if the fifo is empty, a read of this register returns a value of 0x0000.0000 and generates a receive fifo read error. i2s receive fifo data (i2srxfifo) base 0x4005.4000 offset 0x800 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rxfifo ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rxfifo ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field rx data serial audio sample data received. the read of an empty fifo returns a value of 0x0. 0x0000.0000 ro rxfifo 31:0 853 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 8: i 2 s receive fifo configuration (i2srxfifocfg), offset 0x804 this register configures the sample for dual-channel operation. in stereo mode, the lrs bit toggles between left and right as the samples are read from the receive fifo. in mono mode, both the left and right samples are stored in the fifo. the fmm bit can be used to read only the left or right sample as determined by the lrp bit. in compact stereo 8- or 16-bit mode, both the left and right samples are read in one access from the fifo. i2s receive fifo configuration (i2srxfifocfg) base 0x4005.4000 offset 0x804 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 lrs css fmm reserved r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:3 fifo mono mode description value the receiver is in stereo mode. 0 the receiver is in mono mode. if the lrp bit in the i2srxcfg register is clear, data is read while the i2s0rxws signal is low (right channel); if the lrp bit is set, data is read while the i2s0rxws signal is high (left channel). 1 0 r/w fmm 2 compact stereo sample size description value the receiver is in compact 16-bit stereo mode with a 16-bit sample size. 0 the receiver is in compact 8-bit stereo mode with a 8-bit sample size. 1 0 r/w css 1 left-right sample indicator description value the left sample is the next position to be read. 0 the right sample is the next position to be read. 1 this bit is only meaningful in compact stereo mode. 0 r/w lrs 0 july 03, 2014 854 texas instruments-production data inter-integrated circuit sound (i 2 s) interface register 9: i 2 s receive module configuration (i2srxcfg), offset 0x808 this register controls the configuration of the receive module. i2s receive module configuration (i2srxcfg) base 0x4005.4000 offset 0x808 type r/w, reset 0x1400.7df0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved msl reserved rm reserved lrp scp dly jst reserved ro ro ro ro ro ro r/w ro r/w ro r/w r/w r/w r/w ro ro type 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved sdsz ssz ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 1 1 1 1 1 0 1 1 1 1 1 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 31:30 justification of input data description value the data is left-justified. 0 the data is right-justified. 1 0 r/w jst 29 data delay description value data is latched on the next latching edge of i2s0rxsck as defined by the scp bit. this bit should be clear in left-justified or right-justified mode. 0 a one- i2s0rxsck delay from the edge of i2s0rxws is inserted before data is latched. this bit should be set in i 2 s mode. 1 1 r/w dly 28 sclk polarity description value data is latched on the rising edge and the i2s0rxws signal (when the msl bit is set) is launched on the falling edge of i2s0rxsck. 0 data is latched on the falling edge and the i2s0rxws signal (when the msl bit is set) is launched on the rising edge of i2s0rxsck. 1 0 r/w scp 27 855 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field left/right clock polarity description value in stereo mode, i2s0rxws is high during the transmission of the left channel data. in mono mode, data is read while the i2s0rxws signal is low (right channel). 0 in stereo mode, i2s0rxws is high during the transmission of the right channel data. in mono mode, data is read while the i2s0rxws signal is high (left channel). 1 1 r/w lrp 26 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 25 read mode this bit selects the mode in which the receive data is received and stored in the fifo. description value stereo/mono mode i2srxfifocfg fmm bit specifies stereo or mono fifo read behavior. 0 compact stereo mode left/right sample packed. refer to i2srxfifocfg for 8/16-bit sample size selection. 1 0 r/w rm 24 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 23 sclk master/slave description value the receiver is a slave and uses the externally driven i2s0rxsck and i2s0rxws signals. 0 the receiver is a master and uses the internally generated i2s0rxsck and i2s0rxws signals. 1 0 r/w msl 22 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 21:16 sample size this field contains the number of bits minus one in the sample. 0x1f r/w ssz 15:10 system data size this field contains the number of bits minus one during the high or low phase of the i2s0rxws signal. 0x1f r/w sdsz 9:4 july 03, 2014 856 texas instruments-production data inter-integrated circuit sound (i 2 s) interface description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 3:0 857 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 10: i 2 s receive fifo limit (i2srxlimit), offset 0x80c this register sets the upper fifo limit at which a fifo service request is issued. i2s receive fifo limit (i2srxlimit) base 0x4005.4000 offset 0x80c type r/w, reset 0x0000.7fff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 limit reserved r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x7ff ro reserved 15:5 fifo limit this field sets the fifo level at which a fifo service request is issued, generating an interrupt or a dma transfer request. the receive fifo generates a service request when the number of items in the fifo is greater than the level specified by the limit field. for example, if the limit field is set to 4, then a service request is generated when there are more than 4 samples remaining in the transmit fifo. 0x1f r/w limit 4:0 july 03, 2014 858 texas instruments-production data inter-integrated circuit sound (i 2 s) interface register 11: i 2 s receive interrupt status and mask (i2srxism), offset 0x810 this register indicates the receive interrupt status and interrupt masking control. i2s receive interrupt status and mask (i2srxism) base 0x4005.4000 offset 0x810 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ffi reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ffm reserved r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 31:17 receive fifo service request interrupt description value the fifo level is equal to or below the fifo limit. 0 the fifo level is above the fifo limit. 1 0 ro ffi 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 15:1 fifo interrupt mask description value the fifo interrupt is masked and not sent to the cpu. 0 the fifo interrupt is enabled to be sent to the interrupt controller. 1 0 r/w ffm 0 859 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 12: i 2 s receive fifo level (i2srxlev), offset 0x818 the number of samples in the receive fifo can be read using the i2srxlev register. the value ranges from 0 to 16. stereo and compact stereo sample pairs are counted as two. mono samples also increment the count by two. for example, the level field is set to eight if there are four mono samples. i2s receive fifo level (i2srxlev) base 0x4005.4000 offset 0x818 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 level reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:5 number of audio samples this field contains the number of samples in the fifo. 0x00 ro level 4:0 july 03, 2014 860 texas instruments-production data inter-integrated circuit sound (i 2 s) interface register 13: i 2 s module configuration (i2scfg), offset 0xc00 this register enables the transmit and receive serial engines and sets the source of the i2s0txmclk and i2s0rxmclk signals. i2s module configuration (i2scfg) base 0x4005.4000 offset 0xc00 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 txen rxen reserved txslv rxslv reserved r/w r/w ro ro r/w r/w ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:6 use external i2s0rxmclk description value the receiver uses the internally generated mclk as the i2s0rxmclk signal. see clock control on page 838 for information on how to program the i2s0rxmclk. 0 the receiver uses the externally driven i2s0rxmclk signal. 1 0 r/w rxslv 5 use external i2s0txmclk description value the transmitter uses the internally generated mclk as the i2s0txmclk signal. see clock control on page 838 for information on how to program the i2s0txmclk. 0 the transmitter uses the externally driven i2s0txmclk signal. 1 0 r/w txslv 4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 3:2 serial receive engine enable description value disables the serial receive engine. 0 enables the serial receive engine. 1 0 r/w rxen 1 861 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field serial transmit engine enable description value disables the serial transmit engine. 0 enables the serial transmit engine. 1 0 r/w txen 0 july 03, 2014 862 texas instruments-production data inter-integrated circuit sound (i 2 s) interface register 14: i 2 s interrupt mask (i2sim), offset 0xc10 this register masks the interrupts to the cpu. i2s interrupt mask (i2sim) base 0x4005.4000 offset 0xc10 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 txsrim txweim reserved rxsrim rxreim reserved r/w r/w ro ro r/w r/w ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:6 receive fifo read error description value the receive fifo read error interrupt is masked and not sent to the cpu. 0 the receive fifo read error is enabled to be sent to the interrupt controller. 1 0 r/w rxreim 5 receive fifo service request description value the receive fifo service request interrupt is masked and not sent to the cpu. 0 the receive fifo service request is enabled to be sent to the interrupt controller. 1 0 r/w rxsrim 4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 3:2 transmit fifo write error description value the transmit fifo write error interrupt is masked and not sent to the cpu. 0 the transmit fifo write error is enabled to be sent to the interrupt controller. 1 0 r/w txweim 1 863 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field transmit fifo service request description value the transmit fifo service request interrupt is masked and not sent to the cpu. 0 the transmit fifo service request is enabled to be sent to the interrupt controller. 1 0 r/w txsrim 0 july 03, 2014 864 texas instruments-production data inter-integrated circuit sound (i 2 s) interface register 15: i 2 s raw interrupt status (i2sris), offset 0xc14 this register reads the unmasked interrupt status. i2s raw interrupt status (i2sris) base 0x4005.4000 offset 0xc14 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 txsrris txweris reserved rxsrris rxreris reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:6 receive fifo read error description value a receive fifo read error interrupt has occurred. 1 no interrupt 0 this bit is cleared by setting the rxreic bit in the i2sic register. 0 ro rxreris 5 receive fifo service request description value a receive fifo service request interrupt has occurred. 1 no interrupt 0 this bit is cleared when the level in the receive fifo has risen to a value greater than the value programmed in the limit field in the i2srxlimit register. 0 ro rxsrris 4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 3:2 transmit fifo write error description value a transmit fifo write error interrupt has occurred. 1 no interrupt 0 this bit is cleared by setting the txweic bit in the i2sic register. 0 ro txweris 1 865 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field transmit fifo service request description value a transmit fifo service request interrupt has occurred. 1 no interrupt 0 this bit is cleared when the level in the transmit fifo has fallen to a value less than the value programmed in the limit field in the i2stxlimit register. 0 ro txsrris 0 july 03, 2014 866 texas instruments-production data inter-integrated circuit sound (i 2 s) interface register 16: i 2 s masked interrupt status (i2smis), offset 0xc18 this register reads the masked interrupt status. the mask is defined in the i2sim register. i2s masked interrupt status (i2smis) base 0x4005.4000 offset 0xc18 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 txsrmis txwemis reserved rxsrmis rxremis reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 s 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:6 receive fifo read error description value an unmasked interrupt was signaled due to a receive fifo read error. 1 an interrupt has not occurred or is masked. 0 this bit is cleared by setting the rxreic bit in the i2sic register. 0 ro rxremis 5 receive fifo service request description value an unmasked interrupt was signaled due to a receive fifo service request. 1 an interrupt has not occurred or is masked. 0 this bit is cleared when the level in the receive fifo has risen to a value greater than the value programmed in the limit field in the i2srxlimit register. 0 ro rxsrmis 4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0s0 ro reserved 3:2 transmit fifo write error description value an unmasked interrupt was signaled due to a transmit fifo write error. 1 an interrupt has not occurred or is masked. 0 this bit is cleared by setting the txweic bit in the i2sic register. 0 ro txwemis 1 867 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field transmit fifo service request description value an unmasked interrupt was signaled due to a transmit fifo service request. 1 an interrupt has not occurred or is masked. 0 this bit is cleared when the level in the transmit fifo has fallen to a value less than the value programmed in the limit field in the i2stxlimit register. 0 ro txsrmis 0 july 03, 2014 868 texas instruments-production data inter-integrated circuit sound (i 2 s) interface register 17: i 2 s interrupt clear (i2sic), offset 0xc1c writing a 1 to a bit in this register clears the corresponding interrupt. i2s interrupt clear (i2sic) base 0x4005.4000 offset 0xc1c type wo, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved txweic reserved rxreic reserved wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 wo reserved 31:6 receive fifo read error writing a 1 to this bit clears the rxreris bit in the i2cris register and the rxremis bit in the i2cmis register. 0 wo rxreic 5 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 wo reserved 4:2 transmit fifo write error writing a 1 to this bit clears the txweris bit in the i2cris register and the txwemis bit in the i2cmis register. 0 wo txweic 1 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 wo reserved 0 869 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 17 controller area network (can) module controller area network (can) is a multicast, shared serial bus standard for connecting electronic control units (ecus). can was specifically designed to be robust in electromagnetically-noisy environments and can utilize a differential balanced line like rs-485 or a more robust twisted-pair wire. originally created for automotive purposes, it is also used in many embedded control applications (such as industrial and medical). bit rates up to 1 mbps are possible at network lengths less than 40 meters. decreased bit rates allow longer network distances (for example, 125 kbps at 500 meters). the stellaris ? lm3s9gn5 microcontroller includes two can units with the following features: can protocol version 2.0 part a/b bit rates up to 1 mbps 32 message objects with individual identifier masks maskable interrupt disable automatic retransmission mode for time-triggered can (ttcan) applications programmable loopback mode for self-test operation programmable fifo mode enables storage of multiple message objects gluelessly attaches to an external can transceiver through the canntx and cannrx signals july 03, 2014 870 texas instruments-production data controller area network (can) module 17.1 block diagram figure 17-1. can controller block diagram 17.2 signal description the following table lists the external signals of the can controller and describes the function of each. the can controller signals are alternate functions for some gpio signals and default to be gpio signals at reset. the column in the table below titled "pin mux/pin assignment" lists the possible gpio pin placements for the can signals. the afsel bit in the gpio alternate function select (gpioafsel) register (page 429) should be set to choose the can controller function. the number in parentheses is the encoding that must be programmed into the pmcn field in the gpio port control (gpiopctl) register (page 447) to assign the can signal to the specified gpio port pin. for more information on configuring gpios, see general-purpose input/outputs (gpios) on page 405. 871 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller & $ 1 & r q w u r o & $ 1 & r u h & $ 1 , ) & 5 4 & $ 1 , ) & 0 6 . & $ 1 , ) 0 6 . & $ 1 , ) 0 6 . & $ 1 , ) $ 5 % & $ 1 , ) $ 5 % & $ 1 , ) 0 & 7 / & $ 1 , ) ' $ 0 h v v d j h 2 e m h f w 5 h j l v w h u v & $ 1 1 : ' $ & $ 1 7 ; 5 4 & $ 1 7 ; 5 4 & $ 1 1 : ' $ & $ 1 0 6 * , 1 7 & $ 1 0 6 * , 1 7 & $ 1 0 6 * 9 $ / & $ 1 0 6 * 9 $ / & $ 1 7 [ & $ 1 , 1 7 & $ 1 7 6 7 & $ 1 % 5 3 ( & $ 1 ( 5 5 & $ 1 & 7 / & $ 1 6 7 6 & $ 1 % , 7 & $ 1 , q w h u i d f h & $ 1 , ) & 5 4 & $ 1 , ) & 0 6 . & $ 1 , ) 0 6 . & $ 1 , ) 0 6 . & $ 1 , ) $ 5 % & $ 1 , ) $ 5 % & $ 1 , ) 0 & 7 / & $ 1 , ) ' $ & $ 1 , ) ' $ & $ 1 , ) ' % & $ 1 , ) ' % & $ 1 , q w h u i d f h $ 3 % , q w h u i d f h $ 3 % 3 l q v 0 h v v d j h 5 $ 0 0 h v v d j h 2 e m h f w v & $ 1 5 [ & $ 1 , ) ' $ & $ 1 , ) ' % & $ 1 , ) ' % table 17-1. controller area network signals (100lqfp) description buffer type a pin type pin mux / pin assignment pin number pin name can module 0 receive. ttl i pd0 (2) pa4 (5) pa6 (6) pb4 (5) 10 30 34 92 can0rx can module 0 transmit. ttl o pd1 (2) pa5 (5) pa7 (6) pb5 (5) 11 31 35 91 can0tx can module 1 receive. ttl i pf0 (1) 47 can1rx can module 1 transmit. ttl o pf1 (1) 61 can1tx a. the ttl designation indicates the pin has ttl-compatible voltage levels. table 17-2. controller area network signals (108bga) description buffer type a pin type pin mux / pin assignment pin number pin name can module 0 receive. ttl i pd0 (2) pa4 (5) pa6 (6) pb4 (5) g1 l5 l6 a6 can0rx can module 0 transmit. ttl o pd1 (2) pa5 (5) pa7 (6) pb5 (5) g2 m5 m6 b7 can0tx can module 1 receive. ttl i pf0 (1) m9 can1rx can module 1 transmit. ttl o pf1 (1) h12 can1tx a. the ttl designation indicates the pin has ttl-compatible voltage levels. 17.3 functional description the stellaris can controller conforms to the can protocol version 2.0 (parts a and b). message transfers that include data, remote, error, and overload frames with an 11-bit identifier (standard) or a 29-bit identifier (extended) are supported. transfer rates can be programmed up to 1 mbps. the can module consists of three major parts: can protocol controller and message handler message memory can register interface a data frame contains data for transmission, whereas a remote frame contains no data and is used to request the transmission of a specific message object. the can data/remote frame is constructed as shown in figure 17-2. july 03, 2014 872 texas instruments-production data controller area network (can) module figure 17-2. can data/remote frame the protocol controller transfers and receives the serial data from the can bus and passes the data on to the message handler. the message handler then loads this information into the appropriate message object based on the current filtering and identifiers in the message object memory. the message handler is also responsible for generating interrupts based on events on the can bus. the message object memory is a set of 32 identical memory blocks that hold the current configuration, status, and actual data for each message object. these memory blocks are accessed via either of the can message object register interfaces. the message memory is not directly accessible in the stellaris memory map, so the stellaris can controller provides an interface to communicate with the message memory via two can interface register sets for communicating with the message objects. the message object memory cannot be directly accessed, so these two interfaces must be used to read or write to each message object. the two message object interfaces allow parallel access to the can controller message objects when multiple objects may have new information that must be processed. in general, one interface is used for transmit data and one for receive data. 17.3.1 initialization to use the can controller, the peripheral clock must be enabled using the rcgc0 register (see page 262). in addition, the clock to the appropriate gpio module must be enabled via the rcgc2 register (see page 282). to find out which gpio port to enable, refer to table 24-4 on page 1239. set the gpio afsel bits for the appropriate pins (see page 429). configure the pmcn fields in the gpiopctl register to assign the can signals to the appropriate pins. see page 447 and table 24-5 on page 1248. software initialization is started by setting the init bit in the can control (canctl) register (with software or by a hardware reset) or by going bus-off, which occurs when the transmitter's error counter exceeds a count of 255. while init is set, all message transfers to and from the can bus are stopped and the canntx signal is held high. entering the initialization state does not change the configuration of the can controller, the message objects, or the error counters. however, some configuration registers are only accessible while in the initialization state. 873 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 1 x p e h u 2 i % l w v 6 2 ) ( 2 3 , ) 6 % x v , g o h r u $ & . ' d w d ) l h o g & r q w u r o ) l h o g 5 7 5 0 h v v d j h ' h o l p l w h u % x v , g o h % l w 6 w x i i l q j & $ 1 ' d w d ) u d p h $ u e l w u d w l r q ) l h o g & 5 & 6 h t x h q f h & 5 & ) l h o g $ f n q r z o h g j h p h q w ) l h o g ( q g r i ) u d p h ) l h o g , q w h u i u d p h ) l h o g 6 w d u w 2 i ) u d p h 5 h p r w h 7 u d q v p l v v l r q 5 h t x h v w ' h o l p l w h u % l w v & 5 & 6 h t x h q f h to initialize the can controller, set the can bit timing (canbit) register and configure each message object. if a message object is not needed, label it as not valid by clearing the msgval bit in the can ifn arbitration 2 (canifnarb2) register. otherwise, the whole message object must be initialized, as the fields of the message object may not have valid information, causing unexpected results. both the init and cce bits in the canctl register must be set in order to access the canbit register and the can baud rate prescaler extension (canbrpe) register to configure the bit timing. to leave the initialization state, the init bit must be cleared. afterwards, the internal bit stream processor (bsp) synchronizes itself to the data transfer on the can bus by waiting for the occurrence of a sequence of 11 consecutive recessive bits (indicating a bus idle condition) before it takes part in bus activities and starts message transfers. message object initialization does not require the can to be in the initialization state and can be done on the fly. however, message objects should all be configured to particular identifiers or set to not valid before message transfer starts. to change the configuration of a message object during normal operation, clear the msgval bit in the canifnarb2 register to indicate that the message object is not valid during the change. when the configuration is completed, set the msgval bit again to indicate that the message object is once again valid. 17.3.2 operation two sets of can interface registers ( canif1x and canif2x ) are used to access the message objects in the message ram. the can controller coordinates transfers to and from the message ram to and from the registers. the two sets are independent and identical and can be used to queue transactions. generally, one interface is used to transmit data and one is used to receive data. once the can module is initialized and the init bit in the canctl register is cleared, the can module synchronizes itself to the can bus and starts the message transfer. as each message is received, it goes through the message handler's filtering process, and if it passes through the filter, is stored in the message object specified by the mnum bit in the can ifn command request (canifncrq) register. the whole message (including all arbitration bits, data-length code, and eight data bytes) is stored in the message object. if the identifier mask (the msk bits in the can ifn mask 1 and can ifn mask 2 (canifnmskn) registers) is used, the arbitration bits that are masked to "don't care" may be overwritten in the message object. the cpu may read or write each message at any time via the can interface registers. the message handler guarantees data consistency in case of concurrent accesses. the transmission of message objects is under the control of the software that is managing the can hardware. message objects can be used for one-time data transfers or can be permanent message objects used to respond in a more periodic manner. permanent message objects have all arbitration and control set up, and only the data bytes are updated. at the start of transmission, the appropriate txrqst bit in the can transmission request n (cantxrqn) register and the newdat bit in the can new data n (cannwdan) register are set. if several transmit messages are assigned to the same message object (when the number of message objects is not sufficient), the whole message object has to be configured before the transmission of this message is requested. the transmission of any number of message objects may be requested at the same time; they are transmitted according to their internal priority, which is based on the message identifier ( mnum ) for the message object, with 1 being the highest priority and 32 being the lowest priority. messages may be updated or set to not valid any time, even when their requested transmission is still pending. the old data is discarded when a message is updated before its pending transmission has started. depending on the configuration of the message object, the transmission of a message may be requested autonomously by the reception of a remote frame with a matching identifier. july 03, 2014 874 texas instruments-production data controller area network (can) module transmission can be automatically started by the reception of a matching remote frame. to enable this mode, set the rmten bit in the can ifn message control (canifnmctl) register. a matching received remote frame causes the txrqst bit to be set, and the message object automatically transfers its data or generates an interrupt indicating a remote frame was requested. a remote frame can be strictly a single message identifier, or it can be a range of values specified in the message object. the can mask registers, canifnmskn , configure which groups of frames are identified as remote frame requests. the umask bit in the canifnmctl register enables the msk bits in the canifnmskn register to filter which frames are identified as a remote frame request. the mxtd bit in the canifnmsk2 register should be set if a remote frame request is expected to be triggered by 29-bit extended identifiers. 17.3.3 transmitting message objects if the internal transmit shift register of the can module is ready for loading, and if a data transfer is not occurring between the can interface registers and message ram, the valid message object with the highest priority that has a pending transmission request is loaded into the transmit shift register by the message handler and the transmission is started. the message object's newdat bit in the cannwdan register is cleared. after a successful transmission, and if no new data was written to the message object since the start of the transmission, the txrqst bit in the cantxrqn register is cleared. if the can controller is configured to interrupt on a successful transmission of a message object, (the txie bit in the can ifn message control (canifnmctl) register is set), the intpnd bit in the canifnmctl register is set after a successful transmission. if the can module has lost the arbitration or if an error occurred during the transmission, the message is re-transmitted as soon as the can bus is free again. if, meanwhile, the transmission of a message with higher priority has been requested, the messages are transmitted in the order of their priority. 17.3.4 configuring a transmit message object the following steps illustrate how to configure a transmit message object. 1. in the can ifn command mask (canifncmask) register: set the wrnrd bit to specify a write to the canifncmask register; specify whether to transfer the idmask, dir , and mxtd of the message object into the can ifn registers using the mask bit specify whether to transfer the id, dir , xtd , and msgval of the message object into the interface registers using the arb bit specify whether to transfer the control bits into the interface registers using the control bit specify whether to clear the intpnd bit in the canifnmctl register using the clrintpnd bit specify whether to clear the newdat bit in the cannwdan register using the newdat bit specify which bits to transfer using the dataa and datab bits 2. in the canifnmsk1 register, use the msk[15:0] bits to specify which of the bits in the 29-bit or 11-bit message identifier are used for acceptance filtering. note that msk[15:0] in this register are used for bits [15:0] of the 29-bit message identifier and are not used for an 11-bit identifier. a value of 0x00 enables all messages to pass through the acceptance filtering. also 875 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller note that in order for these bits to be used for acceptance filtering, they must be enabled by setting the umask bit in the canifnmctl register. 3. in the canifnmsk2 register, use the msk[12:0] bits to specify which of the bits in the 29-bit or 11-bit message identifier are used for acceptance filtering. note that msk[12:0] are used for bits [28:16] of the 29-bit message identifier; whereas msk[12:2] are used for bits [10:0] of the 11-bit message identifier. use the mxtd and mdir bits to specify whether to use xtd and dir for acceptance filtering. a value of 0x00 enables all messages to pass through the acceptance filtering. also note that in order for these bits to be used for acceptance filtering, they must be enabled by setting the umask bit in the canifnmctl register. 4. for a 29-bit identifier, configure id[15:0] in the canifnarb1 register for bits [15:0] of the message identifier and id[12:0] in the canifnarb2 register for bits [28:16] of the message identifier. set the xtd bit to indicate an extended identifier; set the dir bit to indicate transmit; and set the msgval bit to indicate that the message object is valid. 5. for an 11-bit identifier, disregard the canifnarb1 register and configure id[12:2] in the canifnarb2 register for bits [10:0] of the message identifier. clear the xtd bit to indicate a standard identifier; set the dir bit to indicate transmit; and set the msgval bit to indicate that the message object is valid. 6. in the canifnmctl register: optionally set the umask bit to enable the mask ( msk, mxtd , and mdir specified in the canifnmsk1 and canifnmsk2 registers) for acceptance filtering optionally set the txie bit to enable the intpnd bit to be set after a successful transmission optionally set the rmten bit to enable the txrqst bit to be set on the reception of a matching remote frame allowing automatic transmission set the eob bit for a single message object configure the dlc[3:0] field to specify the size of the data frame. take care during this configuration not to set the newdat, msglst, intpnd or txrqst bits. 7. load the data to be transmitted into the can ifn data (canifnda1, canifnda2, canifndb1, canifndb2) registers. byte 0 of the can data frame is stored in data[7:0] in the canifnda1 register. 8. program the number of the message object to be transmitted in the mnum field in the can ifn command request (canifncrq) register. 9. when everything is properly configured, set the txrqst bit in the canifnmctl register. once this bit is set, the message object is available to be transmitted, depending on priority and bus availability. note that setting the rmten bit in the canifnmctl register can also start message transmission if a matching remote frame has been received. 17.3.5 updating a transmit message object the cpu may update the data bytes of a transmit message object any time via the can interface registers and neither the msgval bit in the canifnarb2 register nor the txrqst bits in the canifnmctl register have to be cleared before the update. july 03, 2014 876 texas instruments-production data controller area network (can) module even if only some of the data bytes are to be updated, all four bytes of the corresponding canifndan / canifndbn register have to be valid before the content of that register is transferred to the message object. either the cpu must write all four bytes into the canifndan / canifndbn register or the message object is transferred to the canifndan / canifndbn register before the cpu writes the new data bytes. in order to only update the data in a message object, the wrnrd, dataa and datab bits in the canifnmskn register are set, followed by writing the updated data into canifnda1 , canifnda2 , canifndb1 , and canifndb2 registers, and then the number of the message object is written to the mnum field in the can ifn command request (canifncrq) register. to begin transmission of the new data as soon as possible, set the txrqst bit in the canifnmskn register. to prevent the clearing of the txrqst bit in the canifnmctl register at the end of a transmission that may already be in progress while the data is updated, the newdat and txrqst bits have to be set at the same time in the canifnmctl register. when these bits are set at the same time, newdat is cleared as soon as the new transmission has started. 17.3.6 accepting received message objects when the arbitration and control field (the id and xtd bits in the canifnarb2 and the rmten and dlc[3:0] bits of the canifnmctl register) of an incoming message is completely shifted into the can controller, the message handling capability of the controller starts scanning the message ram for a matching valid message object. to scan the message ram for a matching message object, the controller uses the acceptance filtering programmed through the mask bits in the canifnmskn register and enabled using the umask bit in the canifnmctl register. each valid message object, starting with object 1, is compared with the incoming message to locate a matching message object in the message ram. if a match occurs, the scanning is stopped and the message handler proceeds depending on whether it is a data frame or remote frame that was received. 17.3.7 receiving a data frame the message handler stores the message from the can controller receive shift register into the matching message object in the message ram. the data bytes, all arbitration bits, and the dlc bits are all stored into the corresponding message object. in this manner, the data bytes are connected with the identifier even if arbitration masks are used. the newdat bit of the canifnmctl register is set to indicate that new data has been received. the cpu should clear this bit when it reads the message object to indicate to the controller that the message has been received, and the buffer is free to receive more messages. if the can controller receives a message and the newdat bit is already set, the msglst bit in the canifnmctl register is set to indicate that the previous data was lost. if the system requires an interrupt on successful reception of a frame, the rxie bit of the canifnmctl register should be set. in this case, the intpnd bit of the same register is set, causing the canint register to point to the message object that just received a message. the txrqst bit of this message object should be cleared to prevent the transmission of a remote frame. 17.3.8 receiving a remote frame a remote frame contains no data, but instead specifies which object should be transmitted. when a remote frame is received, three different configurations of the matching message object have to be considered: 877 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 17-3. message object configurations description configuration in canifnmctl at the reception of a matching remote frame, the txrqst bit of this message object is set. the rest of the message object remains unchanged, and the controller automatically transfers the data in the message object as soon as possible. dir = 1 (direction = transmit); programmed in the canifnarb2 register rmten = 1 (set the txrqst bit of the canifnmctl register at reception of the frame to enable transmission) umask = 1 or 0 at the reception of a matching remote frame, the txrqst bit of this message object remains unchanged, and the remote frame is ignored. this remote frame is disabled, the data is not transferred and nothing indicates that the remote frame ever happened. dir = 1 (direction = transmit); programmed in the canifnarb2 register rmten = 0 (do not change the txrqst bit of the canifnmctl register at reception of the frame) umask = 0 (ignore mask in the canifnmskn register) at the reception of a matching remote frame, the txrqst bit of this message object is cleared. the arbitration and control field ( id + xtd + rmten + dlc ) from the shift register is stored into the message object in the message ram, and the newdat bit of this message object is set. the data field of the message object remains unchanged; the remote frame is treated similar to a received data frame. this mode is useful for a remote data request from another can device for which the stellaris controller does not have readily available data. the software must fill the data and answer the frame manually. dir = 1 (direction = transmit); programmed in the canifnarb2 register rmten = 0 (do not change the txrqst bit of the canifnmctl register at reception of the frame) umask = 1 (use mask ( msk, mxtd , and mdir in the canifnmskn register) for acceptance filtering) 17.3.9 receive/transmit priority the receive/transmit priority for the message objects is controlled by the message number. message object 1 has the highest priority, while message object 32 has the lowest priority. if more than one transmission request is pending, the message objects are transmitted in order based on the message object with the lowest message number. this prioritization is separate from that of the message identifier which is enforced by the can bus. as a result, if message object 1 and message object 2 both have valid messages to be transmitted, message object 1 is always transmitted first regardless of the message identifier in the message object itself. 17.3.10 configuring a receive message object the following steps illustrate how to configure a receive message object. 1. program the can ifn command mask (canifncmask) register as described in the configuring a transmit message object on page 875 section, except that the wrnrd bit is set to specify a write to the message ram. 2. program the canifnmsk1 and canifnmsk2 registers as described in the configuring a transmit message object on page 875 section to configure which bits are used for acceptance filtering. note that in order for these bits to be used for acceptance filtering, they must be enabled by setting the umask bit in the canifnmctl register. 3. in the canifnmsk2 register, use the msk[12:0] bits to specify which of the bits in the 29-bit or 11-bit message identifier are used for acceptance filtering. note that msk[12:0] are used for bits [28:16] of the 29-bit message identifier; whereas msk[12:2] are used for bits [10:0] of the 11-bit message identifier. use the mxtd and mdir bits to specify whether to use xtd and july 03, 2014 878 texas instruments-production data controller area network (can) module dir for acceptance filtering. a value of 0x00 enables all messages to pass through the acceptance filtering. also note that in order for these bits to be used for acceptance filtering, they must be enabled by setting the umask bit in the canifnmctl register. 4. program the canifnarb1 and canifnarb2 registers as described in the configuring a transmit message object on page 875 section to program xtd and id bits for the message identifier to be received; set the msgval bit to indicate a valid message; and clear the dir bit to specify receive. 5. in the canifnmctl register: optionally set the umask bit to enable the mask ( msk, mxtd , and mdir specified in the canifnmsk1 and canifnmsk2 registers) for acceptance filtering optionally set the rxie bit to enable the intpnd bit to be set after a successful reception clear the rmten bit to leave the txrqst bit unchanged set the eob bit for a single message object configure the dlc[3:0] field to specify the size of the data frame take care during this configuration not to set the newdat, msglst, intpnd or txrqst bits. 6. program the number of the message object to be received in the mnum field in the can ifn command request (canifncrq) register. reception of the message object begins as soon as a matching frame is available on the can bus. when the message handler stores a data frame in the message object, it stores the received data length code and eight data bytes in the canifnda1 , canifnda2 , canifndb1 , and canifndb2 register. byte 0 of the can data frame is stored in data[7:0] in the canifnda1 register. if the data length code is less than 8, the remaining bytes of the message object are overwritten by unspecified values. the can mask registers can be used to allow groups of data frames to be received by a message object. the can mask registers, canifnmskn , configure which groups of frames are received by a message object. the umask bit in the canifnmctl register enables the msk bits in the canifnmskn register to filter which frames are received. the mxtd bit in the canifnmsk2 register should be set if only 29-bit extended identifiers are expected by this message object. 17.3.11 handling of received message objects the cpu may read a received message any time via the can interface registers because the data consistency is guaranteed by the message handler state machine. typically, the cpu first writes 0x007f to the canifncmsk register and then writes the number of the message object to the canifncrq register. that combination transfers the whole received message from the message ram into the message buffer registers ( canifnmskn , canifnarbn , and canifnmctl ). additionally, the newdat and intpnd bits are cleared in the message ram, acknowledging that the message has been read and clearing the pending interrupt generated by this message object. if the message object uses masks for acceptance filtering, the canifnarbn registers show the full, unmasked id for the received message. 879 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller the newdat bit in the canifnmctl register shows whether a new message has been received since the last time this message object was read. the msglst bit in the canifnmctl register shows whether more than one message has been received since the last time this message object was read. msglst is not automatically cleared, and should be cleared by software after reading its status. using a remote frame, the cpu may request new data from another can node on the can bus. setting the txrqst bit of a receive object causes the transmission of a remote frame with the receive object's identifier. this remote frame triggers the other can node to start the transmission of the matching data frame. if the matching data frame is received before the remote frame could be transmitted, the txrqst bit is automatically reset. this prevents the possible loss of data when the other device on the can bus has already transmitted the data slightly earlier than expected. 17.3.11.1 configuration of a fifo buffer with the exception of the eob bit in the canifnmctl register, the configuration of receive message objects belonging to a fifo buffer is the same as the configuration of a single receive message object (see configuring a receive message object on page 878). to concatenate two or more message objects into a fifo buffer, the identifiers and masks (if used) of these message objects have to be programmed to matching values. due to the implicit priority of the message objects, the message object with the lowest message object number is the first message object in a fifo buffer. the eob bit of all message objects of a fifo buffer except the last one must be cleared. the eob bit of the last message object of a fifo buffer is set, indicating it is the last entry in the buffer. 17.3.11.2 reception of messages with fifo buffers received messages with identifiers matching to a fifo buffer are stored starting with the message object with the lowest message number. when a message is stored into a message object of a fifo buffer, the newdat of the canifnmctl register bit of this message object is set. by setting newdat while eob is clear, the message object is locked and cannot be written to by the message handler until the cpu has cleared the newdat bit. messages are stored into a fifo buffer until the last message object of this fifo buffer is reached. until all of the preceding message objects have been released by clearing the newdat bit, all further messages for this fifo buffer are written into the last message object of the fifo buffer and therefore overwrite previous messages. 17.3.11.3 reading from a fifo buffer when the cpu transfers the contents of a message object from a fifo buffer by writing its number to the canifncrq register, the txrqst and clrintpnd bits in the canifncmsk register should be set such that the newdat and intpend bits in the canifnmctl register are cleared after the read. the values of these bits in the canifnmctl register always reflect the status of the message object before the bits are cleared. to assure the correct function of a fifo buffer, the cpu should read out the message objects starting with the message object with the lowest message number. when reading from the fifo buffer, the user should be aware that a new received message is placed in the message object with the lowest message number for which the newdat bit of the canifnmctl register is clear. as a result, the order of the received messages in the fifo is not guaranteed. figure 17-3 on page 881 shows how a set of message objects which are concatenated to a fifo buffer can be handled by the cpu. july 03, 2014 880 texas instruments-production data controller area network (can) module figure 17-3. message objects in a fifo buffer 17.3.12 handling of interrupts if several interrupts are pending, the can interrupt (canint) register points to the pending interrupt with the highest priority, disregarding their chronological order. the status interrupt has the highest 881 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 6 7 $ 5 7 1 r < h v : u l w h 0 1 8 0 w r , ) q & r p p d q g 5 h t x h v w 5 h d g 0 h v v d j h w r , ) q 5 h j l v w h u v 5 h v h w 1 ( : ' $ 7 5 h v h w , 1 7 3 1 ' 0 1 8 0 , q w h u u x s w 3 r l q w h u 5 h d g , ) q 0 h v v d j h & r q w u r o 5 h d g ' d w d i u r p , ) q ' d w d $ % 1 ( : ' $ 7 ( 2 % 5 h d g , q w h u u x s w 3 r l q w h u 6 w d w x v & k d q j h , q w h u u x s w + d q g o l q j ( 1 ' 0 h v v d j h , q w h u u x s w < h v 0 1 8 0 0 1 8 0 & d v h , q w h u u x s w 3 r l q w h u h o v h [ [ 1 r priority. among the message interrupts, the message object's interrupt with the lowest message number has the highest priority. a message interrupt is cleared by clearing the message object's intpnd bit in the canifnmctl register or by reading the can status (cansts) register. the status interrupt is cleared by reading the cansts register. the interrupt identifier intid in the canint register indicates the cause of the interrupt. when no interrupt is pending, the register reads as 0x0000. if the value of the intid field is different from 0, then an interrupt is pending. if the ie bit is set in the canctl register, the interrupt line to the interrupt controller is active. the interrupt line remains active until the intid field is 0, meaning that all interrupt sources have been cleared (the cause of the interrupt is reset), or until ie is cleared, which disables interrupts from the can controller. the intid field of the canint register points to the pending message interrupt with the highest interrupt priority. the sie bit in the canctl register controls whether a change of the rxok, txok, and lec bits in the cansts register can cause an interrupt. the eie bit in the canctl register controls whether a change of the boff and ewarn bits in the cansts register can cause an interrupt. the ie bit in the canctl register controls whether any interrupt from the can controller actually generates an interrupt to the interrupt controller. the canint register is updated even when the ie bit in the canctl register is clear, but the interrupt is not indicated to the cpu. a value of 0x8000 in the canint register indicates that an interrupt is pending because the can module has updated, but not necessarily changed, the cansts register, indicating that either an error or status interrupt has been generated. a write access to the cansts register can clear the rxok, txok , and lec bits in that same register; however, the only way to clear the source of a status interrupt is to read the cansts register. the source of an interrupt can be determined in two ways during interrupt handling. the first is to read the intid bit in the canint register to determine the highest priority interrupt that is pending, and the second is to read the can message interrupt pending (canmsgnint) register to see all of the message objects that have pending interrupts. an interrupt service routine reading the message that is the source of the interrupt may read the message and clear the message object's intpnd bit at the same time by setting the clrintpnd bit in the canifncmsk register. once the intpnd bit has been cleared, the canint register contains the message number for the next message object with a pending interrupt. 17.3.13 test mode a test mode is provided which allows various diagnostics to be performed. test mode is entered by setting the test bit in the canctl register. once in test mode, the tx[1:0], lback, silent and basic bits in the can test (cantst) register can be used to put the can controller into the various diagnostic modes. the rx bit in the cantst register allows monitoring of the cannrx signal. all cantst register functions are disabled when the test bit is cleared. 17.3.13.1 silent mode silent mode can be used to analyze the traffic on a can bus without affecting it by the transmission of dominant bits (acknowledge bits, error frames). the can controller is put in silent mode setting the silent bit in the cantst register. in silent mode, the can controller is able to receive valid data frames and valid remote frames, but it sends only recessive bits on the can bus and cannot start a transmission. if the can controller is required to send a dominant bit (ack bit, overload flag, or active error flag), the bit is rerouted internally so that the can controller monitors this dominant bit, although the can bus remains in recessive state. july 03, 2014 882 texas instruments-production data controller area network (can) module 17.3.13.2 loopback mode loopback mode is useful for self-test functions. in loopback mode, the can controller internally routes the canntx signal on to the cannrx signal and treats its own transmitted messages as received messages and stores them (if they pass acceptance filtering) into the message buffer. the can controller is put in loopback mode by setting the lback bit in the cantst register. to be independent from external stimulation, the can controller ignores acknowledge errors (a recessive bit sampled in the acknowledge slot of a data/remote frame) in loopback mode. the actual value of the cannrx signal is disregarded by the can controller. the transmitted messages can be monitored on the canntx signal. 17.3.13.3 loopback combined with silent mode loopback mode and silent mode can be combined to allow the can controller to be tested without affecting a running can system connected to the canntx and cannrx signals. in this mode, the cannrx signal is disconnected from the can controller and the canntx signal is held recessive. this mode is enabled by setting both the lback and silent bits in the cantst register. 17.3.13.4 basic mode basic mode allows the can controller to be operated without the message ram. in basic mode, the canif1 registers are used as the transmit buffer. the transmission of the contents of the if1 registers is requested by setting the busy bit of the canif1crq register. the canif1 registers are locked while the busy bit is set. the busy bit indicates that a transmission is pending. as soon the can bus is idle, the canif1 registers are loaded into the shift register of the can controller and transmission is started. when the transmission has completed, the busy bit is cleared and the locked canif1 registers are released. a pending transmission can be aborted at any time by clearing the busy bit in the canif1crq register while the canif1 registers are locked. if the cpu has cleared the busy bit, a possible retransmission in case of lost arbitration or an error is disabled. the canif2 registers are used as a receive buffer. after the reception of a message, the contents of the shift register are stored in the canif2 registers, without any acceptance filtering. additionally, the actual contents of the shift register can be monitored during the message transfer. each time a read message object is initiated by setting the busy bit of the canif2crq register, the contents of the shift register are stored into the canif2 registers. in basic mode, all message-object-related control and status bits and of the control bits of the canifncmsk registers are not evaluated. the message number of the canifncrq registers is also not evaluated. in the canif2mctl register, the newdat and msglst bits retain their function, the dlc[3:0] field shows the received dlc, the other control bits are cleared. basic mode is enabled by setting the basic bit in the cantst register. 17.3.13.5 transmit control software can directly override control of the canntx signal in four different ways. canntx is controlled by the can controller the sample point is driven on the canntx signal to monitor the bit timing canntx drives a low value canntx drives a high value 883 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller the last two functions, combined with the readable can receive pin cannrx , can be used to check the physical layer of the can bus. the transmit control function is enabled by programming the tx[1:0] field in the cantst register. the three test functions for the canntx signal interfere with all can protocol functions. tx[1:0] must be cleared when can message transfer or loopback mode, silent mode, or basic mode are selected. 17.3.14 bit timing configuration error considerations even if minor errors in the configuration of the can bit timing do not result in immediate failure, the performance of a can network can be reduced significantly. in many cases, the can bit synchronization amends a faulty configuration of the can bit timing to such a degree that only occasionally an error frame is generated. in the case of arbitration, however, when two or more can nodes simultaneously try to transmit a frame, a misplaced sample point may cause one of the transmitters to become error passive. the analysis of such sporadic errors requires a detailed knowledge of the can bit synchronization inside a can node and of the can nodes' interaction on the can bus. 17.3.15 bit time and bit rate the can system supports bit rates in the range of lower than 1 kbps up to 1000 kbps. each member of the can network has its own clock generator. the timing parameter of the bit time can be configured individually for each can node, creating a common bit rate even though the can nodes' oscillator periods may be different. because of small variations in frequency caused by changes in temperature or voltage and by deteriorating components, these oscillators are not absolutely stable. as long as the variations remain inside a specific oscillator's tolerance range, the can nodes are able to compensate for the different bit rates by periodically resynchronizing to the bit stream. according to the can specification, the bit time is divided into four segments (see figure 17-4 on page 885): the synchronization segment, the propagation time segment, the phase buffer segment 1, and the phase buffer segment 2. each segment consists of a specific, programmable number of time quanta (see table 17-4 on page 885). the length of the time quantum ( t q ), which is the basic time unit of the bit time, is defined by the can controller's input clock ( fsys ) and the baud rate prescaler ( brp): t q = brp / fsys the fsys input clock is the system clock frequency as configured by the rcc or rcc2 registers (see page 219 or page 227). the synchronization segment sync is that part of the bit time where edges of the can bus level are expected to occur; the distance between an edge that occurs outside of sync and the sync is called the phase error of that edge. the propagation time segment prop is intended to compensate for the physical delay times within the can network. the phase buffer segments phase1 and phase2 surround the sample point. the (re-)synchronization jump width (sjw) defines how far a resynchronization may move the sample point inside the limits defined by the phase buffer segments to compensate for edge phase errors. a given bit rate may be met by different bit-time configurations, but for the proper function of the can network, the physical delay times and the oscillator's tolerance range have to be considered. july 03, 2014 884 texas instruments-production data controller area network (can) module figure 17-4. can bit time table 17-4. can protocol ranges a remark range parameter defines the length of the time quantum t q . the canbrpe register can be used to extend the range to 1024. [1 .. 64] brp fixed length, synchronization of bus input to system clock 1 t q sync compensates for the physical delay times [1 .. 8] t q prop may be lengthened temporarily by synchronization [1 .. 8] t q phase1 may be shortened temporarily by synchronization [1 .. 8] t q phase2 may not be longer than either phase buffer segment [1 .. 4] t q sjw a. this table describes the minimum programmable ranges required by the can protocol. the bit timing configuration is programmed in two register bytes in the canbit register. in the canbit register, the four components tseg2, tseg1, sjw , and brp have to be programmed to a numerical value that is one less than its functional value; so instead of values in the range of [1..n], values in the range of [0..n-1] are programmed. that way, for example, sjw (functional range of [1..4]) is represented by only two bits in the sjw bit field. table 17-5 shows the relationship between the canbit register values and the parameters. table 17-5. canbit register values setting canbit register field phase2 - 1 tseg2 prop + phase1 - 1 tseg1 sjw - 1 sjw brp brp therefore, the length of the bit time is (programmed values): [tseg1 + tseg2 + 3] t q or (functional values): [sync + prop + phase1 + phase2] t q the data in the canbit register is the configuration input of the can protocol controller. the baud rate prescaler (configured by the brp field) defines the length of the time quantum, the basic time 885 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 6 \ q f 3 u r s 3 k d v h 6 d p s o h 3 r l q w 7 l p h 4 x d q w x p w t t 1 r p l q d o & $ 1 % l w 7 l p h d 7 6 ( * 3 u r s 3 k d v h e 7 6 ( * 3 k d v h f 3 k d v h 3 k d v h r u 3 k d v h 3 k d v h 7 6 ( * d 7 6 ( * e 3 k d v h f unit of the bit time; the bit timing logic (configured by tseg1, tseg2 , and sjw ) defines the number of time quanta in the bit time. the processing of the bit time, the calculation of the position of the sample point, and occasional synchronizations are controlled by the can controller and are evaluated once per time quantum. the can controller translates messages to and from frames. in addition, the controller generates and discards the enclosing fixed format bits, inserts and extracts stuff bits, calculates and checks the crc code, performs the error management, and decides which type of synchronization is to be used. the bit value is received or transmitted at the sample point. the information processing time (ipt) is the time after the sample point needed to calculate the next bit to be transmitted on the can bus. the ipt includes any of the following: retrieving the next data bit, handling a crc bit, determining if bit stuffing is required, generating an error flag or simply going idle. the ipt is application-specific but may not be longer than 2 t q ; the can's ipt is 0 t q . its length is the lower limit of the programmed length of phase2. in case of synchronization, phase2 may be shortened to a value less than ipt, which does not affect bus timing. 17.3.16 calculating the bit timing parameters usually, the calculation of the bit timing configuration starts with a required bit rate or bit time. the resulting bit time (1/bit rate) must be an integer multiple of the system clock period. the bit time may consist of 4 to 25 time quanta. several combinations may lead to the required bit time, allowing iterations of the following steps. the first part of the bit time to be defined is prop. its length depends on the delay times measured in the system. a maximum bus length as well as a maximum node delay has to be defined for expandable can bus systems. the resulting time for prop is converted into time quanta (rounded up to the nearest integer multiple of t q ). sync is 1 t q long (fixed), which leaves (bit time - prop - 1) t q for the two phase buffer segments. if the number of remaining t q is even, the phase buffer segments have the same length, that is, phase2 = phase1, else phase2 = phase1 + 1. the minimum nominal length of phase2 has to be regarded as well. phase2 may not be shorter than the can controller's information processing time, which is, depending on the actual implementation, in the range of [0..2] t q . the length of the synchronization jump width is set to the least of 4, phase1 or phase2. the oscillator tolerance range necessary for the resulting configuration is calculated by the formula given below: where: df = maximum tolerance of oscillator frequency fosc = actual oscillator frequency fnom = nominal oscillator frequency maximum frequency tolerance must take into account the following formulas: july 03, 2014 886 texas instruments-production data controller area network (can) module () ( ) fnom df fosc fnom df + ? 1 1 ( ) () 2 _ 13 2 min 2 _ , 1 _ seg phase tbit seg phase seg phase df ? f no m d f df = 2 max where: phase1 and phase2 are from table 17-4 on page 885 tbit = bit time dfmax = maximum difference between two oscillators if more than one configuration is possible, that configuration allowing the highest oscillator tolerance range should be chosen. can nodes with different system clocks require different configurations to come to the same bit rate. the calculation of the propagation time in the can network, based on the nodes with the longest delay times, is done once for the whole network. the can system's oscillator tolerance range is limited by the node with the lowest tolerance range. the calculation may show that bus length or bit rate have to be decreased or that the oscillator frequencies' stability has to be increased in order to find a protocol-compliant configuration of the can bit timing. 17.3.16.1 example for bit timing at high baud rate in this example, the frequency of can clock is 25 mhz, and the bit rate is 1 mbps. bit time = 1 s = n * t q = 5 * t q t q = 200 ns t q = (baud rate prescaler)/can clock baud rate prescaler = t q * can clock baud rate prescaler = 200e-9 * 25e6 = 5 tsync = 1 * t q = 200 ns \\fixed at 1 time quanta delay of bus driver 50 ns delay of receiver circuit 30 ns delay of bus line (40m) 220 ns tprop 400 ns = 2 * t q \\400 is next integer multiple of t q bit time = tsync + ttseg1 + ttseg2 = 5 * t q bit time = tsync + tprop + tphase 1 + tphase2 tphase 1 + tphase2 = bit time - tsync - tprop tphase 1 + tphase2 = (5 * t q ) - (1 * t q ) - (2 * t q ) tphase 1 + tphase2 = 2 * t q tphase1 = 1 * t q tphase2 = 1 * t q \\tphase2 = tphase1 887 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller () ( ) fnom df fosc fnom df + ? 1 1 ( ) () 2 _ 13 2 min 2 _ , 1 _ seg phase tbit seg phase seg phase df ? f no m d f df = 2 max () ( ) fnom df fosc fnom df + ? 1 1 ( ) () 2 _ 13 2 min 2 _ , 1 _ seg phase tbit seg phase seg phase df ? f no m d f df = 2 max ttseg1 = tprop + tphase1 ttseg1 = (2 * t q ) + (1 * t q ) ttseg1 = 3 * t q ttseg2 = tphase2 ttseg2 = (information processing time + 1) * t q ttseg2 = 1 * t q \\assumes ipt=0 tsjw = 1 * t q \\least of 4, phase1 and phase2 in the above example, the bit field values for the canbit register are: = tseg2 -1 = 1-1 = 0 tseg2 = tseg1 -1 = 3-1 = 2 tseg1 = sjw -1 = 1-1 = 0 sjw = baud rate prescaler - 1 = 5-1 =4 brp the final value programmed into the canbit register = 0x0204. 17.3.16.2 example for bit timing at low baud rate in this example, the frequency of the can clock is 50 mhz, and the bit rate is 100 kbps. bit time = 10 s = n * t q = 10 * t q t q = 1 s t q = (baud rate prescaler)/can clock baud rate prescaler = t q * can clock baud rate prescaler = 1e-6 * 50e6 = 50 tsync = 1 * t q = 1 s \\fixed at 1 time quanta delay of bus driver 200 ns delay of receiver circuit 80 ns delay of bus line (40m) 220 ns tprop 1 s = 1 * t q \\1 s is next integer multiple of t q bit time = tsync + ttseg1 + ttseg2 = 10 * t q bit time = tsync + tprop + tphase 1 + tphase2 tphase 1 + tphase2 = bit time - tsync - tprop tphase 1 + tphase2 = (10 * t q ) - (1 * t q ) - (1 * t q ) tphase 1 + tphase2 = 8 * t q tphase1 = 4 * t q tphase2 = 4 * t q \\tphase1 = tphase2 july 03, 2014 888 texas instruments-production data controller area network (can) module ttseg1 = tprop + tphase1 ttseg1 = (1 * t q ) + (4 * t q ) ttseg1 = 5 * t q ttseg2 = tphase2 ttseg2 = (information processing time + 4) t q ttseg2 = 4 * t q \\assumes ipt=0 tsjw = 4 * t q \\least of 4, phase1, and phase2 = tseg2 -1 = 4-1 = 3 tseg2 = tseg1 -1 = 5-1 = 4 tseg1 = sjw -1 = 4-1 = 3 sjw = baud rate prescaler - 1 = 50-1 =49 brp the final value programmed into the canbit register = 0x34f1. 17.4 register map table 17-6 on page 889 lists the registers. all addresses given are relative to the can base address of: can0: 0x4004.0000 can1: 0x4004.1000 note that the can controller clock must be enabled before the registers can be programmed (see page 262). there must be a delay of 3 system clocks after the can module clock is enabled before any can module registers are accessed. table 17-6. can register map see page description reset type name offset 892 can control 0x0000.0001 r/w canctl 0x000 894 can status 0x0000.0000 r/w cansts 0x004 897 can error counter 0x0000.0000 ro canerr 0x008 898 can bit timing 0x0000.2301 r/w canbit 0x00c 899 can interrupt 0x0000.0000 ro canint 0x010 900 can test 0x0000.0000 r/w cantst 0x014 902 can baud rate prescaler extension 0x0000.0000 r/w canbrpe 0x018 903 can if1 command request 0x0000.0001 r/w canif1crq 0x020 889 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 17-6. can register map (continued) see page description reset type name offset 904 can if1 command mask 0x0000.0000 r/w canif1cmsk 0x024 907 can if1 mask 1 0x0000.ffff r/w canif1msk1 0x028 908 can if1 mask 2 0x0000.ffff r/w canif1msk2 0x02c 910 can if1 arbitration 1 0x0000.0000 r/w canif1arb1 0x030 911 can if1 arbitration 2 0x0000.0000 r/w canif1arb2 0x034 913 can if1 message control 0x0000.0000 r/w canif1mctl 0x038 916 can if1 data a1 0x0000.0000 r/w canif1da1 0x03c 916 can if1 data a2 0x0000.0000 r/w canif1da2 0x040 916 can if1 data b1 0x0000.0000 r/w canif1db1 0x044 916 can if1 data b2 0x0000.0000 r/w canif1db2 0x048 903 can if2 command request 0x0000.0001 r/w canif2crq 0x080 904 can if2 command mask 0x0000.0000 r/w canif2cmsk 0x084 907 can if2 mask 1 0x0000.ffff r/w canif2msk1 0x088 908 can if2 mask 2 0x0000.ffff r/w canif2msk2 0x08c 910 can if2 arbitration 1 0x0000.0000 r/w canif2arb1 0x090 911 can if2 arbitration 2 0x0000.0000 r/w canif2arb2 0x094 913 can if2 message control 0x0000.0000 r/w canif2mctl 0x098 916 can if2 data a1 0x0000.0000 r/w canif2da1 0x09c 916 can if2 data a2 0x0000.0000 r/w canif2da2 0x0a0 916 can if2 data b1 0x0000.0000 r/w canif2db1 0x0a4 916 can if2 data b2 0x0000.0000 r/w canif2db2 0x0a8 917 can transmission request 1 0x0000.0000 ro cantxrq1 0x100 917 can transmission request 2 0x0000.0000 ro cantxrq2 0x104 918 can new data 1 0x0000.0000 ro cannwda1 0x120 918 can new data 2 0x0000.0000 ro cannwda2 0x124 919 can message 1 interrupt pending 0x0000.0000 ro canmsg1int 0x140 919 can message 2 interrupt pending 0x0000.0000 ro canmsg2int 0x144 920 can message 1 valid 0x0000.0000 ro canmsg1val 0x160 920 can message 2 valid 0x0000.0000 ro canmsg2val 0x164 17.5 can register descriptions the remainder of this section lists and describes the can registers, in numerical order by address offset. there are two sets of interface registers that are used to access the message objects in july 03, 2014 890 texas instruments-production data controller area network (can) module the message ram: canif1x and canif2x . the function of the two sets are identical and are used to queue transactions. 891 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 1: can control (canctl), offset 0x000 this control register initializes the module and enables test mode and interrupts. the bus-off recovery sequence (see can specification rev. 2.0) cannot be shortened by setting or clearing init . if the device goes bus-off, it sets init , stopping all bus activities. once init has been cleared by the cpu, the device then waits for 129 occurrences of bus idle (129 * 11 consecutive high bits) before resuming normal operations. at the end of the bus-off recovery sequence, the error management counters are reset. during the waiting time after init is cleared, each time a sequence of 11 high bits has been monitored, a biterror0 code is written to the cansts register (the lec field = 0x5), enabling the cpu to readily check whether the can bus is stuck low or continuously disturbed, and to monitor the proceeding of the bus-off recovery sequence. can control (canctl) can0 base: 0x4004.0000 can1 base: 0x4004.1000 offset 0x000 type r/w, reset 0x0000.0001 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 init ie sie eie reserved dar cce test reserved r/w r/w r/w r/w ro r/w r/w r/w ro ro ro ro ro ro ro ro type 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 test mode enable description value the can controller is operating normally. 0 the can controller is in test mode. 1 0 r/w test 7 configuration change enable description value write accesses to the canbit register are not allowed. 0 write accesses to the canbit register are allowed if the init bit is 1. 1 0 r/w cce 6 disable automatic-retransmission description value auto-retransmission of disturbed messages is enabled. 0 auto-retransmission is disabled. 1 0 r/w dar 5 july 03, 2014 892 texas instruments-production data controller area network (can) module description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 4 error interrupt enable description value no error status interrupt is generated. 0 a change in the boff or ewarn bits in the cansts register generates an interrupt. 1 0 r/w eie 3 status interrupt enable description value no status interrupt is generated. 0 an interrupt is generated when a message has successfully been transmitted or received, or a can bus error has been detected. a change in the txok, rxok or lec bits in the cansts register generates an interrupt. 1 0 r/w sie 2 can interrupt enable description value interrupts disabled. 0 interrupts enabled. 1 0 r/w ie 1 initialization description value normal operation. 0 initialization started. 1 1 r/w init 0 893 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 2: can status (cansts), offset 0x004 important: this register is read-sensitive. see the register description for details. the status register contains information for interrupt servicing such as bus-off, error count threshold, and error types. the lec field holds the code that indicates the type of the last error to occur on the can bus. this field is cleared when a message has been transferred (reception or transmission) without error. the unused error code 0x7 may be written by the cpu to manually set this field to an invalid error so that it can be checked for a change later. an error interrupt is generated by the boff and ewarn bits, and a status interrupt is generated by the rxok, txok , and lec bits, if the corresponding enable bits in the can control (canctl) register are set. a change of the epass bit or a write to the rxok, txok , or lec bits does not generate an interrupt. reading the can status (cansts) register clears the can interrupt (canint) register, if it is pending. can status (cansts) can0 base: 0x4004.0000 can1 base: 0x4004.1000 offset 0x004 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 lec txok rxok epass ewarn boff reserved r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 bus-off status description value the can controller is not in bus-off state. 0 the can controller is in bus-off state. 1 0 ro boff 7 warning status description value both error counters are below the error warning limit of 96. 0 at least one of the error counters has reached the error warning limit of 96. 1 0 ro ewarn 6 july 03, 2014 894 texas instruments-production data controller area network (can) module description reset type name bit/field error passive description value the can module is in the error active state, that is, the receive or transmit error count is less than or equal to 127. 0 the can module is in the error passive state, that is, the receive or transmit error count is greater than 127. 1 0 ro epass 5 received a message successfully description value since this bit was last cleared, no message has been successfully received. 0 since this bit was last cleared, a message has been successfully received, independent of the result of the acceptance filtering. 1 this bit must be cleared by writing a 0 to it. 0 r/w rxok 4 transmitted a message successfully description value since this bit was last cleared, no message has been successfully transmitted. 0 since this bit was last cleared, a message has been successfully transmitted error-free and acknowledged by at least one other node. 1 this bit must be cleared by writing a 0 to it. 0 r/w txok 3 895 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field last error code this is the type of the last error to occur on the can bus. description value no error 0x0 stuff error more than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 0x1 format error a fixed format part of the received frame has the wrong format. 0x2 ack error the message transmitted was not acknowledged by another node. 0x3 bit 1 error when a message is transmitted, the can controller monitors the data lines to detect any conflicts. when the arbitration field is transmitted, data conflicts are a part of the arbitration protocol. when other frame fields are transmitted, data conflicts are considered errors. a bit 1 error indicates that the device wanted to send a high level (logical 1) but the monitored bus value was low (logical 0). 0x4 bit 0 error a bit 0 error indicates that the device wanted to send a low level (logical 0), but the monitored bus value was high (logical 1). during bus-off recovery, this status is set each time a sequence of 11 high bits has been monitored. by checking for this status, software can monitor the proceeding of the bus-off recovery sequence without any disturbances to the bus. 0x5 crc error the crc checksum was incorrect in the received message, indicating that the calculated value received did not match the calculated crc of the data. 0x6 no event when the lec bit shows this value, no can bus event was detected since this value was written to the lec field. 0x7 0x0 r/w lec 2:0 july 03, 2014 896 texas instruments-production data controller area network (can) module register 3: can error counter (canerr), offset 0x008 this register contains the error counter values, which can be used to analyze the cause of an error. can error counter (canerr) can0 base: 0x4004.0000 can1 base: 0x4004.1000 offset 0x008 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tec rec rp ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 received error passive description value the receive error counter is below the error passive level (127 or less). 0 the receive error counter has reached the error passive level (128 or greater). 1 0 ro rp 15 receive error counter this field contains the state of the receiver error counter (0 to 127). 0x00 ro rec 14:8 transmit error counter this field contains the state of the transmit error counter (0 to 255). 0x00 ro tec 7:0 897 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 4: can bit timing (canbit), offset 0x00c this register is used to program the bit width and bit quantum. values are programmed to the system clock frequency. this register is write-enabled by setting the cce and init bits in the canctl register. see bit time and bit rate on page 884 for more information. can bit timing (canbit) can0 base: 0x4004.0000 can1 base: 0x4004.1000 offset 0x00c type r/w, reset 0x0000.2301 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 brp sjw tseg1 tseg2 reserved r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro type 1 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:15 time segment after sample point 0x00-0x07: the actual interpretation by the hardware of this value is such that one more than the value programmed here is used. so, for example, the reset value of 0x2 means that 3 (2+1) bit time quanta are defined for phase2 (see figure 17-4 on page 885). the bit time quanta is defined by the brp field. 0x2 r/w tseg2 14:12 time segment before sample point 0x00-0x0f: the actual interpretation by the hardware of this value is such that one more than the value programmed here is used. so, for example, the reset value of 0x3 means that 4 (3+1) bit time quanta are defined for phase1 (see figure 17-4 on page 885). the bit time quanta is defined by the brp field. 0x3 r/w tseg1 11:8 (re)synchronization jump width 0x00-0x03: the actual interpretation by the hardware of this value is such that one more than the value programmed here is used. during the start of frame (sof), if the can controller detects a phase error (misalignment), it can adjust the length of tseg2 or tseg1 by the value in sjw . so the reset value of 0 adjusts the length by 1 bit time quanta. 0x0 r/w sjw 7:6 baud rate prescaler the value by which the oscillator frequency is divided for generating the bit time quanta. the bit time is built up from a multiple of this quantum. 0x00-0x03f: the actual interpretation by the hardware of this value is such that one more than the value programmed here is used. brp defines the number of can clock periods that make up 1 bit time quanta, so the reset value is 2 bit time quanta (1+1). the canbrpe register can be used to further divide the bit time. 0x1 r/w brp 5:0 july 03, 2014 898 texas instruments-production data controller area network (can) module register 5: can interrupt (canint), offset 0x010 this register indicates the source of the interrupt. if several interrupts are pending, the can interrupt (canint) register points to the pending interrupt with the highest priority, disregarding the order in which the interrupts occurred. an interrupt remains pending until the cpu has cleared it. if the intid field is not 0x0000 (the default) and the ie bit in the canctl register is set, the interrupt is active. the interrupt line remains active until the intid field is cleared by reading the cansts register, or until the ie bit in the canctl register is cleared. note: reading the can status (cansts) register clears the can interrupt (canint) register, if it is pending. can interrupt (canint) can0 base: 0x4004.0000 can1 base: 0x4004.1000 offset 0x010 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 intid ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 interrupt identifier the number in this field indicates the source of the interrupt. description value no interrupt pending 0x0000 number of the message object that caused the interrupt 0x0001-0x0020 reserved 0x0021-0x7fff status interrupt 0x8000 reserved 0x8001-0xffff 0x0000 ro intid 15:0 899 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 6: can test (cantst), offset 0x014 this register is used for self-test and external pin access. it is write-enabled by setting the test bit in the canctl register. different test functions may be combined, however, can transfers are affected if the tx bits in this register are not zero. can test (cantst) can0 base: 0x4004.0000 can1 base: 0x4004.1000 offset 0x014 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved basic silent lback tx rx reserved ro ro r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 receive observation description value the cannrx pin is low. 0 the cannrx pin is high. 1 0 ro rx 7 transmit control overrides control of the canntx pin. description value can module control canntx is controlled by the can module; default operation 0x0 sample point the sample point is driven on the canntx signal. this mode is useful to monitor bit timing. 0x1 driven low canntx drives a low value. this mode is useful for checking the physical layer of the can bus. 0x2 driven high canntx drives a high value. this mode is useful for checking the physical layer of the can bus. 0x3 0x0 r/w tx 6:5 july 03, 2014 900 texas instruments-production data controller area network (can) module description reset type name bit/field loopback mode description value loopback mode is disabled. 0 loopback mode is enabled. in loopback mode, the data from the transmitter is routed into the receiver. any data on the receive input is ignored. 1 0 r/w lback 4 silent mode description value silent mode is disabled. 0 silent mode is enabled. in silent mode, the can controller does not transmit data but instead monitors the bus. this mode is also known as bus monitor mode. 1 0 r/w silent 3 basic mode description value basic mode is disabled. 0 basic mode is enabled. in basic mode, software should use the canif1 registers as the transmit buffer and use the canif2 registers as the receive buffer. 1 0 r/w basic 2 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 1:0 901 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 7: can baud rate prescaler extension (canbrpe), offset 0x018 this register is used to further divide the bit time set with the brp bit in the canbit register. it is write-enabled by setting the cce bit in the canctl register. can baud rate prescaler extension (canbrpe) can0 base: 0x4004.0000 can1 base: 0x4004.1000 offset 0x018 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 brpe reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:4 baud rate prescaler extension 0x00-0x0f: extend the brp bit in the canbit register to values up to 1023. the actual interpretation by the hardware is one more than the value programmed by brpe (msbs) and brp (lsbs). 0x0 r/w brpe 3:0 july 03, 2014 902 texas instruments-production data controller area network (can) module register 8: can if1 command request (canif1crq), offset 0x020 register 9: can if2 command request (canif2crq), offset 0x080 a message transfer is started as soon as there is a write of the message object number to the mnum field when the txrqst bit in the canif1mctl register is set. with this write operation, the busy bit is automatically set to indicate that a transfer between the can interface registers and the internal message ram is in progress. after a wait time of 3 to 6 can_clk periods, the transfer between the interface register and the message ram completes, which then clears the busy bit. can if1 command request (canif1crq) can0 base: 0x4004.0000 can1 base: 0x4004.1000 offset 0x020 type r/w, reset 0x0000.0001 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mnum reserved busy r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro type 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 busy flag description value this bit is cleared when read/write action has finished. 0 this bit is set when a write occurs to the message number in this register. 1 0 ro busy 15 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 14:6 message number selects one of the 32 message objects in the message ram for data transfer. the message objects are numbered from 1 to 32. description value reserved 0 is not a valid message number; it is interpreted as 0x20, or object 32. 0x00 message number indicates specified message object 1 to 32. 0x01-0x20 reserved not a valid message number; values are shifted and it is interpreted as 0x01-0x1f. 0x21-0x3f 0x01 r/w mnum 5:0 903 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 10: can if1 command mask (canif1cmsk), offset 0x024 register 11: can if2 command mask (canif2cmsk), offset 0x084 reading the command mask registers provides status for various functions. writing to the command mask registers specifies the transfer direction and selects which buffer registers are the source or target of the data transfer. note that when a read from the message object buffer occurs when the wrnrd bit is clear and the clrintpnd and/or newdat bits are set, the interrupt pending and/or new data flags in the message object buffer are cleared. can if1 command mask (canif1cmsk) can0 base: 0x4004.0000 can1 base: 0x4004.1000 offset 0x024 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 datab dataa newdat / txrqst clrintpnd control arb mask wrnrd reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 write, not read description value transfer the data in the can message object specified by the the mnum field in the canifncrq register into the canifn registers. 0 transfer the data in the canifn registers to the can message object specified by the mnum field in the can command request (canifncrq) . 1 note: interrupt pending and new data conditions in the message buffer can be cleared by reading from the buffer ( wrnrd = 0) when the clrintpnd and/or newdat bits are set. 0 r/w wrnrd 7 access mask bits description value mask bits unchanged. 0 transfer idmask + dir + mxtd of the message object into the interface registers. 1 0 r/w mask 6 july 03, 2014 904 texas instruments-production data controller area network (can) module description reset type name bit/field access arbitration bits description value arbitration bits unchanged. 0 transfer id + dir + xtd + msgval of the message object into the interface registers. 1 0 r/w arb 5 access control bits description value control bits unchanged. 0 transfer control bits from the canifnmctl register into the interface registers. 1 0 r/w control 4 clear interrupt pending bit the function of this bit depends on the configuration of the wrnrd bit. description value if wrnrd is clear, the interrupt pending status is transferred from the message buffer into the canifnmctl register. if wrnrd is set, the intpnd bit in the message object remains unchanged. 0 if wrnrd is clear, the interrupt pending status is cleared in the message buffer. note the value of this bit that is transferred to the canifnmctl register always reflects the status of the bits before clearing. if wrnrd is set, the intpnd bit is cleared in the message object. 1 0 r/w clrintpnd 3 newdat / txrqst bit the function of this bit depends on the configuration of the wrnrd bit. description value if wrnrd is clear, the value of the new data status is transferred from the message buffer into the canifnmctl register. if wrnrd is set, a transmission is not requested. 0 if wrnrd is clear, the new data status is cleared in the message buffer. note the value of this bit that is transferred to the canifnmctl register always reflects the status of the bits before clearing. if wrnrd is set, a transmission is requested. note that when this bit is set, the txrqst bit in the canifnmctl register is ignored. 1 0 r/w newdat / txrqst 2 905 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field access data byte 0 to 3 the function of this bit depends on the configuration of the wrnrd bit. description value data bytes 0-3 are unchanged. 0 if wrnrd is clear, transfer data bytes 0-3 in canifnda1 and canifnda2 to the message object. if wrnrd is set, transfer data bytes 0-3 in message object to canifnda1 and canifnda2 . 1 0 r/w dataa 1 access data byte 4 to 7 the function of this bit depends on the configuration of the wrnrd bit as follows: description value data bytes 4-7 are unchanged. 0 if wrnrd is clear, transfer data bytes 4-7 in canifnda1 and canifnda2 to the message object. if wrnrd is set, transfer data bytes 4-7 in message object to canifnda1 and canifnda2 . 1 0 r/w datab 0 july 03, 2014 906 texas instruments-production data controller area network (can) module register 12: can if1 mask 1 (canif1msk1), offset 0x028 register 13: can if2 mask 1 (canif2msk1), offset 0x088 the mask information provided in this register accompanies the data ( canifndan ), arbitration information ( canifnarbn ), and control information ( canifnmctl ) to the message object in the message ram. the mask is used with the id bit in the canifnarbn register for acceptance filtering. additional mask information is contained in the canifnmsk2 register. can if1 mask 1 (canif1msk1) can0 base: 0x4004.0000 can1 base: 0x4004.1000 offset 0x028 type r/w, reset 0x0000.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 msk r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 identifier mask when using a 29-bit identifier, these bits are used for bits [15:0] of the id. the msk field in the canifnmsk2 register are used for bits [28:16] of the id. when using an 11-bit identifier, these bits are ignored. description value the corresponding identifier field ( id ) in the message object cannot inhibit the match in acceptance filtering. 0 the corresponding identifier field ( id ) is used for acceptance filtering. 1 0xffff r/w msk 15:0 907 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 14: can if1 mask 2 (canif1msk2), offset 0x02c register 15: can if2 mask 2 (canif2msk2), offset 0x08c this register holds extended mask information that accompanies the canifnmsk1 register. can if1 mask 2 (canif1msk2) can0 base: 0x4004.0000 can1 base: 0x4004.1000 offset 0x02c type r/w, reset 0x0000.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 msk reserved mdir mxtd r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro r/w r/w type 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 mask extended identifier description value the extended identifier bit ( xtd in the canifnarb2 register) has no effect on the acceptance filtering. 0 the extended identifier bit xtd is used for acceptance filtering. 1 1 r/w mxtd 15 mask message direction description value the message direction bit ( dir in the canifnarb2 register) has no effect for acceptance filtering. 0 the message direction bit dir is used for acceptance filtering. 1 1 r/w mdir 14 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 ro reserved 13 july 03, 2014 908 texas instruments-production data controller area network (can) module description reset type name bit/field identifier mask when using a 29-bit identifier, these bits are used for bits [28:16] of the id. the msk field in the canifnmsk1 register are used for bits [15:0] of the id. when using an 11-bit identifier, msk[12:2] are used for bits [10:0] of the id. description value the corresponding identifier field ( id ) in the message object cannot inhibit the match in acceptance filtering. 0 the corresponding identifier field ( id ) is used for acceptance filtering. 1 0xff r/w msk 12:0 909 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 16: can if1 arbitration 1 (canif1arb1), offset 0x030 register 17: can if2 arbitration 1 (canif2arb1), offset 0x090 these registers hold the identifiers for acceptance filtering. can if1 arbitration 1 (canif1arb1) can0 base: 0x4004.0000 can1 base: 0x4004.1000 offset 0x030 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 id r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 message identifier this bit field is used with the id field in the canifnarb2 register to create the message identifier. when using a 29-bit identifier, bits 15:0 of the canifnarb1 register are [15:0] of the id, while bits 12:0 of the canifnarb2 register are [28:16] of the id. when using an 11-bit identifier, these bits are not used. 0x0000 r/w id 15:0 july 03, 2014 910 texas instruments-production data controller area network (can) module register 18: can if1 arbitration 2 (canif1arb2), offset 0x034 register 19: can if2 arbitration 2 (canif2arb2), offset 0x094 these registers hold information for acceptance filtering. can if1 arbitration 2 (canif1arb2) can0 base: 0x4004.0000 can1 base: 0x4004.1000 offset 0x034 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 id dir xtd msgval r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 message valid description value the message object is ignored by the message handler. 0 the message object is configured and ready to be considered by the message handler within the can controller. 1 all unused message objects should have this bit cleared during initialization and before clearing the init bit in the canctl register. the msgval bit must also be cleared before any of the following bits are modified or if the message object is no longer required: the id fields in the canifnarbn registers, the xtd and dir bits in the canifnarb2 register, or the dlc field in the canifnmctl register. 0 r/w msgval 15 extended identifier description value an 11-bit standard identifier is used for this message object. 0 a 29-bit extended identifier is used for this message object. 1 0 r/w xtd 14 911 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field message direction description value receive. when the txrqst bit in the canifnmctl register is set, a remote frame with the identifier of this message object is received. on reception of a data frame with matching identifier, that message is stored in this message object. 0 transmit. when the txrqst bit in the canifnmctl register is set, the respective message object is transmitted as a data frame. on reception of a remote frame with matching identifier, the txrqst bit of this message object is set (if rmten=1). 1 0 r/w dir 13 message identifier this bit field is used with the id field in the canifnarb2 register to create the message identifier. when using a 29-bit identifier, id[15:0] of the canifnarb1 register are [15:0] of the id, while these bits, id[12:0] , are [28:16] of the id. when using an 11-bit identifier, id[12:2] are used for bits [10:0] of the id. the id field in the canifnarb1 register is ignored. 0x000 r/w id 12:0 july 03, 2014 912 texas instruments-production data controller area network (can) module register 20: can if1 message control (canif1mctl), offset 0x038 register 21: can if2 message control (canif2mctl), offset 0x098 this register holds the control information associated with the message object to be sent to the message ram. can if1 message control (canif1mctl) can0 base: 0x4004.0000 can1 base: 0x4004.1000 offset 0x038 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dlc reserved eob txrqst rmten rxie txie umask intpnd msglst newdat r/w r/w r/w r/w ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 new data description value no new data has been written into the data portion of this message object by the message handler since the last time this flag was cleared by the cpu. 0 the message handler or the cpu has written new data into the data portion of this message object. 1 0 r/w newdat 15 message lost description value no message was lost since the last time this bit was cleared by the cpu. 0 the message handler stored a new message into this object when newdat was set; the cpu has lost a message. 1 this bit is only valid for message objects when the dir bit in the canifnarb2 register is clear (receive). 0 r/w msglst 14 interrupt pending description value this message object is not the source of an interrupt. 0 this message object is the source of an interrupt. the interrupt identifier in the canint register points to this message object if there is not another interrupt source with a higher priority. 1 0 r/w intpnd 13 913 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field use acceptance mask description value mask is ignored. 0 use mask ( msk, mxtd , and mdir bits in the canifnmskn registers) for acceptance filtering. 1 0 r/w umask 12 transmit interrupt enable description value the intpnd bit in the canifnmctl register is unchanged after a successful transmission of a frame. 0 the intpnd bit in the canifnmctl register is set after a successful transmission of a frame. 1 0 r/w txie 11 receive interrupt enable description value the intpnd bit in the canifnmctl register is unchanged after a successful reception of a frame. 0 the intpnd bit in the canifnmctl register is set after a successful reception of a frame. 1 0 r/w rxie 10 remote enable description value at the reception of a remote frame, the txrqst bit in the canifnmctl register is left unchanged. 0 at the reception of a remote frame, the txrqst bit in the canifnmctl register is set. 1 0 r/w rmten 9 transmit request description value this message object is not waiting for transmission. 0 the transmission of this message object is requested and is not yet done. 1 note: if the wrnrd and txrqst bits in the canifncmsk register are set, this bit is ignored. 0 r/w txrqst 8 july 03, 2014 914 texas instruments-production data controller area network (can) module description reset type name bit/field end of buffer description value message object belongs to a fifo buffer and is not the last message object of that fifo buffer. 0 single message object or last message object of a fifo buffer. 1 this bit is used to concatenate two or more message objects (up to 32) to build a fifo buffer. for a single message object (thus not belonging to a fifo buffer), this bit must be set. 0 r/w eob 7 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 6:4 data length code description value specifies the number of bytes in the data frame. 0x0-0x8 defaults to a data frame with 8 bytes. 0x9-0xf the dlc field in the canifnmctl register of a message object must be defined the same as in all the corresponding objects with the same identifier at other nodes. when the message handler stores a data frame, it writes dlc to the value given by the received message. 0x0 r/w dlc 3:0 915 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 22: can if1 data a1 (canif1da1), offset 0x03c register 23: can if1 data a2 (canif1da2), offset 0x040 register 24: can if1 data b1 (canif1db1), offset 0x044 register 25: can if1 data b2 (canif1db2), offset 0x048 register 26: can if2 data a1 (canif2da1), offset 0x09c register 27: can if2 data a2 (canif2da2), offset 0x0a0 register 28: can if2 data b1 (canif2db1), offset 0x0a4 register 29: can if2 data b2 (canif2db2), offset 0x0a8 these registers contain the data to be sent or that has been received. in a can data frame, data byte 0 is the first byte to be transmitted or received and data byte 7 is the last byte to be transmitted or received. in can's serial bit stream, the msb of each byte is transmitted first. can if1 data a1 (canif1da1) can0 base: 0x4004.0000 can1 base: 0x4004.1000 offset 0x03c type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 data r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 data the canifnda1 registers contain data bytes 1 and 0; canifnda2 data bytes 3 and 2; canifndb1 data bytes 5 and 4; and canifndb2 data bytes 7 and 6. 0x0000 r/w data 15:0 july 03, 2014 916 texas instruments-production data controller area network (can) module register 30: can transmission request 1 (cantxrq1), offset 0x100 register 31: can transmission request 2 (cantxrq2), offset 0x104 the cantxrq1 and cantxrq2 registers hold the txrqst bits of the 32 message objects. by reading out these bits, the cpu can check which message object has a transmission request pending. the txrqst bit of a specific message object can be changed by three sources: (1) the cpu via the canifnmctl register, (2) the message handler state machine after the reception of a remote frame, or (3) the message handler state machine after a successful transmission. the cantxrq1 register contains the txrqst bits of the first 16 message objects in the message ram; the cantxrq2 register contains the txrqst bits of the second 16 message objects. can transmission request 1 (cantxrq1) can0 base: 0x4004.0000 can1 base: 0x4004.1000 offset 0x100 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 txrqst ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 transmission request bits description value the corresponding message object is not waiting for transmission. 0 the transmission of the corresponding message object is requested and is not yet done. 1 0x0000 ro txrqst 15:0 917 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 32: can new data 1 (cannwda1), offset 0x120 register 33: can new data 2 (cannwda2), offset 0x124 the cannwda1 and cannwda2 registers hold the newdat bits of the 32 message objects. by reading these bits, the cpu can check which message object has its data portion updated. the newdat bit of a specific message object can be changed by three sources: (1) the cpu via the canifnmctl register, (2) the message handler state machine after the reception of a data frame, or (3) the message handler state machine after a successful transmission. the cannwda1 register contains the newdat bits of the first 16 message objects in the message ram; the cannwda2 register contains the newdat bits of the second 16 message objects. can new data 1 (cannwda1) can0 base: 0x4004.0000 can1 base: 0x4004.1000 offset 0x120 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 newdat ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 new data bits description value no new data has been written into the data portion of the corresponding message object by the message handler since the last time this flag was cleared by the cpu. 0 the message handler or the cpu has written new data into the data portion of the corresponding message object. 1 0x0000 ro newdat 15:0 july 03, 2014 918 texas instruments-production data controller area network (can) module register 34: can message 1 interrupt pending (canmsg1int), offset 0x140 register 35: can message 2 interrupt pending (canmsg2int), offset 0x144 the canmsg1int and canmsg2int registers hold the intpnd bits of the 32 message objects. by reading these bits, the cpu can check which message object has an interrupt pending. the intpnd bit of a specific message object can be changed through two sources: (1) the cpu via the canifnmctl register, or (2) the message handler state machine after the reception or transmission of a frame. this field is also encoded in the canint register. the canmsg1int register contains the intpnd bits of the first 16 message objects in the message ram; the canmsg2int register contains the intpnd bits of the second 16 message objects. can message 1 interrupt pending (canmsg1int) can0 base: 0x4004.0000 can1 base: 0x4004.1000 offset 0x140 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 intpnd ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 interrupt pending bits description value the corresponding message object is not the source of an interrupt. 0 the corresponding message object is the source of an interrupt. 1 0x0000 ro intpnd 15:0 919 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 36: can message 1 valid (canmsg1val), offset 0x160 register 37: can message 2 valid (canmsg2val), offset 0x164 the canmsg1val and canmsg2val registers hold the msgval bits of the 32 message objects. by reading these bits, the cpu can check which message object is valid. the message valid bit of a specific message object can be changed with the canifnarb2 register. the canmsg1val register contains the msgval bits of the first 16 message objects in the message ram; the canmsg2val register contains the msgval bits of the second 16 message objects in the message ram. can message 1 valid (canmsg1val) can0 base: 0x4004.0000 can1 base: 0x4004.1000 offset 0x160 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 msgval ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 message valid bits description value the corresponding message object is not configured and is ignored by the message handler. 0 the corresponding message object is configured and should be considered by the message handler. 1 0x0000 ro msgval 15:0 july 03, 2014 920 texas instruments-production data controller area network (can) module 18 ethernet controller the stellaris ? ethernet controller consists of a media access controller (mac) with a media independent interface (mii). the ethernet mac conforms to ieee 802.3 specifications and fully supports 10base-t and 100base-tx standards. the stellaris ethernet mac module has the following features: conforms to the ieee 802.3-2002 specification multiple operational modes C full- and half-duplex 100 mbps C full- and half-duplex 10 mbps highly configurable C programmable mac address C promiscuous mode support C crc error-rejection control C user-configurable interrupts media independent interface (mii) for connection to external 10/100 mbps phy transceivers ieee 1588 precision time protocol: provides highly accurate time stamps for individual packets efficient transfers using micro direct memory access controller (dma) C separate channels for transmit and receive C receive channel request asserted on packet receipt C transmit channel request asserted on empty transmit fifo 18.1 block diagram as shown in figure 18-1 on page 921, the ethernet controller includes the media access controller (mac) layer and a media independent interface (mii) interface for communicating to an external phy layer. these layers correspond to the osi model layers 2 and 1. the cpu accesses the mac layer which provides transmit and receive processing for ethernet frames. the phy layer communicates with the ethernet bus. figure 18-1. ethernet controller 921 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 6 w h o o d u l v ? $ 5 0 & r u w h [ 0 0 h g l d $ f f h v v & r q w u r o o h u 3 k \ v l f d o / d \ h u ( q w l w \ 0 $ & / d \ h u 3 + < / d \ h u 5 - 0 d j q h w l f v 0 , , figure 18-2 on page 922 shows more detail of the internal structure of the ethernet mac and how the register set relates to various functions. figure 18-2. ethernet mac block diagram 18.2 signal description the following table lists the external signals of the ethernet mac and describes the function of each. the mii and mac control signals are alternate functions for gpio signals and default to be gpio signals at reset. the column in the table below titled "pin mux/pin assignment" lists the gpio pin placement for the mii and mac control signals. the afsel bit in the gpio alternate function select (gpioafsel) register (page 429) should be set to choose the mii and mac control function. the number in parentheses is the encoding that must be programmed into the pmcn field in the gpio port control (gpiopctl) register (page 447) to assign the mii and mac control signals to the specified gpio port pins. for more information on configuring gpios, see general-purpose input/outputs (gpios) on page 405. table 18-1. ethernet signals (100lqfp) description buffer type a pin type pin mux / pin assignment pin number pin name mii collision detect. ttl i pg2 (3) 17 col mii carrier sense. ttl i pg3 (3) 16 crs mii management clock. ttl o pf3 (3) 59 mdc mdio of the ethernet phy. od i/o pf4 (3) 58 mdio phy interrupt. ttl i pf2 (3) 60 phyint july 03, 2014 922 texas instruments-production data ethernet controller 0 $ & 5 , 6 0 $ & , $ & . 0 $ & , 0 , q w h u u x s w & r q w u r o 0 $ & 5 & 7 / 0 $ & 1 3 5 h f h l y h & r q w u r o 0 $ & 7 & 7 / 0 $ & 7 + 5 0 $ & 7 5 7 u d q v p l w & r q w u r o 7 u d q v p l w ) , ) 2 5 h f h l y h ) , ) 2 0 $ & , $ 0 $ & , $ , q g l y l g x d o $ g g u h v v 0 $ & 0 & 7 / 0 $ & 0 ' 9 0 , , & r q w u r o 0 $ & ' ' $ 7 $ ' d w d $ f f h v v & 2 / 0 $ & 0 7 ; ' 0 $ & 0 5 ; ' , q w h u u x s w 0 $ & 7 6 5 7 l p h u 6 x s s r u w & 5 6 0 ' & 0 ' , 2 3 + < , 1 7 5 ; & . 5 ; ' > @ 5 ; ' 9 5 ; ( 5 7 ; & . 7 ; ' > @ 7 ; ( 1 7 ; ( 5 table 18-1. ethernet signals (100lqfp) (continued) description buffer type a pin type pin mux / pin assignment pin number pin name mii receive clock. 25 mhz in 100base-tx mode. 2.5 mhz in 10base-t mode. ttl i ph7 (3) pa6 (3) pf0 (4) 15 34 47 rxck mii receive data 0. ttl i pe4 (7) pg4 (3) 6 41 rxd0 mii receive data 1. ttl i pf7 (3) pb7 (7) 42 89 rxd1 mii receive data 2. ttl i pf6 (3) 43 rxd2 mii receive data 3. ttl i pf5 (3) 46 rxd3 mii receive data valid. ttl i pd0 (7) pa5 (3) ph6 (9) 10 31 62 rxdv mii receive error. ttl i pj0 (3) pa7 (3) pf1 (4) 14 35 61 rxer mii transmit clock. 25 mhz in 100base-tx mode. 2.5 mhz in 10base-t mode. ttl i pg6 (3) 37 txck mii transmit data 0. ttl o pa4 (3) ph5 (9) pd7 (4) 30 63 100 txd0 ethernet mii transmit data 1. ttl o pa3 (3) ph4 (9) pd6 (4) 29 76 99 txd1 mii transmit data 2. ttl o pa2 (3) ph3 (9) pd5 (4) 28 83 98 txd2 ethernet mii transmit data 3. ttl o pc4 (3) ph2 (9) pd4 (4) 25 84 97 txd3 mii transmit enable. ttl o pg5 (3) 40 txen mii transmit error. ttl o pd1 (7) pg7 (3) 11 36 txer a. the ttl designation indicates the pin has ttl-compatible voltage levels. table 18-2. ethernet signals (108bga) description buffer type a pin type pin mux / pin assignment pin number pin name mii collision detect. ttl i pg2 (3) j1 col mii carrier sense. ttl i pg3 (3) j2 crs mii management clock. ttl o pf3 (3) j12 mdc mdio of the ethernet phy. od i/o pf4 (3) l9 mdio phy interrupt. ttl i pf2 (3) j11 phyint mii receive clock. 25 mhz in 100base-tx mode. 2.5 mhz in 10base-t mode. ttl i ph7 (3) pa6 (3) pf0 (4) h3 l6 m9 rxck mii receive data 0. ttl i pe4 (7) pg4 (3) b2 k3 rxd0 923 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 18-2. ethernet signals (108bga) (continued) description buffer type a pin type pin mux / pin assignment pin number pin name mii receive data 1. ttl i pf7 (3) pb7 (7) k4 a8 rxd1 mii receive data 2. ttl i pf6 (3) m8 rxd2 mii receive data 3. ttl i pf5 (3) l8 rxd3 mii receive data valid. ttl i pd0 (7) pa5 (3) ph6 (9) g1 m5 g3 rxdv mii receive error. ttl i pj0 (3) pa7 (3) pf1 (4) f3 m6 h12 rxer mii transmit clock. 25 mhz in 100base-tx mode. 2.5 mhz in 10base-t mode. ttl i pg6 (3) l7 txck mii transmit data 0. ttl o pa4 (3) ph5 (9) pd7 (4) l5 f10 a2 txd0 ethernet mii transmit data 1. ttl o pa3 (3) ph4 (9) pd6 (4) l4 b10 a3 txd1 mii transmit data 2. ttl o pa2 (3) ph3 (9) pd5 (4) m4 d10 c6 txd2 ethernet mii transmit data 3. ttl o pc4 (3) ph2 (9) pd4 (4) l1 d11 b5 txd3 mii transmit enable. ttl o pg5 (3) m7 txen mii transmit error. ttl o pd1 (7) pg7 (3) g2 c10 txer a. the ttl designation indicates the pin has ttl-compatible voltage levels. 18.3 functional description the functional description of the ethernet controller is discussed in the following sections. 18.3.1 mac operation the following sections describe the operation of the mac layer, including an overview of the ethernet frame format, the mac layer fifos, ethernet transmission and reception options, packet timestamps, and led indicators. 18.3.1.1 ethernet frame format ethernet data is carried by ethernet frames. the basic frame format is shown in figure 18-3 on page 924. figure 18-3. ethernet frame july 03, 2014 924 texas instruments-production data ethernet controller 3 u h d p e o h 6 ) ' ' h v w l q d w l r q $ g g u h v v 6 r x u f h $ g g u h v v / h q j w k 7 \ s h ) & 6 ' d w d % \ w h v % \ w h v % \ w h v % \ w h v % \ w h % \ w h v % \ w h v the seven fields of the frame are transmitted from left to right. the bits within the frame are transmitted from least to most significant bit. preamble the preamble field is used to synchronize with the received frames timing. the preamble is 7 octets long. start frame delimiter (sfd) the sfd field follows the preamble pattern and indicates the start of the frame. its value is 1010.1011b. destination address (da) this field specifies destination addresses for which the frame is intended. the lsb (bit 16 of da oct 1 in the frame, see table 18-3 on page 926) of the da determines whether the address is an individual (0), or group/multicast (1) address. source address (sa) the source address field identifies the station from which the frame was initiated. length/type field the meaning of this field depends on its numeric value. this field can be interpreted as length or type code. the maximum length of the data field is 1500 octets. if the value of the length/type field is less than or equal to 1500 decimal, it indicates the number of mac client data octets. if the value of this field is greater than or equal to 1536 decimal, then it encodes the type interpretation. the meaning of the length/type field when the value is between 1500 and 1536 decimal is unspecified by the ieee 802.3 standard. however, the ethernet mac assumes type interpretation if the value of the length/type field is greater than 1500 decimal. the definition of the type field is specified in the ieee 802.3 standard. the first of the two octets in this field is most significant. data the data field is a sequence of octets that is at least 46 in length, up to 1500 in length. full data transparency is provided so any values can appear in this field. a minimum frame size of 46 octets is required to meet the ieee standard. if the frame size is too small, the ethernet mac automatically appends extra bits (a pad), thus the pad can have a size of 0 to 46 octets. data padding can be disabled by clearing the paden bit in the ethernet mac transmit control (mactctl) register. for the ethernet mac, data sent/received can be larger than 1500 bytes without causing a frame too long error. instead, a fifo overrun error is reported using the fov bit in the ethernet mac raw interrupt status (macris) register when the frame received is too large to fit into the ethernet macs 2k ram. frame check sequence (fcs) the frame check sequence carries the cyclic redundancy check (crc) value. the crc is computed over the destination address, source address, length/type, and data (including pad) fields using the crc-32 algorithm. the ethernet mac computes the fcs value one nibble at a time. for transmitted frames, this field is automatically inserted by the mac layer, unless disabled by clearing the crc bit in the mactctl register. for received frames, this field is automatically 925 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller checked. if the fcs does not pass, the frame is not placed in the rx fifo, unless the fcs check is disabled by clearing the badcrc bit in the macrctl register. 18.3.1.2 mac layer fifos the ethernet mac is capable of simultaneous transmission and reception. this feature is enabled by setting the duplex bit in the mactctl register. for ethernet frame transmission, a 2-kb transmit fifo is provided that can be used to store a single frame. while the ieee 802.3 specification limits the size of an ethernet frame's payload section to 1500 bytes, the ethernet mac places no such limit. the full buffer can be used for a payload of up to 2032 bytes (as the first 16 bytes in the fifo are reserved for destination address, source address and length/type information). for ethernet frame reception, a 2-kb receive fifo is provided that can be used to store multiple frames, up to a maximum of 31 frames. if a frame is received, and there is insufficient space in the rx fifo, an overflow error is indicated using the fov bit in the macris register. for details regarding the tx and rx fifo layout, refer to table 18-3 on page 926. please note the following difference between tx and rx fifo layout. for the tx fifo, the data length field in the first fifo word refers to the ethernet frame data payload, as shown in the 5th to nth fifo positions. for the rx fifo, the frame length field is the total length of the received ethernet frame, including the length/type bytes and the fcs bits. if fcs generation is disabled by clearing the crc bit in the mactctl register, the last word in the tx fifo must contain the fcs bytes for the frame that has been written to the fifo. also note that if the length of the data payload section is not a multiple of 4, the fcs field is not aligned on a word boundary in the fifo. however, for the rx fifo, the beginning of the next frame is always on a word boundary. table 18-3. tx & rx fifo organization rx fifo (read) tx fifo (write) word bit fields fifo word read/write sequence frame length least significant byte data length least significant byte 7:0 1st frame length most significant byte data length most significant byte 15:8 da oct 1 23:16 da oct 2 31:24 da oct 3 7:0 2nd da oct 4 15:8 da oct 5 23:16 da oct 6 31:24 sa oct 1 7:0 3rd sa oct 2 15:8 sa oct 3 23:16 sa oct 4 31:24 sa oct 5 7:0 4th sa oct 6 15:8 len/type most significant byte 23:16 len/type least significant byte 31:24 july 03, 2014 926 texas instruments-production data ethernet controller table 18-3. tx & rx fifo organization (continued) rx fifo (read) tx fifo (write) word bit fields fifo word read/write sequence data oct n 7:0 5th to nth data oct n+1 15:8 data oct n+2 23:16 data oct n+3 31:24 fcs 1 a 7:0 last fcs 2 a 15:8 fcs 3 a 23:16 fcs 4 a 31:24 a. if the crc bit in the mactctl register is clear, the fcs bytes must be written with the correct crc. if the crc bit is set, the ethernet mac automatically writes the fcs bytes. 18.3.1.3 ethernet transmission options at the mac layer, the transmitter can be configured for both full-duplex and half-duplex operation by using the duplex bit in the mactctl register. note that in 10base-t half-duplex mode, the transmitted data is looped back on the receive path. the ethernet mac automatically generates and inserts the frame check sequence (fcs) at the end of the transmit frame when the crc bit in the mactctl register is set. however, for test purposes, this feature can be disabled in order to generate a frame with an invalid crc by clearing the crc bit. the ieee 802.3 specification requires that the ethernet frame payload section be a minimum of 46 bytes. the ethernet mac automatically pads the data section if the payload data section loaded into the fifo is less than the minimum 46 bytes when the paden bit in the mactctl register is set. this feature can be disabled by clearing the paden bit. the transmitter must be enabled by setting the txen bit in the mactctl register. 18.3.1.4 ethernet reception options the ethernet mac rx fifo should be cleared during software initialization. the receiver should first be disabled by clearing the rxen bit in the ethernet mac receive control (macrctl) register, then the fifo can be cleared by setting the rstfifo bit in the macrctl register. the receiver automatically rejects frames that contain bad crc values in the fcs field. in this case, a receive error interrupt is generated and the receive data is lost. to accept all frames, clear the badcrc bit in the macrctl register. in normal operating mode, the receiver accepts only those frames that have a destination address that matches the address programmed into the ethernet mac individual address 0 (macia0) and ethernet mac individual address 1 (macia1) registers. however, the ethernet receiver can also be configured for promiscuous and multicast modes by setting the prms and amul bits in the macrctl register. it is important to note that when the receiver is enabled, all valid frames with a broadcast address of ff-ff-ff-ff-ff-ff in the destination address field are received and stored in the rx fifo, even if the amul bit is not set. 18.3.1.5 packet timestamps some applications require a very precise clock for time stamping samples or triggering events. the ieee precision time protocol (ptp), or ieee-1588, provides a mechanism for synchronizing clocks 927 july 03, 2014 texas instruments-production data stellaris lm3s9gn5 microcontroller across an ethernet to sub-microsecond precision. the accuracy of the ptp clock depends greatly upon the accuracy of timestamps of the ptp ethernet packets. in a software-only ptp solution, there can be jitter in the ethernet packet timestamps, resulting in a less precise ptp clock on the target. in some stellaris devices, general-purpose timer 3 (gpt3) can be used in conjunction with the ethernet mac timer support (macts) register to provide a more accurate timestamp for ethernet packets. this feature is enabled by setting the tsen bit in the macts register. note that when this feature is enabled, gpt3 must be dedicated to the ethernet mac. gpt3 must be configured to 16-bit edge capture mode, see page 554. timer a of gpt3 stores the transmit time, and timer b stores the receive time. one other general-purpose timer can be set up as a 16-bit free-running timer to synchronize the receiver and transmitter timers and provide a timestamp with which to compare the timestamps stored in gpt3. the enet_ptpd example in the stellarisware ? software package provides a sample ptp application that illustrates both software-only time stamping as well the use of the gpt3 and macts register for more accurate timestamps. this example supports version 1 of the ieee-1588 protocol, but stellaris microcontrollers support both versions 1 and 2. 18.3.2 media independent interface the media independent interface (mii) is used for communication between the mac layer and the off-chip phy layer. the mii can accommodate up to 32 external phys and can communicate at either 10 mb/s or 100 mb/s. the functionality is identical at both data rates, as are the signal timing relationships. the only difference between the two data rates is the nominal clock frequency. an external phy may support only one data rate or both. the signals in this standard interface can be broken down into three groups: receive signals transmit signals control signals 18.3.2.1 receive interface the receive clock, rxck , is a continuous clock that provides a timing reference for the receive data transfer. rxck is sourced by the phy and should be 25% of the nominal receive data rate. for 100base-t, rxck should be 25 mhz; for 10base-t, rxck should be 2.5 mhz. data is received from the phy using 4 data signals, rxd[3:0] , which are driven synchronously from the phy. rxd0 is the lsb and rxd3 is the msb. data from the phy is valid when the data valid signal, rxdv , is asserted. rxdv must be asserted with the first recovered nibbled of the frame and stay asserted through the final recovered nibble. rxdv should be negated prior to the first rxck that follows the final nibble. if the phy detects an error in the frame, the rxer input should be asserted for at least one clock period. table 18-4. receive signal encoding decscription normal inter-frame 0x0 - 0xf 0 0 normal inter-frame 0x0 1 0 reserved 0x1 - 0xd 1 0 false carrier indication 0xe 1 0 reserved 0xf 1 0 normal data reception 0x0 - 0xf 0 1 july 03, 2014 928 texas instruments-production data ethernet controller table 18-4. receive signal encoding (continued) decscription rxd[3:0] rxer rxdv error during data reception 0x0 - 0xf 1 1 18.3.2.2 transmit interface the transmit clock, txck , is a continuous clock that provides a timing reference for the transmit data transfer. txck is sourced by the phy and should be 25% of the nominal transmit data rate. for 100base-t, txck should be 25 mhz; for 10base-t, txck should be 2.5 mhz. data is transmitted from the phy using 4 data signals, txd[3:0] , which are driven synchronously from the mac. txd0 is the lsb and txd3 is the msb. data from the mac is valid when the transmission enable signal, txen , is asserted. txen is asserted with the first nibble of the preamble and stays asserted through the last nibble to be transmitted. txen is negated prior to the first txck following the final nibble of the frame. if the mac detects an error in the frame, the txer input is asserted for at least one clock period. table 18-5. transmit signal encoding decscription txd[3:0] txer txen normal inter-frame 0x0 - 0xf 0 0 reserved 0x0 - 0xf 1 0 normal data transmission 0x0 - 0xf 0 1 transmit error propagation 0x0 - 0xf 1 1 18.3.2.3 control signals the mii control signals consist of two subsets of signals: serial management interface (smi) which is used to access the external phy registers signals that provide information concerning the status of the phy station management a simple serial interface is used for controlling the phy and gathering status from the phy. the station management interface consists of signals that transport the management information across the mii, a frame format and a protocol specification for exchanging management frames, and a register set that can be read and written using these frames. the serial signals consist of the management data clock ( mdc ) signal and the management data input/output ( mdio ) signal. the mdc signal is a period clock which provides the timing reference for the transfer occurring on the mdio signal. the clock divider for the mdc signal is set in the ethernet mac managment divider (macmdv) register. the maximum frequency of the mdc signal is 2.5 mhz. software can select one of up to 32 phys and one of up to 32 registers within any phy and send control data or receive status information. only one register in one phy can be accessed at any given time. phy accesses are configured as follows: 1. program the clock divider for the mdc signal in the macmdv register. 2. if the system has multiple phys, program the address of the phy in the ethernet mac address (macmadd) register. phys can be numbered 0 to 31. 929 july 03, 2014 texas instruments-production data stellaris lm3s9gn5 microcontroller 3. if data is to be written to the phy, store the data in the ethernet mac management transmit data (macmtxd) register. 4. in the ethernet mac management control (macmctl) register, program the address identifier for the specific phy register, 0 to 31. also, configure the write bit appropriately for the transaction whether it is a read or a write and set the start bit in the macmctl register. 5. if data was read from the phy, read the data from the ethernet mac management receive data (macmrxd) register. the station management frame format is different from the regular ethernet frame format as shown in figure 18-4. figure 18-4. management frame format the seven fields of the frame are transmitted from left to right. the bits within the frame are transmitted from least to most significant bit. preamble (pre) at the beginning of each transaction, the mac sends 32 contiguous logic one bits on mdio with 32 corresponding cycles of the mdc clock signal. the preamble is sent at the beginning of every transmission. start (st) start of frame is indicated by 01b. operation code (op) the operation code defines the transaction type. this field is 10b for read and 01b for write. phy address (phyad) the phy address is transmitted msb first. mii register address (regad) the mii register address is transmitted msb first. turnaround (ta) the turnaround time is 2 bit time spacing between the regad field and the data field of a management frame to avoid contention during a read transaction. for a read transaction, both the mac and phy remain in a high-impedance state for the first bit time. during the second bit time, the phy drives mdio low. during a write transaction, the mac drives mdio high for the first bit time and low for the second bit time. data (data) the data field is 16 bits and is transmitted and received msb first. july 03, 2014 930 texas instruments-production data ethernet controller 3 5 ( 6 7 3 + < $ ' ' $ 7 $ , ' / ( e l w v e l w v e l w v e l w v 2 3 e l w v 5 ( * $ ' e l w v 7 $ e l w v idle (idle) between frames, the mdio signal is in a high-impedance state. all three-state drivers must be disabled and a pull-up resistor should be attached to the mdio signal. phy status signals the carrier sense ( crs ) signal is asserted by the external phy when either the transmit or receive interface is not idle. the phy negates the signal when both the transmit and receive interfaces are idle. crs is not synchronous to either txck or rxck . if a collision is detected, the crs signal remains asserted throughout the duration of the collision condition. this signal is not used in full duplex mode. the collision ( col ) signal is asserted by the phy when a collision is detected on either the transmit or receive interface and remains asserted while the collision condition persists. col is not synchronous to either txck or rxck . this signal is not used in full duplex mode. the phyint signal can be asserted by the phy layer to indicate to the mac layer that one of the phy interrupt sources is active. the phyint signal must be asserted for at least 2 system clock periods in order to be recognized as asserted by the microcontroller, at which time the phyint bit in the macris register is set. the phyint signal is not part of the ieee 802.3 standard, and its implementation is optional. 18.3.3 interrupts the ethernet mac can generate an interrupt for one or more of the following conditions: a frame has been received into an empty rx fifo a frame transmission error has occurred a frame has been transmitted successfully a frame has been received with inadequate room in the rx fifo (overrun) a frame has been received with one or more error conditions (for example, fcs failed) an mii management transaction between the mac and phy layers has completed the external phy has signalled an interrupt 18.3.4 dma operation the ethernet peripheral provides request signals to the dma controller and has a dedicated channel for transmit and one for receive. the request is a single type for both channels. burst requests are not supported. the rx channel request is asserted when a packet is received while the tx channel request is asserted when the transmit fifo becomes empty. no special configuration is needed to enable the ethernet peripheral for use with the dma controller. because the size of a received packet is not known until the header is examined, it is best to set up the initial dma transfer to copy the first 4 words including the packet length plus the ethernet header from the rx fifo when the rx request occurs. the dma causes an interrupt when this transfer is complete. upon entering the interrupt handler, the packet length in the fifo and the ethernet header are in a buffer and can be examined. once the packet length is known, then another dma transfer can be set up to transfer the remaining received packet payload from the fifo into 931 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller a buffer. this transfer should be initiated by software. another interrupt occurs when this transfer is done. even though the tx channel generates a tx empty request, the recommended way to handle dma transfers for transmitting packets is to set up the transfer from the buffer containing the packet to the transmit fifo, and then to initiate the transfer with a software request. an interrupt occurs when this transfer is complete. for both channels, the "auto-request" transfer mode should be used. see micro direct memory access (dma) on page 344 for more details about programming the dma controller. 18.4 initialization and configuration the following sections describe the software configuration required to set up the ethernet mac. 18.4.1 software configuration to use the ethernet mac, it must be enabled by setting the emac0 bit in the rcgc2 register (see page 282). in addition, the clock to the appropriate gpio module must be enabled via the rcgc2 register in the system control module. see page 282. to find out which gpio port to enable, refer to table 24-4 on page 1239. configure the pmcn fields in the gpiopctl register to assign the ethernet signals to the appropriate pins. see page 447 and table 24-5 on page 1248. the following steps can then be used to configure the ethernet mac for basic operation. 1. program the macdiv register to obtain a 2.5 mhz clock (or less) on the mii. assuming a 20-mhz system clock, the macdiv value should be 0x03 or greater. 2. the external phy should be initialized; steps may vary depending upon the phy used. 3. program the macia0 and macia1 register for address filtering. 4. program the mactctl register for auto crc generation, padding, and full-duplex operation using a value of 0x16. 5. program the macrctl register to flush the receive fifo and reject frames with bad fcs using a value of 0x18. 6. enable both the transmitter and receive by setting the lsb in both the mactctl and macrctl registers. 7. to transmit a frame, write the frame into the tx fifo using the ethernet mac data (macdata) register. then set the newtx bit in the ethernet mac transmission request (mactr) register to initiate the transmit process. when the newtx bit has been cleared, the tx fifo is available for the next transmit frame. 8. to receive a frame, wait for the npr field in the ethernet mac number of packets (macnp) register to be non-zero. then begin reading the frame from the rx fifo by using the macdata register. to ensure that the entire packet is received, either use the driverlib ethernetpacketget() api or compare the number of bytes received to the length field from the frame to determine when the packet has been completely read. 18.5 register map table 18-6 on page 933 lists the ethernet mac registers. the mac register addresses given are relative to the ethernet base address of 0x4004.8000. note that the ethernet mac clock must be july 03, 2014 932 texas instruments-production data ethernet controller enabled before the registers can be programmed (see page 282). there must be a delay of 3 system clocks after the ethernet module clock is enabled before any ethernet module registers are accessed. the ieee 802.3 standard specifies a register set for controlling and gathering status from the phy layer. the registers are collectively known as the mii management registers and are detailed in section 22.2.4 of the ieee 802.3 specification . the ethernet mac management control (macmctl) register is used to access mii management registers on the external phy device. the format of registers 0 to 15 are defined by the ieee specification and are common to all phy layer implementations. the only variance allowed is for features that may or may not be supported by a specific phy implementation. registers 16 to 31 are vendor-specific registers, used to support features that are specific to a vendor's phy implementation. vendor-specific registers not listed are reserved. table 18-6. ethernet register map see page description reset type name offset 934 ethernet mac raw interrupt status/acknowledge 0x0000.0000 r/w1c macris/maciack 0x000 937 ethernet mac interrupt mask 0x0000.007f r/w macim 0x004 939 ethernet mac receive control 0x0000.0008 r/w macrctl 0x008 941 ethernet mac transmit control 0x0000.0000 r/w mactctl 0x00c 943 ethernet mac data 0x0000.0000 r/w macdata 0x010 945 ethernet mac individual address 0 0x0000.0000 r/w macia0 0x014 946 ethernet mac individual address 1 0x0000.0000 r/w macia1 0x018 947 ethernet mac threshold 0x0000.003f r/w macthr 0x01c 949 ethernet mac management control 0x0000.0000 r/w macmctl 0x020 950 ethernet mac management divider 0x0000.0080 r/w macmdv 0x024 951 ethernet mac management address 0x0000.0000 ro macmadd 0x028 952 ethernet mac management transmit data 0x0000.0000 r/w macmtxd 0x02c 953 ethernet mac management receive data 0x0000.0000 r/w macmrxd 0x030 954 ethernet mac number of packets 0x0000.0000 ro macnp 0x034 955 ethernet mac transmission request 0x0000.0000 r/w mactr 0x038 956 ethernet mac timer support 0x0000.0000 r/w macts 0x03c 18.6 ethernet mac register descriptions the remainder of this section lists and describes the ethernet mac registers, in numerical order by address offset. 933 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 1: ethernet mac raw interrupt status/acknowledge (macris/maciack), offset 0x000 the macris/maciack register is the interrupt status and acknowledge register. on a read, this register gives the current status value of the corresponding interrupt prior to masking. on a write, setting any bit clears the corresponding interrupt status bit. ethernet mac raw interrupt status/acknowledge (macris/maciack) base 0x4004.8000 offset 0x000 type r/w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rxint txer txemp fov rxer mdint phyint reserved r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:7 phy interrupt description value an enabled interrupt in the phy layer has occurred. refer the phy register descriptions to determine the specific phy event that triggered this interrupt. 1 no interrupt. 0 this bit is cleared by writing a 1 to it. 0 r/w1c phyint 6 mii transaction complete description value a transaction (read or write) on the mii interface has completed successfully. 1 no interrupt. 0 this bit is cleared by writing a 1 to it. 0 r/w1c mdint 5 july 03, 2014 934 texas instruments-production data ethernet controller description reset type name bit/field receive error description value an error was encountered on the receiver. the possible errors that can cause this interrupt bit to be set are: 1 a receive error occurs during the reception of a frame (100 mbps only). the frame is not an integer number of bytes (dribble bits) due to an alignment error. the crc of the frame does not pass the fcs check. the length/type field is inconsistent with the frame data size when interpreted as a length field. no interrupt. 0 this bit is cleared by writing a 1 to it. 0 r/w1c rxer 4 fifo overrun description value an overrun was encountered on the receive fifo. 1 no interrupt. 0 this bit is cleared by writing a 1 to it. 0 r/w1c fov 3 transmit fifo empty description value the packet was transmitted and that the tx fifo is empty. 1 no interrupt. 0 this bit is cleared by writing a 1 to it. 0 r/w1c txemp 2 transmit error description value an error was encountered on the transmitter. the possible errors that can cause this interrupt bit to be set are: 1 the data length field stored in the tx fifo exceeds 2032 decimal (buffer length - 16 bytes of header data). the frame is not sent when this error occurs. the retransmission attempts during the backoff process have exceeded the maximum limit of 16 decimal. no interrupt. 0 writing a 1 to this bit clears it and resets the tx fifo write pointer. 0 r/w1c txer 1 935 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field packet received description value at least one packet has been received and is stored in the receiver fifo. 1 no interrupt. 0 this bit is cleared by writing a 1 to it. 0 r/w1c rxint 0 july 03, 2014 936 texas instruments-production data ethernet controller register 2: ethernet mac interrupt mask (macim), offset 0x004 this register allows software to enable/disable ethernet mac interrupts. clearing a bit disables the interrupt, while setting the bit enables it. ethernet mac interrupt mask (macim) base 0x4004.8000 offset 0x004 type r/w, reset 0x0000.007f 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rxintm txerm txempm fovm rxerm mdintm phyintm reserved r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro type 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:7 mask phy interrupt description value an interrupt is sent to the interrupt controller when the phyint bit in the macris/maciack register is set. 1 the phyint interrupt is suppressed and not sent to the interrupt controller. 0 1 r/w phyintm 6 mask mii transaction complete description value an interrupt is sent to the interrupt controller when the mdint bit in the macris/maciack register is set. 1 the mdint interrupt is suppressed and not sent to the interrupt controller. 0 1 r/w mdintm 5 mask receive error description value an interrupt is sent to the interrupt controller when the rxer bit in the macris/maciack register is set. 1 the rxer interrupt is suppressed and not sent to the interrupt controller. 0 1 r/w rxerm 4 937 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field mask fifo overrun description value an interrupt is sent to the interrupt controller when the fov bit in the macris/maciack register is set. 1 the fov interrupt is suppressed and not sent to the interrupt controller. 0 1 r/w fovm 3 mask transmit fifo empty description value an interrupt is sent to the interrupt controller when the txemp bit in the macris/maciack register is set. 1 the txemp interrupt is suppressed and not sent to the interrupt controller. 0 1 r/w txempm 2 mask transmit error description value an interrupt is sent to the interrupt controller when the txer bit in the macris/maciack register is set. 1 the txer interrupt is suppressed and not sent to the interrupt controller. 0 1 r/w txerm 1 mask packet received description value an interrupt is sent to the interrupt controller when the rxint bit in the macris/maciack register is set. 1 the rxint interrupt is suppressed and not sent to the interrupt controller. 0 1 r/w rxintm 0 july 03, 2014 938 texas instruments-production data ethernet controller register 3: ethernet mac receive control (macrctl), offset 0x008 this register configures the receiver and controls the types of frames that are received. it is important to note that when the receiver is enabled, all valid frames with a broadcast address of ff-ff-ff-ff-ff-ff in the destination address field are received and stored in the rx fifo, even if the amul bit is not set. ethernet mac receive control (macrctl) base 0x4004.8000 offset 0x008 type r/w, reset 0x0000.0008 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rxen amul prms badcrc rstfifo reserved r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:5 clear receive fifo description value clear the receive fifo. the receive fifo should be cleared when software initialization is performed. 1 no effect. 0 this bit is automatically cleared when read. the receiver should be disabled ( rxen = 0), before a reset is initiated (rstfifo = 1). this sequence flushes and resets the rx fifo. 0 r/w rstfifo 4 enable reject bad crc description value enables the rejection of frames with an incorrectly calculated crc. if a bad crc is encountered, the rxer bit in the macris register is set and the receiver fifo is reset. 1 disables the rejection of frames with an incorrectly calculated crc. 0 1 r/w badcrc 3 enable promiscuous mode description value enables promiscuous mode, which accepts all valid frames, regardless of the specified destination address. 1 disables promiscuous mode, accepting only frames with the programmed destination address. 0 0 r/w prms 2 939 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field enable multicast frames description value enables the reception of multicast frames. 1 disables the reception of multicast frames. 0 0 r/w amul 1 enable receiver description value enables the ethernet receiver. 1 disables the receiver. all frames are ignored. 0 0 r/w rxen 0 july 03, 2014 940 texas instruments-production data ethernet controller register 4: ethernet mac transmit control (mactctl), offset 0x00c this register configures the transmitter and controls the frames that are transmitted. ethernet mac transmit control (mactctl) base 0x4004.8000 offset 0x00c type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 txen paden crc reserved duplex reserved r/w r/w r/w ro r/w ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:5 enable duplex mode description value enables duplex mode, allowing simultaneous transmission and reception. 1 disables duplex mode. 0 0 r/w duplex 4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 3 enable crc generation description value enables the automatic generation of the crc and its placement at the end of the packet. 1 the frames placed in the tx fifo are sent exactly as they are written into the fifo. 0 note that this bit should generally be set. 0 r/w crc 2 enable packet padding description value enables the automatic padding of packets that do not meet the minimum frame size. 1 disables automatic padding. 0 note that this bit should generally be set. 0 r/w paden 1 941 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field enable transmitter description value enables the transmitter. 1 disables the transmitter. 0 0 r/w txen 0 july 03, 2014 942 texas instruments-production data ethernet controller register 5: ethernet mac data (macdata), offset 0x010 important: this register is read-sensitive. see the register description for details. this register enables software to access the tx and rx fifos. reads from this register return the data stored in the rx fifo from the location indicated by the read pointer. the read pointer is then auto incremented to the next rx fifo location. reading from the rx fifo when a frame has not been received or is in the process of being received returns indeterminate data and does not increment the read pointer. writes to this register store the data in the tx fifo at the location indicated by the write pointer. the write pointer is then auto incremented to the next tx fifo location. writing more data into the tx fifo than indicated in the length field results in the data being lost. writing less data into the tx fifo than indicated in the length field results in indeterminate data being appended to the end of the frame to achieve the indicated length. attempting to write the next frame into the tx fifo before transmission of the first has completed results in the data being lost. bytes may not be randomly accessed in either the rx or tx fifos. data must be read from the rx fifo sequentially and stored in a buffer for further processing. once a read has been performed, the data in the fifo cannot be re-read. data must be written to the tx fifo sequentially. if an error is made in placing the frame into the tx fifo, the write pointer can be reset to the start of the tx fifo by writing the txer bit of the maciack register and then the data re-written. reads ethernet mac data (macdata) base 0x4004.8000 offset 0x010 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rxdata ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rxdata ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field receive fifo data the rxdata bits represent the next word of data stored in the rx fifo. 0x0000.0000 ro rxdata 31:0 943 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller writes ethernet mac data (macdata) base 0x4004.8000 offset 0x010 type wo, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 txdata wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 txdata wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field transmit fifo data the txdata bits represent the next word of data to place in the tx fifo for transmission. 0x0000.0000 wo txdata 31:0 july 03, 2014 944 texas instruments-production data ethernet controller register 6: ethernet mac individual address 0 (macia0), offset 0x014 this register enables software to program the first four bytes of the hardware mac address of the network interface card (nic). the last two bytes are in macia1 . the 6-byte individual address is compared against the incoming destination address fields to determine whether the frame should be received. ethernet mac individual address 0 (macia0) base 0x4004.8000 offset 0x014 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 macoct3 macoct4 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 macoct1 macoct2 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field mac address octet 4 the macoct4 bits represent the fourth octet of the mac address used to uniquely identify the ethernet mac. 0x00 r/w macoct4 31:24 mac address octet 3 the macoct3 bits represent the third octet of the mac address used to uniquely identify the ethernet mac. 0x00 r/w macoct3 23:16 mac address octet 2 the macoct2 bits represent the second octet of the mac address used to uniquely identify the ethernet mac. 0x00 r/w macoct2 15:8 mac address octet 1 the macoct1 bits represent the first octet of the mac address used to uniquely identify the ethernet mac. 0x00 r/w macoct1 7:0 945 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 7: ethernet mac individual address 1 (macia1), offset 0x018 this register enables software to program the last two bytes of the hardware mac address of the network interface card (nic). the first four bytes are in macia0 . the 6-byte iar is compared against the incoming destination address fields to determine whether the frame should be received. ethernet mac individual address 1 (macia1) base 0x4004.8000 offset 0x018 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 macoct5 macoct6 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 mac address octet 6 the macoct6 bits represent the sixth octet of the mac address used to uniquely identify each ethernet mac. 0x00 r/w macoct6 15:8 mac address octet 5 the macoct5 bits represent the fifth octet of the mac address used to uniquely identify the ethernet mac. 0x00 r/w macoct5 7:0 july 03, 2014 946 texas instruments-production data ethernet controller register 8: ethernet mac threshold (macthr), offset 0x01c in order to increase the transmission rate, it is possible to program the ethernet mac to begin transmission of the next frame prior to the completion of the transmission of the current frame. caution C extreme care must be used when implementing this function. software must be able to guarantee that the complete frame is able to be stored in the transmission fifo prior to the completion of the transmission frame. this register enables software to set the threshold level at which the transmission of the frame begins. if the thresh bits are set to 0x3f, which is the reset value, the early transmission feature is disabled, and transmission does not start until the newtx bit is set in the mactr register. writing the thresh field to any value besides 0x3f enables the early transmission feature. once the byte count of data in the tx fifo reaches the value derived from the thresh bits as shown below, transmission of the frame begins. when the thresh field is clear, transmission of the frame begins after 4 bytes (a single write) are stored in the tx fifo. each increment of the thresh bit field waits for an additional 32 bytes of data (eight writes) to be stored in the tx fifo. therefore, a value of 0x01 causes the transmitter to wait for 36 bytes of data to be written while a value of 0x02 makes the wait equal to 68 bytes of written data. in general, early transmission starts when: number of bytes 4 (( thresh x 8) + 1) reaching the threshold level has the same effect as setting the newtx bit in the mactr register. transmission of the frame begins, and then the number of bytes indicated by the data length field is transmitted. because underrun checking is not performed, if any event, such as an interrupt, delays the filling of the fifo, the tail pointer may reach and pass the write pointer in the tx fifo. in this event, indeterminate values are transmitted rather than the end of the frame. therefore, sufficient bus bandwidth for writing to the tx fifo must be guaranteed by the software. if a frame smaller than the threshold level must be sent, the newtx bit in the mactr register must be set with an explicit write, which initiates the transmission of the frame even though the threshold limit has not been reached. if the threshold level is set too small, it is possible for the transmitter to underrun. if this occurs, the transmit frame is aborted, and a transmit error occurs. note that in this case, the txer bit in the is not set, meaning that the cpu receives no indication that a transmit error happened. ethernet mac threshold (macthr) base 0x4004.8000 offset 0x01c type r/w, reset 0x0000.003f 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 thresh reserved r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro type 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:6 947 july 03, 2014 texas instruments-production data stellaris lm3s9gn5 microcontroller description reset type name bit/field threshold value the thresh bits represent the early transmit threshold. once the amount of data in the tx fifo exceeds the value represented by the above equation, transmission of the packet begins. 0x3f r/w thresh 5:0 july 03, 2014 948 texas instruments-production data ethernet controller register 9: ethernet mac management control (macmctl), offset 0x020 this register enables software to control the transfer of data to and from the mii management registers in the ethernet phy layer. see the documentation for the external phy device for the mii register address and functional description. in order to initiate a read transaction from the mii management registers, the write bit must be cleared during the same cycle that the start bit is set. in order to initiate a write transaction to the mii management registers, the write bit must be set during the same cycle that the start bit is set. ethernet mac management control (macmctl) base 0x4004.8000 offset 0x020 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 start write reserved regadr reserved r/w r/w ro r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 mii register address the regadr bit field represents the mii management register address for the next mii management interface transaction. refer to the external phy documentation for the phy register offsets. 0x0 r/w regadr 7:3 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 2 mii register transaction type description value the next operation of the next mii management interface is a write transaction. 1 the next operation of the next mii management interface is a read transaction. 0 0 r/w write 1 mii register transaction enable description value the mii register located at regadr is read ( write =0) or written (write=1). 1 no effect. 0 0 r/w start 0 949 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 10: ethernet mac management divider (macmdv), offset 0x024 this register enables software to set the clock divider for the management data clock (mdc). this clock is used to synchronize read and write transactions on the smi. the frequency of the mdc clock can be calculated from the following formula: the clock divider must be written with a value that ensures that the mdc clock does not exceed a frequency of 2.5 mhz. ethernet mac management divider (macmdv) base 0x4004.8000 offset 0x024 type r/w, reset 0x0000.0080 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 div reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 clock divider the div bits are used to set the clock divider for the mdc clock signal used to transmit data between the mac and phy layers over the serial management interface. 0x80 r/w div 7:0 july 03, 2014 950 texas instruments-production data ethernet controller () 1 macmdv 2 + = ipclk mdc f f register 11: ethernet mac management address (macmadd), offset 0x028 this register enables software to choose the address of the phy for the next mii management register transaction. ethernet mac management address (macmadd) base 0x4004.8000 offset 0x028 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 phyadr reserved r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:5 phy address the phyadr bits represent the address of the phy that is accessed in the next smi management transaction. 0x0 r/w phyadr 4:0 951 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 12: ethernet mac management transmit data (macmtxd), offset 0x02c this register holds the next value to be written to the mii management registers. ethernet mac management transmit data (macmtxd) base 0x4004.8000 offset 0x02c type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mdtx r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 mii register transmit data the mdtx bits represent the data to be written in the next mii management transaction. 0x0000 r/w mdtx 15:0 july 03, 2014 952 texas instruments-production data ethernet controller register 13: ethernet mac management receive data (macmrxd), offset 0x030 this register holds the last value read from the mii management registers. ethernet mac management receive data (macmrxd) base 0x4004.8000 offset 0x030 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mdrx r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 mii register receive data the mdrx bits represent the data that was read in the previous mii management transaction. 0x0000 r/w mdrx 15:0 953 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 14: ethernet mac number of packets (macnp), offset 0x034 this register holds the number of frames that are currently in the rx fifo. when npr is 0, there are no frames in the rx fifo, and the rxint bit is clear. when npr is any other value, at least one frame is in the rx fifo, and the rxint bit in the macris register is set. note: the fcs bytes are not included in the npr value. as a result, the npr value could be zero before the fcs bytes are read from the fifo. in addition, a new packet could be received before the npr value reaches zero. to ensure that the entire packet is received, either use the driverlib ethernetpacketget() api or compare the number of bytes received to the length field from the frame to determine when the packet has been completely read. ethernet mac number of packets (macnp) base 0x4004.8000 offset 0x034 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 npr reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:6 number of packets in receive fifo the npr bits represent the number of packets stored in the rx fifo. while the npr field is greater than 0, the rxint interrupt in the macris register is set. 0x00 ro npr 5:0 july 03, 2014 954 texas instruments-production data ethernet controller register 15: ethernet mac transmission request (mactr), offset 0x038 this register enables software to initiate the transmission of the frame currently located in the tx fifo. once the frame has been transmitted from the tx fifo or a transmission error has been encountered, the newtx bit is automatically cleared. ethernet mac transmission request (mactr) base 0x4004.8000 offset 0x038 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 newtx reserved r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:1 new transmission description value initiates an ethernet transmission once the packet has been placed in the tx fifo. 1 the transmission has completed. 0 if early transmission is being used (see the macthr register), this bit does not need to be set. 0 r/w newtx 0 955 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 16: ethernet mac timer support (macts), offset 0x03c this register enables software to enable highly precise timing on the transmission and reception of frames. to enable this function, set the tsen bit. ethernet mac timer support (macts) base 0x4004.8000 offset 0x03c type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tsen reserved r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:1 time stamp enable description value the tx and rx interrupts are routed to the ccp inputs of general-purpose timer 3. 1 no effect. 0 0 r/w tsen 0 july 03, 2014 956 texas instruments-production data ethernet controller 19 universal serial bus (usb) controller the stellaris ? usb controller operates as a full-speed or low-speed function controller during point-to-point communications with usb host, device, or otg functions. the controller complies with the usb 2.0 standard, which includes suspend and resume signaling. 32 endpoints including two hard-wired for control transfers (one endpoint for in and one endpoint for out) plus 30 endpoints defined by firmware along with a dynamic sizable fifo support multiple packet queueing. dma access to the fifo allows minimal interference from system software. software-controlled connect and disconnect allows flexibility during usb device start-up. the controller complies with otg standard's session request protocol (srp) and host negotiation protocol (hnp). the stellaris usb module has the following features: complies with usb-if certification standards usb 2.0 full-speed (12 mbps) and low-speed (1.5 mbps) operation with integrated phy 4 transfer types: control, interrupt, bulk, and isochronous 32 endpoints C 1 dedicated control in endpoint and 1 dedicated control out endpoint C 15 configurable in endpoints and 15 configurable out endpoints 4 kb dedicated endpoint memory: one endpoint may be defined for double-buffered 1023-byte isochronous packet size vbus droop and valid id detection and interrupt efficient transfers using micro direct memory access controller (dma) C separate channels for transmit and receive for up to three in endpoints and three out endpoints C channel requests asserted when fifo contains required amount of data 957 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 19.1 block diagram figure 19-1. usb module block diagram 19.2 signal description the following table lists the external signals of the usb controller and describes the function of each. some usb controller signals are alternate functions for some gpio signals and default to be gpio signals at reset. the column in the table below titled "pin mux/pin assignment" lists the possible gpio pin placements for these usb signals. the afsel bit in the gpio alternate function select (gpioafsel) register (page 429) should be set to choose the usb function. the number in parentheses is the encoding that must be programmed into the pmcn field in the gpio port control (gpiopctl) register (page 447) to assign the usb signal to the specified gpio port pin. the usb0vbus and usb0id signals are configured by clearing the appropriate den bit in the gpio digital enable (gpioden) register. for more information on configuring gpios, see general-purpose input/outputs (gpios) on page 405. the remaining signals (with the word "fixed" in the pin mux/pin assignment column) have a fixed pin assignment and function. note: when used in otg mode, usb0vbus and usb0id do not require any configuration as they are dedicated pins for the usb controller and directly connect to the usb connector's vbus and id signals. if the usb controller is used as either a dedicated host or device, the devmodotg and devmod bits in the usb general-purpose control and status (usbgpcs) register can be used to connect the usb0vbus and usb0id inputs to fixed levels internally, freeing the pb0 and pb1 pins for gpio use. for proper self-powered device operation, the vbus value must still be monitored to assure that if the host removes vbus, the self-powered device disables the d+/d- pull-up resistors. this function can be accomplished by connecting a standard gpio to vbus. the termination resistors for the usb phy have been added internally, and thus there is no need for external resistors. for a device, there is a 1.5 kohm pull-up on the d+ and for a host there are 15 kohm pull-downs on both d+ and d-. july 03, 2014 958 texas instruments-production data universal serial bus (usb) controller 3 d f n h w ( q f r g h ' h f r g h ( q g s r l q w & r q w u r o ( 3 & r q w u r o 7 u d q v p l w 5 h f h l y h & r p e l q h ( q g s r l q w v + r v w 7 u d q v d f w l r q 6 f k h g x o h u 3 d f n h w ( q f r g h 3 d f n h w ' h f r g h & 5 & * h q & k h f n ) , ) 2 5 $ 0 & r q w u r o o h u & \ f o h & r q w u r o 5 [ % x i i 5 [ % x i i 7 [ % x i i 7 [ % x i i ' 0 $ 5 h t x h v w v & 3 8 , q w h u i d f h , q w h u u x s w & r q w u r o ( 3 5 h j ' h f r g h u & r p p r q 5 h j v & \ f o h & r q w u r o ) , ) 2 ' h f r g h u , q w h u u x s w v $ + % e x v 6 o d y h p r g h 8 7 0 6 \ q f k u r q l ] d w l r q ' d w d 6 \ q f + 1 3 6 5 3 7 l p h u v 8 6 % ) 6 / 6 3 + < 8 6 % 3 + < 8 6 % ' d w d / l q h v ' d q g ' table 19-1. usb signals (100lqfp) description buffer type a pin type pin mux / pin assignment pin number pin name bidirectional differential data pin (d- per usb specification) for usb0. analog i/o fixed 70 usb0dm bidirectional differential data pin (d+ per usb specification) for usb0. analog i/o fixed 71 usb0dp optionally used in host mode to control an external power source to supply power to the usb bus. ttl o pg0 (7) pc5 (6) pa6 (8) pb2 (8) ph3 (4) 19 24 34 72 83 usb0epen this signal senses the state of the usb id signal. the usb phy enables an integrated pull-up, and an external element (usb connector) indicates the initial state of the usb controller (pulled down is the a side of the cable and pulled up is the b side). analog i pb0 66 usb0id optionally used in host mode by an external power source to indicate an error state by that power source. ttl i pc7 (6) pc6 (7) pa7 (8) pb3 (8) pe0 (9) ph4 (4) pj1 (9) 22 23 35 65 74 76 87 usb0pflt 9.1-k resistor (1% precision) used internally for usb analog circuitry. analog o fixed 73 usb0rbias this signal is used during the session request protocol. this signal allows the usb phy to both sense the voltage level of vbus, and pull up vbus momentarily during vbus pulsing. analog i/o pb1 67 usb0vbus a. the ttl designation indicates the pin has ttl-compatible voltage levels. table 19-2. usb signals (108bga) description buffer type a pin type pin mux / pin assignment pin number pin name bidirectional differential data pin (d- per usb specification) for usb0. analog i/o fixed c11 usb0dm bidirectional differential data pin (d+ per usb specification) for usb0. analog i/o fixed c12 usb0dp optionally used in host mode to control an external power source to supply power to the usb bus. ttl o pg0 (7) pc5 (6) pa6 (8) pb2 (8) ph3 (4) k1 m1 l6 a11 d10 usb0epen this signal senses the state of the usb id signal. the usb phy enables an integrated pull-up, and an external element (usb connector) indicates the initial state of the usb controller (pulled down is the a side of the cable and pulled up is the b side). analog i pb0 e12 usb0id 959 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 19-2. usb signals (108bga) (continued) description buffer type a pin type pin mux / pin assignment pin number pin name optionally used in host mode by an external power source to indicate an error state by that power source. ttl i pc7 (6) pc6 (7) pa7 (8) pb3 (8) pe0 (9) ph4 (4) pj1 (9) l2 m2 m6 e11 b11 b10 b6 usb0pflt 9.1-k resistor (1% precision) used internally for usb analog circuitry. analog o fixed b12 usb0rbias this signal is used during the session request protocol. this signal allows the usb phy to both sense the voltage level of vbus, and pull up vbus momentarily during vbus pulsing. analog i/o pb1 d12 usb0vbus a. the ttl designation indicates the pin has ttl-compatible voltage levels. 19.3 functional description note: a 9.1-k resistor should be connected between the usb0rbias and ground. the 9.1-k resistor should have a 1% tolerance and should be located in close proximity to the usb0rbias pin. power dissipation in the resistor is low, so a chip resistor of any geometry may be used. the stellaris usb controller provides full otg negotiation by supporting both the session request protocol (srp) and the host negotiation protocol (hnp). the session request protocol allows devices on the b side of a cable to request the a side device turn on vbus. the host negotiation protocol is used after the initial session request protocol has powered the bus and provides a method to determine which end of the cable will act as the host controller. when the device is connected to non-otg peripherals or devices, the controller can detect which cable end was used and provides a register to indicate if the controller should act as the host or the device controller. this indication and the mode of operation are handled automatically by the usb controller. this auto-detection allows the system to use a single a/b connector instead of having both a and b connectors in the system and supports full otg negotiations with other otg devices. in addition, the usb controller provides support for connecting to non-otg peripherals or host controllers. the usb controller can be configured to act as either a dedicated host or device, in which case, the usb0vbus and usb0id signals can be used as gpios. however, when the usb controller is acting as a self-powered device, a gpio input or analog comparator input must be connected to vbus and configured to generate an interrupt when the vbus level drops. this interrupt is used to disable the pullup resistor on the usb0dp signal. note: when the usb module is in operation, mosc must be the clock source, either with or without using the pll, and the system clock must be at least 30 mhz. 19.3.1 operation as a device this section describes the stellaris usb controller's actions when it is being used as a usb device. before the usb controller's operating mode is changed from device to host or host to device, software must reset the usb controller by setting the usb0 bit in the software reset control 2 (srcr2) register (see page 296). in endpoints, out endpoints, entry into and exit from suspend mode, and recognition of start of frame (sof) are all described. july 03, 2014 960 texas instruments-production data universal serial bus (usb) controller when in device mode, in transactions are controlled by an endpoints transmit interface and use the transmit endpoint registers for the given endpoint. out transactions are handled with an endpoint's receive interface and use the receive endpoint registers for the given endpoint. when configuring the size of the fifos for endpoints, take into account the maximum packet size for an endpoint. bulk. bulk endpoints should be the size of the maximum packet (up to 64 bytes) or twice the maximum packet size if double buffering is used (described further in the following section). interrupt. interrupt endpoints should be the size of the maximum packet (up to 64 bytes) or twice the maximum packet size if double buffering is used. isochronous. isochronous endpoints are more flexible and can be up to 1023 bytes. control. it is also possible to specify a separate control endpoint for a usb device. however, in most cases the usb device should use the dedicated control endpoint on the usb controllers endpoint 0. 19.3.1.1 endpoints when operating as a device, the usb controller provides two dedicated control endpoints (in and out) and 30 configurable endpoints (15 in and 15 out) that can be used for communications with a host controller. the endpoint number and direction associated with an endpoint is directly related to its register designation. for example, when the host is transmitting to endpoint 1, all configuration and data is in the endpoint 1 transmit register interface. endpoint 0 is a dedicated control endpoint used for all control transactions to endpoint 0 during enumeration or when any other control requests are made to endpoint 0. endpoint 0 uses the first 64 bytes of the usb controller's fifo ram as a shared memory for both in and out transactions. the remaining 30 endpoints can be configured as control, bulk, interrupt, or isochronous endpoints. they should be treated as 15 configurable in and 15 configurable out endpoints. the endpoint pairs are not required to have the same type for their in and out endpoint configuration. for example, the out portion of an endpoint pair could be a bulk endpoint, while the in portion of that endpoint pair could be an interrupt endpoint. the address and size of the fifos attached to each endpoint can be modified to fit the application's needs. 19.3.1.2 in transactions as a device when operating as a usb device, data for in transactions is handled through the fifos attached to the transmit endpoints. the sizes of the fifos for the 15 configurable in endpoints are determined by the usb transmit fifo start address (usbtxfifoadd) register. the maximum size of a data packet that may be placed in a transmit endpoints fifo for transmission is programmable and is determined by the value written to the usb maximum transmit data endpoint n (usbtxmaxpn) register for that endpoint. the endpoints fifo can also be configured to use double-packet or single-packet buffering. when double-packet buffering is enabled, two data packets can be buffered in the fifo, which also requires that the fifo is at least two packets in size. when double-packet buffering is disabled, only one packet can be buffered, even if the packet size is less than half the fifo size. note: the maximum packet size set for any endpoint must not exceed the fifo size. the usbtxmaxpn register should not be written to while data is in the fifo as unexpected results may occur. 961 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller single-packet buffering if the size of the transmit endpoint's fifo is less than twice the maximum packet size for this endpoint (as set in the usb transmit dynamic fifo sizing (usbtxfifosz) register), only one packet can be buffered in the fifo and single-packet buffering is required. when each packet is completely loaded into the transmit fifo, the txrdy bit in the usb transmit control and status endpoint n low (usbtxcsrln) register must be set. if the autoset bit in the usb transmit control and status endpoint n high (usbtxcsrhn) register is set, the txrdy bit is automatically set when a maximum-sized packet is loaded into the fifo. for packet sizes less than the maximum, the txrdy bit must be set manually. when the txrdy bit is set, either manually or automatically, the packet is ready to be sent. when the packet has been successfully sent, both txrdy and fifone are cleared, and the appropriate transmit endpoint interrupt signaled. at this point, the next packet can be loaded into the fifo. double-packet buffering if the size of the transmit endpoint's fifo is at least twice the maximum packet size for this endpoint, two packets can be buffered in the fifo and double-packet buffering is allowed. as each packet is loaded into the transmit fifo, the txrdy bit in the usbtxcsrln register must be set. if the autoset bit in the usbtxcsrhn register is set, the txrdy bit is automatically set when a maximum-sized packet is loaded into the fifo. for packet sizes less than the maximum, txrdy must be set manually. when the txrdy bit is set, either manually or automatically, the packet is ready to be sent. after the first packet is loaded, txrdy is immediately cleared and an interrupt is generated. a second packet can now be loaded into the transmit fifo and txrdy set again (either manually or automatically if the packet is the maximum size). at this point, both packets are ready to be sent. after each packet has been successfully sent, txrdy is automatically cleared and the appropriate transmit endpoint interrupt signaled to indicate that another packet can now be loaded into the transmit fifo. the state of the fifone bit in the usbtxcsrln register at this point indicates how many packets may be loaded. if the fifone bit is set, then another packet is in the fifo and only one more packet can be loaded. if the fifone bit is clear, then no packets are in the fifo and two more packets can be loaded. note: double-packet buffering is disabled if an endpoints corresponding epn bit is set in the usb transmit double packet buffer disable (usbtxdpktbufdis) register. this bit is set by default, so it must be cleared to enable double-packet buffering. 19.3.1.3 out transactions as a device when in device mode, out transactions are handled through the usb controller receive fifos. the sizes of the receive fifos for the 15 configurable out endpoints are determined by the usb receive fifo start address (usbrxfifoadd) register. the maximum amount of data received by an endpoint in any packet is determined by the value written to the usb maximum receive data endpoint n (usbrxmaxpn) register for that endpoint. when double-packet buffering is enabled, two data packets can be buffered in the fifo. when double-packet buffering is disabled, only one packet can be buffered even if the packet is less than half the fifo size. note: in all cases, the maximum packet size must not exceed the fifo size. single-packet buffering if the size of the receive endpoint fifo is less than twice the maximum packet size for an endpoint, only one data packet can be buffered in the fifo and single-packet buffering is required. when a packet is received and placed in the receive fifo, the rxrdy and full bits in the usb receive control and status endpoint n low (usbrxcsrln) register are set and the appropriate receive endpoint is signaled, indicating that a packet can now be unloaded from the fifo. after the packet july 03, 2014 962 texas instruments-production data universal serial bus (usb) controller has been unloaded, the rxrdy bit must be cleared in order to allow further packets to be received. this action also generates the acknowledge signaling to the host controller. if the autocl bit in the usb receive control and status endpoint n high (usbrxcsrhn) register is set and a maximum-sized packet is unloaded from the fifo, the rxrdy and full bits are cleared automatically. for packet sizes less than the maximum, rxrdy must be cleared manually. double-packet buffering if the size of the receive endpoint fifo is at least twice the maximum packet size for the endpoint, two data packets can be buffered and double-packet buffering can be used. when the first packet is received and loaded into the receive fifo, the rxrdy bit in the usbrxcsrln register is set and the appropriate receive endpoint interrupt is signaled to indicate that a packet can now be unloaded from the fifo. note: the full bit in usbrxcsrln is not set when the first packet is received. it is only set if a second packet is received and loaded into the receive fifo. after each packet has been unloaded, the rxrdy bit must be cleared to allow further packets to be received. if the autocl bit in the usbrxcsrhn register is set and a maximum-sized packet is unloaded from the fifo, the rxrdy bit is cleared automatically. for packet sizes less than the maximum, rxrdy must be cleared manually. if the full bit is set when rxrdy is cleared, the usb controller first clears the full bit, then sets rxrdy again to indicate that there is another packet waiting in the fifo to be unloaded. note: double-packet buffering is disabled if an endpoints corresponding epn bit is set in the usb receive double packet buffer disable (usbrxdpktbufdis) register. this bit is set by default, so it must be cleared to enable double-packet buffering. 19.3.1.4 scheduling the device has no control over the scheduling of transactions as scheduling is determined by the host controller. the stellaris usb controller can set up a transaction at any time. the usb controller waits for the request from the host controller and generates an interrupt when the transaction is complete or if it was terminated due to some error. if the host controller makes a request and the device controller is not ready, the usb controller sends a busy response (nak) to all requests until it is ready. 19.3.1.5 additional actions the usb controller responds automatically to certain conditions on the usb bus or actions by the host controller such as when the usb controller automatically stalls a control transfer or unexpected zero length out data packets. stalled control transfer the usb controller automatically issues a stall handshake to a control transfer under the following conditions: 1. the host sends more data during an out data phase of a control transfer than was specified in the device request during the setup phase. this condition is detected by the usb controller when the host sends an out token (instead of an in token) after the last out packet has been unloaded and the dataend bit in the usb control and status endpoint 0 low (usbcsrl0) register has been set. 2. the host requests more data during an in data phase of a control transfer than was specified in the device request during the setup phase. this condition is detected by the usb controller 963 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller when the host sends an in token (instead of an out token) after the cpu has cleared txrdy and set dataend in response to the ack issued by the host to what should have been the last packet. 3. the host sends more than usbrxmaxpn bytes of data with an out data token. 4. the host sends more than a zero length data packet for the out status phase. zero length out data packets a zero-length out data packet is used to indicate the end of a control transfer. in normal operation, such packets should only be received after the entire length of the device request has been transferred. however, if the host sends a zero-length out data packet before the entire length of device request has been transferred, it is signaling the premature end of the transfer. in this case, the usb controller automatically flushes any in token ready for the data phase from the fifo and sets the dataend bit in the usbcsrl0 register. setting the device address when a host is attempting to enumerate the usb device, it requests that the device change its address from zero to some other value. the address is changed by writing the value that the host requested to the usb device functional address (usbfaddr) register. however, care should be taken when writing to usbfaddr to avoid changing the address before the transaction is complete. this register should only be set after the set_address command is complete. like all control transactions, the transaction is only complete after the device has left the status phase. in the case of a set_address command, the transaction is completed by responding to the in request from the host with a zero-byte packet. once the device has responded to the in request, the usbfaddr register should be programmed to the new value as soon as possible to avoid missing any new commands sent to the new address. note: if the usbfaddr register is set to the new value as soon as the device receives the out transaction with the set_address command in the packet, it changes the address during the control transfer. in this case, the device does not receive the in request that allows the usb transaction to exit the status phase of the control transfer because it is sent to the old address. as a result, the host does not get a response to the in request, and the host fails to enumerate the device. 19.3.1.6 device mode suspend when no activity has occurred on the usb bus for 3 ms, the usb controller automatically enters suspend mode. if the suspend interrupt has been enabled in the usb interrupt enable (usbie) register, an interrupt is generated at this time. when in suspend mode, the phy also goes into suspend mode. when resume signaling is detected, the usb controller exits suspend mode and takes the phy out of suspend. if the resume interrupt is enabled, an interrupt is generated. the usb controller can also be forced to exit suspend mode by setting the resume bit in the usb power (usbpower) register. when this bit is set, the usb controller exits suspend mode and drives resume signaling onto the bus. the resume bit must be cleared after 10 ms (a maximum of 15 ms) to end resume signaling. to meet usb power requirements, the controller can be put into deep sleep mode which keeps the controller in a static state. july 03, 2014 964 texas instruments-production data universal serial bus (usb) controller 19.3.1.7 start-of-frame when the usb controller is operating in device mode, it receives a start-of-frame (sof) packet from the host once every millisecond. when the sof packet is received, the 11-bit frame number contained in the packet is written into the usb frame value (usbframe) register, and an sof interrupt is also signaled and can be handled by the application. once the usb controller has started to receive sof packets, it expects one every millisecond. if no sof packet is received after 1.00358 ms, the packet is assumed to have been lost, and the usbframe register is not updated. the usb controller continues and resynchronizes these pulses to the received sof packets when these packets are successfully received again. 19.3.1.8 usb reset when the usb controller is in device mode and a reset condition is detected on the usb bus, the usb controller automatically performs the following actions: clears the usbfaddr register. clears the usb endpoint index (usbepidx) register. flushes all endpoint fifos. clears all control/status registers. enables all endpoint interrupts. generates a reset interrupt. when the application software driving the usb controller receives a reset interrupt, any open pipes are closed and the usb controller waits for bus enumeration to begin. 19.3.1.9 connect/disconnect the usb controller connection to the usb bus is handled by software. the usb phy can be switched between normal mode and non-driving mode by setting or clearing the softconn bit of the usbpower register. when the softconn bit is set, the phy is placed in its normal mode, and the usb0dp/ usb0dm lines of the usb bus are enabled. at the same time, the usb controller is placed into a state, in which it does not respond to any usb signaling except a usb reset. when the softconn bit is cleared, the phy is put into non-driving mode, usb0dp and usb0dm are tristated, and the usb controller appears to other devices on the usb bus as if it has been disconnected. the non-driving mode is the default so the usb controller appears disconnected until the softconn bit has been set. the application software can then choose when to set the phy into its normal mode. systems with a lengthy initialization procedure may use this to ensure that initialization is complete, and the system is ready to perform enumeration before connecting to the usb bus. once the softconn bit has been set, the usb controller can be disconnected by clearing this bit. note: the usb controller does not generate an interrupt when the device is connected to the host. however, an interrupt is generated when the host terminates a session. 19.3.2 operation as a host when the stellaris usb controller is operating in host mode, it can either be used for point-to-point communications with another usb device or, when attached to a hub, for communication with multiple devices. before the usb controller's operating mode is changed from host to device or 965 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller device to host, software must reset the usb controller by setting the usb0 bit in the software reset control 2 (srcr2) register (see page 296). full-speed and low-speed usb devices are supported, both for point-to-point communication and for operation through a hub. the usb controller automatically carries out the necessary transaction translation needed to allow a low-speed or full-speed device to be used with a usb 2.0 hub. control, bulk, isochronous, and interrupt transactions are supported. this section describes the usb controller's actions when it is being used as a usb host. configuration of in endpoints, out endpoints, entry into and exit from suspend mode, and reset are all described. when in host mode, in transactions are controlled by an endpoints receive interface. all in transactions use the receive endpoint registers and all out endpoints use the transmit endpoint registers for a given endpoint. as in device mode, the fifos for endpoints should take into account the maximum packet size for an endpoint. bulk. bulk endpoints should be the size of the maximum packet (up to 64 bytes) or twice the maximum packet size if double buffering is used (described further in the following section). interrupt. interrupt endpoints should be the size of the maximum packet (up to 64 bytes) or twice the maximum packet size if double buffering is used. isochronous. isochronous endpoints are more flexible and can be up to 1023 bytes. control. it is also possible to specify a separate control endpoint to communicate with a device. however, in most cases the usb controller should use the dedicated control endpoint to communicate with a devices endpoint 0. 19.3.2.1 endpoints the endpoint registers are used to control the usb endpoint interfaces which communicate with device(s) that are connected. the endpoints consist of a dedicated control in endpoint, a dedicated control out endpoint, 15 configurable out endpoints, and 15 configurable in endpoints. the dedicated control interface can only be used for control transactions to endpoint 0 of devices. these control transactions are used during enumeration or other control functions that communicate using endpoint 0 of devices. this control endpoint shares the first 64 bytes of the usb controllers fifo ram for in and out transactions. the remaining in and out interfaces can be configured to communicate with control, bulk, interrupt, or isochronous device endpoints. these usb interfaces can be used to simultaneously schedule as many as 15 independent out and 15 independent in transactions to any endpoints on any device. the in and out controls are paired in three sets of registers. however, they can be configured to communicate with different types of endpoints and different endpoints on devices. for example, the first pair of endpoint controls can be split so that the out portion is communicating with a devices bulk out endpoint 1, while the in portion is communicating with a devices interrupt in endpoint 2. before accessing any device, whether for point-to-point communications or for communications via a hub, the relevant usb receive functional address endpoint n (usbrxfuncaddrn) or usb transmit functional address endpoint n (usbtxfuncaddrn) registers must be set for each receive or transmit endpoint to record the address of the device being accessed. the usb controller also supports connections to devices through a usb hub by providing a register that specifies the hub address and port of each usb transfer. the fifo address and size are customizable and can be specified for each usb in and out transfer. customization includes allowing one fifo per transaction, sharing a fifo across transactions, and allowing for double-buffered fifos. july 03, 2014 966 texas instruments-production data universal serial bus (usb) controller 19.3.2.2 in transactions as a host in transactions are handled in a similar manner to the way in which out transactions are handled when the usb controller is in device mode except that the transaction first must be initiated by setting the reqpkt bit in the usbcsrl0 register, indicating to the transaction scheduler that there is an active transaction on this endpoint. the transaction scheduler then sends an in token to the target device. when the packet is received and placed in the receive fifo, the rxrdy bit in the usbcsrl0 register is set, and the appropriate receive endpoint interrupt is signaled to indicate that a packet can now be unloaded from the fifo. when the packet has been unloaded, rxrdy must be cleared. the autocl bit in the usbrxcsrhn register can be used to have rxrdy automatically cleared when a maximum-sized packet has been unloaded from the fifo. the autorq bit in usbrxcsrhn causes the reqpkt bit to be automatically set when the rxrdy bit is cleared. the autocl and autorq bits can be used with dma accesses to perform complete bulk transfers without main processor intervention. when the rxrdy bit is cleared, the controller sends an acknowledge to the device. when there is a known number of packets to be transferred, the usb request packet count in block transfer endpoint n (usbrqpktcountn) register associated with the endpoint should be configured to the number of packets to be transferred. the usb controller decrements the value in the usbrqpktcountn register following each request. when the usbrqpktcountn value decrements to 0, the autorq bit is cleared to prevent any further transactions being attempted. for cases where the size of the transfer is unknown, usbrqpktcountn should be cleared. autorq then remains set until cleared by the reception of a short packet (that is, less than the maxload value in the usbrxmaxpn register) such as may occur at the end of a bulk transfer. if the device responds to a bulk or interrupt in token with a nak, the usb host controller keeps retrying the transaction until any nak limit that has been set has been reached. if the target device responds with a stall, however, the usb host controller does not retry the transaction but sets the stalled bit in the usbcsrl0 register. if the target device does not respond to the in token within the required time, or the packet contained a crc or bit-stuff error, the usb host controller retries the transaction. if after three attempts the target device has still not responded, the usb host controller clears the reqpkt bit and sets the error bit in the usbcsrl0 register. 19.3.2.3 out transactions as a host out transactions are handled in a similar manner to the way in which in transactions are handled when the usb controller is in device mode. the txrdy bit in the usbtxcsrln register must be set as each packet is loaded into the transmit fifo. again, setting the autoset bit in the usbtxcsrhn register automatically sets txrdy when a maximum-sized packet has been loaded into the fifo. furthermore, autoset can be used with the dma controller to perform complete bulk transfers without software intervention. if the target device responds to the out token with a nak, the usb host controller keeps retrying the transaction until the nak limit that has been set has been reached. however, if the target device responds with a stall, the usb controller does not retry the transaction but interrupts the main processor by setting the stalled bit in the usbtxcsrln register. if the target device does not respond to the out token within the required time, or the packet contained a crc or bit-stuff error, the usb host controller retries the transaction. if after three attempts the target device has still not responded, the usb controller flushes the fifo and sets the error bit in the usbtxcsrln register. 19.3.2.4 transaction scheduling scheduling of transactions is handled automatically by the usb host controller. the host controller allows configuration of the endpoint communication scheduling based on the type of endpoint transaction. interrupt transactions can be scheduled to occur in the range of every frame to every 967 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 255 frames in 1 frame increments. bulk endpoints do not allow scheduling parameters, but do allow for a nak timeout in the event an endpoint on a device is not responding. isochronous endpoints can be scheduled from every frame to every 2 16 frames, in powers of 2. the usb controller maintains a frame counter. if the target device is a full-speed device, the usb controller automatically sends an sof packet at the start of each frame and increments the frame counter. if the target device is a low-speed device, a k state is transmitted on the bus to act as a keep-alive to stop the low-speed device from going into suspend mode. after the sof packet has been transmitted, the usb host controller cycles through all the configured endpoints looking for active transactions. an active transaction is defined as a receive endpoint for which the reqpkt bit is set or a transmit endpoint for which the txrdy bit and/or the fifone bit is set. an isochronous or interrupt transaction is started if the transaction is found on the first scheduler cycle of a frame and if the interval counter for that endpoint has counted down to zero. as a result, only one interrupt or isochronous transaction occurs per endpoint every n frames, where n is the interval set via the usb host transmit interval endpoint n (usbtxintervaln) or usb host receive interval endpoint n (usbrxintervaln) register for that endpoint. an active bulk transaction starts immediately, provided sufficient time is left in the frame to complete the transaction before the next sof packet is due. if the transaction must be retried (for example, because a nak was received or the target device did not respond), then the transaction is not retried until the transaction scheduler has first checked all the other endpoints for active transactions. this process ensures that an endpoint that is sending a lot of naks does not block other transactions on the bus. the controller also allows the user to specify a limit to the length of time for naks to be received from a target device before the endpoint times out. 19.3.2.5 usb hubs the following setup requirements apply to the usb host controller only if it is used with a usb hub. when a full- or low-speed device is connected to the usb controller via a usb 2.0 hub, details of the hub address and the hub port also must be recorded in the corresponding usb receive hub address endpoint n (usbrxhubaddrn) and usb receive hub port endpoint n (usbrxhubportn) or the usb transmit hub address endpoint n (usbtxhubaddrn) and usb transmit hub port endpoint n (usbtxhubportn) registers. in addition, the speed at which the device operates (full or low) must be recorded in the usb type endpoint 0 (usbtype0) (endpoint 0), usb host configure transmit type endpoint n (usbtxtypen) , or usb host configure receive type endpoint n (usbrxtypen) registers for each endpoint that is accessed by the device. for hub communications, the settings in these registers record the current allocation of the endpoints to the attached usb devices. to maximize the number of devices supported, the usb host controller allows this allocation to be changed dynamically by simply updating the address and speed information recorded in these registers. any changes in the allocation of endpoints to device functions must be made following the completion of any on-going transactions on the endpoints affected. 19.3.2.6 babble the usb host controller does not start a transaction until the bus has been inactive for at least the minimum inter-packet delay. the controller also does not start a transaction unless it can be finished before the end of the frame. if the bus is still active at the end of a frame, then the usb host controller assumes that the target device to which it is connected has malfunctioned, and the usb controller suspends all transactions and generates a babble interrupt. july 03, 2014 968 texas instruments-production data universal serial bus (usb) controller 19.3.2.7 host suspend if the suspend bit in the usbpower register is set, the usb host controller completes the current transaction then stops the transaction scheduler and frame counter. no further transactions are started and no sof packets are generated. to exit suspend mode, set the resume bit and clear the suspend bit. while the resume bit is set, the usb host controller generates resume signaling on the bus. after 20 ms, the resume bit must be cleared, at which point the frame counter and transaction scheduler start. the host supports the detection of a remote wake-up. 19.3.2.8 usb reset if the reset bit in the usbpower register is set, the usb host controller generates usb reset signaling on the bus. the reset bit must be set for at least 20 ms to ensure correct resetting of the target device. after the cpu has cleared the bit, the usb host controller starts its frame counter and transaction scheduler. 19.3.2.9 connect/disconnect a session is started by setting the session bit in the usb device control (usbdevctl) register, enabling the usb controller to wait for a device to be connected. when a device is detected, a connect interrupt is generated. the speed of the device that has been connected can be determined by reading the usbdevctl register where the fsdev bit is set for a full-speed device, and the lsdev bit is set for a low-speed device. the usb controller must generate a reset to the device, and then the usb host controller can begin device enumeration. if the device is disconnected while a session is in progress, a disconnect interrupt is generated. 19.3.3 otg mode to conserve power, the usb on-the-go (otg) supplement allows vbus to only be powered up when required and to be turned off when the bus is not in use. vbus is always supplied by the a device on the bus. the usb otg controller determines whether it is the a device or the b device by sampling the id input from the phy. this signal is pulled low when an a-type plug is sensed (signifying that the usb otg controller should act as the a device) but taken high when a b-type plug is sensed (signifying that the usb controller is a b device). note that when switching between otg a and otg b, the usb controller retains all register contents. 19.3.3.1 starting a session when the usb otg controller is ready to start a session, the session bit must be set in the usbdevctl register. the usb otg controller then enables id pin sensing. the id input is either taken low if an a-type connection is detected or high if a b-type connection is detected. the dev bit in the usbdevctl register is also set to indicate whether the usb otg controller has adopted the role of the a device or the b device. the usb otg controller also provides an interrupt to indicate that id pin sensing has completed and the mode value in the usbdevctl register is valid. this interrupt is enabled in the usbidvim register, and the status is checked in the usbidvisc register. as soon as the usb controller has detected that it is on the a side of the cable, it must enable vbus power within 100ms or the usb controller reverts to device mode. if the usb otg controller is the a device, then the usb otg controller enters host mode (the a device is always the default host), turns on vbus, and waits for vbus to go above the vbus valid threshold, as indicated by the vbus bit in the usbdevctl register going to 0x3. the usb otg controller then waits for a peripheral to be connected. when a peripheral is detected, a connect interrupt is signaled and either the fsdev or lsdev bit in the usbdevctl register is set, depending whether a full-speed or a low-speed peripheral is detected. the usb controller then issues a reset 969 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller to the connected device. the session bit in the usbdevctl register can be cleared to end a session. the usb otg controller also automatically ends the session if babble is detected or if vbus drops below session valid. note: the usb otg controller may not remain in host mode when connected to high-current devices. some devices draw enough current to momentarily drop vbus below the vbus-valid level causing the controller to drop out of host mode. the only way to get back into host mode is to allow vbus to go below the session end level. in this situation, the device is causing vbus to drop repeatedly and pull vbus back low the next time vbus is enabled. in addition, the usb otg controller may not remain in host mode when a device is told that it can start using it's active configuration. at this point the device starts drawing more current and can also drop vbus below vbus valid. if the usb otg controller is the b device, then the usb otg controller requests a session using the session request protocol defined in the usb on-the-go supplement, that is, it first discharges vbus. then when vbus has gone below the session end threshold ( vbus bit in the usbdevctl register goes to 0x0) and the line state has been a single-ended zero for > 2 ms, the usb otg controller pulses the data line, then pulses vbus. at the end of the session, the session bit is cleared either by the usb otg controller or by the application software. the usb otg controller then causes the phy to switch out the pull-up resistor on d+, signaling the a device to end the session. 19.3.3.2 detecting activity when the other device of the otg setup wishes to start a session, it either raises vbus above the session valid threshold if it is the a device, or if it is the b device, it pulses the data line then pulses vbus. depending on which of these actions happens, the usb controller can determine whether it is the a device or the b device in the current setup and act accordingly. if vbus is raised above the session valid threshold, then the usb controller is the b device. the usb controller sets the session bit in the usbdevctl register. when reset signaling is detected on the bus, a reset interrupt is signaled, which is interpreted as the start of a session. the usb controller is in device mode as the b device is the default mode. at the end of the session, the a device turns off the power to vbus. when vbus drops below the session valid threshold, the usb controller detects this drop and clears the session bit to indicate that the session has ended, causing a disconnect interrupt to be signaled. if data line and vbus pulsing is detected, then the usb controller is the a device. the controller generates a session request interrupt to indicate that the b device is requesting a session. the session bit in the usbdevctl register must be set to start a session. 19.3.3.3 host negotiation when the usb controller is the a device, id is low, and the controller automatically enters host mode when a session starts. when the usb controller is the b device, id is high, and the controller automatically enters device mode when a session starts. however, software can request that the usb controller become the host by setting the hostreq bit in the usbdevctl register. this bit can be set either at the same time as requesting a session start by setting the session bit in the usbdevctl register or at any time after a session has started. when the usb controller next enters suspend mode and if the hostreq bit remains set, the controller enters host mode and begins host negotiation (as specified in the usb on-the-go supplement) by causing the phy to disconnect the pull-up resistor on the d+ line, causing the a device to switch to device mode and connect its own pull-up resistor. when the usb controller detects this, a connect interrupt is generated and the reset bit in the usbpower register is set to begin resetting the a device. the july 03, 2014 970 texas instruments-production data universal serial bus (usb) controller usb controller begins this reset sequence automatically to ensure that reset is started as required within 1 ms of the a device connecting its pull-up resistor. the main processor should wait at least 20 ms, then clear the reset bit and enumerate the a device. when the usb otg controller b device has finished using the bus, the usb controller goes into suspend mode by setting the suspend bit in the usbpower register. the a device detects this and either terminates the session or reverts to host mode. if the a device is usb otg controller, it generates a disconnect interrupt. 19.3.4 dma operation the usb peripheral provides an interface connected to the dma controller with separate channels for 3 transmit endpoints and 3 receive endpoints. software selects which endpoints to service with the dma channels using the usb dma select (usbdmasel) register. the dma operation of the usb is enabled through the usbtxcsrhn and usbrxcsrhn registers, for the tx and rx channels respectively. when dma operation is enabled, the usb asserts a dma request on the enabled receive or transmit channel when the associated fifo can transfer data. when either fifo can transfer data, the burst request for that channel is asserted. the dma channel must be configured to operate in basic mode, and the size of the dma transfer must be restricted to whole multiples of the size of the usb fifo. both read and write transfers of the usb fifos using dma must be configured in this manner. for example, if the usb endpoint is configured with a fifo size of 64 bytes, the dma channel can be used to transfer 64 bytes to or from the endpoint fifo. if the number of bytes to transfer is less than 64, then a programmed i/o method must be used to copy the data to or from the fifo. if the dmamod bit in the usbtxcsrhn / usbrxcsrhn register is clear, an interrupt is generated after every packet is transferred, but the dma continues transferring data. if the dmamod bit is set, an interrupt is generated only when the entire dma transfer is complete. the interrupt occurs on the usb interrupt vector. therefore, if interrupts are used for usb operation and the dma is enabled, the usb interrupt handler must be designed to handle the dma completion interrupt. care must be taken when using the dma to unload the receive fifo as data is read from the receive fifo in 4 byte chunks regardless of value of the maxload field in the usbrxcsrhn register. the rxrdy bit is cleared as follows. table 19-3. remainder (maxload/4) description value maxload = 64 bytes 0 maxload = 61 bytes 1 maxload = 62 bytes 2 maxload = 63 bytes 3 table 19-4. actual bytes read description value maxload 0 maxload+3 1 maxload+2 2 maxload+1 3 971 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 19-5. packet sizes that clear rxrdy description value maxload, maxload-1, maxload-2, maxload-3 0 maxload 1 maxload, maxload-1 2 maxload, maxload-1, maxload-2 3 to enable dma operation for the endpoint receive channel, the dmaen bit of the usbrxcsrhn register should be set. to enable dma operation for the endpoint transmit channel, the dmaen bit of the usbtxcsrhn register must be set. see micro direct memory access (dma) on page 344 for more details about programming the dma controller. 19.4 initialization and configuration to use the usb controller, the peripheral clock must be enabled via the rcgc2 register (see page 282). in addition, the clock to the appropriate gpio module must be enabled via the rcgc2 register in the system control module (see page 282). to find out which gpio port to enable, refer to table 24-4 on page 1239. configure the pmcn fields in the gpiopctl register to assign the usb signals to the appropriate pins (see page 447 and table 24-5 on page 1248). the initial configuration in all cases requires that the processor enable the usb controller and usb controllers physical layer interface (phy) before setting any registers. the next step is to enable the usb pll so that the correct clocking is provided to the phy. to ensure that voltage is not supplied to the bus incorrectly, the external power control signal, usb0epen , should be negated on start up by configuring the usb0epen and usb0pflt pins to be controlled by the usb controller and not exhibit their default gpio behavior. note: when used in otg mode, usb0vbus and usb0id do not require any configuration as they are dedicated pins for the usb controller and directly connect to the usb connector's vbus and id signals. if the usb controller is used as either a dedicated host or device, the devmodotg and devmod bits in the usb general-purpose control and status (usbgpcs) register can be used to connect the usb0vbus and usb0id inputs to fixed levels internally, freeing the pb0 and pb1 pins for gpio use. for proper self-powered device operation, the vbus value must still be monitored to assure that if the host removes vbus, the self-powered device disables the d+/d- pull-up resistors. this function can be accomplished by connecting a standard gpio to vbus. the termination resistors for the usb phy have been added internally, and thus there is no need for external resistors. for a device, there is a 1.5 kohm pull-up on the d+ and for a host there are 15 kohm pull-downs on both d+ and d-. 19.4.1 pin configuration when using the device controller portion of the usb controller in a system that also provides host functionality, the power to vbus must be disabled to allow the external host controller to supply power. usually, the usb0epen signal is used to control the external regulator and should be negated to avoid having two devices driving the usb0vbus power pin on the usb connector. when the usb controller is acting as a host, it is in control of two signals that are attached to an external voltage supply that provides power to vbus. the host controller uses the usb0epen signal to enable or disable power to the usb0vbus pin on the usb connector. an input pin, usb0pflt, provides feedback when there has been a power fault on vbus. the usb0pflt signal can be july 03, 2014 972 texas instruments-production data universal serial bus (usb) controller configured to either automatically negate the usb0epen signal to disable power, and/or it can generate an interrupt to the interrupt controller to allow software to handle the power fault condition. the polarity and actions related to both usb0epen and usb0pflt are fully configurable in the usb controller. the controller also provides interrupts on device insertion and removal to allow the host controller code to respond to these external events. 19.4.2 endpoint configuration to start communication in host or device mode, the endpoint registers must first be configured. in host mode, this configuration establishes a connection between an endpoint register and an endpoint on a device. in device mode, an endpoint must be configured before enumerating to the host controller. in both cases, the endpoint 0 configuration is limited because it is a fixed-function, fixed-fifo-size endpoint. in device and host modes, the endpoint requires little setup but does require a software-based state machine to progress through the setup, data, and status phases of a standard control transaction. in device mode, the configuration of the remaining endpoints is done once before enumerating and then only changed if an alternate configuration is selected by the host controller. in host mode, the endpoints must be configured to operate as control, bulk, interrupt or isochronous mode. once the type of endpoint is configured, a fifo area must be assigned to each endpoint. in the case of bulk, control and interrupt endpoints, each has a maximum of 64 bytes per transaction. isochronous endpoints can have packets with up to 1023 bytes per packet. in either mode, the maximum packet size for the given endpoint must be set prior to sending or receiving data. configuring each endpoints fifo involves reserving a portion of the overall usb fifo ram to each endpoint. the total fifo ram available is 4 kbytes with the first 64 bytes reserved for endpoint 0. the endpoints fifo must be at least as large as the maximum packet size. the fifo can also be configured as a double-buffered fifo so that interrupts occur at the end of each packet and allow filling the other half of the fifo. if operating as a device, the usb device controller's soft connect must be enabled when the device is ready to start communications, indicating to the host controller that the device is ready to start the enumeration process. if operating as a host controller, the device soft connect must be disabled and power must be provided to vbus via the usb0epen signal. 19.5 register map table 19-6 on page 973 lists the registers. all addresses given are relative to the usb base address of 0x4005.0000. note that the usb controller clock must be enabled before the registers can be programmed (see page 282). there must be a delay of 3 system clocks after the usb module clock is enabled before any usb module registers are accessed. table 19-6. universal serial bus (usb) controller register map see page description reset type name offset 985 usb device functional address 0x00 r/w usbfaddr 0x000 986 usb power 0x20 r/w usbpower 0x001 989 usb transmit interrupt status 0x0000 ro usbtxis 0x002 991 usb receive interrupt status 0x0000 ro usbrxis 0x004 993 usb transmit interrupt enable 0xffff r/w usbtxie 0x006 973 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 19-6. universal serial bus (usb) controller register map (continued) see page description reset type name offset 995 usb receive interrupt enable 0xfffe r/w usbrxie 0x008 997 usb general interrupt status 0x00 ro usbis 0x00a 1000 usb interrupt enable 0x06 r/w usbie 0x00b 1003 usb frame value 0x0000 ro usbframe 0x00c 1004 usb endpoint index 0x00 r/w usbepidx 0x00e 1005 usb test mode 0x00 r/w usbtest 0x00f 1007 usb fifo endpoint 0 0x0000.0000 r/w usbfifo0 0x020 1007 usb fifo endpoint 1 0x0000.0000 r/w usbfifo1 0x024 1007 usb fifo endpoint 2 0x0000.0000 r/w usbfifo2 0x028 1007 usb fifo endpoint 3 0x0000.0000 r/w usbfifo3 0x02c 1007 usb fifo endpoint 4 0x0000.0000 r/w usbfifo4 0x030 1007 usb fifo endpoint 5 0x0000.0000 r/w usbfifo5 0x034 1007 usb fifo endpoint 6 0x0000.0000 r/w usbfifo6 0x038 1007 usb fifo endpoint 7 0x0000.0000 r/w usbfifo7 0x03c 1007 usb fifo endpoint 8 0x0000.0000 r/w usbfifo8 0x040 1007 usb fifo endpoint 9 0x0000.0000 r/w usbfifo9 0x044 1007 usb fifo endpoint 10 0x0000.0000 r/w usbfifo10 0x048 1007 usb fifo endpoint 11 0x0000.0000 r/w usbfifo11 0x04c 1007 usb fifo endpoint 12 0x0000.0000 r/w usbfifo12 0x050 1007 usb fifo endpoint 13 0x0000.0000 r/w usbfifo13 0x054 1007 usb fifo endpoint 14 0x0000.0000 r/w usbfifo14 0x058 1007 usb fifo endpoint 15 0x0000.0000 r/w usbfifo15 0x05c 1009 usb device control 0x80 r/w usbdevctl 0x060 1011 usb transmit dynamic fifo sizing 0x00 r/w usbtxfifosz 0x062 1011 usb receive dynamic fifo sizing 0x00 r/w usbrxfifosz 0x063 1012 usb transmit fifo start address 0x0000 r/w usbtxfifoadd 0x064 1012 usb receive fifo start address 0x0000 r/w usbrxfifoadd 0x066 1013 usb connect timing 0x5c r/w usbcontim 0x07a 1014 usb otg vbus pulse timing 0x3c r/w usbvplen 0x07b 1015 usb full-speed last transaction to end of frame timing 0x77 r/w usbfseof 0x07d 1016 usb low-speed last transaction to end of frame timing 0x72 r/w usblseof 0x07e july 03, 2014 974 texas instruments-production data universal serial bus (usb) controller table 19-6. universal serial bus (usb) controller register map (continued) see page description reset type name offset 1017 usb transmit functional address endpoint 0 0x00 r/w usbtxfuncaddr0 0x080 1019 usb transmit hub address endpoint 0 0x00 r/w usbtxhubaddr0 0x082 1021 usb transmit hub port endpoint 0 0x00 r/w usbtxhubport0 0x083 1017 usb transmit functional address endpoint 1 0x00 r/w usbtxfuncaddr1 0x088 1019 usb transmit hub address endpoint 1 0x00 r/w usbtxhubaddr1 0x08a 1021 usb transmit hub port endpoint 1 0x00 r/w usbtxhubport1 0x08b 1023 usb receive functional address endpoint 1 0x00 r/w usbrxfuncaddr1 0x08c 1025 usb receive hub address endpoint 1 0x00 r/w usbrxhubaddr1 0x08e 1027 usb receive hub port endpoint 1 0x00 r/w usbrxhubport1 0x08f 1017 usb transmit functional address endpoint 2 0x00 r/w usbtxfuncaddr2 0x090 1019 usb transmit hub address endpoint 2 0x00 r/w usbtxhubaddr2 0x092 1021 usb transmit hub port endpoint 2 0x00 r/w usbtxhubport2 0x093 1023 usb receive functional address endpoint 2 0x00 r/w usbrxfuncaddr2 0x094 1025 usb receive hub address endpoint 2 0x00 r/w usbrxhubaddr2 0x096 1027 usb receive hub port endpoint 2 0x00 r/w usbrxhubport2 0x097 1017 usb transmit functional address endpoint 3 0x00 r/w usbtxfuncaddr3 0x098 1019 usb transmit hub address endpoint 3 0x00 r/w usbtxhubaddr3 0x09a 1021 usb transmit hub port endpoint 3 0x00 r/w usbtxhubport3 0x09b 1023 usb receive functional address endpoint 3 0x00 r/w usbrxfuncaddr3 0x09c 1025 usb receive hub address endpoint 3 0x00 r/w usbrxhubaddr3 0x09e 1027 usb receive hub port endpoint 3 0x00 r/w usbrxhubport3 0x09f 1017 usb transmit functional address endpoint 4 0x00 r/w usbtxfuncaddr4 0x0a0 1019 usb transmit hub address endpoint 4 0x00 r/w usbtxhubaddr4 0x0a2 1021 usb transmit hub port endpoint 4 0x00 r/w usbtxhubport4 0x0a3 1023 usb receive functional address endpoint 4 0x00 r/w usbrxfuncaddr4 0x0a4 1025 usb receive hub address endpoint 4 0x00 r/w usbrxhubaddr4 0x0a6 1027 usb receive hub port endpoint 4 0x00 r/w usbrxhubport4 0x0a7 1017 usb transmit functional address endpoint 5 0x00 r/w usbtxfuncaddr5 0x0a8 1019 usb transmit hub address endpoint 5 0x00 r/w usbtxhubaddr5 0x0aa 1021 usb transmit hub port endpoint 5 0x00 r/w usbtxhubport5 0x0ab 1023 usb receive functional address endpoint 5 0x00 r/w usbrxfuncaddr5 0x0ac 1025 usb receive hub address endpoint 5 0x00 r/w usbrxhubaddr5 0x0ae 975 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 19-6. universal serial bus (usb) controller register map (continued) see page description reset type name offset 1027 usb receive hub port endpoint 5 0x00 r/w usbrxhubport5 0x0af 1017 usb transmit functional address endpoint 6 0x00 r/w usbtxfuncaddr6 0x0b0 1019 usb transmit hub address endpoint 6 0x00 r/w usbtxhubaddr6 0x0b2 1021 usb transmit hub port endpoint 6 0x00 r/w usbtxhubport6 0x0b3 1023 usb receive functional address endpoint 6 0x00 r/w usbrxfuncaddr6 0x0b4 1025 usb receive hub address endpoint 6 0x00 r/w usbrxhubaddr6 0x0b6 1027 usb receive hub port endpoint 6 0x00 r/w usbrxhubport6 0x0b7 1017 usb transmit functional address endpoint 7 0x00 r/w usbtxfuncaddr7 0x0b8 1019 usb transmit hub address endpoint 7 0x00 r/w usbtxhubaddr7 0x0ba 1021 usb transmit hub port endpoint 7 0x00 r/w usbtxhubport7 0x0bb 1023 usb receive functional address endpoint 7 0x00 r/w usbrxfuncaddr7 0x0bc 1025 usb receive hub address endpoint 7 0x00 r/w usbrxhubaddr7 0x0be 1027 usb receive hub port endpoint 7 0x00 r/w usbrxhubport7 0x0bf 1017 usb transmit functional address endpoint 8 0x00 r/w usbtxfuncaddr8 0x0c0 1019 usb transmit hub address endpoint 8 0x00 r/w usbtxhubaddr8 0x0c2 1021 usb transmit hub port endpoint 8 0x00 r/w usbtxhubport8 0x0c3 1023 usb receive functional address endpoint 8 0x00 r/w usbrxfuncaddr8 0x0c4 1025 usb receive hub address endpoint 8 0x00 r/w usbrxhubaddr8 0x0c6 1027 usb receive hub port endpoint 8 0x00 r/w usbrxhubport8 0x0c7 1017 usb transmit functional address endpoint 9 0x00 r/w usbtxfuncaddr9 0x0c8 1019 usb transmit hub address endpoint 9 0x00 r/w usbtxhubaddr9 0x0ca 1021 usb transmit hub port endpoint 9 0x00 r/w usbtxhubport9 0x0cb 1023 usb receive functional address endpoint 9 0x00 r/w usbrxfuncaddr9 0x0cc 1025 usb receive hub address endpoint 9 0x00 r/w usbrxhubaddr9 0x0ce 1027 usb receive hub port endpoint 9 0x00 r/w usbrxhubport9 0x0cf 1017 usb transmit functional address endpoint 10 0x00 r/w usbtxfuncaddr10 0x0d0 1019 usb transmit hub address endpoint 10 0x00 r/w usbtxhubaddr10 0x0d2 1021 usb transmit hub port endpoint 10 0x00 r/w usbtxhubport10 0x0d3 1023 usb receive functional address endpoint 10 0x00 r/w usbrxfuncaddr10 0x0d4 1025 usb receive hub address endpoint 10 0x00 r/w usbrxhubaddr10 0x0d6 1027 usb receive hub port endpoint 10 0x00 r/w usbrxhubport10 0x0d7 1017 usb transmit functional address endpoint 11 0x00 r/w usbtxfuncaddr11 0x0d8 july 03, 2014 976 texas instruments-production data universal serial bus (usb) controller table 19-6. universal serial bus (usb) controller register map (continued) see page description reset type name offset 1019 usb transmit hub address endpoint 11 0x00 r/w usbtxhubaddr11 0x0da 1021 usb transmit hub port endpoint 11 0x00 r/w usbtxhubport11 0x0db 1023 usb receive functional address endpoint 11 0x00 r/w usbrxfuncaddr11 0x0dc 1025 usb receive hub address endpoint 11 0x00 r/w usbrxhubaddr11 0x0de 1027 usb receive hub port endpoint 11 0x00 r/w usbrxhubport11 0x0df 1017 usb transmit functional address endpoint 12 0x00 r/w usbtxfuncaddr12 0x0e0 1019 usb transmit hub address endpoint 12 0x00 r/w usbtxhubaddr12 0x0e2 1021 usb transmit hub port endpoint 12 0x00 r/w usbtxhubport12 0x0e3 1023 usb receive functional address endpoint 12 0x00 r/w usbrxfuncaddr12 0x0e4 1025 usb receive hub address endpoint 12 0x00 r/w usbrxhubaddr12 0x0e6 1027 usb receive hub port endpoint 12 0x00 r/w usbrxhubport12 0x0e7 1017 usb transmit functional address endpoint 13 0x00 r/w usbtxfuncaddr13 0x0e8 1019 usb transmit hub address endpoint 13 0x00 r/w usbtxhubaddr13 0x0ea 1021 usb transmit hub port endpoint 13 0x00 r/w usbtxhubport13 0x0eb 1023 usb receive functional address endpoint 13 0x00 r/w usbrxfuncaddr13 0x0ec 1025 usb receive hub address endpoint 13 0x00 r/w usbrxhubaddr13 0x0ee 1027 usb receive hub port endpoint 13 0x00 r/w usbrxhubport13 0x0ef 1017 usb transmit functional address endpoint 14 0x00 r/w usbtxfuncaddr14 0x0f0 1019 usb transmit hub address endpoint 14 0x00 r/w usbtxhubaddr14 0x0f2 1021 usb transmit hub port endpoint 14 0x00 r/w usbtxhubport14 0x0f3 1023 usb receive functional address endpoint 14 0x00 r/w usbrxfuncaddr14 0x0f4 1025 usb receive hub address endpoint 14 0x00 r/w usbrxhubaddr14 0x0f6 1027 usb receive hub port endpoint 14 0x00 r/w usbrxhubport14 0x0f7 1017 usb transmit functional address endpoint 15 0x00 r/w usbtxfuncaddr15 0x0f8 1019 usb transmit hub address endpoint 15 0x00 r/w usbtxhubaddr15 0x0fa 1021 usb transmit hub port endpoint 15 0x00 r/w usbtxhubport15 0x0fb 1023 usb receive functional address endpoint 15 0x00 r/w usbrxfuncaddr15 0x0fc 1025 usb receive hub address endpoint 15 0x00 r/w usbrxhubaddr15 0x0fe 1027 usb receive hub port endpoint 15 0x00 r/w usbrxhubport15 0x0ff 1031 usb control and status endpoint 0 low 0x00 w1c usbcsrl0 0x102 1035 usb control and status endpoint 0 high 0x00 w1c usbcsrh0 0x103 1037 usb receive byte count endpoint 0 0x00 ro usbcount0 0x108 977 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 19-6. universal serial bus (usb) controller register map (continued) see page description reset type name offset 1038 usb type endpoint 0 0x00 r/w usbtype0 0x10a 1039 usb nak limit 0x00 r/w usbnaklmt 0x10b 1029 usb maximum transmit data endpoint 1 0x0000 r/w usbtxmaxp1 0x110 1040 usb transmit control and status endpoint 1 low 0x00 r/w usbtxcsrl1 0x112 1045 usb transmit control and status endpoint 1 high 0x00 r/w usbtxcsrh1 0x113 1049 usb maximum receive data endpoint 1 0x0000 r/w usbrxmaxp1 0x114 1051 usb receive control and status endpoint 1 low 0x00 r/w usbrxcsrl1 0x116 1056 usb receive control and status endpoint 1 high 0x00 r/w usbrxcsrh1 0x117 1061 usb receive byte count endpoint 1 0x0000 ro usbrxcount1 0x118 1063 usb host transmit configure type endpoint 1 0x00 r/w usbtxtype1 0x11a 1065 usb host transmit interval endpoint 1 0x00 r/w usbtxinterval1 0x11b 1067 usb host configure receive type endpoint 1 0x00 r/w usbrxtype1 0x11c 1069 usb host receive polling interval endpoint 1 0x00 r/w usbrxinterval1 0x11d 1029 usb maximum transmit data endpoint 2 0x0000 r/w usbtxmaxp2 0x120 1040 usb transmit control and status endpoint 2 low 0x00 r/w usbtxcsrl2 0x122 1045 usb transmit control and status endpoint 2 high 0x00 r/w usbtxcsrh2 0x123 1049 usb maximum receive data endpoint 2 0x0000 r/w usbrxmaxp2 0x124 1051 usb receive control and status endpoint 2 low 0x00 r/w usbrxcsrl2 0x126 1056 usb receive control and status endpoint 2 high 0x00 r/w usbrxcsrh2 0x127 1061 usb receive byte count endpoint 2 0x0000 ro usbrxcount2 0x128 1063 usb host transmit configure type endpoint 2 0x00 r/w usbtxtype2 0x12a 1065 usb host transmit interval endpoint 2 0x00 r/w usbtxinterval2 0x12b 1067 usb host configure receive type endpoint 2 0x00 r/w usbrxtype2 0x12c 1069 usb host receive polling interval endpoint 2 0x00 r/w usbrxinterval2 0x12d 1029 usb maximum transmit data endpoint 3 0x0000 r/w usbtxmaxp3 0x130 1040 usb transmit control and status endpoint 3 low 0x00 r/w usbtxcsrl3 0x132 1045 usb transmit control and status endpoint 3 high 0x00 r/w usbtxcsrh3 0x133 1049 usb maximum receive data endpoint 3 0x0000 r/w usbrxmaxp3 0x134 1051 usb receive control and status endpoint 3 low 0x00 r/w usbrxcsrl3 0x136 1056 usb receive control and status endpoint 3 high 0x00 r/w usbrxcsrh3 0x137 1061 usb receive byte count endpoint 3 0x0000 ro usbrxcount3 0x138 1063 usb host transmit configure type endpoint 3 0x00 r/w usbtxtype3 0x13a july 03, 2014 978 texas instruments-production data universal serial bus (usb) controller table 19-6. universal serial bus (usb) controller register map (continued) see page description reset type name offset 1065 usb host transmit interval endpoint 3 0x00 r/w usbtxinterval3 0x13b 1067 usb host configure receive type endpoint 3 0x00 r/w usbrxtype3 0x13c 1069 usb host receive polling interval endpoint 3 0x00 r/w usbrxinterval3 0x13d 1029 usb maximum transmit data endpoint 4 0x0000 r/w usbtxmaxp4 0x140 1040 usb transmit control and status endpoint 4 low 0x00 r/w usbtxcsrl4 0x142 1045 usb transmit control and status endpoint 4 high 0x00 r/w usbtxcsrh4 0x143 1049 usb maximum receive data endpoint 4 0x0000 r/w usbrxmaxp4 0x144 1051 usb receive control and status endpoint 4 low 0x00 r/w usbrxcsrl4 0x146 1056 usb receive control and status endpoint 4 high 0x00 r/w usbrxcsrh4 0x147 1061 usb receive byte count endpoint 4 0x0000 ro usbrxcount4 0x148 1063 usb host transmit configure type endpoint 4 0x00 r/w usbtxtype4 0x14a 1065 usb host transmit interval endpoint 4 0x00 r/w usbtxinterval4 0x14b 1067 usb host configure receive type endpoint 4 0x00 r/w usbrxtype4 0x14c 1069 usb host receive polling interval endpoint 4 0x00 r/w usbrxinterval4 0x14d 1029 usb maximum transmit data endpoint 5 0x0000 r/w usbtxmaxp5 0x150 1040 usb transmit control and status endpoint 5 low 0x00 r/w usbtxcsrl5 0x152 1045 usb transmit control and status endpoint 5 high 0x00 r/w usbtxcsrh5 0x153 1049 usb maximum receive data endpoint 5 0x0000 r/w usbrxmaxp5 0x154 1051 usb receive control and status endpoint 5 low 0x00 r/w usbrxcsrl5 0x156 1056 usb receive control and status endpoint 5 high 0x00 r/w usbrxcsrh5 0x157 1061 usb receive byte count endpoint 5 0x0000 ro usbrxcount5 0x158 1063 usb host transmit configure type endpoint 5 0x00 r/w usbtxtype5 0x15a 1065 usb host transmit interval endpoint 5 0x00 r/w usbtxinterval5 0x15b 1067 usb host configure receive type endpoint 5 0x00 r/w usbrxtype5 0x15c 1069 usb host receive polling interval endpoint 5 0x00 r/w usbrxinterval5 0x15d 1029 usb maximum transmit data endpoint 6 0x0000 r/w usbtxmaxp6 0x160 1040 usb transmit control and status endpoint 6 low 0x00 r/w usbtxcsrl6 0x162 1045 usb transmit control and status endpoint 6 high 0x00 r/w usbtxcsrh6 0x163 1049 usb maximum receive data endpoint 6 0x0000 r/w usbrxmaxp6 0x164 1051 usb receive control and status endpoint 6 low 0x00 r/w usbrxcsrl6 0x166 1056 usb receive control and status endpoint 6 high 0x00 r/w usbrxcsrh6 0x167 1061 usb receive byte count endpoint 6 0x0000 ro usbrxcount6 0x168 979 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 19-6. universal serial bus (usb) controller register map (continued) see page description reset type name offset 1063 usb host transmit configure type endpoint 6 0x00 r/w usbtxtype6 0x16a 1065 usb host transmit interval endpoint 6 0x00 r/w usbtxinterval6 0x16b 1067 usb host configure receive type endpoint 6 0x00 r/w usbrxtype6 0x16c 1069 usb host receive polling interval endpoint 6 0x00 r/w usbrxinterval6 0x16d 1029 usb maximum transmit data endpoint 7 0x0000 r/w usbtxmaxp7 0x170 1040 usb transmit control and status endpoint 7 low 0x00 r/w usbtxcsrl7 0x172 1045 usb transmit control and status endpoint 7 high 0x00 r/w usbtxcsrh7 0x173 1049 usb maximum receive data endpoint 7 0x0000 r/w usbrxmaxp7 0x174 1051 usb receive control and status endpoint 7 low 0x00 r/w usbrxcsrl7 0x176 1056 usb receive control and status endpoint 7 high 0x00 r/w usbrxcsrh7 0x177 1061 usb receive byte count endpoint 7 0x0000 ro usbrxcount7 0x178 1063 usb host transmit configure type endpoint 7 0x00 r/w usbtxtype7 0x17a 1065 usb host transmit interval endpoint 7 0x00 r/w usbtxinterval7 0x17b 1067 usb host configure receive type endpoint 7 0x00 r/w usbrxtype7 0x17c 1069 usb host receive polling interval endpoint 7 0x00 r/w usbrxinterval7 0x17d 1029 usb maximum transmit data endpoint 8 0x0000 r/w usbtxmaxp8 0x180 1040 usb transmit control and status endpoint 8 low 0x00 r/w usbtxcsrl8 0x182 1045 usb transmit control and status endpoint 8 high 0x00 r/w usbtxcsrh8 0x183 1049 usb maximum receive data endpoint 8 0x0000 r/w usbrxmaxp8 0x184 1051 usb receive control and status endpoint 8 low 0x00 r/w usbrxcsrl8 0x186 1056 usb receive control and status endpoint 8 high 0x00 r/w usbrxcsrh8 0x187 1061 usb receive byte count endpoint 8 0x0000 ro usbrxcount8 0x188 1063 usb host transmit configure type endpoint 8 0x00 r/w usbtxtype8 0x18a 1065 usb host transmit interval endpoint 8 0x00 r/w usbtxinterval8 0x18b 1067 usb host configure receive type endpoint 8 0x00 r/w usbrxtype8 0x18c 1069 usb host receive polling interval endpoint 8 0x00 r/w usbrxinterval8 0x18d 1029 usb maximum transmit data endpoint 9 0x0000 r/w usbtxmaxp9 0x190 1040 usb transmit control and status endpoint 9 low 0x00 r/w usbtxcsrl9 0x192 1045 usb transmit control and status endpoint 9 high 0x00 r/w usbtxcsrh9 0x193 1049 usb maximum receive data endpoint 9 0x0000 r/w usbrxmaxp9 0x194 1051 usb receive control and status endpoint 9 low 0x00 r/w usbrxcsrl9 0x196 1056 usb receive control and status endpoint 9 high 0x00 r/w usbrxcsrh9 0x197 july 03, 2014 980 texas instruments-production data universal serial bus (usb) controller table 19-6. universal serial bus (usb) controller register map (continued) see page description reset type name offset 1061 usb receive byte count endpoint 9 0x0000 ro usbrxcount9 0x198 1063 usb host transmit configure type endpoint 9 0x00 r/w usbtxtype9 0x19a 1065 usb host transmit interval endpoint 9 0x00 r/w usbtxinterval9 0x19b 1067 usb host configure receive type endpoint 9 0x00 r/w usbrxtype9 0x19c 1069 usb host receive polling interval endpoint 9 0x00 r/w usbrxinterval9 0x19d 1029 usb maximum transmit data endpoint 10 0x0000 r/w usbtxmaxp10 0x1a0 1040 usb transmit control and status endpoint 10 low 0x00 r/w usbtxcsrl10 0x1a2 1045 usb transmit control and status endpoint 10 high 0x00 r/w usbtxcsrh10 0x1a3 1049 usb maximum receive data endpoint 10 0x0000 r/w usbrxmaxp10 0x1a4 1051 usb receive control and status endpoint 10 low 0x00 r/w usbrxcsrl10 0x1a6 1056 usb receive control and status endpoint 10 high 0x00 r/w usbrxcsrh10 0x1a7 1061 usb receive byte count endpoint 10 0x0000 ro usbrxcount10 0x1a8 1063 usb host transmit configure type endpoint 10 0x00 r/w usbtxtype10 0x1aa 1065 usb host transmit interval endpoint 10 0x00 r/w usbtxinterval10 0x1ab 1067 usb host configure receive type endpoint 10 0x00 r/w usbrxtype10 0x1ac 1069 usb host receive polling interval endpoint 10 0x00 r/w usbrxinterval10 0x1ad 1029 usb maximum transmit data endpoint 11 0x0000 r/w usbtxmaxp11 0x1b0 1040 usb transmit control and status endpoint 11 low 0x00 r/w usbtxcsrl11 0x1b2 1045 usb transmit control and status endpoint 11 high 0x00 r/w usbtxcsrh11 0x1b3 1049 usb maximum receive data endpoint 11 0x0000 r/w usbrxmaxp11 0x1b4 1051 usb receive control and status endpoint 11 low 0x00 r/w usbrxcsrl11 0x1b6 1056 usb receive control and status endpoint 11 high 0x00 r/w usbrxcsrh11 0x1b7 1061 usb receive byte count endpoint 11 0x0000 ro usbrxcount11 0x1b8 1063 usb host transmit configure type endpoint 11 0x00 r/w usbtxtype11 0x1ba 1065 usb host transmit interval endpoint 11 0x00 r/w usbtxinterval11 0x1bb 1067 usb host configure receive type endpoint 11 0x00 r/w usbrxtype11 0x1bc 1069 usb host receive polling interval endpoint 11 0x00 r/w usbrxinterval11 0x1bd 1029 usb maximum transmit data endpoint 12 0x0000 r/w usbtxmaxp12 0x1c0 1040 usb transmit control and status endpoint 12 low 0x00 r/w usbtxcsrl12 0x1c2 1045 usb transmit control and status endpoint 12 high 0x00 r/w usbtxcsrh12 0x1c3 1049 usb maximum receive data endpoint 12 0x0000 r/w usbrxmaxp12 0x1c4 1051 usb receive control and status endpoint 12 low 0x00 r/w usbrxcsrl12 0x1c6 981 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 19-6. universal serial bus (usb) controller register map (continued) see page description reset type name offset 1056 usb receive control and status endpoint 12 high 0x00 r/w usbrxcsrh12 0x1c7 1061 usb receive byte count endpoint 12 0x0000 ro usbrxcount12 0x1c8 1063 usb host transmit configure type endpoint 12 0x00 r/w usbtxtype12 0x1ca 1065 usb host transmit interval endpoint 12 0x00 r/w usbtxinterval12 0x1cb 1067 usb host configure receive type endpoint 12 0x00 r/w usbrxtype12 0x1cc 1069 usb host receive polling interval endpoint 12 0x00 r/w usbrxinterval12 0x1cd 1029 usb maximum transmit data endpoint 13 0x0000 r/w usbtxmaxp13 0x1d0 1040 usb transmit control and status endpoint 13 low 0x00 r/w usbtxcsrl13 0x1d2 1045 usb transmit control and status endpoint 13 high 0x00 r/w usbtxcsrh13 0x1d3 1049 usb maximum receive data endpoint 13 0x0000 r/w usbrxmaxp13 0x1d4 1051 usb receive control and status endpoint 13 low 0x00 r/w usbrxcsrl13 0x1d6 1056 usb receive control and status endpoint 13 high 0x00 r/w usbrxcsrh13 0x1d7 1061 usb receive byte count endpoint 13 0x0000 ro usbrxcount13 0x1d8 1063 usb host transmit configure type endpoint 13 0x00 r/w usbtxtype13 0x1da 1065 usb host transmit interval endpoint 13 0x00 r/w usbtxinterval13 0x1db 1067 usb host configure receive type endpoint 13 0x00 r/w usbrxtype13 0x1dc 1069 usb host receive polling interval endpoint 13 0x00 r/w usbrxinterval13 0x1dd 1029 usb maximum transmit data endpoint 14 0x0000 r/w usbtxmaxp14 0x1e0 1040 usb transmit control and status endpoint 14 low 0x00 r/w usbtxcsrl14 0x1e2 1045 usb transmit control and status endpoint 14 high 0x00 r/w usbtxcsrh14 0x1e3 1049 usb maximum receive data endpoint 14 0x0000 r/w usbrxmaxp14 0x1e4 1051 usb receive control and status endpoint 14 low 0x00 r/w usbrxcsrl14 0x1e6 1056 usb receive control and status endpoint 14 high 0x00 r/w usbrxcsrh14 0x1e7 1061 usb receive byte count endpoint 14 0x0000 ro usbrxcount14 0x1e8 1063 usb host transmit configure type endpoint 14 0x00 r/w usbtxtype14 0x1ea 1065 usb host transmit interval endpoint 14 0x00 r/w usbtxinterval14 0x1eb 1067 usb host configure receive type endpoint 14 0x00 r/w usbrxtype14 0x1ec 1069 usb host receive polling interval endpoint 14 0x00 r/w usbrxinterval14 0x1ed 1029 usb maximum transmit data endpoint 15 0x0000 r/w usbtxmaxp15 0x1f0 1040 usb transmit control and status endpoint 15 low 0x00 r/w usbtxcsrl15 0x1f2 1045 usb transmit control and status endpoint 15 high 0x00 r/w usbtxcsrh15 0x1f3 1049 usb maximum receive data endpoint 15 0x0000 r/w usbrxmaxp15 0x1f4 july 03, 2014 982 texas instruments-production data universal serial bus (usb) controller table 19-6. universal serial bus (usb) controller register map (continued) see page description reset type name offset 1051 usb receive control and status endpoint 15 low 0x00 r/w usbrxcsrl15 0x1f6 1056 usb receive control and status endpoint 15 high 0x00 r/w usbrxcsrh15 0x1f7 1061 usb receive byte count endpoint 15 0x0000 ro usbrxcount15 0x1f8 1063 usb host transmit configure type endpoint 15 0x00 r/w usbtxtype15 0x1fa 1065 usb host transmit interval endpoint 15 0x00 r/w usbtxinterval15 0x1fb 1067 usb host configure receive type endpoint 15 0x00 r/w usbrxtype15 0x1fc 1069 usb host receive polling interval endpoint 15 0x00 r/w usbrxinterval15 0x1fd 1071 usb request packet count in block transfer endpoint 1 0x0000 r/w usbrqpktcount1 0x304 1071 usb request packet count in block transfer endpoint 2 0x0000 r/w usbrqpktcount2 0x308 1071 usb request packet count in block transfer endpoint 3 0x0000 r/w usbrqpktcount3 0x30c 1071 usb request packet count in block transfer endpoint 4 0x0000 r/w usbrqpktcount4 0x310 1071 usb request packet count in block transfer endpoint 5 0x0000 r/w usbrqpktcount5 0x314 1071 usb request packet count in block transfer endpoint 6 0x0000 r/w usbrqpktcount6 0x318 1071 usb request packet count in block transfer endpoint 7 0x0000 r/w usbrqpktcount7 0x31c 1071 usb request packet count in block transfer endpoint 8 0x0000 r/w usbrqpktcount8 0x320 1071 usb request packet count in block transfer endpoint 9 0x0000 r/w usbrqpktcount9 0x324 1071 usb request packet count in block transfer endpoint 10 0x0000 r/w usbrqpktcount10 0x328 1071 usb request packet count in block transfer endpoint 11 0x0000 r/w usbrqpktcount11 0x32c 1071 usb request packet count in block transfer endpoint 12 0x0000 r/w usbrqpktcount12 0x330 1071 usb request packet count in block transfer endpoint 13 0x0000 r/w usbrqpktcount13 0x334 1071 usb request packet count in block transfer endpoint 14 0x0000 r/w usbrqpktcount14 0x338 1071 usb request packet count in block transfer endpoint 15 0x0000 r/w usbrqpktcount15 0x33c 1073 usb receive double packet buffer disable 0x0000 r/w usbrxdpktbufdis 0x340 1075 usb transmit double packet buffer disable 0x0000 r/w usbtxdpktbufdis 0x342 983 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 19-6. universal serial bus (usb) controller register map (continued) see page description reset type name offset 1077 usb external power control 0x0000.0000 r/w usbepc 0x400 1080 usb external power control raw interrupt status 0x0000.0000 ro usbepcris 0x404 1081 usb external power control interrupt mask 0x0000.0000 r/w usbepcim 0x408 1082 usb external power control interrupt status and clear 0x0000.0000 r/w usbepcisc 0x40c 1083 usb device resume raw interrupt status 0x0000.0000 ro usbdrris 0x410 1084 usb device resume interrupt mask 0x0000.0000 r/w usbdrim 0x414 1085 usb device resume interrupt status and clear 0x0000.0000 w1c usbdrisc 0x418 1086 usb general-purpose control and status 0x0000.0001 r/w usbgpcs 0x41c 1087 usb vbus droop control 0x0000.0000 r/w usbvdc 0x430 1088 usb vbus droop control raw interrupt status 0x0000.0000 ro usbvdcris 0x434 1089 usb vbus droop control interrupt mask 0x0000.0000 r/w usbvdcim 0x438 1090 usb vbus droop control interrupt status and clear 0x0000.0000 r/w usbvdcisc 0x43c 1091 usb id valid detect raw interrupt status 0x0000.0000 ro usbidvris 0x444 1092 usb id valid detect interrupt mask 0x0000.0000 r/w usbidvim 0x448 1093 usb id valid detect interrupt status and clear 0x0000.0000 r/w1c usbidvisc 0x44c 1094 usb dma select 0x0033.2211 r/w usbdmasel 0x450 19.6 register descriptions the lm3s9gn5 usb controller has on-the-go (otg) capabilities as specified in the usb0 bit field in the dc6 register (see page 251). otg b / device this icon indicates that the register is used in otg b or device mode. some registers are used for both host and device mode and may have different bit definitions depending on the mode. otg a / host this icon indicates that the register is used in otg a or host mode. some registers are used for both host and device mode and may have different bit definitions depending on the mode. the usb controller is in otg b or device mode upon reset, so the reset values shown for these registers apply to the device mode definition. otg this icon indicates that the register is used for otg-specific functions such as id detection and negotiation. once otg negotiation is complete, then the usb controller registers are used according to their host or device mode meanings depending on whether the otg negotiations made the usb controller otg a (host) or otg b (device). july 03, 2014 984 texas instruments-production data universal serial bus (usb) controller register 1: usb device functional address (usbfaddr), offset 0x000 otg b / device usbfaddr is an 8-bit register that contains the 7-bit address of the device part of the transaction. when the usb controller is being used in device mode (the host bit in the usbdevctl register is clear), this register must be written with the address received through a set_address command, which is then used for decoding the function address in subsequent token packets. important: see the section called setting the device address on page 964 for special considerations when writing this register. usb device functional address (usbfaddr) base 0x4005.0000 offset 0x000 type r/w, reset 0x00 0 1 2 3 4 5 6 7 funcaddr reserved r/w r/w r/w r/w r/w r/w r/w ro type 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7 function address function address of device as received through set_address. 0x00 r/w funcaddr 6:0 985 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 2: usb power (usbpower), offset 0x001 otg a / host otg b / device usbpower is an 8-bit register used for controlling suspend and resume signaling and some basic operational aspects of the usb controller. otg a / host mode usb power (usbpower) base 0x4005.0000 offset 0x001 type r/w, reset 0x20 0 1 2 3 4 5 6 7 pwrdnphy suspend resume reset reserved r/w r/w1s r/w r/w ro ro ro ro type 0 0 0 0 0 1 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x2 ro reserved 7:4 reset signaling description value enables reset signaling on the bus. 1 ends reset signaling on the bus. 0 0 r/w reset 3 resume signaling description value enables resume signaling when the device is in suspend mode. 1 ends resume signaling on the bus. 0 this bit must be cleared by software 20 ms after being set. 0 r/w resume 2 suspend mode description value enables suspend mode. 1 no effect. 0 0 r/w1s suspend 1 july 03, 2014 986 texas instruments-production data universal serial bus (usb) controller description reset type name bit/field power down phy description value powers down the internal usb phy. 1 no effect. 0 0 r/w pwrdnphy 0 otg b / device mode usb power (usbpower) base 0x4005.0000 offset 0x001 type r/w, reset 0x20 0 1 2 3 4 5 6 7 pwrdnphy suspend resume reset reserved softconn isoup r/w ro r/w ro ro ro r/w r/w type 0 0 0 0 0 1 0 0 reset description reset type name bit/field isochronous update description value the usb controller waits for an sof token from the time the txrdy bit is set in the usbtxcsrln register before sending the packet. if an in token is received before an sof token, then a zero-length data packet is sent. 1 no effect. 0 note: this bit is only valid for isochronous transfers. 0 r/w isoup 7 soft connect/disconnect description value the usb d+/d- lines are enabled. 1 the usb d+/d- lines are tri-stated. 0 0 r/w softconn 6 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x2 ro reserved 5:4 reset signaling description value reset signaling is present on the bus. 1 reset signaling is not present on the bus. 0 0 ro reset 3 987 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field resume signaling description value enables resume signaling when the device is in suspend mode. 1 ends resume signaling on the bus. 0 this bit must be cleared by software 10 ms (a maximum of 15 ms) after being set. 0 r/w resume 2 suspend mode description value the usb controller is in suspend mode. 1 this bit is cleared when software reads the interrupt register or sets the resume bit above. 0 0 ro suspend 1 power down phy description value powers down the internal usb phy. 1 no effect. 0 0 r/w pwrdnphy 0 july 03, 2014 988 texas instruments-production data universal serial bus (usb) controller register 3: usb transmit interrupt status (usbtxis), offset 0x002 important: this register is read-sensitive. see the register description for details. otg a / host otg b / device usbtxis is a 16-bit read-only register that indicates which interrupts are currently active for endpoint 0 and the transmit endpoints 1C15. the meaning of the epn bits in this register is based on the mode of the device. the ep1 through ep15 bits always indicate that the usb controller is sending data; however, in host mode, the bits refer to out endpoints; while in device mode, the bits refer to in endpoints. the ep0 bit is special in host and device modes and indicates that either a control in or control out endpoint has generated an interrupt. note: bits relating to endpoints that have not been configured always return 0. note also that all active interrupts are cleared when this register is read. usb transmit interrupt status (usbtxis) base 0x4005.0000 offset 0x002 type ro, reset 0x0000 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ep0 ep1 ep2 ep3 ep4 ep5 ep6 ep7 ep8 ep9 ep10 ep11 ep12 ep13 ep14 ep15 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field tx endpoint 15 interrupt description value no interrupt. 0 the endpoint 15 transmit interrupt is asserted. 1 0 ro ep15 15 tx endpoint 14 interrupt same description as ep15. 0 ro ep14 14 tx endpoint 13 interrupt same description as ep15. 0 ro ep13 13 tx endpoint 12 interrupt same description as ep15. 0 ro ep12 12 tx endpoint 11 interrupt same description as ep15. 0 ro ep11 11 tx endpoint 10 interrupt same description as ep15. 0 ro ep10 10 tx endpoint 9 interrupt same description as ep15. 0 ro ep9 9 tx endpoint 8 interrupt same description as ep15. 0 ro ep8 8 tx endpoint 7 interrupt same description as ep15. 0 ro ep7 7 989 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field tx endpoint 6 interrupt same description as ep15. 0 ro ep6 6 tx endpoint 5 interrupt same description as ep15. 0 ro ep5 5 tx endpoint 4 interrupt same description as ep15. 0 ro ep4 4 tx endpoint 3 interrupt same description as ep15. 0 ro ep3 3 tx endpoint 2 interrupt same description as ep15. 0 ro ep2 2 tx endpoint 1 interrupt same description as ep15. 0 ro ep1 1 tx and rx endpoint 0 interrupt description value no interrupt. 0 the endpoint 0 transmit and receive interrupt is asserted. 1 0 ro ep0 0 july 03, 2014 990 texas instruments-production data universal serial bus (usb) controller register 4: usb receive interrupt status (usbrxis), offset 0x004 important: this register is read-sensitive. see the register description for details. otg a / host otg b / device usbrxis is a 16-bit read-only register that indicates which of the interrupts for receive endpoints 1C15 are currently active. note: bits relating to endpoints that have not been configured always return 0. note also that all active interrupts are cleared when this register is read. usb receive interrupt status (usbrxis) base 0x4005.0000 offset 0x004 type ro, reset 0x0000 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved ep1 ep2 ep3 ep4 ep5 ep6 ep7 ep8 ep9 ep10 ep11 ep12 ep13 ep14 ep15 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field rx endpoint 15 interrupt description value no interrupt. 0 the endpoint 15 receive interrupt is asserted. 1 0 ro ep15 15 rx endpoint 14 interrupt same description as ep15. 0 ro ep14 14 rx endpoint 13 interrupt same description as ep15. 0 ro ep13 13 rx endpoint 12 interrupt same description as ep15. 0 ro ep12 12 rx endpoint 11 interrupt same description as ep15. 0 ro ep11 11 rx endpoint 10 interrupt same description as ep15. 0 ro ep10 10 rx endpoint 9 interrupt same description as ep15. 0 ro ep9 9 rx endpoint 8 interrupt same description as ep15. 0 ro ep8 8 rx endpoint 7 interrupt same description as ep15. 0 ro ep7 7 rx endpoint 6 interrupt same description as ep15. 0 ro ep6 6 991 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field rx endpoint 5 interrupt same description as ep15. 0 ro ep5 5 rx endpoint 4 interrupt same description as ep15. 0 ro ep4 4 rx endpoint 3 interrupt same description as ep15. 0 ro ep3 3 rx endpoint 2 interrupt same description as ep15. 0 ro ep2 2 rx endpoint 1 interrupt same description as ep15. 0 ro ep1 1 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 0 july 03, 2014 992 texas instruments-production data universal serial bus (usb) controller register 5: usb transmit interrupt enable (usbtxie), offset 0x006 otg a / host otg b / device usbtxie is a 16-bit register that provides interrupt enable bits for the interrupts in the usbtxis register. when a bit is set, the usb interrupt is asserted to the interrupt controller when the corresponding interrupt bit in the usbtxis register is set. when a bit is cleared, the interrupt in the usbtxis register is still set but the usb interrupt to the interrupt controller is not asserted. on reset, all interrupts are enabled. usb transmit interrupt enable (usbtxie) base 0x4005.0000 offset 0x006 type r/w, reset 0xffff 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ep0 ep1 ep2 ep3 ep4 ep5 ep6 ep7 ep8 ep9 ep10 ep11 ep12 ep13 ep14 ep15 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field tx endpoint 15 interrupt enable description value an interrupt is sent to the interrupt controller when the ep15 bit in the usbtxis register is set. 1 the ep15 transmit interrupt is suppressed and not sent to the interrupt controller. 0 1 r/w ep15 15 tx endpoint 14 interrupt enable same description as ep15. 1 r/w ep14 14 tx endpoint 13 interrupt enable same description as ep15. 1 r/w ep13 13 tx endpoint 12 interrupt enable same description as ep15. 1 r/w ep12 12 tx endpoint 11 interrupt enable same description as ep15. 1 r/w ep11 11 tx endpoint 10 interrupt enable same description as ep15. 1 r/w ep10 10 tx endpoint 9 interrupt enable same description as ep15. 1 r/w ep9 9 tx endpoint 8 interrupt enable same description as ep15. 1 r/w ep8 8 tx endpoint 7 interrupt enable same description as ep15. 1 r/w ep7 7 tx endpoint 6 interrupt enable same description as ep15. 1 r/w ep6 6 993 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field tx endpoint 5 interrupt enable same description as ep15. 1 r/w ep5 5 tx endpoint 4 interrupt enable same description as ep15. 1 r/w ep4 4 tx endpoint 3 interrupt enable same description as ep15. 1 r/w ep3 3 tx endpoint 2 interrupt enable same description as ep15. 1 r/w ep2 2 tx endpoint 1 interrupt enable same description as ep15. 1 r/w ep1 1 tx and rx endpoint 0 interrupt enable description value an interrupt is sent to the interrupt controller when the ep0 bit in the usbtxis register is set. 1 the ep0 transmit and receive interrupt is suppressed and not sent to the interrupt controller. 0 1 r/w ep0 0 july 03, 2014 994 texas instruments-production data universal serial bus (usb) controller register 6: usb receive interrupt enable (usbrxie), offset 0x008 otg a / host otg b / device usbrxie is a 16-bit register that provides interrupt enable bits for the interrupts in the usbrxis register. when a bit is set, the usb interrupt is asserted to the interrupt controller when the corresponding interrupt bit in the usbrxis register is set. when a bit is cleared, the interrupt in the usbrxis register is still set but the usb interrupt to the interrupt controller is not asserted. on reset, all interrupts are enabled. usb receive interrupt enable (usbrxie) base 0x4005.0000 offset 0x008 type r/w, reset 0xfffe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved ep1 ep2 ep3 ep4 ep5 ep6 ep7 ep8 ep9 ep10 ep11 ep12 ep13 ep14 ep15 ro r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset type name bit/field rx endpoint 15 interrupt enable description value an interrupt is sent to the interrupt controller when the ep15 bit in the usbrxis register is set. 1 the ep15 receive interrupt is suppressed and not sent to the interrupt controller. 0 1 r/w ep15 15 rx endpoint 14 interrupt enable same description as ep15. 1 r/w ep14 14 rx endpoint 13 interrupt enable same description as ep15. 1 r/w ep13 13 rx endpoint 12 interrupt enable same description as ep15. 1 r/w ep12 12 rx endpoint 11 interrupt enable same description as ep15. 1 r/w ep11 11 rx endpoint 10 interrupt enable same description as ep15. 1 r/w ep10 10 rx endpoint 9 interrupt enable same description as ep15. 1 r/w ep9 9 rx endpoint 8 interrupt enable same description as ep15. 1 r/w ep8 8 rx endpoint 7 interrupt enable same description as ep15. 1 r/w ep7 7 rx endpoint 6 interrupt enable same description as ep15. 1 r/w ep6 6 995 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field rx endpoint 5 interrupt enable same description as ep15. 1 r/w ep5 5 rx endpoint 4 interrupt enable same description as ep15. 1 r/w ep4 4 rx endpoint 3 interrupt enable same description as ep15. 1 r/w ep3 3 rx endpoint 2 interrupt enable same description as ep15. 1 r/w ep2 2 rx endpoint 1 interrupt enable same description as ep15. 1 r/w ep1 1 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 0 july 03, 2014 996 texas instruments-production data universal serial bus (usb) controller register 7: usb general interrupt status (usbis), offset 0x00a important: this register is read-sensitive. see the register description for details. otg a / host otg b / device usbis is an 8-bit read-only register that indicates which usb interrupts are currently active. all active interrupts are cleared when this register is read. otg a / host mode usb general interrupt status (usbis) base 0x4005.0000 offset 0x00a type ro, reset 0x00 0 1 2 3 4 5 6 7 reserved resume babble sof conn discon sesreq vbuserr ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 reset description reset type name bit/field vbus error description value vbus has dropped below the vbus valid threshold during a session. 1 no interrupt. 0 0 ro vbuserr 7 session request description value session request signaling has been detected. 1 no interrupt. 0 0 ro sesreq 6 session disconnect description value a device disconnect has been detected. 1 no interrupt. 0 0 ro discon 5 session connect description value a device connection has been detected. 1 no interrupt. 0 0 ro conn 4 997 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field start of frame description value a new frame has started. 1 no interrupt. 0 0 ro sof 3 babble detected description value babble has been detected. this interrupt is active only after the first sof has been sent. 1 no interrupt. 0 0 ro babble 2 resume signaling detected description value resume signaling has been detected on the bus while the usb controller is in suspend mode. 1 no interrupt. 0 this interrupt can only be used if the usb controller's system clock is enabled. if the user disables the clock programming, the usbdrris , usbdrim , and usbdrisc registers should be used. 0 ro resume 1 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 0 otg b / device mode usb general interrupt status (usbis) base 0x4005.0000 offset 0x00a type ro, reset 0x00 0 1 2 3 4 5 6 7 suspend resume reset sof reserved discon reserved ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 7:6 session disconnect description value the device has been disconnected from the host. 1 no interrupt. 0 0 ro discon 5 july 03, 2014 998 texas instruments-production data universal serial bus (usb) controller description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 4 start of frame description value a new frame has started. 1 no interrupt. 0 0 ro sof 3 reset signaling detected description value reset signaling has been detected on the bus. 1 no interrupt. 0 0 ro reset 2 resume signaling detected description value resume signaling has been detected on the bus while the usb controller is in suspend mode. 1 no interrupt. 0 this interrupt can only be used if the usb controller's system clock is enabled. if the user disables the clock programming, the usbdrris , usbdrim , and usbdrisc registers should be used. 0 ro resume 1 suspend signaling detected description value suspend signaling has been detected on the bus. 1 no interrupt. 0 0 ro suspend 0 999 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 8: usb interrupt enable (usbie), offset 0x00b otg a / host otg b / device usbie is an 8-bit register that provides interrupt enable bits for each of the interrupts in usbis . at reset interrupts 1 and 2 are enabled in device mode. otg a / host mode usb interrupt enable (usbie) base 0x4005.0000 offset 0x00b type r/w, reset 0x06 0 1 2 3 4 5 6 7 reserved resume babble sof conn discon sesreq vbuserr ro r/w r/w r/w r/w r/w r/w r/w type 0 1 1 0 0 0 0 0 reset description reset type name bit/field enable vbus error interrupt description value an interrupt is sent to the interrupt controller when the vbuserr bit in the usbis register is set. 1 the vbuserr interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w vbuserr 7 enable session request description value an interrupt is sent to the interrupt controller when the sesreeq bit in the usbis register is set. 1 the sesreq interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w sesreq 6 enable disconnect interrupt description value an interrupt is sent to the interrupt controller when the discon bit in the usbis register is set. 1 the discon interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w discon 5 july 03, 2014 1000 texas instruments-production data universal serial bus (usb) controller description reset type name bit/field enable connect interrupt description value an interrupt is sent to the interrupt controller when the conn bit in the usbis register is set. 1 the conn interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w conn 4 enable start-of-frame interrupt description value an interrupt is sent to the interrupt controller when the sof bit in the usbis register is set. 1 the sof interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w sof 3 enable babble interrupt description value an interrupt is sent to the interrupt controller when the babble bit in the usbis register is set. 1 the babble interrupt is suppressed and not sent to the interrupt controller. 0 1 r/w babble 2 enable resume interrupt description value an interrupt is sent to the interrupt controller when the resume bit in the usbis register is set. 1 the resume interrupt is suppressed and not sent to the interrupt controller. 0 1 r/w resume 1 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 0 otg b / device mode usb interrupt enable (usbie) base 0x4005.0000 offset 0x00b type r/w, reset 0x06 0 1 2 3 4 5 6 7 suspend resume reset sof reserved discon reserved r/w r/w r/w r/w ro r/w ro ro type 0 1 1 0 0 0 0 0 reset 1001 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 7:6 enable disconnect interrupt description value an interrupt is sent to the interrupt controller when the discon bit in the usbis register is set. 1 the discon interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w discon 5 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 4 enable start-of-frame interrupt description value an interrupt is sent to the interrupt controller when the sof bit in the usbis register is set. 1 the sof interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w sof 3 enable reset interrupt description value an interrupt is sent to the interrupt controller when the reset bit in the usbis register is set. 1 the reset interrupt is suppressed and not sent to the interrupt controller. 0 1 r/w reset 2 enable resume interrupt description value an interrupt is sent to the interrupt controller when the resume bit in the usbis register is set. 1 the resume interrupt is suppressed and not sent to the interrupt controller. 0 1 r/w resume 1 enable suspend interrupt description value an interrupt is sent to the interrupt controller when the suspend bit in the usbis register is set. 1 the suspend interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w suspend 0 july 03, 2014 1002 texas instruments-production data universal serial bus (usb) controller register 9: usb frame value (usbframe), offset 0x00c otg a / host otg b / device usbframe is a 16-bit read-only register that holds the last received frame number. usb frame value (usbframe) base 0x4005.0000 offset 0x00c type ro, reset 0x0000 0123456789 10 11 12 13 14 15 frame reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0000000000000000 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 15:11 frame number 0x000 ro frame 10:0 1003 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 10: usb endpoint index (usbepidx), offset 0x00e otg a / host otg b / device each endpoint's buffer can be accessed by configuring a fifo size and starting address. the usbepidx 8-bit register is used with the usbtxfifosz , usbrxfifosz , usbtxfifoadd , and usbrxfifoadd registers. usb endpoint index (usbepidx) base 0x4005.0000 offset 0x00e type r/w, reset 0x00 01234567 epidx reserved r/w r/w r/w r/w ro ro ro ro type 00000000 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 7:4 endpoint index this bit field configures which endpoint is accessed when reading or writing to one of the usb controller's indexed registers. a value of 0x0 corresponds to endpoint 0 and a value of 0xf corresponds to endpoint 15. 0x0 r/w epidx 3:0 july 03, 2014 1004 texas instruments-production data universal serial bus (usb) controller register 11: usb test mode (usbtest), offset 0x00f otg a / host otg b / device usbtest is an 8-bit register that is primarily used to put the usb controller into one of the four test modes for operation described in the usb 2.0 specification , in response to a set feature: usbtestmode command. this register is not used in normal operation. note: only one of these bits should be set at any time. otg a / host mode usb test mode (usbtest) base 0x4005.0000 offset 0x00f type r/w, reset 0x00 0 1 2 3 4 5 6 7 reserved forcefs fifoacc forceh ro ro ro ro ro r/w r/w1s r/w type 0 0 0 0 0 0 0 0 reset description reset type name bit/field force host mode description value forces the usb controller to enter host mode when the session bit is set, regardless of whether the usb controller is connected to any peripheral. the state of the usb0dp and usb0dm signals is ignored. the usb controller then remains in host mode until the session bit is cleared, even if a device is disconnected. if the forceh bit remains set, the usb controller re-enters host mode the next time the session bit is set. 1 no effect. 0 while in this mode, status of the bus connection may be read using the dev bit of the usbdevctl register. the operating speed is determined from the forcefs bit. 0 r/w forceh 7 fifo access description value transfers the packet in the endpoint 0 transmit fifo to the endpoint 0 receive fifo. 1 no effect. 0 this bit is cleared automatically. 0 r/w1s fifoacc 6 force full-speed mode description value forces the usb controller into full-speed mode upon receiving a usb reset. 1 the usb controller operates at low speed. 0 0 r/w forcefs 5 1005 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 4:0 otg b / device mode usb test mode (usbtest) base 0x4005.0000 offset 0x00f type r/w, reset 0x00 0 1 2 3 4 5 6 7 reserved fifoacc reserved ro ro ro ro ro ro r/w1s ro type 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7 fifo access description value transfers the packet in the endpoint 0 transmit fifo to the endpoint 0 receive fifo. 1 no effect. 0 this bit is cleared automatically. 0 r/w1s fifoacc 6 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 5:0 july 03, 2014 1006 texas instruments-production data universal serial bus (usb) controller register 12: usb fifo endpoint 0 (usbfifo0), offset 0x020 register 13: usb fifo endpoint 1 (usbfifo1), offset 0x024 register 14: usb fifo endpoint 2 (usbfifo2), offset 0x028 register 15: usb fifo endpoint 3 (usbfifo3), offset 0x02c register 16: usb fifo endpoint 4 (usbfifo4), offset 0x030 register 17: usb fifo endpoint 5 (usbfifo5), offset 0x034 register 18: usb fifo endpoint 6 (usbfifo6), offset 0x038 register 19: usb fifo endpoint 7 (usbfifo7), offset 0x03c register 20: usb fifo endpoint 8 (usbfifo8), offset 0x040 register 21: usb fifo endpoint 9 (usbfifo9), offset 0x044 register 22: usb fifo endpoint 10 (usbfifo10), offset 0x048 register 23: usb fifo endpoint 11 (usbfifo11), offset 0x04c register 24: usb fifo endpoint 12 (usbfifo12), offset 0x050 register 25: usb fifo endpoint 13 (usbfifo13), offset 0x054 register 26: usb fifo endpoint 14 (usbfifo14), offset 0x058 register 27: usb fifo endpoint 15 (usbfifo15), offset 0x05c important: this register is read-sensitive. see the register description for details. otg a / host otg b / device these 32-bit registers provide an address for cpu access to the fifos for each endpoint. writing to these addresses loads data into the transmit fifo for the corresponding endpoint. reading from these addresses unloads data from the receive fifo for the corresponding endpoint. transfers to and from fifos may be 8-bit, 16-bit or 32-bit as required, and any combination of accesses is allowed provided the data accessed is contiguous. all transfers associated with one packet must be of the same width so that the data is consistently byte-, halfword- or word-aligned. however, the last transfer may contain fewer bytes than the previous transfers in order to complete an odd-byte or odd-word transfer. depending on the size of the fifo and the expected maximum packet size, the fifos support either single-packet or double-packet buffering (see the section called single-packet buffering on page 962). burst writing of multiple packets is not supported as flags must be set after each packet is written. following a stall response or a transmit error on endpoint 1C15, the associated fifo is completely flushed. 1007 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller usb fifo endpoint 0 (usbfifo0) base 0x4005.0000 offset 0x020 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 epdata r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 epdata r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field endpoint data writing to this register loads the data into the transmit fifo and reading unloads data from the receive fifo. 0x0000.0000 r/w epdata 31:0 july 03, 2014 1008 texas instruments-production data universal serial bus (usb) controller register 28: usb device control (usbdevctl), offset 0x060 otg a / host usbdevctl is an 8-bit register used for controlling and monitoring the usb vbus line. if the phy is suspended, no phy clock is received and the vbus is not sampled. in addition, in host mode, usbdevctl provides the status information for the current operating mode (host or device) of the usb controller. if the usb controller is in host mode, this register also indicates if a full- or low-speed device has been connected. usb device control (usbdevctl) base 0x4005.0000 offset 0x060 type r/w, reset 0x80 0 1 2 3 4 5 6 7 session hostreq host vbus lsdev fsdev dev r/w r/w ro ro ro ro ro ro type 0 0 0 0 0 0 0 1 reset description reset type name bit/field device mode description value the usb controller is operating on the otg a side of the cable. 0 the usb controller is operating on the otg b side of the cable. 1 note: this value is only valid while a session is in progress. 1 ro dev 7 full-speed device detected description value a full-speed device has not been detected on the port. 0 a full-speed device has been detected on the port. 1 0 ro fsdev 6 low-speed device detected description value a low-speed device has not been detected on the port. 0 a low-speed device has been detected on the port. 1 0 ro lsdev 5 vbus level description value below sessionend vbus is detected as under 0.5 v. 0x0 above sessionend, below avalid vbus is detected as above 0.5 v and under 1.5 v. 0x1 above avalid, below vbusvalid vbus is detected as above 1.5 v and below 4.75 v. 0x2 above vbusvalid vbus is detected as above 4.75 v. 0x3 0x0 ro vbus 4:3 1009 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field host mode description value the usb controller is acting as a device. 0 the usb controller is acting as a host. 1 note: this value is only valid while a session is in progress. 0 ro host 2 host request description value no effect. 0 initiates the host negotiation when suspend mode is entered. 1 this bit is cleared when host negotiation is completed. 0 r/w hostreq 1 session start/end when operating as an otg a device: description value when cleared by software, this bit ends a session. 0 when set by software, this bit starts a session. 1 when operating as an otg b device: description value the usb controller has ended a session. when the usb controller is in suspend mode, this bit may be cleared by software to perform a software disconnect. 0 the usb controller has started a session. when set by software, the session request protocol is initiated. 1 note: clearing this bit when the usb controller is not suspended results in undefined behavior. 0 r/w session 0 july 03, 2014 1010 texas instruments-production data universal serial bus (usb) controller register 29: usb transmit dynamic fifo sizing (usbtxfifosz), offset 0x062 register 30: usb receive dynamic fifo sizing (usbrxfifosz), offset 0x063 otg a / host otg b / device these 8-bit registers allow the selected tx/rx endpoint fifos to be dynamically sized. usbepidx is used to configure each transmit endpoint's fifo size. usb transmit dynamic fifo sizing (usbtxfifosz) base 0x4005.0000 offset 0x062 type r/w, reset 0x00 01234567 size dpb reserved r/w r/w r/w r/w r/w ro ro ro type 00000000 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 7:5 double packet buffer support description value only single-packet buffering is supported. 0 double-packet buffering is supported. 1 0 r/w dpb 4 max packet size maximum packet size to be allowed. if dpb = 0, the fifo also is this size; if dpb = 1, the fifo is twice this size. packet size (bytes) value 80x0 16 0x1 32 0x2 64 0x3 128 0x4 256 0x5 512 0x6 1024 0x7 2048 0x8 reserved 0x9-0xf 0x0 r/w size 3:0 1011 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 31: usb transmit fifo start address (usbtxfifoadd), offset 0x064 register 32: usb receive fifo start address (usbrxfifoadd), offset 0x066 otg a / host otg b / device usbtxfifoadd and usbrxfifoadd are 16-bit registers that control the start address of the selected transmit and receive endpoint fifos. usb transmit fifo start address (usbtxfifoadd) base 0x4005.0000 offset 0x064 type r/w, reset 0x0000 0123456789 10 11 12 13 14 15 addr reserved r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro type 0000000000000000 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 15:9 transmit/receive start address start address of the endpoint fifo. start address value 00x0 80x1 160x2 240x3 320x4 400x5 480x6 560x7 640x8 ...... 4095 0x1ff 0x00 r/w addr 8:0 july 03, 2014 1012 texas instruments-production data universal serial bus (usb) controller register 33: usb connect timing (usbcontim), offset 0x07a otg a / host otg b / device this 8-bit configuration register specifies connection and negotiation delays. usb connect timing (usbcontim) base 0x4005.0000 offset 0x07a type r/w, reset 0x5c 01234567 wtid wtcon r/w r/w r/w r/w r/w r/w r/w r/w type 00111010 reset description reset type name bit/field connect wait this field configures the wait required to allow for the users connect/disconnect filter, in units of 533.3 ns. the default corresponds to 2.667 s. 0x5 r/w wtcon 7:4 wait id this field configures the delay required from the enable of the id detection to when the id value is valid, in units of 4.369 ms. the default corresponds to 52.43 ms. 0xc r/w wtid 3:0 1013 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 34: usb otg vbus pulse timing (usbvplen), offset 0x07b otg this 8-bit configuration register specifies the duration of the vbus pulsing charge. usb otg vbus pulse timing (usbvplen) base 0x4005.0000 offset 0x07b type r/w, reset 0x3c 0 1 2 3 4 5 6 7 vplen r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 1 1 1 1 0 0 reset description reset type name bit/field vbus pulse length this field configures the duration of the vbus pulsing charge in units of 546.1 s. the default corresponds to 32.77 ms. 0x3c r/w vplen 7:0 july 03, 2014 1014 texas instruments-production data universal serial bus (usb) controller register 35: usb full-speed last transaction to end of frame timing (usbfseof), offset 0x07d otg a / host otg b / device this 8-bit configuration register specifies the minimum time gap allowed between the start of the last transaction and the eof for full-speed transactions. usb full-speed last transaction to end of frame timing (usbfseof) base 0x4005.0000 offset 0x07d type r/w, reset 0x77 01234567 fseofg r/w r/w r/w r/w r/w r/w r/w r/w type 11101110 reset description reset type name bit/field full-speed end-of-frame gap this field is used during full-speed transactions to configure the gap between the last transaction and the end-of-frame (eof), in units of 533.3 ns. the default corresponds to 63.46 s. 0x77 r/w fseofg 7:0 1015 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 36: usb low-speed last transaction to end of frame timing (usblseof), offset 0x07e otg a / host otg b / device this 8-bit configuration register specifies the minimum time gap that is to be allowed between the start of the last transaction and the eof for low-speed transactions. usb low-speed last transaction to end of frame timing (usblseof) base 0x4005.0000 offset 0x07e type r/w, reset 0x72 01234567 lseofg r/w r/w r/w r/w r/w r/w r/w r/w type 01001110 reset description reset type name bit/field low-speed end-of-frame gap this field is used during low-speed transactions to set the gap between the last transaction and the end-of-frame (eof), in units of 1.067 s. the default corresponds to 121.6 s. 0x72 r/w lseofg 7:0 july 03, 2014 1016 texas instruments-production data universal serial bus (usb) controller register 37: usb transmit functional address endpoint 0 (usbtxfuncaddr0), offset 0x080 register 38: usb transmit functional address endpoint 1 (usbtxfuncaddr1), offset 0x088 register 39: usb transmit functional address endpoint 2 (usbtxfuncaddr2), offset 0x090 register 40: usb transmit functional address endpoint 3 (usbtxfuncaddr3), offset 0x098 register 41: usb transmit functional address endpoint 4 (usbtxfuncaddr4), offset 0x0a0 register 42: usb transmit functional address endpoint 5 (usbtxfuncaddr5), offset 0x0a8 register 43: usb transmit functional address endpoint 6 (usbtxfuncaddr6), offset 0x0b0 register 44: usb transmit functional address endpoint 7 (usbtxfuncaddr7), offset 0x0b8 register 45: usb transmit functional address endpoint 8 (usbtxfuncaddr8), offset 0x0c0 register 46: usb transmit functional address endpoint 9 (usbtxfuncaddr9), offset 0x0c8 register 47: usb transmit functional address endpoint 10 (usbtxfuncaddr10), offset 0x0d0 register 48: usb transmit functional address endpoint 11 (usbtxfuncaddr11), offset 0x0d8 register 49: usb transmit functional address endpoint 12 (usbtxfuncaddr12), offset 0x0e0 register 50: usb transmit functional address endpoint 13 (usbtxfuncaddr13), offset 0x0e8 register 51: usb transmit functional address endpoint 14 (usbtxfuncaddr14), offset 0x0f0 register 52: usb transmit functional address endpoint 15 (usbtxfuncaddr15), offset 0x0f8 otg a / host usbtxfuncaddrn is an 8-bit read/write register that records the address of the target function to be accessed through the associated endpoint (epn). usbtxfuncaddrn must be defined for each transmit endpoint that is used. note: usbtxfuncaddr0 is used for both receive and transmit for endpoint 0. 1017 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller usb transmit functional address endpoint 0 (usbtxfuncaddr0) base 0x4005.0000 offset 0x080 type r/w, reset 0x00 0 1 2 3 4 5 6 7 addr reserved r/w r/w r/w r/w r/w r/w r/w ro type 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7 device address specifies the usb bus address for the target device. 0x00 r/w addr 6:0 july 03, 2014 1018 texas instruments-production data universal serial bus (usb) controller register 53: usb transmit hub address endpoint 0 (usbtxhubaddr0), offset 0x082 register 54: usb transmit hub address endpoint 1 (usbtxhubaddr1), offset 0x08a register 55: usb transmit hub address endpoint 2 (usbtxhubaddr2), offset 0x092 register 56: usb transmit hub address endpoint 3 (usbtxhubaddr3), offset 0x09a register 57: usb transmit hub address endpoint 4 (usbtxhubaddr4), offset 0x0a2 register 58: usb transmit hub address endpoint 5 (usbtxhubaddr5), offset 0x0aa register 59: usb transmit hub address endpoint 6 (usbtxhubaddr6), offset 0x0b2 register 60: usb transmit hub address endpoint 7 (usbtxhubaddr7), offset 0x0ba register 61: usb transmit hub address endpoint 8 (usbtxhubaddr8), offset 0x0c2 register 62: usb transmit hub address endpoint 9 (usbtxhubaddr9), offset 0x0ca register 63: usb transmit hub address endpoint 10 (usbtxhubaddr10), offset 0x0d2 register 64: usb transmit hub address endpoint 11 (usbtxhubaddr11), offset 0x0da register 65: usb transmit hub address endpoint 12 (usbtxhubaddr12), offset 0x0e2 register 66: usb transmit hub address endpoint 13 (usbtxhubaddr13), offset 0x0ea register 67: usb transmit hub address endpoint 14 (usbtxhubaddr14), offset 0x0f2 register 68: usb transmit hub address endpoint 15 (usbtxhubaddr15), offset 0x0fa otg a / host usbtxhubaddrn is an 8-bit read/write register that, like usbtxhubportn , only must be written when a usb device is connected to transmit endpoint epn via a usb 2.0 hub. this register records the address of the usb 2.0 hub through which the target associated with the endpoint is accessed. note: usbtxhubaddr0 is used for both receive and transmit for endpoint 0. 1019 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller usb transmit hub address endpoint 0 (usbtxhubaddr0) base 0x4005.0000 offset 0x082 type r/w, reset 0x00 0 1 2 3 4 5 6 7 addr reserved r/w r/w r/w r/w r/w r/w r/w ro type 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7 hub address this field specifies the usb bus address for the usb 2.0 hub. 0x00 r/w addr 6:0 july 03, 2014 1020 texas instruments-production data universal serial bus (usb) controller register 69: usb transmit hub port endpoint 0 (usbtxhubport0), offset 0x083 register 70: usb transmit hub port endpoint 1 (usbtxhubport1), offset 0x08b register 71: usb transmit hub port endpoint 2 (usbtxhubport2), offset 0x093 register 72: usb transmit hub port endpoint 3 (usbtxhubport3), offset 0x09b register 73: usb transmit hub port endpoint 4 (usbtxhubport4), offset 0x0a3 register 74: usb transmit hub port endpoint 5 (usbtxhubport5), offset 0x0ab register 75: usb transmit hub port endpoint 6 (usbtxhubport6), offset 0x0b3 register 76: usb transmit hub port endpoint 7 (usbtxhubport7), offset 0x0bb register 77: usb transmit hub port endpoint 8 (usbtxhubport8), offset 0x0c3 register 78: usb transmit hub port endpoint 9 (usbtxhubport9), offset 0x0cb register 79: usb transmit hub port endpoint 10 (usbtxhubport10), offset 0x0d3 register 80: usb transmit hub port endpoint 11 (usbtxhubport11), offset 0x0db register 81: usb transmit hub port endpoint 12 (usbtxhubport12), offset 0x0e3 register 82: usb transmit hub port endpoint 13 (usbtxhubport13), offset 0x0eb register 83: usb transmit hub port endpoint 14 (usbtxhubport14), offset 0x0f3 register 84: usb transmit hub port endpoint 15 (usbtxhubport15), offset 0x0fb otg a / host usbtxhubportn is an 8-bit read/write register that, like usbtxhubaddrn , only must be written when a full- or low-speed device is connected to transmit endpoint epn via a usb 2.0 hub. this register records the port of the usb 2.0 hub through which the target associated with the endpoint is accessed. note: usbtxhubport0 is used for both receive and transmit for endpoint 0. 1021 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller usb transmit hub port endpoint 0 (usbtxhubport0) base 0x4005.0000 offset 0x083 type r/w, reset 0x00 0 1 2 3 4 5 6 7 port reserved r/w r/w r/w r/w r/w r/w r/w ro type 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7 hub port this field specifies the usb hub port number. 0x00 r/w port 6:0 july 03, 2014 1022 texas instruments-production data universal serial bus (usb) controller register 85: usb receive functional address endpoint 1 (usbrxfuncaddr1), offset 0x08c register 86: usb receive functional address endpoint 2 (usbrxfuncaddr2), offset 0x094 register 87: usb receive functional address endpoint 3 (usbrxfuncaddr3), offset 0x09c register 88: usb receive functional address endpoint 4 (usbrxfuncaddr4), offset 0x0a4 register 89: usb receive functional address endpoint 5 (usbrxfuncaddr5), offset 0x0ac register 90: usb receive functional address endpoint 6 (usbrxfuncaddr6), offset 0x0b4 register 91: usb receive functional address endpoint 7 (usbrxfuncaddr7), offset 0x0bc register 92: usb receive functional address endpoint 8 (usbrxfuncaddr8), offset 0x0c4 register 93: usb receive functional address endpoint 9 (usbrxfuncaddr9), offset 0x0cc register 94: usb receive functional address endpoint 10 (usbrxfuncaddr10), offset 0x0d4 register 95: usb receive functional address endpoint 11 (usbrxfuncaddr11), offset 0x0dc register 96: usb receive functional address endpoint 12 (usbrxfuncaddr12), offset 0x0e4 register 97: usb receive functional address endpoint 13 (usbrxfuncaddr13), offset 0x0ec register 98: usb receive functional address endpoint 14 (usbrxfuncaddr14), offset 0x0f4 register 99: usb receive functional address endpoint 15 (usbrxfuncaddr15), offset 0x0fc otg a / host usbrxfuncaddrn is an 8-bit read/write register that records the address of the target function accessed through the associated endpoint (epn). usbrxfuncaddrn must be defined for each receive endpoint that is used. note: usbtxfuncaddr0 is used for both receive and transmit for endpoint 0. 1023 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller usb receive functional address endpoint 1 (usbrxfuncaddr1) base 0x4005.0000 offset 0x08c type r/w, reset 0x00 0 1 2 3 4 5 6 7 addr reserved r/w r/w r/w r/w r/w r/w r/w ro type 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7 device address this field specifies the usb bus address for the target device. 0x00 r/w addr 6:0 july 03, 2014 1024 texas instruments-production data universal serial bus (usb) controller register 100: usb receive hub address endpoint 1 (usbrxhubaddr1), offset 0x08e register 101: usb receive hub address endpoint 2 (usbrxhubaddr2), offset 0x096 register 102: usb receive hub address endpoint 3 (usbrxhubaddr3), offset 0x09e register 103: usb receive hub address endpoint 4 (usbrxhubaddr4), offset 0x0a6 register 104: usb receive hub address endpoint 5 (usbrxhubaddr5), offset 0x0ae register 105: usb receive hub address endpoint 6 (usbrxhubaddr6), offset 0x0b6 register 106: usb receive hub address endpoint 7 (usbrxhubaddr7), offset 0x0be register 107: usb receive hub address endpoint 8 (usbrxhubaddr8), offset 0x0c6 register 108: usb receive hub address endpoint 9 (usbrxhubaddr9), offset 0x0ce register 109: usb receive hub address endpoint 10 (usbrxhubaddr10), offset 0x0d6 register 110: usb receive hub address endpoint 11 (usbrxhubaddr11), offset 0x0de register 111: usb receive hub address endpoint 12 (usbrxhubaddr12), offset 0x0e6 register 112: usb receive hub address endpoint 13 (usbrxhubaddr13), offset 0x0ee register 113: usb receive hub address endpoint 14 (usbrxhubaddr14), offset 0x0f6 register 114: usb receive hub address endpoint 15 (usbrxhubaddr15), offset 0x0fe otg a / host usbrxhubaddrn is an 8-bit read/write register that, like usbrxhubportn , only must be written when a full- or low-speed device is connected to receive endpoint epn via a usb 2.0 hub. this register records the address of the usb 2.0 hub through which the target associated with the endpoint is accessed. note: usbtxhubaddr0 is used for both receive and transmit for endpoint 0. 1025 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller usb receive hub address endpoint 1 (usbrxhubaddr1) base 0x4005.0000 offset 0x08e type r/w, reset 0x00 0 1 2 3 4 5 6 7 addr reserved r/w r/w r/w r/w r/w r/w r/w ro type 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7 hub address this field specifies the usb bus address for the usb 2.0 hub. 0x00 r/w addr 6:0 july 03, 2014 1026 texas instruments-production data universal serial bus (usb) controller register 115: usb receive hub port endpoint 1 (usbrxhubport1), offset 0x08f register 116: usb receive hub port endpoint 2 (usbrxhubport2), offset 0x097 register 117: usb receive hub port endpoint 3 (usbrxhubport3), offset 0x09f register 118: usb receive hub port endpoint 4 (usbrxhubport4), offset 0x0a7 register 119: usb receive hub port endpoint 5 (usbrxhubport5), offset 0x0af register 120: usb receive hub port endpoint 6 (usbrxhubport6), offset 0x0b7 register 121: usb receive hub port endpoint 7 (usbrxhubport7), offset 0x0bf register 122: usb receive hub port endpoint 8 (usbrxhubport8), offset 0x0c7 register 123: usb receive hub port endpoint 9 (usbrxhubport9), offset 0x0cf register 124: usb receive hub port endpoint 10 (usbrxhubport10), offset 0x0d7 register 125: usb receive hub port endpoint 11 (usbrxhubport11), offset 0x0df register 126: usb receive hub port endpoint 12 (usbrxhubport12), offset 0x0e7 register 127: usb receive hub port endpoint 13 (usbrxhubport13), offset 0x0ef register 128: usb receive hub port endpoint 14 (usbrxhubport14), offset 0x0f7 register 129: usb receive hub port endpoint 15 (usbrxhubport15), offset 0x0ff otg a / host usbrxhubportn is an 8-bit read/write register that, like usbrxhubaddrn , only must be written when a full- or low-speed device is connected to receive endpoint epn via a usb 2.0 hub. this register records the port of the usb 2.0 hub through which the target associated with the endpoint is accessed. note: usbtxhubport0 is used for both receive and transmit for endpoint 0. 1027 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller usb receive hub port endpoint 1 (usbrxhubport1) base 0x4005.0000 offset 0x08f type r/w, reset 0x00 0 1 2 3 4 5 6 7 port reserved r/w r/w r/w r/w r/w r/w r/w ro type 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7 hub port this field specifies the usb hub port number. 0x00 r/w port 6:0 july 03, 2014 1028 texas instruments-production data universal serial bus (usb) controller register 130: usb maximum transmit data endpoint 1 (usbtxmaxp1), offset 0x110 register 131: usb maximum transmit data endpoint 2 (usbtxmaxp2), offset 0x120 register 132: usb maximum transmit data endpoint 3 (usbtxmaxp3), offset 0x130 register 133: usb maximum transmit data endpoint 4 (usbtxmaxp4), offset 0x140 register 134: usb maximum transmit data endpoint 5 (usbtxmaxp5), offset 0x150 register 135: usb maximum transmit data endpoint 6 (usbtxmaxp6), offset 0x160 register 136: usb maximum transmit data endpoint 7 (usbtxmaxp7), offset 0x170 register 137: usb maximum transmit data endpoint 8 (usbtxmaxp8), offset 0x180 register 138: usb maximum transmit data endpoint 9 (usbtxmaxp9), offset 0x190 register 139: usb maximum transmit data endpoint 10 (usbtxmaxp10), offset 0x1a0 register 140: usb maximum transmit data endpoint 11 (usbtxmaxp11), offset 0x1b0 register 141: usb maximum transmit data endpoint 12 (usbtxmaxp12), offset 0x1c0 register 142: usb maximum transmit data endpoint 13 (usbtxmaxp13), offset 0x1d0 register 143: usb maximum transmit data endpoint 14 (usbtxmaxp14), offset 0x1e0 register 144: usb maximum transmit data endpoint 15 (usbtxmaxp15), offset 0x1f0 otg a / host otg b / device the usbtxmaxpn 16-bit register defines the maximum amount of data that can be transferred through the transmit endpoint in a single operation. bits 10:0 define (in bytes) the maximum payload transmitted in a single transaction. the value set can be up to 1024 bytes but is subject to the constraints placed by the usb specification on packet sizes for bulk, interrupt and isochronous transfers in full-speed operation. the total amount of data represented by the value written to this register must not exceed the fifo size for the transmit endpoint, and must not exceed half the fifo size if double-buffering is required. 1029 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller if this register is changed after packets have been sent from the endpoint, the transmit endpoint fifo must be completely flushed (using the flush bit in usbtxcsrln ) after writing the new value to this register. note: usbtxmaxpn must be set to an even number of bytes for proper interrupt generation in dma basic mode. usb maximum transmit data endpoint 1 (usbtxmaxp1) base 0x4005.0000 offset 0x110 type r/w, reset 0x0000 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 maxload reserved r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 15:11 maximum payload this field specifies the maximum payload in bytes per transaction. 0x000 r/w maxload 10:0 july 03, 2014 1030 texas instruments-production data universal serial bus (usb) controller register 145: usb control and status endpoint 0 low (usbcsrl0), offset 0x102 otg a / host otg b / device usbcsrl0 is an 8-bit register that provides control and status bits for endpoint 0. otg a / host mode usb control and status endpoint 0 low (usbcsrl0) base 0x4005.0000 offset 0x102 type w1c, reset 0x00 0 1 2 3 4 5 6 7 rxrdy txrdy stalled setup error reqpkt status nakto r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 reset description reset type name bit/field nak timeout description value no timeout. 0 indicates that endpoint 0 is halted following the receipt of nak responses for longer than the time set by the usbnaklmt register. 1 software must clear this bit to allow the endpoint to continue. 0 r/w nakto 7 status packet description value no transaction. 0 initiates a status stage transaction. this bit must be set at the same time as the txrdy or reqpkt bit is set. 1 setting this bit ensures that the dt bit is set in the usbcsrh0 register so that a data1 packet is used for the status stage transaction. this bit is automatically cleared when the status stage is over. 0 r/w status 6 request packet description value no request. 0 requests an in transaction. 1 this bit is cleared when the rxrdy bit is set. 0 r/w reqpkt 5 1031 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field error description value no error. 0 three attempts have been made to perform a transaction with no response from the peripheral. the ep0 bit in the usbtxis register is also set in this situation. 1 software must clear this bit. 0 r/w error 4 setup packet description value sends an out token. 0 sends a setup token instead of an out token for the transaction. this bit should be set at the same time as the txrdy bit is set. 1 setting this bit always clears the dt bit in the usbcsrh0 register to send a data0 packet. 0 r/w setup 3 endpoint stalled description value no handshake has been received. 0 a stall handshake has been received. 1 software must clear this bit. 0 r/w stalled 2 transmit packet ready description value no transmit packet is ready. 0 software sets this bit after loading a data packet into the tx fifo. the ep0 bit in the usbtxis register is also set in this situation. if both the txrdy and setup bits are set, a setup packet is sent. if just txrdy is set, an out packet is sent. 1 this bit is cleared automatically when the data packet has been transmitted. 0 r/w txrdy 1 receive packet ready description value no received packet has been received. 0 indicates that a data packet has been received in the rx fifo. the ep0 bit in the usbtxis register is also set in this situation. 1 software must clear this bit after the packet has been read from the fifo to acknowledge that the data has been read from the fifo. 0 r/w rxrdy 0 july 03, 2014 1032 texas instruments-production data universal serial bus (usb) controller otg b / device mode usb control and status endpoint 0 low (usbcsrl0) base 0x4005.0000 offset 0x102 type w1c, reset 0x00 0 1 2 3 4 5 6 7 rxrdy txrdy stalled dataend setend stall rxrdyc setendc ro r/w r/w r/w ro r/w w1c w1c type 0 0 0 0 0 0 0 0 reset description reset type name bit/field setup end clear writing a 1 to this bit clears the setend bit. 0 w1c setendc 7 rxrdy clear writing a 1 to this bit clears the rxrdy bit. 0 w1c rxrdyc 6 send stall description value no effect. 0 terminates the current transaction and transmits the stall handshake. 1 this bit is cleared automatically after the stall handshake is transmitted. 0 r/w stall 5 setup end description value a control transaction has not ended or ended after the dataend bit was set. 0 a control transaction has ended before the dataend bit has been set. the ep0 bit in the usbtxis register is also set in this situation. 1 this bit is cleared by writing a 1 to the setendc bit. 0 ro setend 4 data end description value no effect. 0 set this bit in the following situations: 1 when setting txrdy for the last data packet when clearing rxrdy after unloading the last data packet when setting txrdy for a zero-length data packet this bit is cleared automatically. 0 r/w dataend 3 1033 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field endpoint stalled description value a stall handshake has not been transmitted. 0 a stall handshake has been transmitted. 1 software must clear this bit. 0 r/w stalled 2 transmit packet ready description value no transmit packet is ready. 0 software sets this bit after loading an in data packet into the tx fifo. the ep0 bit in the usbtxis register is also set in this situation. 1 this bit is cleared automatically when the data packet has been transmitted. 0 r/w txrdy 1 receive packet ready description value no data packet has been received. 0 a data packet has been received. the ep0 bit in the usbtxis register is also set in this situation. 1 this bit is cleared by writing a 1 to the rxrdyc bit. 0 ro rxrdy 0 july 03, 2014 1034 texas instruments-production data universal serial bus (usb) controller register 146: usb control and status endpoint 0 high (usbcsrh0), offset 0x103 otg a / host otg b / device usbsr0h is an 8-bit register that provides control and status bits for endpoint 0. otg a / host mode usb control and status endpoint 0 high (usbcsrh0) base 0x4005.0000 offset 0x103 type w1c, reset 0x00 0 1 2 3 4 5 6 7 flush dt dtwe reserved r/w r/w r/w ro ro ro ro ro type 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 7:3 data toggle write enable description value the dt bit cannot be written. 0 enables the current state of the endpoint 0 data toggle to be written (see dt bit). 1 this bit is automatically cleared once the new value is written. 0 r/w dtwe 2 data toggle when read, this bit indicates the current state of the endpoint 0 data toggle. if dtwe is set, this bit may be written with the required setting of the data toggle. if dtwe is low, this bit cannot be written. care should be taken when writing to this bit as it should only be changed to reset usb endpoint 0. 0 r/w dt 1 1035 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field flush fifo description value no effect. 0 flushes the next packet to be transmitted/read from the endpoint 0 fifo. the fifo pointer is reset and the txrdy/ rxrdy bit is cleared. 1 this bit is automatically cleared after the flush is performed. important: this bit should only be set when txrdy is clear and rxrdy is set. at other times, it may cause data to be corrupted. 0 r/w flush 0 otg b / device mode usb control and status endpoint 0 high (usbcsrh0) base 0x4005.0000 offset 0x103 type w1c, reset 0x00 0 1 2 3 4 5 6 7 flush reserved r/w ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 7:1 flush fifo description value no effect. 0 flushes the next packet to be transmitted/read from the endpoint 0 fifo. the fifo pointer is reset and the txrdy/ rxrdy bit is cleared. 1 this bit is automatically cleared after the flush is performed. important: this bit should only be set when txrdy is clear and rxrdy is set. at other times, it may cause data to be corrupted. 0 r/w flush 0 july 03, 2014 1036 texas instruments-production data universal serial bus (usb) controller register 147: usb receive byte count endpoint 0 (usbcount0), offset 0x108 otg a / host otg b / device usbcount0 is an 8-bit read-only register that indicates the number of received data bytes in the endpoint 0 fifo. the value returned changes as the contents of the fifo change and is only valid while the rxrdy bit is set. usb receive byte count endpoint 0 (usbcount0) base 0x4005.0000 offset 0x108 type ro, reset 0x00 01234567 count reserved ro ro ro ro ro ro ro ro type 00000000 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7 fifo count count is a read-only value that indicates the number of received data bytes in the endpoint 0 fifo. 0x00 ro count 6:0 1037 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 148: usb type endpoint 0 (usbtype0), offset 0x10a otg a / host this is an 8-bit register that must be written with the operating speed of the targeted device being communicated with using endpoint 0. usb type endpoint 0 (usbtype0) base 0x4005.0000 offset 0x10a type r/w, reset 0x00 0 1 2 3 4 5 6 7 reserved speed ro ro ro ro ro ro r/w r/w type 0 0 0 0 0 0 0 0 reset description reset type name bit/field operating speed this field specifies the operating speed of the target device. if selected, the target is assumed to have the same connection speed as the usb controller. description value reserved 0x0 - 0x1 full 0x2 low 0x3 0x0 r/w speed 7:6 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 5:0 july 03, 2014 1038 texas instruments-production data universal serial bus (usb) controller register 149: usb nak limit (usbnaklmt), offset 0x10b otg a / host usbnaklmt is an 8-bit register that sets the number of frames after which endpoint 0 should time out on receiving a stream of nak responses. (equivalent settings for other endpoints can be made through their usbtxintervaln and usbrxintervaln registers.) the number of frames selected is 2 (m-1) (where m is the value set in the register, with valid values of 2C16). if the host receives nak responses from the target for more frames than the number represented by the limit set in this register, the endpoint is halted. note: a value of 0 or 1 disables the nak timeout function. usb nak limit (usbnaklmt) base 0x4005.0000 offset 0x10b type r/w, reset 0x00 0 1 2 3 4 5 6 7 naklmt reserved r/w r/w r/w r/w r/w ro ro ro type 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 7:5 ep0 nak limit this field specifies the number of frames after receiving a stream of nak responses. 0x0 r/w naklmt 4:0 1039 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 150: usb transmit control and status endpoint 1 low (usbtxcsrl1), offset 0x112 register 151: usb transmit control and status endpoint 2 low (usbtxcsrl2), offset 0x122 register 152: usb transmit control and status endpoint 3 low (usbtxcsrl3), offset 0x132 register 153: usb transmit control and status endpoint 4 low (usbtxcsrl4), offset 0x142 register 154: usb transmit control and status endpoint 5 low (usbtxcsrl5), offset 0x152 register 155: usb transmit control and status endpoint 6 low (usbtxcsrl6), offset 0x162 register 156: usb transmit control and status endpoint 7 low (usbtxcsrl7), offset 0x172 register 157: usb transmit control and status endpoint 8 low (usbtxcsrl8), offset 0x182 register 158: usb transmit control and status endpoint 9 low (usbtxcsrl9), offset 0x192 register 159: usb transmit control and status endpoint 10 low (usbtxcsrl10), offset 0x1a2 register 160: usb transmit control and status endpoint 11 low (usbtxcsrl11), offset 0x1b2 register 161: usb transmit control and status endpoint 12 low (usbtxcsrl12), offset 0x1c2 register 162: usb transmit control and status endpoint 13 low (usbtxcsrl13), offset 0x1d2 register 163: usb transmit control and status endpoint 14 low (usbtxcsrl14), offset 0x1e2 register 164: usb transmit control and status endpoint 15 low (usbtxcsrl15), offset 0x1f2 otg a / host otg b / device usbtxcsrln is an 8-bit register that provides control and status bits for transfers through the currently selected transmit endpoint. july 03, 2014 1040 texas instruments-production data universal serial bus (usb) controller otg a / host mode usb transmit control and status endpoint 1 low (usbtxcsrl1) base 0x4005.0000 offset 0x112 type r/w, reset 0x00 0 1 2 3 4 5 6 7 txrdy fifone error flush setup stalled clrdt nakto r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 reset description reset type name bit/field nak timeout description value no timeout. 0 bulk endpoints only: indicates that the transmit endpoint is halted following the receipt of nak responses for longer than the time set by the naklmt field in the usbtxintervaln register. software must clear this bit to allow the endpoint to continue. 1 0 r/w nakto 7 clear data toggle writing a 1 to this bit clears the dt bit in the usbtxcsrhn register. 0 r/w clrdt 6 endpoint stalled description value a stall handshake has not been received. 0 indicates that a stall handshake has been received. when this bit is set, any dma request that is in progress is stopped, the fifo is completely flushed, and the txrdy bit is cleared. 1 software must clear this bit. 0 r/w stalled 5 setup packet description value no setup token is sent. 0 sends a setup token instead of an out token for the transaction. this bit should be set at the same time as the txrdy bit is set. 1 note: setting this bit also clears the dt bit in the usbtxcsrhn register. 0 r/w setup 4 1041 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field flush fifo description value no effect. 0 flushes the latest packet from the endpoint transmit fifo. the fifo pointer is reset and the txrdy bit is cleared. the epn bit in the usbtxis register is also set in this situation. 1 this bit may be set simultaneously with the txrdy bit to abort the packet that is currently being loaded into the fifo. note that if the fifo is double-buffered, flush may have to be set twice to completely clear the fifo. important: this bit should only be set when the txrdy bit is clear. at other times, it may cause data to be corrupted. 0 r/w flush 3 error description value no error. 0 three attempts have been made to send a packet and no handshake packet has been received. the txrdy bit is cleared, the epn bit in the usbtxis register is set, and the fifo is completely flushed in this situation. 1 software must clear this bit. note: this is valid only when the endpoint is operating in bulk or interrupt mode. 0 r/w error 2 fifo not empty description value the fifo is empty. 0 at least one packet is in the transmit fifo. 1 0 r/w fifone 1 transmit packet ready description value no transmit packet is ready. 0 software sets this bit after loading a data packet into the tx fifo. 1 this bit is cleared automatically when a data packet has been transmitted. the epn bit in the usbtxis register is also set at this point. txrdy is also automatically cleared prior to loading a second packet into a double-buffered fifo. 0 r/w txrdy 0 july 03, 2014 1042 texas instruments-production data universal serial bus (usb) controller otg b / device mode usb transmit control and status endpoint 1 low (usbtxcsrl1) base 0x4005.0000 offset 0x112 type r/w, reset 0x00 0 1 2 3 4 5 6 7 txrdy fifone undrn flush stall stalled clrdt reserved r/w r/w r/w r/w r/w r/w r/w ro type 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7 clear data toggle writing a 1 to this bit clears the dt bit in the usbtxcsrhn register. 0 r/w clrdt 6 endpoint stalled description value a stall handshake has not been transmitted. 0 a stall handshake has been transmitted. the fifo is flushed and the txrdy bit is cleared. 1 software must clear this bit. 0 r/w stalled 5 send stall description value no effect. 0 issues a stall handshake to an in token. 1 software clears this bit to terminate the stall condition. note: this bit has no effect in isochronous transfers. 0 r/w stall 4 flush fifo description value no effect. 0 flushes the latest packet from the endpoint transmit fifo. the fifo pointer is reset and the txrdy bit is cleared. the epn bit in the usbtxis register is also set in this situation. 1 this bit may be set simultaneously with the txrdy bit to abort the packet that is currently being loaded into the fifo. note that if the fifo is double-buffered, flush may have to be set twice to completely clear the fifo. important: this bit should only be set when the txrdy bit is clear. at other times, it may cause data to be corrupted. 0 r/w flush 3 1043 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field underrun description value no underrun. 0 an in token has been received when txrdy is not set. 1 software must clear this bit. 0 r/w undrn 2 fifo not empty description value the fifo is empty. 0 at least one packet is in the transmit fifo. 1 0 r/w fifone 1 transmit packet ready description value no transmit packet is ready. 0 software sets this bit after loading a data packet into the tx fifo. 1 this bit is cleared automatically when a data packet has been transmitted. the epn bit in the usbtxis register is also set at this point. txrdy is also automatically cleared prior to loading a second packet into a double-buffered fifo. 0 r/w txrdy 0 july 03, 2014 1044 texas instruments-production data universal serial bus (usb) controller register 165: usb transmit control and status endpoint 1 high (usbtxcsrh1), offset 0x113 register 166: usb transmit control and status endpoint 2 high (usbtxcsrh2), offset 0x123 register 167: usb transmit control and status endpoint 3 high (usbtxcsrh3), offset 0x133 register 168: usb transmit control and status endpoint 4 high (usbtxcsrh4), offset 0x143 register 169: usb transmit control and status endpoint 5 high (usbtxcsrh5), offset 0x153 register 170: usb transmit control and status endpoint 6 high (usbtxcsrh6), offset 0x163 register 171: usb transmit control and status endpoint 7 high (usbtxcsrh7), offset 0x173 register 172: usb transmit control and status endpoint 8 high (usbtxcsrh8), offset 0x183 register 173: usb transmit control and status endpoint 9 high (usbtxcsrh9), offset 0x193 register 174: usb transmit control and status endpoint 10 high (usbtxcsrh10), offset 0x1a3 register 175: usb transmit control and status endpoint 11 high (usbtxcsrh11), offset 0x1b3 register 176: usb transmit control and status endpoint 12 high (usbtxcsrh12), offset 0x1c3 register 177: usb transmit control and status endpoint 13 high (usbtxcsrh13), offset 0x1d3 register 178: usb transmit control and status endpoint 14 high (usbtxcsrh14), offset 0x1e3 register 179: usb transmit control and status endpoint 15 high (usbtxcsrh15), offset 0x1f3 otg a / host otg b / device usbtxcsrhn is an 8-bit register that provides additional control for transfers through the currently selected transmit endpoint. 1045 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller otg a / host mode usb transmit control and status endpoint 1 high (usbtxcsrh1) base 0x4005.0000 offset 0x113 type r/w, reset 0x00 0 1 2 3 4 5 6 7 dt dtwe dmamod fdt dmaen mode reserved autoset r/w r/w r/w r/w r/w r/w ro r/w type 0 0 0 0 0 0 0 0 reset description reset type name bit/field auto set description value the txrdy bit must be set manually. 0 enables the txrdy bit to be automatically set when data of the maximum packet size (value in usbtxmaxpn ) is loaded into the transmit fifo. if a packet of less than the maximum packet size is loaded, then the txrdy bit must be set manually. 1 0 r/w autoset 7 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 6 mode description value enables the endpoint direction as rx. 0 enables the endpoint direction as tx. 1 note: this bit only has an effect when the same endpoint fifo is used for both transmit and receive transactions. 0 r/w mode 5 dma request enable description value disables the dma request for the transmit endpoint. 0 enables the dma request for the transmit endpoint. 1 note: 3 tx and 3 /rx endpoints can be connected to the dma module. if this bit is set for a particular endpoint, the dmaatx, dmabtx , or dmactx field in the usb dma select (usbdmasel) register must be programmed correspondingly. 0 r/w dmaen 4 force data toggle description value no effect. 0 forces the endpoint dt bit to switch and the data packet to be cleared from the fifo, regardless of whether an ack was received. this bit can be used by interrupt transmit endpoints that are used to communicate rate feedback for isochronous endpoints. 1 0 r/w fdt 3 july 03, 2014 1046 texas instruments-production data universal serial bus (usb) controller description reset type name bit/field dma request mode description value an interrupt is generated after every dma packet transfer. 0 an interrupt is generated only after the entire dma transfer is complete. 1 note: this bit must not be cleared either before or in the same cycle as the above dmaen bit is cleared. 0 r/w dmamod 2 data toggle write enable description value the dt bit cannot be written. 0 enables the current state of the transmit endpoint data to be written (see dt bit). 1 this bit is automatically cleared once the new value is written. 0 r/w dtwe 1 data toggle when read, this bit indicates the current state of the transmit endpoint data toggle. if dtwe is high, this bit may be written with the required setting of the data toggle. if dtwe is low, any value written to this bit is ignored. care should be taken when writing to this bit as it should only be changed to reset the transmit endpoint. 0 r/w dt 0 otg b / device mode usb transmit control and status endpoint 1 high (usbtxcsrh1) base 0x4005.0000 offset 0x113 type r/w, reset 0x00 0 1 2 3 4 5 6 7 reserved dmamod fdt dmaen mode iso autoset ro ro r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 reset description reset type name bit/field auto set description value the txrdy bit must be set manually. 0 enables the txrdy bit to be automatically set when data of the maximum packet size (value in usbtxmaxpn ) is loaded into the transmit fifo. if a packet of less than the maximum packet size is loaded, then the txrdy bit must be set manually. 1 0 r/w autoset 7 1047 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field isochronous transfers description value enables the transmit endpoint for bulk or interrupt transfers. 0 enables the transmit endpoint for isochronous transfers. 1 0 r/w iso 6 mode description value enables the endpoint direction as rx. 0 enables the endpoint direction as tx. 1 note: this bit only has an effect where the same endpoint fifo is used for both transmit and receive transactions. 0 r/w mode 5 dma request enable description value disables the dma request for the transmit endpoint. 0 enables the dma request for the transmit endpoint. 1 note: 3 tx and 3 rx endpoints can be connected to the dma module. if this bit is set for a particular endpoint, the dmaatx, dmabtx , or dmactx field in the usb dma select (usbdmasel) register must be programmed correspondingly. 0 r/w dmaen 4 force data toggle description value no effect. 0 forces the endpoint dt bit to switch and the data packet to be cleared from the fifo, regardless of whether an ack was received. this bit can be used by interrupt transmit endpoints that are used to communicate rate feedback for isochronous endpoints. 1 0 r/w fdt 3 dma request mode description value an interrupt is generated after every dma packet transfer. 0 an interrupt is generated only after the entire dma transfer is complete. 1 note: this bit must not be cleared either before or in the same cycle as the above dmaen bit is cleared. 0 r/w dmamod 2 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 1:0 july 03, 2014 1048 texas instruments-production data universal serial bus (usb) controller register 180: usb maximum receive data endpoint 1 (usbrxmaxp1), offset 0x114 register 181: usb maximum receive data endpoint 2 (usbrxmaxp2), offset 0x124 register 182: usb maximum receive data endpoint 3 (usbrxmaxp3), offset 0x134 register 183: usb maximum receive data endpoint 4 (usbrxmaxp4), offset 0x144 register 184: usb maximum receive data endpoint 5 (usbrxmaxp5), offset 0x154 register 185: usb maximum receive data endpoint 6 (usbrxmaxp6), offset 0x164 register 186: usb maximum receive data endpoint 7 (usbrxmaxp7), offset 0x174 register 187: usb maximum receive data endpoint 8 (usbrxmaxp8), offset 0x184 register 188: usb maximum receive data endpoint 9 (usbrxmaxp9), offset 0x194 register 189: usb maximum receive data endpoint 10 (usbrxmaxp10), offset 0x1a4 register 190: usb maximum receive data endpoint 11 (usbrxmaxp11), offset 0x1b4 register 191: usb maximum receive data endpoint 12 (usbrxmaxp12), offset 0x1c4 register 192: usb maximum receive data endpoint 13 (usbrxmaxp13), offset 0x1d4 register 193: usb maximum receive data endpoint 14 (usbrxmaxp14), offset 0x1e4 register 194: usb maximum receive data endpoint 15 (usbrxmaxp15), offset 0x1f4 otg a / host otg b / device the usbrxmaxpn is a 16-bit register which defines the maximum amount of data that can be transferred through the selected receive endpoint in a single operation. bits 10:0 define (in bytes) the maximum payload transmitted in a single transaction. the value set can be up to 1024 bytes but is subject to the constraints placed by the usb specification on packet sizes for bulk, interrupt and isochronous transfers in full-speed operations. the total amount of data represented by the value written to this register must not exceed the fifo size for the receive endpoint, and must not exceed half the fifo size if double-buffering is required. 1049 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller note: usbrxmaxpn must be set to an even number of bytes for proper interrupt generation in dma basic mode. usb maximum receive data endpoint 1 (usbrxmaxp1) base 0x4005.0000 offset 0x114 type r/w, reset 0x0000 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 maxload reserved r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 15:11 maximum payload the maximum payload in bytes per transaction. 0x000 r/w maxload 10:0 july 03, 2014 1050 texas instruments-production data universal serial bus (usb) controller register 195: usb receive control and status endpoint 1 low (usbrxcsrl1), offset 0x116 register 196: usb receive control and status endpoint 2 low (usbrxcsrl2), offset 0x126 register 197: usb receive control and status endpoint 3 low (usbrxcsrl3), offset 0x136 register 198: usb receive control and status endpoint 4 low (usbrxcsrl4), offset 0x146 register 199: usb receive control and status endpoint 5 low (usbrxcsrl5), offset 0x156 register 200: usb receive control and status endpoint 6 low (usbrxcsrl6), offset 0x166 register 201: usb receive control and status endpoint 7 low (usbrxcsrl7), offset 0x176 register 202: usb receive control and status endpoint 8 low (usbrxcsrl8), offset 0x186 register 203: usb receive control and status endpoint 9 low (usbrxcsrl9), offset 0x196 register 204: usb receive control and status endpoint 10 low (usbrxcsrl10), offset 0x1a6 register 205: usb receive control and status endpoint 11 low (usbrxcsrl11), offset 0x1b6 register 206: usb receive control and status endpoint 12 low (usbrxcsrl12), offset 0x1c6 register 207: usb receive control and status endpoint 13 low (usbrxcsrl13), offset 0x1d6 register 208: usb receive control and status endpoint 14 low (usbrxcsrl14), offset 0x1e6 register 209: usb receive control and status endpoint 15 low (usbrxcsrl15), offset 0x1f6 otg a / host otg b / device usbrxcsrln is an 8-bit register that provides control and status bits for transfers through the currently selected receive endpoint. 1051 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller otg a / host mode usb receive control and status endpoint 1 low (usbrxcsrl1) base 0x4005.0000 offset 0x116 type r/w, reset 0x00 0 1 2 3 4 5 6 7 rxrdy full error dataerr / nakto flush reqpkt stalled clrdt r/w ro r/w r/w r/w r/w r/w w1c type 0 0 0 0 0 0 0 0 reset description reset type name bit/field clear data toggle writing a 1 to this bit clears the dt bit in the usbrxcsrhn register. 0 w1c clrdt 7 endpoint stalled description value a stall handshake has not been received. 0 a stall handshake has been received. the epn bit in the usbrxis register is also set. 1 software must clear this bit. 0 r/w stalled 6 request packet description value no request. 0 requests an in transaction. 1 this bit is cleared when rxrdy is set. 0 r/w reqpkt 5 flush fifo description value no effect. 0 flushes the next packet to be read from the endpoint receive fifo. the fifo pointer is reset and the rxrdy bit is cleared. 1 note that if the fifo is double-buffered, flush may have to be set twice to completely clear the fifo. important: this bit should only be set when the rxrdy bit is set. at other times, it may cause data to be corrupted. 0 r/w flush 4 july 03, 2014 1052 texas instruments-production data universal serial bus (usb) controller description reset type name bit/field data error / nak timeout description value normal operation. 0 isochronous endpoints only: indicates that rxrdy is set and the data packet has a crc or bit-stuff error. this bit is cleared when rxrdy is cleared. bulk endpoints only: indicates that the receive endpoint is halted following the receipt of nak responses for longer than the time set by the naklmt field in the usbrxintervaln register. software must clear this bit to allow the endpoint to continue. 1 0 r/w dataerr / nakto 3 error description value no error. 0 three attempts have been made to receive a packet and no data packet has been received. the epn bit in the usbrxis register is set in this situation. 1 software must clear this bit. note: this bit is only valid when the receive endpoint is operating in bulk or interrupt mode. in isochronous mode, it always returns zero. 0 r/w error 2 fifo full description value the receive fifo is not full. 0 no more packets can be loaded into the receive fifo. 1 0 ro full 1 receive packet ready description value no data packet has been received. 0 a data packet has been received. the epn bit in the usbrxis register is also set in this situation. 1 if the autoclr bit in the usbrxcsrhn register is set, then the this bit is automatically cleared when a packet of usbrxmaxpn bytes has been unloaded from the receive fifo. if the autoclr bit is clear, or if packets of less than the maximum packet size are unloaded, then software must clear this bit manually when the packet has been unloaded from the receive fifo. 0 r/w rxrdy 0 1053 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller otg b / device mode usb receive control and status endpoint 1 low (usbrxcsrl1) base 0x4005.0000 offset 0x116 type r/w, reset 0x00 0 1 2 3 4 5 6 7 rxrdy full over dataerr flush stall stalled clrdt r/w ro r/w ro r/w r/w r/w w1c type 0 0 0 0 0 0 0 0 reset description reset type name bit/field clear data toggle writing a 1 to this bit clears the dt bit in the usbrxcsrhn register. 0 w1c clrdt 7 endpoint stalled description value a stall handshake has not been transmitted. 0 a stall handshake has been transmitted. 1 software must clear this bit. 0 r/w stalled 6 send stall description value no effect. 0 issues a stall handshake. 1 software must clear this bit to terminate the stall condition. note: this bit has no effect where the endpoint is being used for isochronous transfers. 0 r/w stall 5 flush fifo description value no effect. 0 flushes the next packet from the endpoint receive fifo. the fifo pointer is reset and the rxrdy bit is cleared. 1 the cpu writes a 1 to this bit to flush the next packet to be read from the endpoint receive fifo. the fifo pointer is reset and the rxrdy bit is cleared. note that if the fifo is double-buffered, flush may have to be set twice to completely clear the fifo. important: this bit should only be set when the rxrdy bit is set. at other times, it may cause data to be corrupted. 0 r/w flush 4 july 03, 2014 1054 texas instruments-production data universal serial bus (usb) controller description reset type name bit/field data error description value normal operation. 0 indicates that rxrdy is set and the data packet has a crc or bit-stuff error. 1 this bit is cleared when rxrdy is cleared. note: this bit is only valid when the endpoint is operating in isochronous mode. in bulk mode, it always returns zero. 0 ro dataerr 3 overrun description value no overrun error. 0 indicates that an out packet cannot be loaded into the receive fifo. 1 software must clear this bit. note: this bit is only valid when the endpoint is operating in isochronous mode. in bulk mode, it always returns zero. 0 r/w over 2 fifo full description value the receive fifo is not full. 0 no more packets can be loaded into the receive fifo. 1 0 ro full 1 receive packet ready description value no data packet has been received. 0 a data packet has been received. the epn bit in the usbrxis register is also set in this situation. 1 if the autoclr bit in the usbrxcsrhn register is set, then the this bit is automatically cleared when a packet of usbrxmaxpn bytes has been unloaded from the receive fifo. if the autoclr bit is clear, or if packets of less than the maximum packet size are unloaded, then software must clear this bit manually when the packet has been unloaded from the receive fifo. 0 r/w rxrdy 0 1055 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 210: usb receive control and status endpoint 1 high (usbrxcsrh1), offset 0x117 register 211: usb receive control and status endpoint 2 high (usbrxcsrh2), offset 0x127 register 212: usb receive control and status endpoint 3 high (usbrxcsrh3), offset 0x137 register 213: usb receive control and status endpoint 4 high (usbrxcsrh4), offset 0x147 register 214: usb receive control and status endpoint 5 high (usbrxcsrh5), offset 0x157 register 215: usb receive control and status endpoint 6 high (usbrxcsrh6), offset 0x167 register 216: usb receive control and status endpoint 7 high (usbrxcsrh7), offset 0x177 register 217: usb receive control and status endpoint 8 high (usbrxcsrh8), offset 0x187 register 218: usb receive control and status endpoint 9 high (usbrxcsrh9), offset 0x197 register 219: usb receive control and status endpoint 10 high (usbrxcsrh10), offset 0x1a7 register 220: usb receive control and status endpoint 11 high (usbrxcsrh11), offset 0x1b7 register 221: usb receive control and status endpoint 12 high (usbrxcsrh12), offset 0x1c7 register 222: usb receive control and status endpoint 13 high (usbrxcsrh13), offset 0x1d7 register 223: usb receive control and status endpoint 14 high (usbrxcsrh14), offset 0x1e7 register 224: usb receive control and status endpoint 15 high (usbrxcsrh15), offset 0x1f7 otg a / host otg b / device usbrxcsrhn is an 8-bit register that provides additional control and status bits for transfers through the currently selected receive endpoint. july 03, 2014 1056 texas instruments-production data universal serial bus (usb) controller otg a / host mode usb receive control and status endpoint 1 high (usbrxcsrh1) base 0x4005.0000 offset 0x117 type r/w, reset 0x00 0 1 2 3 4 5 6 7 reserved dt dtwe dmamod piderr dmaen autorq autocl ro ro ro r/w ro r/w r/w r/w type 0 0 0 0 0 0 0 0 reset description reset type name bit/field auto clear description value no effect. 0 enables the rxrdy bit to be automatically cleared when a packet of usbrxmaxpn bytes has been unloaded from the receive fifo. when packets of less than the maximum packet size are unloaded, rxrdy must be cleared manually. care must be taken when using dma to unload the receive fifo as data is read from the receive fifo in 4 byte chunks regardless of the value of the maxload field in the usbrxmaxpn register, see dma operation on page 971. 1 0 r/w autocl 7 auto request description value no effect. 0 enables the reqpkt bit to be automatically set when the rxrdy bit is cleared. 1 note: this bit is automatically cleared when a short packet is received. 0 r/w autorq 6 dma request enable description value disables the dma request for the receive endpoint. 0 enables the dma request for the receive endpoint. 1 note: 3 tx and 3 rx endpoints can be connected to the dma module. if this bit is set for a particular endpoint, the dmaarx, dmabrx , or dmacrx field in the usb dma select (usbdmasel) register must be programmed correspondingly. 0 r/w dmaen 5 pid error description value no error. 0 indicates a pid error in the received packet of an isochronous transaction. 1 this bit is ignored in bulk or interrupt transactions. 0 ro piderr 4 1057 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field dma request mode description value an interrupt is generated after every dma packet transfer. 0 an interrupt is generated only after the entire dma transfer is complete. 1 note: this bit must not be cleared either before or in the same cycle as the above dmaen bit is cleared. 0 r/w dmamod 3 data toggle write enable description value the dt bit cannot be written. 0 enables the current state of the receive endpoint data to be written (see dt bit). 1 this bit is automatically cleared once the new value is written. 0 ro dtwe 2 data toggle when read, this bit indicates the current state of the receive data toggle. if dtwe is high, this bit may be written with the required setting of the data toggle. if dtwe is low, any value written to this bit is ignored. care should be taken when writing to this bit as it should only be changed to reset the receive endpoint. 0 ro dt 1 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 0 otg b / device mode usb receive control and status endpoint 1 high (usbrxcsrh1) base 0x4005.0000 offset 0x117 type r/w, reset 0x00 0 1 2 3 4 5 6 7 reserved dmamod disnyet / piderr dmaen iso autocl ro ro ro r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 reset july 03, 2014 1058 texas instruments-production data universal serial bus (usb) controller description reset type name bit/field auto clear description value no effect. 0 enables the rxrdy bit to be automatically cleared when a packet of usbrxmaxpn bytes has been unloaded from the receive fifo. when packets of less than the maximum packet size are unloaded, rxrdy must be cleared manually. care must be taken when using dma to unload the receive fifo as data is read from the receive fifo in 4 byte chunks regardless of the value of the maxload field in the usbrxmaxpn register, see dma operation on page 971. 1 0 r/w autocl 7 isochronous transfers description value enables the receive endpoint for isochronous transfers. 0 enables the receive endpoint for bulk/interrupt transfers. 1 0 r/w iso 6 dma request enable description value disables the dma request for the receive endpoint. 0 enables the dma request for the receive endpoint. 1 note: 3 tx and 3 rx endpoints can be connected to the dma module. if this bit is set for a particular endpoint, the dmaarx, dmabrx , or dmacrx field in the usb dma select (usbdmasel) register must be programmed correspondingly. 0 r/w dmaen 5 disable nyet / pid error description value no effect. 0 for bulk or interrupt transactions: disables the sending of nyet handshakes. when this bit is set, all successfully received packets are acknowledged, including at the point at which the fifo becomes full. for isochronous transactions: indicates a pid error in the received packet. 1 0 r/w disnyet / piderr 4 dma request mode description value an interrupt is generated after every dma packet transfer. 0 an interrupt is generated only after the entire dma transfer is complete. 1 note: this bit must not be cleared either before or in the same cycle as the above dmaen bit is cleared. 0 r/w dmamod 3 1059 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 2:0 july 03, 2014 1060 texas instruments-production data universal serial bus (usb) controller register 225: usb receive byte count endpoint 1 (usbrxcount1), offset 0x118 register 226: usb receive byte count endpoint 2 (usbrxcount2), offset 0x128 register 227: usb receive byte count endpoint 3 (usbrxcount3), offset 0x138 register 228: usb receive byte count endpoint 4 (usbrxcount4), offset 0x148 register 229: usb receive byte count endpoint 5 (usbrxcount5), offset 0x158 register 230: usb receive byte count endpoint 6 (usbrxcount6), offset 0x168 register 231: usb receive byte count endpoint 7 (usbrxcount7), offset 0x178 register 232: usb receive byte count endpoint 8 (usbrxcount8), offset 0x188 register 233: usb receive byte count endpoint 9 (usbrxcount9), offset 0x198 register 234: usb receive byte count endpoint 10 (usbrxcount10), offset 0x1a8 register 235: usb receive byte count endpoint 11 (usbrxcount11), offset 0x1b8 register 236: usb receive byte count endpoint 12 (usbrxcount12), offset 0x1c8 register 237: usb receive byte count endpoint 13 (usbrxcount13), offset 0x1d8 register 238: usb receive byte count endpoint 14 (usbrxcount14), offset 0x1e8 register 239: usb receive byte count endpoint 15 (usbrxcount15), offset 0x1f8 otg a / host otg b / device note: the value returned changes as the fifo is unloaded and is only valid while the rxrdy bit in the usbrxcsrln register is set. usbrxcountn is a 16-bit read-only register that holds the number of data bytes in the packet currently in line to be read from the receive fifo. if the packet is transmitted as multiple bulk packets, the number given is for the combined packet. 1061 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller usb receive byte count endpoint 1 (usbrxcount1) base 0x4005.0000 offset 0x118 type ro, reset 0x0000 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 count reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 15:13 receive packet count indicates the number of bytes in the receive packet. 0x000 ro count 12:0 july 03, 2014 1062 texas instruments-production data universal serial bus (usb) controller register 240: usb host transmit configure type endpoint 1 (usbtxtype1), offset 0x11a register 241: usb host transmit configure type endpoint 2 (usbtxtype2), offset 0x12a register 242: usb host transmit configure type endpoint 3 (usbtxtype3), offset 0x13a register 243: usb host transmit configure type endpoint 4 (usbtxtype4), offset 0x14a register 244: usb host transmit configure type endpoint 5 (usbtxtype5), offset 0x15a register 245: usb host transmit configure type endpoint 6 (usbtxtype6), offset 0x16a register 246: usb host transmit configure type endpoint 7 (usbtxtype7), offset 0x17a register 247: usb host transmit configure type endpoint 8 (usbtxtype8), offset 0x18a register 248: usb host transmit configure type endpoint 9 (usbtxtype9), offset 0x19a register 249: usb host transmit configure type endpoint 10 (usbtxtype10), offset 0x1aa register 250: usb host transmit configure type endpoint 11 (usbtxtype11), offset 0x1ba register 251: usb host transmit configure type endpoint 12 (usbtxtype12), offset 0x1ca register 252: usb host transmit configure type endpoint 13 (usbtxtype13), offset 0x1da register 253: usb host transmit configure type endpoint 14 (usbtxtype14), offset 0x1ea register 254: usb host transmit configure type endpoint 15 (usbtxtype15), offset 0x1fa otg a / host usbtxtypen is an 8-bit register that must be written with the endpoint number to be targeted by the endpoint, the transaction protocol to use for the currently selected transmit endpoint, and its operating speed. 1063 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller usb host transmit configure type endpoint 1 (usbtxtype1) base 0x4005.0000 offset 0x11a type r/w, reset 0x00 0 1 2 3 4 5 6 7 tep proto speed r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 reset description reset type name bit/field operating speed this bit field specifies the operating speed of the target device: description value default the target is assumed to be using the same connection speed as the usb controller. 0x0 reserved 0x1 full0x2 low0x3 0x0 r/w speed 7:6 protocol software must configure this bit field to select the required protocol for the transmit endpoint: description value control 0x0 isochronous 0x1 bulk 0x2 interrupt 0x3 0x0 r/w proto 5:4 target endpoint number software must configure this value to the endpoint number contained in the transmit endpoint descriptor returned to the usb controller during device enumeration. 0x0 r/w tep 3:0 july 03, 2014 1064 texas instruments-production data universal serial bus (usb) controller register 255: usb host transmit interval endpoint 1 (usbtxinterval1), offset 0x11b register 256: usb host transmit interval endpoint 2 (usbtxinterval2), offset 0x12b register 257: usb host transmit interval endpoint 3 (usbtxinterval3), offset 0x13b register 258: usb host transmit interval endpoint 4 (usbtxinterval4), offset 0x14b register 259: usb host transmit interval endpoint 5 (usbtxinterval5), offset 0x15b register 260: usb host transmit interval endpoint 6 (usbtxinterval6), offset 0x16b register 261: usb host transmit interval endpoint 7 (usbtxinterval7), offset 0x17b register 262: usb host transmit interval endpoint 8 (usbtxinterval8), offset 0x18b register 263: usb host transmit interval endpoint 9 (usbtxinterval9), offset 0x19b register 264: usb host transmit interval endpoint 10 (usbtxinterval10), offset 0x1ab register 265: usb host transmit interval endpoint 11 (usbtxinterval11), offset 0x1bb register 266: usb host transmit interval endpoint 12 (usbtxinterval12), offset 0x1cb register 267: usb host transmit interval endpoint 13 (usbtxinterval13), offset 0x1db register 268: usb host transmit interval endpoint 14 (usbtxinterval14), offset 0x1eb register 269: usb host transmit interval endpoint 15 (usbtxinterval15), offset 0x1fb otg a / host usbtxintervaln is an 8-bit register that, for interrupt and isochronous transfers, defines the polling interval for the currently selected transmit endpoint. for bulk endpoints, this register defines the number of frames after which the endpoint should time out on receiving a stream of nak responses. the usbtxintervaln register value defines a number of frames, as follows: 1065 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller interpretation valid values (m) speed transfer type the polling interval is m frames. 0x01 C 0xff low-speed or full-speed interrupt the polling interval is 2 (m-1) frames. 0x01 C 0x10 full-speed isochronous the nak limit is 2 (m-1) frames. a value of 0 or 1 disables the nak timeout function. 0x02 C 0x10 full-speed bulk usb host transmit interval endpoint 1 (usbtxinterval1) base 0x4005.0000 offset 0x11b type r/w, reset 0x00 0 1 2 3 4 5 6 7 txpoll / naklmt r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 reset description reset type name bit/field tx polling / nak limit the polling interval for interrupt/isochronous transfers; the nak limit for bulk transfers. see table above for valid entries; other values are reserved. 0x00 r/w txpoll / naklmt 7:0 july 03, 2014 1066 texas instruments-production data universal serial bus (usb) controller register 270: usb host configure receive type endpoint 1 (usbrxtype1), offset 0x11c register 271: usb host configure receive type endpoint 2 (usbrxtype2), offset 0x12c register 272: usb host configure receive type endpoint 3 (usbrxtype3), offset 0x13c register 273: usb host configure receive type endpoint 4 (usbrxtype4), offset 0x14c register 274: usb host configure receive type endpoint 5 (usbrxtype5), offset 0x15c register 275: usb host configure receive type endpoint 6 (usbrxtype6), offset 0x16c register 276: usb host configure receive type endpoint 7 (usbrxtype7), offset 0x17c register 277: usb host configure receive type endpoint 8 (usbrxtype8), offset 0x18c register 278: usb host configure receive type endpoint 9 (usbrxtype9), offset 0x19c register 279: usb host configure receive type endpoint 10 (usbrxtype10), offset 0x1ac register 280: usb host configure receive type endpoint 11 (usbrxtype11), offset 0x1bc register 281: usb host configure receive type endpoint 12 (usbrxtype12), offset 0x1cc register 282: usb host configure receive type endpoint 13 (usbrxtype13), offset 0x1dc register 283: usb host configure receive type endpoint 14 (usbrxtype14), offset 0x1ec register 284: usb host configure receive type endpoint 15 (usbrxtype15), offset 0x1fc otg a / host usbrxtypen is an 8-bit register that must be written with the endpoint number to be targeted by the endpoint, the transaction protocol to use for the currently selected receive endpoint, and its operating speed. 1067 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller usb host configure receive type endpoint 1 (usbrxtype1) base 0x4005.0000 offset 0x11c type r/w, reset 0x00 0 1 2 3 4 5 6 7 tep proto speed r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 reset description reset type name bit/field operating speed this bit field specifies the operating speed of the target device: description value default the target is assumed to be using the same connection speed as the usb controller. 0x0 reserved 0x1 full0x2 low0x3 0x0 r/w speed 7:6 protocol software must configure this bit field to select the required protocol for the receive endpoint: description value control 0x0 isochronous 0x1 bulk 0x2 interrupt 0x3 0x0 r/w proto 5:4 target endpoint number software must set this value to the endpoint number contained in the receive endpoint descriptor returned to the usb controller during device enumeration. 0x0 r/w tep 3:0 july 03, 2014 1068 texas instruments-production data universal serial bus (usb) controller register 285: usb host receive polling interval endpoint 1 (usbrxinterval1), offset 0x11d register 286: usb host receive polling interval endpoint 2 (usbrxinterval2), offset 0x12d register 287: usb host receive polling interval endpoint 3 (usbrxinterval3), offset 0x13d register 288: usb host receive polling interval endpoint 4 (usbrxinterval4), offset 0x14d register 289: usb host receive polling interval endpoint 5 (usbrxinterval5), offset 0x15d register 290: usb host receive polling interval endpoint 6 (usbrxinterval6), offset 0x16d register 291: usb host receive polling interval endpoint 7 (usbrxinterval7), offset 0x17d register 292: usb host receive polling interval endpoint 8 (usbrxinterval8), offset 0x18d register 293: usb host receive polling interval endpoint 9 (usbrxinterval9), offset 0x19d register 294: usb host receive polling interval endpoint 10 (usbrxinterval10), offset 0x1ad register 295: usb host receive polling interval endpoint 11 (usbrxinterval11), offset 0x1bd register 296: usb host receive polling interval endpoint 12 (usbrxinterval12), offset 0x1cd register 297: usb host receive polling interval endpoint 13 (usbrxinterval13), offset 0x1dd register 298: usb host receive polling interval endpoint 14 (usbrxinterval14), offset 0x1ed register 299: usb host receive polling interval endpoint 15 (usbrxinterval15), offset 0x1fd otg a / host usbrxintervaln is an 8-bit register that, for interrupt and isochronous transfers, defines the polling interval for the currently selected receive endpoint. for bulk endpoints, this register defines the number of frames after which the endpoint should time out on receiving a stream of nak responses. the usbrxintervaln register value defines a number of frames, as follows: interpretation valid values (m) speed transfer type the polling interval is m frames. 0x01 C 0xff low-speed or full-speed interrupt the polling interval is 2 (m-1) frames. 0x01 C 0x10 full-speed isochronous 1069 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller interpretation valid values (m) speed transfer type the nak limit is 2 (m-1) frames. a value of 0 or 1 disables the nak timeout function. 0x02 C 0x10 full-speed bulk usb host receive polling interval endpoint 1 (usbrxinterval1) base 0x4005.0000 offset 0x11d type r/w, reset 0x00 0 1 2 3 4 5 6 7 txpoll / naklmt r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 reset description reset type name bit/field rx polling / nak limit the polling interval for interrupt/isochronous transfers; the nak limit for bulk transfers. see table above for valid entries; other values are reserved. 0x00 r/w txpoll / naklmt 7:0 july 03, 2014 1070 texas instruments-production data universal serial bus (usb) controller register 300: usb request packet count in block transfer endpoint 1 (usbrqpktcount1), offset 0x304 register 301: usb request packet count in block transfer endpoint 2 (usbrqpktcount2), offset 0x308 register 302: usb request packet count in block transfer endpoint 3 (usbrqpktcount3), offset 0x30c register 303: usb request packet count in block transfer endpoint 4 (usbrqpktcount4), offset 0x310 register 304: usb request packet count in block transfer endpoint 5 (usbrqpktcount5), offset 0x314 register 305: usb request packet count in block transfer endpoint 6 (usbrqpktcount6), offset 0x318 register 306: usb request packet count in block transfer endpoint 7 (usbrqpktcount7), offset 0x31c register 307: usb request packet count in block transfer endpoint 8 (usbrqpktcount8), offset 0x320 register 308: usb request packet count in block transfer endpoint 9 (usbrqpktcount9), offset 0x324 register 309: usb request packet count in block transfer endpoint 10 (usbrqpktcount10), offset 0x328 register 310: usb request packet count in block transfer endpoint 11 (usbrqpktcount11), offset 0x32c register 311: usb request packet count in block transfer endpoint 12 (usbrqpktcount12), offset 0x330 register 312: usb request packet count in block transfer endpoint 13 (usbrqpktcount13), offset 0x334 register 313: usb request packet count in block transfer endpoint 14 (usbrqpktcount14), offset 0x338 register 314: usb request packet count in block transfer endpoint 15 (usbrqpktcount15), offset 0x33c otg a / host this 16-bit read/write register is used in host mode to specify the number of packets that are to be transferred in a block transfer of one or more bulk packets to receive endpoint n. the usb controller uses the value recorded in this register to determine the number of requests to issue where the autorq bit in the usbrxcsrhn register has been set. see in transactions as a host on page 967. note: multiple packets combined into a single bulk packet within the fifo count as one packet. 1071 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller usb request packet count in block transfer endpoint 1 (usbrqpktcount1) base 0x4005.0000 offset 0x304 type r/w, reset 0x0000 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 count r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field block transfer packet count sets the number of packets of the size defined by the maxload bit field that are to be transferred in a block transfer. note: this is only used in host mode when autorq is set. the bit has no effect in device mode or when autorq is not set. 0x0000 r/w count 15:0 july 03, 2014 1072 texas instruments-production data universal serial bus (usb) controller register 315: usb receive double packet buffer disable (usbrxdpktbufdis), offset 0x340 otg a / host otg b / device usbrxdpktbufdis is a 16-bit register that indicates which of the receive endpoints have disabled the double-packet buffer functionality (see the section called double-packet buffering on page 963). usb receive double packet buffer disable (usbrxdpktbufdis) base 0x4005.0000 offset 0x340 type r/w, reset 0x0000 0123456789 10 11 12 13 14 15 reserved ep1 ep2 ep3 ep4 ep5 ep6 ep7 ep8 ep9 ep10 ep11 ep12 ep13 ep14 ep15 ro r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0000000000000000 reset description reset type name bit/field ep15 rx double-packet buffer disable description value disables double-packet buffering. 0 enables double-packet buffering. 1 0 r/w ep15 15 ep14 rx double-packet buffer disable same description as ep15. 0 r/w ep14 14 ep13 rx double-packet buffer disable same description as ep15. 0 r/w ep13 13 ep12 rx double-packet buffer disable same description as ep15. 0 r/w ep12 12 ep11 rx double-packet buffer disable same description as ep15. 0 r/w ep11 11 ep10 rx double-packet buffer disable same description as ep15. 0 r/w ep10 10 ep9 rx double-packet buffer disable same description as ep15. 0 r/w ep9 9 ep8 rx double-packet buffer disable same description as ep15. 0 r/w ep8 8 ep7 rx double-packet buffer disable same description as ep15. 0 r/w ep7 7 ep6 rx double-packet buffer disable same description as ep15. 0 r/w ep6 6 ep5 rx double-packet buffer disable same description as ep15. 0 r/w ep5 5 ep4 rx double-packet buffer disable same description as ep15. 0 r/w ep4 4 1073 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field ep3 rx double-packet buffer disable same description as ep15. 0 r/w ep3 3 ep2 rx double-packet buffer disable same description as ep15. 0 r/w ep2 2 ep1 rx double-packet buffer disable same description as ep15. 0 r/w ep1 1 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 0 july 03, 2014 1074 texas instruments-production data universal serial bus (usb) controller register 316: usb transmit double packet buffer disable (usbtxdpktbufdis), offset 0x342 otg a / host otg b / device usbtxdpktbufdis is a 16-bit register that indicates which of the transmit endpoints have disabled the double-packet buffer functionality (see the section called double-packet buffering on page 962). usb transmit double packet buffer disable (usbtxdpktbufdis) base 0x4005.0000 offset 0x342 type r/w, reset 0x0000 0123456789 10 11 12 13 14 15 reserved ep1 ep2 ep3 ep4 ep5 ep6 ep7 ep8 ep9 ep10 ep11 ep12 ep13 ep14 ep15 ro r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0000000000000000 reset description reset type name bit/field ep15 tx double-packet buffer disable description value disables double-packet buffering. 0 enables double-packet buffering. 1 0 r/w ep15 15 ep14 tx double-packet buffer disable same description as ep15. 0 r/w ep14 14 ep13 tx double-packet buffer disable same description as ep15. 0 r/w ep13 13 ep12 tx double-packet buffer disable same description as ep15. 0 r/w ep12 12 ep11 tx double-packet buffer disable same description as ep15. 0 r/w ep11 11 ep10 tx double-packet buffer disable same description as ep15. 0 r/w ep10 10 ep9 tx double-packet buffer disable same description as ep15. 0 r/w ep9 9 ep8 tx double-packet buffer disable same description as ep15. 0 r/w ep8 8 ep7 tx double-packet buffer disable same description as ep15. 0 r/w ep7 7 ep6 tx double-packet buffer disable same description as ep15. 0 r/w ep6 6 ep5 tx double-packet buffer disable same description as ep15. 0 r/w ep5 5 ep4 tx double-packet buffer disable same description as ep15. 0 r/w ep4 4 1075 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field ep3 tx double-packet buffer disable same description as ep15. 0 r/w ep3 3 ep2 tx double-packet buffer disable same description as ep15. 0 r/w ep2 2 ep1 tx double-packet buffer disable same description as ep15. 0 r/w ep1 1 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 0 july 03, 2014 1076 texas instruments-production data universal serial bus (usb) controller register 317: usb external power control (usbepc), offset 0x400 otg a / host otg b / device this 32-bit register specifies the function of the two-pin external power interface ( usb0epen and usb0pflt ). the assertion of the power fault input may generate an automatic action, as controlled by the hardware configuration registers. the automatic action is necessary because the fault condition may require a response faster than one provided by firmware. usb external power control (usbepc) base 0x4005.0000 offset 0x400 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 epen epende reserved pflten pfltsen pfltaen reserved pfltact reserved r/w r/w r/w ro r/w r/w r/w ro r/w r/w ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0 ro reserved 31:10 power fault action this bit field specifies how the usb0epen signal is changed when detecting a usb power fault. description value unchanged usb0epen is controlled by the combination of the epen and epende bits. 0x0 tristate usb0epen is undriven (tristate). 0x1 low usb0epen is driven low. 0x2 high usb0epen is driven high. 0x3 0x0 r/w pfltact 9:8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7 1077 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field power fault action enable this bit specifies whether a usb power fault triggers any automatic corrective action regarding the driven state of the usb0epen signal. description value disabled usb0epen is controlled by the combination of the epen and epende bits. 0 enabled the usb0epen output is automatically changed to the state specified by the pfltact field. 1 0 r/w pfltaen 6 power fault sense this bit specifies the logical sense of the usb0pflt input signal that indicates an error condition. the complementary state is the inactive state. description value low fault if usb0pflt is driven low, the power fault is signaled internally (if enabled by the pflten bit). 0 high fault if usb0pflt is driven high, the power fault is signaled internally (if enabled by the pflten bit). 1 0 r/w pfltsen 5 power fault input enable this bit specifies whether the usb0pflt input signal is used in internal logic. description value not used the usb0pflt signal is ignored. 0 used the usb0pflt signal is used internally. 1 0 r/w pflten 4 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 3 july 03, 2014 1078 texas instruments-production data universal serial bus (usb) controller description reset type name bit/field epen drive enable this bit specifies whether the usb0epen signal is driven or undriven (tristate). when driven, the signal value is specified by the epen field. when not driven, the epen field is ignored and the usb0epen signal is placed in a high-impedance state. description value not driven the usb0epen signal is high impedance. 0 driven the usb0epen signal is driven to the logical value specified by the value of the epen field. 1 the usb0epen signal is undriven at reset because the sense of the external power supply enable is unknown. by adding the high-impedance state, system designers may bias the power supply enable to the disabled state using a large resistor (100 k) and later configure and drive the output signal to enable the power supply. 0 r/w epende 2 external power supply enable configuration this bit field specifies and controls the logical value driven on the usb0epen signal. description value power enable active low the usb0epen signal is driven low if the epende bit is set. 0x0 power enable active high the usb0epen signal is driven high if the epende bit is set. 0x1 power enable high if vbus low the usb0epen signal is driven high when the a device is not recognized. 0x2 power enable high if vbus high the usb0epen signal is driven high when the a device is recognized. 0x3 0x0 r/w epen 1:0 1079 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 318: usb external power control raw interrupt status (usbepcris), offset 0x404 otg a / host otg b / device this 32-bit register specifies the unmasked interrupt status of the two-pin external power interface. usb external power control raw interrupt status (usbepcris) base 0x4005.0000 offset 0x404 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0000000000000000 reset 0123456789 10 11 12 13 14 15 pf reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0000000000000000 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:1 usb power fault interrupt status description value a power fault status has been detected. 1 an interrupt has not occurred. 0 this bit is cleared by writing a 1 to the pf bit in the usbepcisc register. 0 ro pf 0 july 03, 2014 1080 texas instruments-production data universal serial bus (usb) controller register 319: usb external power control interrupt mask (usbepcim), offset 0x408 otg a / host otg b / device this 32-bit register specifies the interrupt mask of the two-pin external power interface. usb external power control interrupt mask (usbepcim) base 0x4005.0000 offset 0x408 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0000000000000000 reset 0123456789 10 11 12 13 14 15 pf reserved r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0000000000000000 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:1 usb power fault interrupt mask description value the raw interrupt signal from a detected power fault is sent to the interrupt controller. 1 a detected power fault does not affect the interrupt status. 0 0 r/w pf 0 1081 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 320: usb external power control interrupt status and clear (usbepcisc), offset 0x40c otg a / host otg b / device this 32-bit register specifies the masked interrupt status of the two-pin external power interface. it also provides a method to clear the interrupt state. usb external power control interrupt status and clear (usbepcisc) base 0x4005.0000 offset 0x40c type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0000000000000000 reset 0123456789 10 11 12 13 14 15 pf reserved r/w1c ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0000000000000000 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:1 usb power fault interrupt status and clear description value the pf bits in the usbepcris and usbepcim registers are set, providing an interrupt to the interrupt controller. 1 no interrupt has occurred or the interrupt is masked. 0 this bit is cleared by writing a 1. clearing this bit also clears the pf bit in the usbepcris register. 0 r/w1c pf 0 july 03, 2014 1082 texas instruments-production data universal serial bus (usb) controller register 321: usb device resume raw interrupt status (usbdrris), offset 0x410 otg a / host otg b / device the usbdrris 32-bit register is the raw interrupt status register. on a read, this register gives the current raw status value of the corresponding interrupt prior to masking. a write has no effect. usb device resume raw interrupt status (usbdrris) base 0x4005.0000 offset 0x410 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0000000000000000 reset 0123456789 10 11 12 13 14 15 resume reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0000000000000000 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:1 resume interrupt status description value a resume status has been detected. 1 an interrupt has not occurred. 0 this bit is cleared by writing a 1 to the resume bit in the usbdrisc register. 0 ro resume 0 1083 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 322: usb device resume interrupt mask (usbdrim), offset 0x414 otg a / host otg b / device the usbdrim 32-bit register is the masked interrupt status register. on a read, this register gives the current value of the mask on the corresponding interrupt. setting a bit sets the mask, preventing the interrupt from being signaled to the interrupt controller. clearing a bit clears the corresponding mask, enabling the interrupt to be sent to the interrupt controller. usb device resume interrupt mask (usbdrim) base 0x4005.0000 offset 0x414 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 resume reserved r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:1 resume interrupt mask description value the raw interrupt signal from a detected resume is sent to the interrupt controller. this bit should only be set when a suspend has been detected (the suspend bit in the usbis register is set). 1 a detected resume does not affect the interrupt status. 0 0 r/w resume 0 july 03, 2014 1084 texas instruments-production data universal serial bus (usb) controller register 323: usb device resume interrupt status and clear (usbdrisc), offset 0x418 otg a / host otg b / device the usbdrisc 32-bit register is the interrupt clear register. on a write of 1, the corresponding interrupt is cleared. a write of 0 has no effect. usb device resume interrupt status and clear (usbdrisc) base 0x4005.0000 offset 0x418 type w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0000000000000000 reset 0123456789 10 11 12 13 14 15 resume reserved r/w1c ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0000000000000000 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:1 resume interrupt status and clear description value the resume bits in the usbdrris and usbdrcim registers are set, providing an interrupt to the interrupt controller. 1 no interrupt has occurred or the interrupt is masked. 0 this bit is cleared by writing a 1. clearing this bit also clears the resume bit in the usbdrcris register. 0 r/w1c resume 0 1085 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 324: usb general-purpose control and status (usbgpcs), offset 0x41c otg a / host otg b / device usbgpcs provides the state of the internal id signal. note: when used in otg mode, usb0vbus and usb0id do not require any configuration as they are dedicated pins for the usb controller and directly connect to the usb connector's vbus and id signals. if the usb controller is used as either a dedicated host or device, the devmodotg and devmod bits in the usb general-purpose control and status (usbgpcs) register can be used to connect the usb0vbus and usb0id inputs to fixed levels internally, freeing the pb0 and pb1 pins for gpio use. for proper self-powered device operation, the vbus value must still be monitored to assure that if the host removes vbus, the self-powered device disables the d+/d- pull-up resistors. this function can be accomplished by connecting a standard gpio to vbus. the termination resistors for the usb phy have been added internally, and thus there is no need for external resistors. for a device, there is a 1.5 kohm pull-up on the d+ and for a host there are 15 kohm pull-downs on both d+ and d-. usb general-purpose control and status (usbgpcs) base 0x4005.0000 offset 0x41c type r/w, reset 0x0000.0001 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 devmod devmodotg reserved r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:2 enable device mode this bit enables the devmod bit to control the state of the internal id signal in otg mode. description value the mode is specified by the state of the internal id signal. 0 this bit enables the devmod bit to control the internal id signal. 1 0 r/w devmodotg 1 device mode this bit specifies the state of the internal id signal in host mode and in otg mode when the devmodotg bit is set. in device mode this bit is ignored (assumed set). description value host mode 0 device mode 1 1 r/w devmod 0 july 03, 2014 1086 texas instruments-production data universal serial bus (usb) controller register 325: usb vbus droop control (usbvdc), offset 0x430 otg a / host this 32-bit register enables a controlled masking of vbus to compensate for any in-rush current by a device that is connected to the host controller. the in-rush current can cause vbus to droop, causing the usb controller's behavior to be unexpected. the usb host controller allows vbus to fall lower than the vbus valid level (4.75 v) but not below avalid (2.0 v) for 65 microseconds without signaling a vbuserr interrupt in the controller. without this, any glitch on vbus would force the usb host controller to remove power from vbus and then re-enumerate the device. usb vbus droop control (usbvdc) base 0x4005.0000 offset 0x430 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 vbden reserved r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:1 vbus droop enable description value no effect. 0 any changes from vbusvalid are masked when vbus goes below 4.75 v but not lower than 2.0 v for 65 microseconds. during this time, the vbus state indicates vbusvalid. 1 0 r/w vbden 0 1087 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 326: usb vbus droop control raw interrupt status (usbvdcris), offset 0x434 otg a / host this 32-bit register specifies the unmasked interrupt status of the vbus droop limit of 65 microseconds. usb vbus droop control raw interrupt status (usbvdcris) base 0x4005.0000 offset 0x434 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 vd reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:1 vbus droop raw interrupt status description value a vbus droop lasting for 65 microseconds has been detected. 1 an interrupt has not occurred. 0 this bit is cleared by writing a 1 to the vd bit in the usbvdcisc register. 0 ro vd 0 july 03, 2014 1088 texas instruments-production data universal serial bus (usb) controller register 327: usb vbus droop control interrupt mask (usbvdcim), offset 0x438 otg a / host this 32-bit register specifies the interrupt mask of the vbus droop. usb vbus droop control interrupt mask (usbvdcim) base 0x4005.0000 offset 0x438 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 vd reserved r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:1 vbus droop interrupt mask description value the raw interrupt signal from a detected vbus droop is sent to the interrupt controller. 1 a detected vbus droop does not affect the interrupt status. 0 0 r/w vd 0 1089 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 328: usb vbus droop control interrupt status and clear (usbvdcisc), offset 0x43c otg a / host this 32-bit register specifies the masked interrupt status of the vbus droop and provides a method to clear the interrupt state. usb vbus droop control interrupt status and clear (usbvdcisc) base 0x4005.0000 offset 0x43c type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 vd reserved r/w1c ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:1 vbus droop interrupt status and clear description value the vd bits in the usbvdcris and usbvdcim registers are set, providing an interrupt to the interrupt controller. 1 no interrupt has occurred or the interrupt is masked. 0 this bit is cleared by writing a 1. clearing this bit also clears the vd bit in the usbvdcris register. 0 r/w1c vd 0 july 03, 2014 1090 texas instruments-production data universal serial bus (usb) controller register 329: usb id valid detect raw interrupt status (usbidvris), offset 0x444 otg this 32-bit register specifies whether the unmasked interrupt status of the id value is valid. usb id valid detect raw interrupt status (usbidvris) base 0x4005.0000 offset 0x444 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 id reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:1 id valid detect raw interrupt status description value a valid id has been detected. 1 an interrupt has not occurred. 0 this bit is cleared by writing a 1 to the id bit in the usbidvisc register. 0 ro id 0 1091 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 330: usb id valid detect interrupt mask (usbidvim), offset 0x448 otg this 32-bit register specifies the interrupt mask of the id valid detection. usb id valid detect interrupt mask (usbidvim) base 0x4005.0000 offset 0x448 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 id reserved r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:1 id valid detect interrupt mask description value the raw interrupt signal from a detected id valid is sent to the interrupt controller. 1 a detected id valid does not affect the interrupt status. 0 0 r/w id 0 july 03, 2014 1092 texas instruments-production data universal serial bus (usb) controller register 331: usb id valid detect interrupt status and clear (usbidvisc), offset 0x44c otg this 32-bit register specifies the masked interrupt status of the id valid detect. it also provides a method to clear the interrupt state. usb id valid detect interrupt status and clear (usbidvisc) base 0x4005.0000 offset 0x44c type r/w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 id reserved r/w1c ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:1 id valid detect interrupt status and clear description value the id bits in the usbidvris and usbidvim registers are set, providing an interrupt to the interrupt controller. 1 no interrupt has occurred or the interrupt is masked. 0 this bit is cleared by writing a 1. clearing this bit also clears the id bit in the usbidvris register. 0 r/w1c id 0 1093 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 332: usb dma select (usbdmasel), offset 0x450 otg a / host otg b / device this 32-bit register specifies which endpoints are mapped to the 6 allocated dma channels, see table 7-1 on page 346 for more information on channel assignments. usb dma select (usbdmasel) base 0x4005.0000 offset 0x450 type r/w, reset 0x0033.2211 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 dmacrx dmactx reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 1100110000000000 reset 0123456789 10 11 12 13 14 15 dmaarx dmaatx dmabrx dmabtx r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 1000100001000100 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:24 dma c tx select specifies the tx mapping of the third usb endpoint on dma channel 5 (primary assignment). description value reserved 0x0 endpoint 1 tx 0x1 endpoint 2 tx 0x2 endpoint 3 tx 0x3 endpoint 4 tx 0x4 endpoint 5 tx 0x5 endpoint 6 tx 0x6 endpoint 7 tx 0x7 endpoint 8 tx 0x8 endpoint 9 tx 0x9 endpoint 10 tx 0xa endpoint 11 tx 0xb endpoint 12 tx 0xc endpoint 13 tx 0xd endpoint 14 tx 0xe endpoint 15 tx 0xf 0x3 r/w dmactx 23:20 july 03, 2014 1094 texas instruments-production data universal serial bus (usb) controller description reset type name bit/field dma c rx select specifies the rx and tx mapping of the third usb endpoint on dma channel 4 (primary assignment). description value reserved 0x0 endpoint 1 rx 0x1 endpoint 2 rx 0x2 endpoint 3 rx 0x3 endpoint 4 rx 0x4 endpoint 5 rx 0x5 endpoint 6 rx 0x6 endpoint 7 rx 0x7 endpoint 8 rx 0x8 endpoint 9 rx 0x9 endpoint 10 rx 0xa endpoint 11 rx 0xb endpoint 12 rx 0xc endpoint 13 rx 0xd endpoint 14 rx 0xe endpoint 15 rx 0xf 0x3 r/w dmacrx 19:16 dma b tx select specifies the tx mapping of the second usb endpoint on dma channel 3 (primary assignment). same bit definitions as the dmactx field. 0x2 r/w dmabtx 15:12 dma b rx select specifies the rx mapping of the second usb endpoint on dma channel 2 (primary assignment). same bit definitions as the dmacrx field. 0x2 r/w dmabrx 11:8 dma a tx select specifies the tx mapping of the first usb endpoint on dma channel 1 (primary assignment). same bit definitions as the dmactx field. 0x1 r/w dmaatx 7:4 dma a rx select specifies the rx mapping of the first usb endpoint on dma channel 0 (primary assignment). same bit definitions as the dmacrx field. 0x1 r/w dmaarx 3:0 1095 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 20 analog comparators an analog comparator is a peripheral that compares two analog voltages and provides a logical output that signals the comparison result. note: not all comparators have the option to drive an output pin. see signal description on page 1097 for more information. the comparator can provide its output to a device pin, acting as a replacement for an analog comparator on the board. in addition, the comparator can signal the application via interrupts or trigger the start of a sample sequence in the adc. the interrupt generation and adc triggering logic is separate and independent. this flexibility means, for example, that an interrupt can be generated on a rising edge and the adc triggered on a falling edge. the stellaris ? lm3s9gn5 microcontroller provides three independent integrated analog comparators with the following functions: compare external pin input to external pin input or to internal programmable voltage reference compare a test voltage against any one of the following voltages: C an individual external reference voltage C a shared single external reference voltage C a shared internal reference voltage july 03, 2014 1096 texas instruments-production data analog comparators 20.1 block diagram figure 20-1. analog comparator module block diagram 20.2 signal description the following table lists the external signals of the analog comparators and describes the function of each. the analog comparator output signals are alternate functions for some gpio signals and default to be gpio signals at reset. the column in the table below titled "pin mux/pin assignment" lists the possible gpio pin placements for the analog comparator signals. the afsel bit in the gpio alternate function select (gpioafsel) register (page 429) should be set to choose the analog comparator function. the number in parentheses is the encoding that must be programmed into the pmcn field in the gpio port control (gpiopctl) register (page 447) to assign the analog comparator signal to the specified gpio port pin. the positive and negative input signals are configured by clearing the den bit in the gpio digital enable (gpioden) register. for more information on configuring gpios, see general-purpose input/outputs (gpios) on page 405. table 20-1. analog comparators signals (100lqfp) description buffer type a pin type pin mux / pin assignment pin number pin name analog comparator 0 positive input. analog i pb6 90 c0+ analog comparator 0 negative input. analog i pb4 92 c0- 1097 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller & & r x w s x w y h l q s x w d o w h u q d w h y h l q s x w l q w h u u x s w y h l q s x w u h i h u h q f h l q s x w & r p s d u d w r u $ & 6 7 $ 7 $ & & 7 / & & r x w s x w y h l q s x w d o w h u q d w h y h l q s x w l q w h u u x s w y h l q s x w u h i h u h q f h l q s x w & r p s d u d w r u $ & 6 7 $ 7 $ & & 7 / & r 9 r o w d j h 5 h i $ & 5 ( ) & 7 / r x w s x w y h l q s x w d o w h u q d w h y h l q s x w l q w h u u x s w y h l q s x w u h i h u h q f h l q s x w & r p s d u d w r u $ & 6 7 $ 7 $ & & 7 / & l q w h u q d o e x v & & r & r w u l j j h u w u l j j h u w u l j j h u w u l j j h u w u l j j h u w u l j j h u , q w h u u x s w & r q w u r o $ & 5 , 6 $ & 0 , 6 $ & , 1 7 ( 1 l q w h u u x s w table 20-1. analog comparators signals (100lqfp) (continued) description buffer type a pin type pin mux / pin assignment pin number pin name analog comparator 0 output. ttl o pc5 (3) pf4 (2) pb6 (3) pb5 (1) pd7 (2) 24 58 90 91 100 c0o analog comparator 1 positive input. analog i pc5 24 c1+ analog comparator 1 negative input. analog i pb5 91 c1- analog comparator 1 output. ttl o pe6 (2) pc7 (7) pc5 (2) pf5 (2) ph2 (2) 2 22 24 46 84 c1o analog comparator 2 positive input. analog i pc6 23 c2+ analog comparator 2 negative input. analog i pc7 22 c2- analog comparator 2 output. ttl o pe7 (2) pc6 (3) pf6 (2) 1 23 43 c2o a. the ttl designation indicates the pin has ttl-compatible voltage levels. table 20-2. analog comparators signals (108bga) description buffer type a pin type pin mux / pin assignment pin number pin name analog comparator 0 positive input. analog i pb6 a7 c0+ analog comparator 0 negative input. analog i pb4 a6 c0- analog comparator 0 output. ttl o pc5 (3) pf4 (2) pb6 (3) pb5 (1) pd7 (2) m1 l9 a7 b7 a2 c0o analog comparator 1 positive input. analog i pc5 m1 c1+ analog comparator 1 negative input. analog i pb5 b7 c1- analog comparator 1 output. ttl o pe6 (2) pc7 (7) pc5 (2) pf5 (2) ph2 (2) a1 l2 m1 l8 d11 c1o analog comparator 2 positive input. analog i pc6 m2 c2+ analog comparator 2 negative input. analog i pc7 l2 c2- analog comparator 2 output. ttl o pe7 (2) pc6 (3) pf6 (2) b1 m2 m8 c2o a. the ttl designation indicates the pin has ttl-compatible voltage levels. 20.3 functional description the comparator compares the vin- and vin+ inputs to produce an output, vout. vin- < vin+, vout = 1 vin- > vin+, vout = 0 july 03, 2014 1098 texas instruments-production data analog comparators as shown in figure 20-2 on page 1099, the input source for vin- is an external input, cn- . in addition to an external input, cn+ , input sources for vin+ can be the c0+ or an internal reference, v iref . figure 20-2. structure of comparator unit a comparator is configured through two status/control registers, analog comparator control (acctl) and analog comparator status (acstat) . the internal reference is configured through one control register, analog comparator reference voltage control (acrefctl) . interrupt status and control are configured through three registers, analog comparator masked interrupt status (acmis) , analog comparator raw interrupt status (acris) , and analog comparator interrupt enable (acinten) . typically, the comparator output is used internally to generate an interrupt as controlled by the isen bit in the acctl register. the output may also be used to drive an external pin, co or generate an analog-to-digital converter (adc) trigger. important: the asrcp bits in the acctl register must be set before using the analog comparators. 20.3.1 internal reference programming the structure of the internal reference is shown in figure 20-3 on page 1099. the internal reference is controlled by a single configuration register ( acrefctl ). figure 20-3. comparator internal reference structure the internal reference can be programmed in one of two modes (low range or high range) depending on the rng bit in the acrefctl register. when rng is clear, the internal reference is in high-range mode, and when rng is set the internal reference is in low-range mode. 1099 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller $ & & 7 / & , 1 9 l q w h u q d o e x v l q w h u u x s w w u l j j h u 7 u l j * h q r x w s x w $ & 6 7 $ 7 , q w * h q y h l q s x w d o w h u q d w h y h l q s x w y h l q s x w u h i h u h q f h l q s x w 5 5 5 5 5 ? ? ? ? ? ? ' h f r g h u 9 ' ' $ ( 1 l q w h u q d o u h i h u h q f h 9 , 5 ( ) 9 5 ( ) 5 1 * in each range, the internal reference, v iref , has 16 pre-programmed thresholds or step values. the threshold to be used to compare the external input voltage against is selected using the vref field in the acrefctl register. in the high-range mode, the v iref threshold voltages start at the ideal high-range starting voltage of v dda /3.875 and increase in ideal constant voltage steps of v dda /31. in the low-range mode, the v iref threshold voltages start at:0v and increase in ideal constant voltage steps of v dda /23. the ideal v iref step voltages for each mode and their dependence on the rng and vref fields are summarized in table 20-3 on page 1100. table 20-3. internal reference voltage and acrefctl field values output reference voltage based on vref field value acrefctl register rng bit value en bit value 0 v (gnd) for any value of vref . it is recommended that rng =1 and vref =0 to minimize noise on the reference ground. rng=x en=0 total resistance in ladder is 31 r. the range of internal reference in this mode is 0.85-2.448 v. rng=0 en=1 total resistance in ladder is 23 r. the range of internal reference for this mode is 0-2.152 v. rng=1 20.4 initialization and configuration the following example shows how to configure an analog comparator to read back its output value from an internal register. july 03, 2014 1100 texas instruments-production data analog comparators t vref dda iref r r v v = () 31 8 + = vref v v dda iref v ref v iref + = 106 . 0 85 . 0 t vref dda iref r r v v = 23 vref v v dda iref = vref v iref = 143 . 0 t vref dda iref r r v v = () 31 8 + = vref v v dda iref v ref v iref + = 106 . 0 85 . 0 t vref dda iref r r v v = 23 vref v v dda iref = vref v iref = 143 . 0 t vref dda iref r r v v = () 31 8 + = vref v v dda iref v ref v iref + = 106 . 0 85 . 0 t vref dda iref r r v v = 23 vref v v dda iref = vref v iref = 143 . 0 t vref dda iref r r v v = () 31 8 + = vref v v dda iref v ref v iref + = 106 . 0 85 . 0 t vref dda iref r r v v = 23 vref v v dda iref = vref v iref = 143 . 0 t vref dda iref r r v v = () 31 8 + = vref v v dda iref v ref v iref + = 106 . 0 85 . 0 t vref dda iref r r v v = 23 vref v v dda iref = vref v iref = 143 . 0 t vref dda iref r r v v = () 31 8 + = vref v v dda iref v ref v iref + = 106 . 0 85 . 0 t vref dda iref r r v v = 23 vref v v dda iref = vref v iref = 143 . 0 1. enable the analog comparator clock by writing a value of 0x0010.0000 to the rcgc1 register in the system control module (see page 270). 2. enable the clock to the appropriate gpio modules via the rcgc2 register (see page 282). to find out which gpio ports to enable, refer to table 24-5 on page 1248. 3. in the gpio module, enable the gpio port/pin associated with the input signals as gpio inputs. to determine which gpio to configure, see table 24-4 on page 1239. 4. configure the pmcn fields in the gpiopctl register to assign the analog comparator output signals to the appropriate pins (see page 447 and table 24-5 on page 1248). 5. configure the internal voltage reference to 1.65 v by writing the acrefctl register with the value 0x0000.030c. 6. configure the comparator to use the internal voltage reference and to not invert the output by writing the acctln register with the value of 0x0000.040c. 7. delay for 10 s. 8. read the comparator output value by reading the acstatn registers oval value. change the level of the comparator negative input signal c- to see the oval value change. 20.5 register map table 20-4 on page 1101 lists the comparator registers. the offset listed is a hexadecimal increment to the registers address, relative to the analog comparator base address of 0x4003.c000. note that the analog comparator clock must be enabled before the registers can be programmed (see page 270). there must be a delay of 3 system clocks after the analog comparator module clock is enabled before any analog comparator module registers are accessed. table 20-4. analog comparators register map see page description reset type name offset 1103 analog comparator masked interrupt status 0x0000.0000 r/w1c acmis 0x000 1104 analog comparator raw interrupt status 0x0000.0000 ro acris 0x004 1105 analog comparator interrupt enable 0x0000.0000 r/w acinten 0x008 1106 analog comparator reference voltage control 0x0000.0000 r/w acrefctl 0x010 1107 analog comparator status 0 0x0000.0000 ro acstat0 0x020 1108 analog comparator control 0 0x0000.0000 r/w acctl0 0x024 1107 analog comparator status 1 0x0000.0000 ro acstat1 0x040 1108 analog comparator control 1 0x0000.0000 r/w acctl1 0x044 1107 analog comparator status 2 0x0000.0000 ro acstat2 0x060 1108 analog comparator control 2 0x0000.0000 r/w acctl2 0x064 1101 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 20.6 register descriptions the remainder of this section lists and describes the analog comparator registers, in numerical order by address offset. july 03, 2014 1102 texas instruments-production data analog comparators register 1: analog comparator masked interrupt status (acmis), offset 0x000 this register provides a summary of the interrupt status (masked) of the comparators. analog comparator masked interrupt status (acmis) base 0x4003.c000 offset 0x000 type r/w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 in0 in1 in2 reserved r/w1c r/w1c r/w1c ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:3 comparator 2 masked interrupt status description value the in2 bits in the acris register and the acinten registers are set, providing an interrupt to the interrupt controller. 1 no interrupt has occurred or the interrupt is masked. 0 this bit is cleared by writing a 1. clearing this bit also clears the in2 bit in the acris register. 0 r/w1c in2 2 comparator 1 masked interrupt status description value the in1 bits in the acris register and the acinten registers are set, providing an interrupt to the interrupt controller. 1 no interrupt has occurred or the interrupt is masked. 0 this bit is cleared by writing a 1. clearing this bit also clears the in1 bit in the acris register. 0 r/w1c in1 1 comparator 0 masked interrupt status description value the in0 bits in the acris register and the acinten registers are set, providing an interrupt to the interrupt controller. 1 no interrupt has occurred or the interrupt is masked. 0 this bit is cleared by writing a 1. clearing this bit also clears the in0 bit in the acris register. 0 r/w1c in0 0 1103 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 2: analog comparator raw interrupt status (acris), offset 0x004 this register provides a summary of the interrupt status (raw) of the comparators. the bits in this register must be enabled to generate interrupts using the acinten register. analog comparator raw interrupt status (acris) base 0x4003.c000 offset 0x004 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 in0 in1 in2 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:3 comparator 2 interrupt status description value comparator 2 has generated an interrupt for an event as configured by the isen bit in the acctl2 register. 1 an interrupt has not occurred. 0 this bit is cleared by writing a 1 to the in2 bit in the acmis register. 0 ro in2 2 comparator 1 interrupt status description value comparator 1 has generated an interruptfor an event as configured by the isen bit in the acctl1 register. 1 an interrupt has not occurred. 0 this bit is cleared by writing a 1 to the in1 bit in the acmis register. 0 ro in1 1 comparator 0 interrupt status description value comparator 0 has generated an interrupt for an event as configured by the isen bit in the acctl0 register. 1 an interrupt has not occurred. 0 this bit is cleared by writing a 1 to the in0 bit in the acmis register. 0 ro in0 0 july 03, 2014 1104 texas instruments-production data analog comparators register 3: analog comparator interrupt enable (acinten), offset 0x008 this register provides the interrupt enable for the comparators. analog comparator interrupt enable (acinten) base 0x4003.c000 offset 0x008 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 in0 in1 in2 reserved r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:3 comparator 2 interrupt enable description value the raw interrupt signal comparator 2 is sent to the interrupt controller. 1 a comparator 2 interrupt does not affect the interrupt status. 0 0 r/w in2 2 comparator 1 interrupt enable description value the raw interrupt signal comparator 1 is sent to the interrupt controller. 1 a comparator 1 interrupt does not affect the interrupt status. 0 0 r/w in1 1 comparator 0 interrupt enable description value the raw interrupt signal comparator 0 is sent to the interrupt controller. 1 a comparator 0 interrupt does not affect the interrupt status. 0 0 r/w in0 0 1105 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 4: analog comparator reference voltage control (acrefctl), offset 0x010 this register specifies whether the resistor ladder is powered on as well as the range and tap. analog comparator reference voltage control (acrefctl) base 0x4003.c000 offset 0x010 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 vref reserved rng en reserved r/w r/w r/w r/w ro ro ro ro r/w r/w ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0 ro reserved 31:10 resistor ladder enable description value the resistor ladder is unpowered. 0 powers on the resistor ladder. the resistor ladder is connected to v dda . 1 this bit is cleared at reset so that the internal reference consumes the least amount of power if it is not used. 0 r/w en 9 resistor ladder range description value the resistor ladder has a total resistance of 31 r. 0 the resistor ladder has a total resistance of 23 r. 1 0 r/w rng 8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 7:4 resistor ladder voltage ref the vref bit field specifies the resistor ladder tap that is passed through an analog multiplexer. the voltage corresponding to the tap position is the internal reference voltage available for comparison. see table 20-3 on page 1100 for some output reference voltage examples. 0x0 r/w vref 3:0 july 03, 2014 1106 texas instruments-production data analog comparators register 5: analog comparator status 0 (acstat0), offset 0x020 register 6: analog comparator status 1 (acstat1), offset 0x040 register 7: analog comparator status 2 (acstat2), offset 0x060 these registers specify the current output value of the comparator. analog comparator status 0 (acstat0) base 0x4003.c000 offset 0x020 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved oval reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:2 comparator output value description value vin- > vin+ 0 vin- < vin+ 1 vin - is the voltage on the cn- pin. vin+ is the voltage on the cn+ pin, the c0+ pin, or the internal voltage reference (v iref ) as defined by the asrcp bit in the acctl register. 0 ro oval 1 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 0 1107 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 8: analog comparator control 0 (acctl0), offset 0x024 register 9: analog comparator control 1 (acctl1), offset 0x044 register 10: analog comparator control 2 (acctl2), offset 0x064 these registers configure the comparators input and output. analog comparator control 0 (acctl0) base 0x4003.c000 offset 0x024 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved cinv isen islval tsen tslval reserved asrcp toen reserved ro r/w r/w r/w r/w r/w r/w r/w ro r/w r/w r/w ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0 ro reserved 31:12 trigger output enable description value adc events are suppressed and not sent to the adc. 0 adc events are sent to the adc. 1 0 r/w toen 11 analog source positive the asrcp field specifies the source of input voltage to the vin+ terminal of the comparator. the encodings for this field are as follows: description value pin value of cn+ 0x0 pin value of c0+ 0x1 internal voltage reference (v iref ) 0x2 reserved 0x3 0x0 r/w asrcp 10:9 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 8 trigger sense level value description value an adc event is generated if the comparator output is low. 0 an adc event is generated if the comparator output is high. 1 0 r/w tslval 7 july 03, 2014 1108 texas instruments-production data analog comparators description reset type name bit/field trigger sense the tsen field specifies the sense of the comparator output that generates an adc event. the sense conditioning is as follows: description value level sense, see tslval 0x0 falling edge 0x1 rising edge 0x2 either edge 0x3 0x0 r/w tsen 6:5 interrupt sense level value description value an interrupt is generated if the comparator output is low. 0 an interrupt is generated if the comparator output is high. 1 0 r/w islval 4 interrupt sense the isen field specifies the sense of the comparator output that generates an interrupt. the sense conditioning is as follows: description value level sense, see islval 0x0 falling edge 0x1 rising edge 0x2 either edge 0x3 0x0 r/w isen 3:2 comparator output invert description value the output of the comparator is unchanged. 0 the output of the comparator is inverted prior to being processed by hardware. 1 0 r/w cinv 1 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 0 1109 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 21 pulse width modulator (pwm) pulse width modulation (pwm) is a powerful technique for digitally encoding analog signal levels. high-resolution counters are used to generate a square wave, and the duty cycle of the square wave is modulated to encode an analog signal. typical applications include switching power supplies and motor control. the stellaris ? microcontroller contains one pwm module, with four pwm generator blocks and a control block, for a total of 8 pwm outputs. the control block determines the polarity of the pwm signals, and which signals are passed through to the pins. each pwm generator block produces two pwm signals that share the same timer and frequency and can either be programmed with independent actions or as a single pair of complementary signals with dead-band delays inserted. the output signals, pwma' and pwmb', of the pwm generation blocks are managed by the output control block before being passed to the device pins as pwm0 and pwm1 or pwm2 and pwm3 , and so on. the stellaris pwm module provides a great deal of flexibility and can generate simple pwm signals, such as those required by a simple charge pump as well as paired pwm signals with dead-band delays, such as those required by a half-h bridge driver. three generator blocks can also generate the full six channels of gate controls required by a 3-phase inverter bridge. each pwm generator block has the following features: four fault-condition handling inputs to quickly provide low-latency shutdown and prevent damage to the motor being controlled one 16-bit counter C runs in down or up/down mode C output frequency controlled by a 16-bit load value C load value updates can be synchronized C produces output signals at zero and load value two pwm comparators C comparator value updates can be synchronized C produces output signals on match pwm signal generator C output pwm signal is constructed based on actions taken as a result of the counter and pwm comparator output signals C produces two independent pwm signals dead-band generator C produces two pwm signals with programmable dead-band delays suitable for driving a half-h bridge C can be bypassed, leaving input pwm signals unmodified july 03, 2014 1110 texas instruments-production data pulse width modulator (pwm) can initiate an adc sample sequence the control block determines the polarity of the pwm signals and which signals are passed through to the pins. the output of the pwm generation blocks are managed by the output control block before being passed to the device pins. the pwm control block has the following options: pwm output enable of each pwm signal optional output inversion of each pwm signal (polarity control) optional fault handling for each pwm signal synchronization of timers in the pwm generator blocks synchronization of timer/comparator updates across the pwm generator blocks extended pwm synchronization of timer/comparator updates across the pwm generator blocks interrupt status summary of the pwm generator blocks extended pwm fault handling, with multiple fault signals, programmable polarities, and filtering pwm generators can be operated independently or synchronized with other generators 21.1 block diagram figure 21-1 on page 1112 provides the stellaris pwm module diagram and figure 21-2 on page 1112 provides a more detailed diagram of a stellaris pwm generator. the lm3s9gn5 controller contains four generator blocks that generate eight independent pwm signals or four paired pwm signals with dead-band delays inserted. 1111 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller figure 21-1. pwm module diagram figure 21-2. pwm generator block diagram 21.2 signal description the following table lists the external signals of the pwm module and describes the function of each. the pwm controller signals are alternate functions for some gpio signals and default to be gpio july 03, 2014 1112 texas instruments-production data pulse width modulator (pwm) 3 : 0 , 1 7 ( 1 , q w h u u x s w 3 : 0 5 , 6 3 : 0 , 6 & 3 : 0 & 7 / & r q w u r o d q g 6 w d w x v 3 : 0 6 < 1 & 3 : 0 6 7 $ 7 8 6 3 : 0 * h q h u d w r u 3 : 0 * h q h u d w r u 3 : 0 * h q h u d w r u 3 : 0 * h q h u d w r u 3 : 0 3 : 0 3 : 0 3 : 0 3 : 0 3 : 0 3 : 0 3 : 0 3 : 0 2 x w s x w & r q w u r o / r j l f 3 : 0 & o r f n 6 \ v w h p & o r f n , q w h u u x s w v 7 u l j j h u v s z p $ ? s z p % ? s z p $ ? s z p % ? s z p $ ? s z p % ? s z p $ ? s z p % ? s z p i d x o w s z p i d x o w s z p i d x o w s z p i d x o w 7 u l j j h u v ) d x o w v 3 : 0 ( 1 $ % / ( 2 x w s x w 3 : 0 , 1 9 ( 5 7 3 : 0 ) $ 8 / 7 3 : 0 ) $ 8 / 7 9 $ / 3 : 0 ( 1 8 3 ' 3 : 0 q & 0 3 $ & r p s d u d w r u v 3 : 0 q & 0 3 % 3 : 0 q / 2 $ ' 7 l p h u 3 : 0 q & 2 8 1 7 3 : 0 q ' % & 7 / ' h d g % d q g * h q h u d w r u 3 : 0 q ' % 5 , 6 ( 3 : 0 q ' % ) $ / / 3 : 0 q & 7 / & r q w u r o 3 : 0 q ) / 7 6 5 & ) d x o w & r q g l w l r q 3 : 0 q ) / 7 6 5 & 3 : 0 q 0 , 1 ) / 7 3 ( 5 3 : 0 q ) / 7 6 ( 1 3 : 0 q ) / 7 6 7 $ 7 3 : 0 q ) / 7 6 7 $ 7 3 : 0 & o r f n 3 : 0 * h q h u d w r u % o r f n 6 l j q d o * h q h u d w r u 3 : 0 q * ( 1 $ 3 : 0 q * ( 1 % 3 : 0 q , 1 7 ( 1 , q w h u u x s w d q g 7 u l j j h u * h q h u d w r u 3 : 0 q 5 , 6 3 : 0 q , 6 & ' l j l w d o 7 u l j j h u v ) d x o w v s z p $ ? s z p % ? , q w h u u x s w v 7 u l j j h u v s z p i d x o w f p s $ f p s % ] h u r o r d g g l u s z p $ s z p % signals at reset. the column in the table below titled "pin mux/pin assignment" lists the possible gpio pin placements for these pwm signals. the afsel bit in the gpio alternate function select (gpioafsel) register (page 429) should be set to choose the pwm function. the number in parentheses is the encoding that must be programmed into the pmcn field in the gpio port control (gpiopctl) register (page 447) to assign the pwm signal to the specified gpio port pin. for more information on configuring gpios, see general-purpose input/outputs (gpios) on page 405. table 21-1. pwm signals (100lqfp) description buffer type a pin type pin mux / pin assignment pin number pin name pwm fault 0. ttl i pe4 (4) pg3 (8) pg2 (4) pj2 (10) pf4 (4) pb3 (2) pe1 (3) ph3 (2) pd6 (1) 6 16 17 39 58 65 75 83 99 fault0 pwm fault 1. ttl i pg6 (8) pg5 (5) pg4 (4) pf7 (9) pb6 (4) 37 40 41 42 90 fault1 pwm fault 2. ttl i pg3 (4) pc5 (4) ph5 (10) 16 24 63 fault2 pwm fault 3. ttl i pb3 (4) ph2 (4) 65 84 fault3 pwm 0. this signal is controlled by pwm generator 0. ttl o pd0 (1) pj0 (10) pg2 (1) pg0 (2) pa6 (4) pf0 (3) 10 14 17 19 34 47 pwm0 pwm 1. this signal is controlled by pwm generator 0. ttl o pd1 (1) pg3 (1) pg1 (2) pa7 (4) pf1 (3) pj1 (10) 11 16 18 35 61 87 pwm1 pwm 2. this signal is controlled by pwm generator 1. ttl o pd2 (3) pf2 (4) pb0 (2) ph0 (2) 12 60 66 86 pwm2 pwm 3. this signal is controlled by pwm generator 1. ttl o pd3 (3) pf3 (4) pb1 (2) ph1 (2) 13 59 67 85 pwm3 1113 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 21-1. pwm signals (100lqfp) (continued) description buffer type a pin type pin mux / pin assignment pin number pin name pwm 4. this signal is controlled by pwm generator 2. ttl o pe6 (1) pg0 (4) pa2 (4) pa6 (5) pf2 (2) ph6 (10) pe0 (1) ph0 (9) 2 19 28 34 60 62 74 86 pwm4 pwm 5. this signal is controlled by pwm generator 2. ttl o pe7 (1) ph7 (10) pg1 (4) pa3 (4) pa7 (5) pf3 (2) pe1 (1) ph1 (9) 1 15 18 29 35 59 75 85 pwm5 pwm 6. this signal is controlled by pwm generator 3. ttl o pc4 (4) pa4 (4) pg6 (4) pg4 (9) 25 30 37 41 pwm6 pwm 7. this signal is controlled by pwm generator 3. ttl o pc6 (4) pa5 (4) pg7 (4) pg5 (8) 23 31 36 40 pwm7 a. the ttl designation indicates the pin has ttl-compatible voltage levels. table 21-2. pwm signals (108bga) description buffer type a pin type pin mux / pin assignment pin number pin name pwm fault 0. ttl i pe4 (4) pg3 (8) pg2 (4) pj2 (10) pf4 (4) pb3 (2) pe1 (3) ph3 (2) pd6 (1) b2 j2 j1 k6 l9 e11 a12 d10 a3 fault0 pwm fault 1. ttl i pg6 (8) pg5 (5) pg4 (4) pf7 (9) pb6 (4) l7 m7 k3 k4 a7 fault1 pwm fault 2. ttl i pg3 (4) pc5 (4) ph5 (10) j2 m1 f10 fault2 pwm fault 3. ttl i pb3 (4) ph2 (4) e11 d11 fault3 july 03, 2014 1114 texas instruments-production data pulse width modulator (pwm) table 21-2. pwm signals (108bga) (continued) description buffer type a pin type pin mux / pin assignment pin number pin name pwm 0. this signal is controlled by pwm generator 0. ttl o pd0 (1) pj0 (10) pg2 (1) pg0 (2) pa6 (4) pf0 (3) g1 f3 j1 k1 l6 m9 pwm0 pwm 1. this signal is controlled by pwm generator 0. ttl o pd1 (1) pg3 (1) pg1 (2) pa7 (4) pf1 (3) pj1 (10) g2 j2 k2 m6 h12 b6 pwm1 pwm 2. this signal is controlled by pwm generator 1. ttl o pd2 (3) pf2 (4) pb0 (2) ph0 (2) h2 j11 e12 c9 pwm2 pwm 3. this signal is controlled by pwm generator 1. ttl o pd3 (3) pf3 (4) pb1 (2) ph1 (2) h1 j12 d12 c8 pwm3 pwm 4. this signal is controlled by pwm generator 2. ttl o pe6 (1) pg0 (4) pa2 (4) pa6 (5) pf2 (2) ph6 (10) pe0 (1) ph0 (9) a1 k1 m4 l6 j11 g3 b11 c9 pwm4 pwm 5. this signal is controlled by pwm generator 2. ttl o pe7 (1) ph7 (10) pg1 (4) pa3 (4) pa7 (5) pf3 (2) pe1 (1) ph1 (9) b1 h3 k2 l4 m6 j12 a12 c8 pwm5 pwm 6. this signal is controlled by pwm generator 3. ttl o pc4 (4) pa4 (4) pg6 (4) pg4 (9) l1 l5 l7 k3 pwm6 pwm 7. this signal is controlled by pwm generator 3. ttl o pc6 (4) pa5 (4) pg7 (4) pg5 (8) m2 m5 c10 m7 pwm7 a. the ttl designation indicates the pin has ttl-compatible voltage levels. 21.3 functional description 21.3.1 pwm timer the timer in each pwm generator runs in one of two modes: count-down mode or count-up/down mode. in count-down mode, the timer counts from the load value to zero, goes back to the load value, and continues counting down. in count-up/down mode, the timer counts from zero up to the load value, back down to zero, back up to the load value, and so on. generally, count-down mode 1115 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller is used for generating left- or right-aligned pwm signals, while the count-up/down mode is used for generating center-aligned pwm signals. the timers output three signals that are used in the pwm generation process: the direction signal (this is always low in count-down mode, but alternates between low and high in count-up/down mode), a single-clock-cycle-width high pulse when the counter is zero, and a single-clock-cycle-width high pulse when the counter is equal to the load value. note that in count-down mode, the zero pulse is immediately followed by the load pulse. in the figures in this chapter, these signals are labelled "dir," "zero," and "load." 21.3.2 pwm comparators each pwm generator has two comparators that monitor the value of the counter; when either comparator matches the counter, they output a single-clock-cycle-width high pulse, labelled "cmpa" and "cmpb" in the figures in this chapter. when in count-up/down mode, these comparators match both when counting up and when counting down, and thus are qualified by the counter direction signal. these qualified pulses are used in the pwm generation process. if either comparator match value is greater than the counter load value, then that comparator never outputs a high pulse. figure 21-3 on page 1117 shows the behavior of the counter and the relationship of these pulses when the counter is in count-down mode. figure 21-4 on page 1117 shows the behavior of the counter and the relationship of these pulses when the counter is in count-up/down mode. in these figures, the following definitions apply: load is the value in the pwmnload register compa is the value in the pwmncmpa register compb is the value in the pwmncmpb register 0 is the value zero load is the internal signal that has a single-clock-cycle-width high pulse when the counter is equal to the load value zero is the internal signal that has a single-clock-cycle-width high pulse when the counter is zero cmpa is the internal signal that has a single-clock-cycle-width high pulse when the counter is equal to compa cmpb is the internal signal that has a single-clock-cycle-width high pulse when the counter is equal to compb dir is the internal signal that indicates the count direction july 03, 2014 1116 texas instruments-production data pulse width modulator (pwm) figure 21-3. pwm count-down mode figure 21-4. pwm count-up/down mode 21.3.3 pwm signal generator each pwm generator takes the load, zero, cmpa, and cmpb pulses (qualified by the dir signal) and generates two internal pwm signals, pwma and pwmb. in count-down mode, there are four events that can affect these signals: zero, load, match a down, and match b down. in count-up/down mode, there are six events that can affect these signals: zero, load, match a down, match a up, match b down, and match b up. the match a or match b events are ignored when they coincide with the zero or load events. if the match a and match b events coincide, the first signal, pwma, is generated based only on the match a event, and the second signal, pwmb, is generated based only on the match b event. for each event, the effect on each output pwm signal is programmable: it can be left alone (ignoring the event), it can be toggled, it can be driven low, or it can be driven high. these actions can be used to generate a pair of pwm signals of various positions and duty cycles, which do or do not overlap. figure 21-5 on page 1118 shows the use of count-up/down mode to generate a pair of 1117 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller / 2 $ ' & 2 0 3 % & 2 0 3 $ o r d g ] h u r f p s % f p s $ g l u $ ' r z q % ' r z q / 2 $ ' & 2 0 3 $ o r d g ] h u r f p s % f p s $ g l u % 8 s $ 8 s $ ' r z q % ' r z q & 2 0 3 % center-aligned, overlapped pwm signals that have different duty cycles. this figure shows the pwma and pwmb signals before they have passed through the dead-band generator. figure 21-5. pwm generation example in count-up/down mode in this example, the first generator is set to drive high on match a up, drive low on match a down, and ignore the other four events. the second generator is set to drive high on match b up, drive low on match b down, and ignore the other four events. changing the value of comparator a changes the duty cycle of the pwma signal, and changing the value of comparator b changes the duty cycle of the pwmb signal. 21.3.4 dead-band generator the pwma and pwmb signals produced by each pwm generator are passed to the dead-band generator. if the dead-band generator is disabled, the pwm signals simply pass through to the pwma' and pwmb' signals unmodified. if the dead-band generator is enabled, the pwmb signal is lost and two pwm signals are generated based on the pwma signal. the first output pwm signal, pwma' is the pwma signal with the rising edge delayed by a programmable amount. the second output pwm signal, pwmb', is the inversion of the pwma signal with a programmable delay added between the falling edge of the pwma signal and the rising edge of the pwmb' signal. the resulting signals are a pair of active high signals where one is always high, except for a programmable amount of time at transitions where both are low. these signals are therefore suitable for driving a half-h bridge, with the dead-band delays preventing shoot-through current from damaging the power electronics. figure 21-6 on page 1118 shows the effect of the dead-band generator on the pwma signal and the resulting pwma' and pwmb' signals that are transmitted to the output control block. figure 21-6. pwm dead-band generator 21.3.5 interrupt/adc-trigger selector each pwm generator also takes the same four (or six) counter events and uses them to generate an interrupt or an adc trigger. any of these events or a set of these events can be selected as a source for an interrupt; when any of the selected events occur, an interrupt is generated. additionally, the same event, a different event, the same set of events, or a different set of events can be selected as a source for an adc trigger; when any of these selected events occur, an adc trigger pulse is generated. the selection of events allows the interrupt or adc trigger to occur at a specific position july 03, 2014 1118 texas instruments-production data pulse width modulator (pwm) / 2 $ ' & 2 0 3 % & 2 0 3 $ s z p % s z p $ s z p $ s z p $ ? s z p % ? 5 l v l q j ( g j h ' h o d \ ) d o o l q j ( g j h ' h o d \ within the pwma or pwmb signal. note that interrupts and adc triggers are based on the raw events; delays in the pwm signal edges caused by the dead-band generator are not taken into account. 21.3.6 synchronization methods the pwm module provides four pwm generators, each providing two pwm outputs that may be used in a wide variety of applications. generally speaking, the pwm is used in one of two categories of operation: unsynchronized. the pwm generator and its two output signals are used alone, independent of other pwm generators. synchronized. the pwm generator and its two outputs signals are used in conjunction with other pwm generators using a common, unified time base. if multiple pwm generators are configured with the same counter load value, synchronization can be used to guarantee that they also have the same count value (the pwm generators must be configured before they are synchronized). with this feature, more than two pwmn signals can be produced with a known relationship between the edges of those signals because the counters always have the same values. other states in the module provide mechanisms to maintain the common time base and mutual synchronization. the counter in a pwm generator can be reset to zero by writing the pwm time base sync (pwmsync) register and setting the syncn bit associated with the generator. multiple pwm generators can be synchronized together by setting all necessary syncn bits in one access. for example, setting the sync0 and sync1 bits in the pwmsync register causes the counters in pwm generators 0 and 1 to reset together. additional synchronization can occur between multiple pwm generators by updating register contents in one of the following three ways: immediately. the write value has immediate effect, and the hardware reacts immediately. locally synchronized. the write value does not affect the logic until the counter reaches the value zero at the end of the pwm cycle. in this case, the effect of the write is deferred, providing a guaranteed defined behavior and preventing overly short or overly long output pwm pulses. globally synchronized. the write value does not affect the logic until two sequential events have occurred: (1) the update mode for the generator function is programmed for global synchronization in the pwmnctl register, and (2) the counter reaches zero at the end of the pwm cycle. in this case, the effect of the write is deferred until the end of the pwm cycle following the end of all updates. this mode allows multiple items in multiple pwm generators to be updated simultaneously without odd effects during the update; everything runs from the old values until a point at which they all run from the new values. the update mode of the load and comparator match values can be individually configured in each pwm generator block. it typically makes sense to use the synchronous update mechanism across pwm generator blocks when the timers in those blocks are synchronized, although this is not required in order for this mechanism to function properly. the following registers provide either local or global synchronization based on the state of various update mode bits and fields in the pwmnctl register ( loadupd; cmpaupd; cmpbupd): generator registers: pwmnload , pwmncmpa , and pwmncmpb the following registers default to immediate update, but are provided with the optional functionality of synchronously updating rather than having all updates take immediate effect: 1119 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller module-level register: pwmenable (based on the state of the enupdn bits in the pwmenupd register). generator register: pwmngena , pwmngenb , pwmndbctl , pwmndbrise , and pwmndbfall (based on the state of various update mode bits and fields in the pwmnctl register ( genaupd; genbupd; dbctlupd; dbriseupd; dbfallupd)). all other registers are considered statically provisioned for the execution of an application or are used dynamically for purposes unrelated to maintaining synchronization and therefore do not need synchronous update functionality. 21.3.7 fault conditions a fault condition is one in which the controller must be signaled to stop normal pwm function and then set the pwmn signals to a safe state. two basic situations cause fault conditions: the microcontroller is stalled and cannot perform the necessary computation in the time required for motion control an external error or event is detected the pwm generator can use the following inputs to generate a fault condition, including: faultn pin assertion a stall of the controller generated by the debugger the trigger of an adc digital comparator fault conditions are calculated on a per-pwm generator basis. each pwm generator configures the necessary conditions to indicate a fault condition exists. this method allows the development of applications with dependent and independent control. four fault input pins ( fault0-fault3 ) are available. these inputs may be used with circuits that generate an active high or active low signal to indicate an error condition. a faultn pins may be individually programmed for the appropriate logic sense using the pwmnfltsen register. the pwm generator's mode control, including fault condition handling, is provided in the pwmnctl register. this register determines whether the input or a combination of faultn input signals and/or digital comparator triggers (as configured by the pwmnfltsrc0 and pwmnfltsrc1 registers) is used to generate a fault condition. the pwmnctl register also selects whether the fault condition is maintained as long as the external condition lasts or if it is latched until the fault condition until cleared by software. finally, this register also enables a counter that may be used to extend the period of a fault condition for external events to assure that the duration is a minimum length. the minimum fault period count is specified in the pwmnminfltper register. status regarding the specific fault cause is provided in the pwmnfltstat0 and pwmnfltstat1 registers. pwm generator fault conditions may be promoted to a controller interrupt using the pwminten register. 21.3.8 output control block the output control block takes care of the final conditioning of the pwma' and pwmb' signals before they go to the pins as the pwmn signals. via a single register, the pwm output enable (pwnenable) register, the set of pwm signals that are actually enabled to the pins can be modified. july 03, 2014 1120 texas instruments-production data pulse width modulator (pwm) this function can be used, for example, to perform commutation of a brushless dc motor with a single register write (and without modifying the individual pwm generators, which are modified by the feedback control loop). in addition, the updating of the bits in the pwmenable register can be configured to be immediate or locally or globally synchronized to the next synchronous update using the pwm enable update (pwmenupd) register. during fault conditions, the pwm output signals, pwmn , usually must be driven to safe values so that external equipment may be safely controlled. the pwmfault register specifies whether during a fault condition, the generated signal continues to be passed driven or to an encoding specified in the pwmfaultval register. a final inversion can be applied to any of the pwmn signals, making them active low instead of the default active high using the pwm output inversion (pwminvert) . the inversion is applied even if a value has been enabled in the pwmfault register and specified in the pwmfaultval register. in other words, if a bit is set in the pwmfault , pwmfaultval , and pwminvert registers, the output on the pwmn signal is 0, not 1 as specified in the pwmfaultval register. 21.4 initialization and configuration the following example shows how to initialize pwm generator 0 with a 25-khz frequency, a 25% duty cycle on the pwm0 pin, and a 75% duty cycle on the pwm1 pin. this example assumes the system clock is 20 mhz. 1. enable the pwm clock by writing a value of 0x0010.0000 to the rcgc0 register in the system control module (see page 262). 2. enable the clock to the appropriate gpio module via the rcgc2 register in the system control module (see page 282). 3. in the gpio module, enable the appropriate pins for their alternate function using the gpioafsel register. to determine which gpios to configure, see table 24-4 on page 1239. 4. configure the pmcn fields in the gpiopctl register to assign the pwm signals to the appropriate pins (see page 447 and table 24-5 on page 1248). 5. configure the run-mode clock configuration (rcc) register in the system control module to use the pwm divide ( usepwmdiv ) and set the divider (pwmdiv ) to divide by 2 (000). 6. configure the pwm generator for countdown mode with immediate updates to the parameters. write the pwm0ctl register with a value of 0x0000.0000. write the pwm0gena register with a value of 0x0000.008c. write the pwm0genb register with a value of 0x0000.080c. 7. set the period. for a 25-khz frequency, the period = 1/25,000, or 40 microseconds. the pwm clock source is 10 mhz; the system clock divided by 2. thus there are 400 clock ticks per period. use this value to set the pwm0load register. in count-down mode, set the load field in the pwm0load register to the requested period minus one. write the pwm0load register with a value of 0x0000.018f. 8. set the pulse width of the pwm0 pin for a 25% duty cycle. write the pwm0cmpa register with a value of 0x0000.012b. 1121 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 9. set the pulse width of the pwm1 pin for a 75% duty cycle. write the pwm0cmpb register with a value of 0x0000.0063. 10. start the timers in pwm generator 0. write the pwm0ctl register with a value of 0x0000.0001. 11. enable pwm outputs. write the pwmenable register with a value of 0x0000.0003. 21.5 register map table 21-3 on page 1122 lists the pwm registers. the offset listed is a hexadecimal increment to the register's address, relative to the pwm module's base address: pwm0: 0x4002.8000 note that the pwm module clock must be enabled before the registers can be programmed (see page 262). there must be a delay of 3 system clocks after the pwm module clock is enabled before any pwm module registers are accessed. table 21-3. pwm register map see page description reset type name offset 1126 pwm master control 0x0000.0000 r/w pwmctl 0x000 1128 pwm time base sync 0x0000.0000 r/w pwmsync 0x004 1129 pwm output enable 0x0000.0000 r/w pwmenable 0x008 1131 pwm output inversion 0x0000.0000 r/w pwminvert 0x00c 1133 pwm output fault 0x0000.0000 r/w pwmfault 0x010 1135 pwm interrupt enable 0x0000.0000 r/w pwminten 0x014 1137 pwm raw interrupt status 0x0000.0000 ro pwmris 0x018 1140 pwm interrupt status and clear 0x0000.0000 r/w1c pwmisc 0x01c 1143 pwm status 0x0000.0000 ro pwmstatus 0x020 1145 pwm fault condition value 0x0000.0000 r/w pwmfaultval 0x024 1147 pwm enable update 0x0000.0000 r/w pwmenupd 0x028 1151 pwm0 control 0x0000.0000 r/w pwm0ctl 0x040 1156 pwm0 interrupt and trigger enable 0x0000.0000 r/w pwm0inten 0x044 1159 pwm0 raw interrupt status 0x0000.0000 ro pwm0ris 0x048 1161 pwm0 interrupt status and clear 0x0000.0000 r/w1c pwm0isc 0x04c 1163 pwm0 load 0x0000.0000 r/w pwm0load 0x050 1164 pwm0 counter 0x0000.0000 ro pwm0count 0x054 1165 pwm0 compare a 0x0000.0000 r/w pwm0cmpa 0x058 july 03, 2014 1122 texas instruments-production data pulse width modulator (pwm) table 21-3. pwm register map (continued) see page description reset type name offset 1166 pwm0 compare b 0x0000.0000 r/w pwm0cmpb 0x05c 1167 pwm0 generator a control 0x0000.0000 r/w pwm0gena 0x060 1170 pwm0 generator b control 0x0000.0000 r/w pwm0genb 0x064 1173 pwm0 dead-band control 0x0000.0000 r/w pwm0dbctl 0x068 1174 pwm0 dead-band rising-edge delay 0x0000.0000 r/w pwm0dbrise 0x06c 1175 pwm0 dead-band falling-edge-delay 0x0000.0000 r/w pwm0dbfall 0x070 1176 pwm0 fault source 0 0x0000.0000 r/w pwm0fltsrc0 0x074 1178 pwm0 fault source 1 0x0000.0000 r/w pwm0fltsrc1 0x078 1181 pwm0 minimum fault period 0x0000.0000 r/w pwm0minfltper 0x07c 1151 pwm1 control 0x0000.0000 r/w pwm1ctl 0x080 1156 pwm1 interrupt and trigger enable 0x0000.0000 r/w pwm1inten 0x084 1159 pwm1 raw interrupt status 0x0000.0000 ro pwm1ris 0x088 1161 pwm1 interrupt status and clear 0x0000.0000 r/w1c pwm1isc 0x08c 1163 pwm1 load 0x0000.0000 r/w pwm1load 0x090 1164 pwm1 counter 0x0000.0000 ro pwm1count 0x094 1165 pwm1 compare a 0x0000.0000 r/w pwm1cmpa 0x098 1166 pwm1 compare b 0x0000.0000 r/w pwm1cmpb 0x09c 1167 pwm1 generator a control 0x0000.0000 r/w pwm1gena 0x0a0 1170 pwm1 generator b control 0x0000.0000 r/w pwm1genb 0x0a4 1173 pwm1 dead-band control 0x0000.0000 r/w pwm1dbctl 0x0a8 1174 pwm1 dead-band rising-edge delay 0x0000.0000 r/w pwm1dbrise 0x0ac 1175 pwm1 dead-band falling-edge-delay 0x0000.0000 r/w pwm1dbfall 0x0b0 1176 pwm1 fault source 0 0x0000.0000 r/w pwm1fltsrc0 0x0b4 1178 pwm1 fault source 1 0x0000.0000 r/w pwm1fltsrc1 0x0b8 1181 pwm1 minimum fault period 0x0000.0000 r/w pwm1minfltper 0x0bc 1151 pwm2 control 0x0000.0000 r/w pwm2ctl 0x0c0 1156 pwm2 interrupt and trigger enable 0x0000.0000 r/w pwm2inten 0x0c4 1159 pwm2 raw interrupt status 0x0000.0000 ro pwm2ris 0x0c8 1161 pwm2 interrupt status and clear 0x0000.0000 r/w1c pwm2isc 0x0cc 1163 pwm2 load 0x0000.0000 r/w pwm2load 0x0d0 1164 pwm2 counter 0x0000.0000 ro pwm2count 0x0d4 1165 pwm2 compare a 0x0000.0000 r/w pwm2cmpa 0x0d8 1123 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 21-3. pwm register map (continued) see page description reset type name offset 1166 pwm2 compare b 0x0000.0000 r/w pwm2cmpb 0x0dc 1167 pwm2 generator a control 0x0000.0000 r/w pwm2gena 0x0e0 1170 pwm2 generator b control 0x0000.0000 r/w pwm2genb 0x0e4 1173 pwm2 dead-band control 0x0000.0000 r/w pwm2dbctl 0x0e8 1174 pwm2 dead-band rising-edge delay 0x0000.0000 r/w pwm2dbrise 0x0ec 1175 pwm2 dead-band falling-edge-delay 0x0000.0000 r/w pwm2dbfall 0x0f0 1176 pwm2 fault source 0 0x0000.0000 r/w pwm2fltsrc0 0x0f4 1178 pwm2 fault source 1 0x0000.0000 r/w pwm2fltsrc1 0x0f8 1181 pwm2 minimum fault period 0x0000.0000 r/w pwm2minfltper 0x0fc 1151 pwm3 control 0x0000.0000 r/w pwm3ctl 0x100 1156 pwm3 interrupt and trigger enable 0x0000.0000 r/w pwm3inten 0x104 1159 pwm3 raw interrupt status 0x0000.0000 ro pwm3ris 0x108 1161 pwm3 interrupt status and clear 0x0000.0000 r/w1c pwm3isc 0x10c 1163 pwm3 load 0x0000.0000 r/w pwm3load 0x110 1164 pwm3 counter 0x0000.0000 ro pwm3count 0x114 1165 pwm3 compare a 0x0000.0000 r/w pwm3cmpa 0x118 1166 pwm3 compare b 0x0000.0000 r/w pwm3cmpb 0x11c 1167 pwm3 generator a control 0x0000.0000 r/w pwm3gena 0x120 1170 pwm3 generator b control 0x0000.0000 r/w pwm3genb 0x124 1173 pwm3 dead-band control 0x0000.0000 r/w pwm3dbctl 0x128 1174 pwm3 dead-band rising-edge delay 0x0000.0000 r/w pwm3dbrise 0x12c 1175 pwm3 dead-band falling-edge-delay 0x0000.0000 r/w pwm3dbfall 0x130 1176 pwm3 fault source 0 0x0000.0000 r/w pwm3fltsrc0 0x134 1178 pwm3 fault source 1 0x0000.0000 r/w pwm3fltsrc1 0x138 1181 pwm3 minimum fault period 0x0000.0000 r/w pwm3minfltper 0x13c 1182 pwm0 fault pin logic sense 0x0000.0000 r/w pwm0fltsen 0x800 1183 pwm0 fault status 0 0x0000.0000 - pwm0fltstat0 0x804 1185 pwm0 fault status 1 0x0000.0000 - pwm0fltstat1 0x808 1182 pwm1 fault pin logic sense 0x0000.0000 r/w pwm1fltsen 0x880 1183 pwm1 fault status 0 0x0000.0000 - pwm1fltstat0 0x884 1185 pwm1 fault status 1 0x0000.0000 - pwm1fltstat1 0x888 1182 pwm2 fault pin logic sense 0x0000.0000 r/w pwm2fltsen 0x900 july 03, 2014 1124 texas instruments-production data pulse width modulator (pwm) table 21-3. pwm register map (continued) see page description reset type name offset 1183 pwm2 fault status 0 0x0000.0000 - pwm2fltstat0 0x904 1185 pwm2 fault status 1 0x0000.0000 - pwm2fltstat1 0x908 1182 pwm3 fault pin logic sense 0x0000.0000 r/w pwm3fltsen 0x980 1183 pwm3 fault status 0 0x0000.0000 - pwm3fltstat0 0x984 1185 pwm3 fault status 1 0x0000.0000 - pwm3fltstat1 0x988 21.6 register descriptions the remainder of this section lists and describes the pwm registers, in numerical order by address offset. 1125 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 1: pwm master control (pwmctl), offset 0x000 this register provides master control over the pwm generation blocks. pwm master control (pwmctl) pwm0 base: 0x4002.8000 offset 0x000 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 globalsync0 globalsync1 globalsync2 globalsync3 reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:4 update pwm generator 3 description value any queued update to a load or comparator register in pwm generator 3 is applied the next time the corresponding counter becomes zero. 1 no effect. 0 this bit automatically clears when the updates have completed; it cannot be cleared by software. 0 r/w globalsync3 3 update pwm generator 2 description value any queued update to a load or comparator register in pwm generator 2 is applied the next time the corresponding counter becomes zero. 1 no effect. 0 this bit automatically clears when the updates have completed; it cannot be cleared by software. 0 r/w globalsync2 2 july 03, 2014 1126 texas instruments-production data pulse width modulator (pwm) description reset type name bit/field update pwm generator 1 description value any queued update to a load or comparator register in pwm generator 1 is applied the next time the corresponding counter becomes zero. 1 no effect. 0 this bit automatically clears when the updates have completed; it cannot be cleared by software. 0 r/w globalsync1 1 update pwm generator 0 description value any queued update to a load or comparator register in pwm generator 0 is applied the next time the corresponding counter becomes zero. 1 no effect. 0 this bit automatically clears when the updates have completed; it cannot be cleared by software. 0 r/w globalsync0 0 1127 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 2: pwm time base sync (pwmsync), offset 0x004 this register provides a method to perform synchronization of the counters in the pwm generation blocks. setting a bit in this register causes the specified counter to reset back to 0; setting multiple bits resets multiple counters simultaneously. the bits auto-clear after the reset has occurred; reading them back as zero indicates that the synchronization has completed. pwm time base sync (pwmsync) pwm0 base: 0x4002.8000 offset 0x004 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 sync0 sync1 sync2 sync3 reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:4 reset generator 3 counter description value resets the pwm generator 3 counter. 1 no effect. 0 0 r/w sync3 3 reset generator 2 counter description value resets the pwm generator 2 counter. 1 no effect. 0 0 r/w sync2 2 reset generator 1 counter description value resets the pwm generator 1 counter. 1 no effect. 0 0 r/w sync1 1 reset generator 0 counter description value resets the pwm generator 0 counter. 1 no effect. 0 0 r/w sync0 0 july 03, 2014 1128 texas instruments-production data pulse width modulator (pwm) register 3: pwm output enable (pwmenable), offset 0x008 this register provides a master control of which generated pwma' and pwmb' signals are output to the pwmn pins. by disabling a pwm output, the generation process can continue (for example, when the time bases are synchronized) without driving pwm signals to the pins. when bits in this register are set, the corresponding pwma' or pwmb' signal is passed through to the output stage. when bits are clear, the pwma' or pwmb' signal is replaced by a zero value which is also passed to the output stage. the pwminvert register controls the output stage, so if the corresponding bit is set in that register, the value seen on the pwmn signal is inverted from what is configured by the bits in this register. updates to the bits in this register can be immediate or locally or globally synchronized to the next synchronous update as controlled by the enupdn fields in the pwmenupd register. pwm output enable (pwmenable) pwm0 base: 0x4002.8000 offset 0x008 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pwm0en pwm1en pwm2en pwm3en pwm4en pwm5en pwm6en pwm7en reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 pwm7 output enable description value the generated pwm3b' signal is passed to the pwm7 pin. 1 the pwm7 signal has a zero value. 0 0 r/w pwm7en 7 pwm6 output enable description value the generated pwm3a' signal is passed to the pwm6 pin. 1 the pwm6 signal has a zero value. 0 0 r/w pwm6en 6 pwm5 output enable description value the generated pwm2b' signal is passed to the pwm5 pin. 1 the pwm5 signal has a zero value. 0 0 r/w pwm5en 5 1129 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field pwm4 output enable description value the generated pwm2a' signal is passed to the pwm4 pin. 1 the pwm4 signal has a zero value. 0 0 r/w pwm4en 4 pwm3 output enable description value the generated pwm1b' signal is passed to the pwm3 pin. 1 the pwm3 signal has a zero value. 0 0 r/w pwm3en 3 pwm2 output enable description value the generated pwm1a' signal is passed to the pwm2 pin. 1 the pwm2 signal has a zero value. 0 0 r/w pwm2en 2 pwm1 output enable description value the generated pwm0b' signal is passed to the pwm1 pin. 1 the pwm1 signal has a zero value. 0 0 r/w pwm1en 1 pwm0 output enable description value the generated pwm0a' signal is passed to the pwm0 pin. 1 the pwm0 signal has a zero value. 0 0 r/w pwm0en 0 july 03, 2014 1130 texas instruments-production data pulse width modulator (pwm) register 4: pwm output inversion (pwminvert), offset 0x00c this register provides a master control of the polarity of the pwmn signals on the device pins. the pwma' and pwmb' signals generated by the pwm generator are active high; but can be made active low via this register. disabled pwm channels are also passed through the output inverter (if so configured) so that inactive signals can be high. in addition, if the pwmfault register enables a specific value to be placed on the pwmn signals during a fault condition, that value is inverted if the corresponding bit in this register is set. pwm output inversion (pwminvert) pwm0 base: 0x4002.8000 offset 0x00c type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pwm0inv pwm1inv pwm2inv pwm3inv pwm4inv pwm5inv pwm6inv pwm7inv reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 invert pwm7 signal description value the pwm7 signal is inverted. 1 the pwm7 signal is not inverted. 0 0 r/w pwm7inv 7 invert pwm6 signal description value the pwm6 signal is inverted. 1 the pwm6 signal is not inverted. 0 0 r/w pwm6inv 6 invert pwm5 signal description value the pwm5 signal is inverted. 1 the pwm5 signal is not inverted. 0 0 r/w pwm5inv 5 invert pwm4 signal description value the pwm4 signal is inverted. 1 the pwm4 signal is not inverted. 0 0 r/w pwm4inv 4 1131 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field invert pwm3 signal description value the pwm3 signal is inverted. 1 the pwm3 signal is not inverted. 0 0 r/w pwm3inv 3 invert pwm2 signal description value the pwm2 signal is inverted. 1 the pwm2 signal is not inverted. 0 0 r/w pwm2inv 2 invert pwm1 signal description value the pwm1 signal is inverted. 1 the pwm1 signal is not inverted. 0 0 r/w pwm1inv 1 invert pwm0 signal description value the pwm0 signal is inverted. 1 the pwm0 signal is not inverted. 0 0 r/w pwm0inv 0 july 03, 2014 1132 texas instruments-production data pulse width modulator (pwm) register 5: pwm output fault (pwmfault), offset 0x010 this register controls the behavior of the pwmn outputs in the presence of fault conditions. both the fault inputs ( faultn pins and digital comparator outputs) and debug events are considered fault conditions. on a fault condition, each pwma' or pwmb' signal can be passed through unmodified or driven to the value specified by the corresponding bit in the pwmfaultval register. for outputs that are configured for pass-through, the debug event handling on the corresponding pwm generator also determines if the pwma' or pwmb' signal continues to be generated. fault condition control occurs before the output inverter, so pwm signals driven to a specified value on fault are inverted if the channel is configured for inversion (therefore, the pin is driven to the logical complement of the specified value on a fault condition). pwm output fault (pwmfault) pwm0 base: 0x4002.8000 offset 0x010 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 fault0 fault1 fault2 fault3 fault4 fault5 fault6 fault7 reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 pwm7 fault description value the pwm7 output signal is driven to the value specified by the pwm7 bit in the pwmfaultval register. 1 the generated pwm3b' signal is passed to the pwm7 pin. 0 0 r/w fault7 7 pwm6 fault description value the pwm6 output signal is driven to the value specified by the pwm6 bit in the pwmfaultval register. 1 the generated pwm3a' signal is passed to the pwm6 pin. 0 0 r/w fault6 6 pwm5 fault description value the pwm5 output signal is driven to the value specified by the pwm5 bit in the pwmfaultval register. 1 the generated pwm2b' signal is passed to the pwm5 pin. 0 0 r/w fault5 5 1133 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field pwm4 fault description value the pwm4 output signal is driven to the value specified by the pwm4 bit in the pwmfaultval register. 1 the generated pwm2a' signal is passed to the pwm4 pin. 0 0 r/w fault4 4 pwm3 fault description value the pwm3 output signal is driven to the value specified by the pwm3 bit in the pwmfaultval register. 1 the generated pwm1b' signal is passed to the pwm3 pin. 0 0 r/w fault3 3 pwm2 fault description value the pwm2 output signal is driven to the value specified by the pwm2 bit in the pwmfaultval register. 1 the generated pwm1a' signal is passed to the pwm2 pin. 0 0 r/w fault2 2 pwm1 fault description value the pwm1 output signal is driven to the value specified by the pwm1 bit in the pwmfaultval register. 1 the generated pwm0b' signal is passed to the pwm1 pin. 0 0 r/w fault1 1 pwm0 fault description value the pwm0 output signal is driven to the value specified by the pwm0 bit in the pwmfaultval register. 1 the generated pwm0a' signal is passed to the pwm0 pin. 0 0 r/w fault0 0 july 03, 2014 1134 texas instruments-production data pulse width modulator (pwm) register 6: pwm interrupt enable (pwminten), offset 0x014 this register controls the global interrupt generation capabilities of the pwm module. the events that can cause an interrupt are the fault input and the individual interrupts from the pwm generators. note: the "n" in the intfaultn and intpwmn bits in this register correspond to the pwm generators, not to the faultn signals. pwm interrupt enable (pwminten) pwm0 base: 0x4002.8000 offset 0x014 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 intfault0 intfault1 intfault2 intfault3 reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 intpwm0 intpwm1 intpwm2 intpwm3 reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 31:20 interrupt fault 3 description value an interrupt is sent to the interrupt controller when the fault condition for pwm generator 3 is asserted. 1 the fault condition for pwm generator 3 is suppressed and not sent to the interrupt controller. 0 0 r/w intfault3 19 interrupt fault 2 description value an interrupt is sent to the interrupt controller when the fault condition for pwm generator 2 is asserted. 1 the fault condition for pwm generator 2 is suppressed and not sent to the interrupt controller. 0 0 r/w intfault2 18 interrupt fault 1 description value an interrupt is sent to the interrupt controller when the fault condition for pwm generator 1 is asserted. 1 the fault condition for pwm generator 1 is suppressed and not sent to the interrupt controller. 0 0 r/w intfault1 17 1135 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field interrupt fault 0 description value an interrupt is sent to the interrupt controller when the fault condition for pwm generator 0 is asserted. 1 the fault condition for pwm generator 0 is suppressed and not sent to the interrupt controller. 0 0 r/w intfault0 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 15:4 pwm3 interrupt enable description value an interrupt is sent to the interrupt controller when the pwm generator 3 block asserts an interrupt. 1 the pwm generator 3 interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w intpwm3 3 pwm2 interrupt enable description value an interrupt is sent to the interrupt controller when the pwm generator 2 block asserts an interrupt. 1 the pwm generator 2 interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w intpwm2 2 pwm1 interrupt enable description value an interrupt is sent to the interrupt controller when the pwm generator 1 block asserts an interrupt. 1 the pwm generator 1 interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w intpwm1 1 pwm0 interrupt enable description value an interrupt is sent to the interrupt controller when the pwm generator 0 block asserts an interrupt. 1 the pwm generator 0 interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w intpwm0 0 july 03, 2014 1136 texas instruments-production data pulse width modulator (pwm) register 7: pwm raw interrupt status (pwmris), offset 0x018 this register provides the current set of interrupt sources that are asserted, regardless of whether they are enabled to cause an interrupt to be asserted to the interrupt controller. the fault interrupt is asserted based on the fault condition source that is specified by the pwmnctl , pwmnfltsrc0 and pwmnfltsrc1 registers. the fault interrupt is latched on detection and must be cleared through the pwm interrupt status and clear (pwmisc) register. the actual value of the faultn signals can be observed using the pwmstatus register. the pwm generator interrupts simply reflect the status of the pwm generators and are cleared via the interrupt status register in the pwm generator blocks. if a bit is set, the event is active; if a bit is clear the event is not active. pwm raw interrupt status (pwmris) pwm0 base: 0x4002.8000 offset 0x018 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 intfault0 intfault1 intfault2 intfault3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 intpwm0 intpwm1 intpwm2 intpwm3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 31:20 interrupt fault pwm 3 description value the fault condition for pwm generator 3 is asserted. 1 the fault condition for pwm generator 3 has not been asserted. 0 this bit is cleared by writing a 1 to the intfault3 bit in the pwmisc register. 0 ro intfault3 19 interrupt fault pwm 2 description value the fault condition for pwm generator 2 is asserted. 1 the fault condition for pwm generator 2 has not been asserted. 0 this bit is cleared by writing a 1 to the intfault2 bit in the pwmisc register. 0 ro intfault2 18 1137 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field interrupt fault pwm 1 description value the fault condition for pwm generator 1 is asserted. 1 the fault condition for pwm generator 1 has not been asserted. 0 this bit is cleared by writing a 1 to the intfault1 bit in the pwmisc register. 0 ro intfault1 17 interrupt fault pwm 0 description value the fault condition for pwm generator 0 is asserted. 1 the fault condition for pwm generator 0 has not been asserted. 0 this bit is cleared by writing a 1 to the intfault0 bit in the pwmisc register. 0 ro intfault0 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 15:4 pwm3 interrupt asserted description value the pwm generator 3 block interrupt is asserted. 1 the pwm generator 3 block interrupt has not been asserted. 0 the pwm3ris register shows the source of this interrupt. this bit is cleared by writing a 1 to the corresponding bit in the pwm3isc register. 0 ro intpwm3 3 pwm2 interrupt asserted description value the pwm generator 2 block interrupt is asserted. 1 the pwm generator 2 block interrupt has not been asserted. 0 the pwm2ris register shows the source of this interrupt. this bit is cleared by writing a 1 to the corresponding bit in the pwm2isc register. 0 ro intpwm2 2 pwm1 interrupt asserted description value the pwm generator 1 block interrupt is asserted. 1 the pwm generator 1 block interrupt has not been asserted. 0 the pwm1ris register shows the source of this interrupt. this bit is cleared by writing a 1 to the corresponding bit in the pwm1isc register. 0 ro intpwm1 1 july 03, 2014 1138 texas instruments-production data pulse width modulator (pwm) description reset type name bit/field pwm0 interrupt asserted description value the pwm generator 0 block interrupt is asserted. 1 the pwm generator 0 block interrupt has not been asserted. 0 the pwm0ris register shows the source of this interrupt. this bit is cleared by writing a 1 to the corresponding bit in the pwm0isc register. 0 ro intpwm0 0 1139 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 8: pwm interrupt status and clear (pwmisc), offset 0x01c this register provides a summary of the interrupt status of the individual pwm generator blocks. if a fault interrupt is set, the corresponding faultn input has caused an interrupt. for the fault interrupt, a write of 1 to that bit position clears the latched interrupt status. if an block interrupt bit is set, the corresponding generator block is asserting an interrupt. the individual interrupt status registers, pwmnisc , in each block must be consulted to determine the reason for the interrupt and used to clear the interrupt. pwm interrupt status and clear (pwmisc) pwm0 base: 0x4002.8000 offset 0x01c type r/w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 intfault0 intfault1 intfault2 intfault3 reserved r/w1c r/w1c r/w1c r/w1c ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 intpwm0 intpwm1 intpwm2 intpwm3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 31:20 fault3 interrupt asserted description value an enabled interrupt for the fault condition for pwm generator 3 is asserted or is latched. 1 the fault condition for pwm generator 3 has not been asserted or is not enabled. 0 writing a 1 to this bit clears it and the intfault3 bit in the pwmris register. 0 r/w1c intfault3 19 fault2 interrupt asserted description value an enabled interrupt for the fault condition for pwm generator 2 is asserted or is latched. 1 the fault condition for pwm generator 2 has not been asserted or is not enabled. 0 writing a 1 to this bit clears it and the intfault2 bit in the pwmris register. 0 r/w1c intfault2 18 july 03, 2014 1140 texas instruments-production data pulse width modulator (pwm) description reset type name bit/field fault1 interrupt asserted description value an enabled interrupt for the fault condition for pwm generator 1 is asserted or is latched. 1 the fault condition for pwm generator 1 has not been asserted or is not enabled. 0 writing a 1 to this bit clears it and the intfault1 bit in the pwmris register. 0 r/w1c intfault1 17 fault0 interrupt asserted description value an enabled interrupt for the fault condition for pwm generator 0 is asserted or is latched. 1 the fault condition for pwm generator 0 has not been asserted or is not enabled. 0 writing a 1 to this bit clears it and the intfault0 bit in the pwmris register. 0 r/w1c intfault0 16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 15:4 pwm3 interrupt status description value an enabled interrupt for the pwm generator 3 block is asserted. 1 the pwm generator 3 block interrupt is not asserted or is not enabled. 0 the pwm3ris register shows the source of this interrupt. this bit is cleared by writing a 1 to the corresponding bit in the pwm3isc register. 0 ro intpwm3 3 pwm2 interrupt status description value an enabled interrupt for the pwm generator 2 block is asserted. 1 the pwm generator 2 block interrupt is not asserted or is not enabled. 0 the pwm2ris register shows the source of this interrupt. this bit is cleared by writing a 1 to the corresponding bit in the pwm2isc register. 0 ro intpwm2 2 pwm1 interrupt status description value an enabled interrupt for the pwm generator 1 block is asserted. 1 the pwm generator 1 block interrupt is not asserted or is not enabled. 0 the pwm1ris register shows the source of this interrupt. this bit is cleared by writing a 1 to the corresponding bit in the pwm1isc register. 0 ro intpwm1 1 1141 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field pwm0 interrupt status description value an enabled interrupt for the pwm generator 0 block is asserted. 1 the pwm generator 0 block interrupt is not asserted or is not enabled. 0 the pwm0ris register shows the source of this interrupt. this bit is cleared by writing a 1 to the corresponding bit in the pwm0isc register. 0 ro intpwm0 0 july 03, 2014 1142 texas instruments-production data pulse width modulator (pwm) register 9: pwm status (pwmstatus), offset 0x020 this register provides the unlatched status of the pwm generator fault condition. pwm status (pwmstatus) pwm0 base: 0x4002.8000 offset 0x020 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 fault0 fault1 fault2 fault3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:4 generator 3 fault status description value the fault condition for pwm generator 3 is asserted. if the fltsrc bit in the pwm3ctl register is clear, the input is the source of the fault condition, and is therefore asserted. 1 the fault condition for pwm generator 3 is not asserted. 0 0 ro fault3 3 generator 2 fault status description value the fault condition for pwm generator 2 is asserted. if the fltsrc bit in the pwm2ctl register is clear, the input is the source of the fault condition, and is therefore asserted. 1 the fault condition for pwm generator 2 is not asserted. 0 0 ro fault2 2 generator 1 fault status description value the fault condition for pwm generator 1 is asserted. if the fltsrc bit in the pwm1ctl register is clear, the input is the source of the fault condition, and is therefore asserted. 1 the fault condition for pwm generator 1 is not asserted. 0 0 ro fault1 1 1143 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field generator 0 fault status description value the fault condition for pwm generator 0 is asserted. if the fltsrc bit in the pwm0ctl register is clear, the input is the source of the fault condition, and is therefore asserted. 1 the fault condition for pwm generator 0 is not asserted. 0 0 ro fault0 0 july 03, 2014 1144 texas instruments-production data pulse width modulator (pwm) register 10: pwm fault condition value (pwmfaultval), offset 0x024 this register specifies the output value driven on the pwmn signals during a fault condition if enabled by the corresponding bit in the pwmfault register. note that if the corresponding bit in the pwminvert register is set, the output value is driven to the logical not of the bit value in this register. pwm fault condition value (pwmfaultval) pwm0 base: 0x4002.8000 offset 0x024 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pwm0 pwm1 pwm2 pwm3 pwm4 pwm5 pwm6 pwm7 reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 pwm7 fault value description value the pwm7 output signal is driven high during fault conditions if the fault7 bit in the pwmfault register is set. 1 the pwm7 output signal is driven low during fault conditions if the fault7 bit in the pwmfault register is set. 0 0 r/w pwm7 7 pwm6 fault value description value the pwm6 output signal is driven high during fault conditions if the fault 6 bit in the pwmfault register is set. 1 the pwm6 output signal is driven low during fault conditions if the fault6 bit in the pwmfault register is set. 0 0 r/w pwm6 6 pwm5 fault value description value the pwm5 output signal is driven high during fault conditions if the fault5 bit in the pwmfault register is set. 1 the pwm5 output signal is driven low during fault conditions if the fault5 bit in the pwmfault register is set. 0 0 r/w pwm5 5 1145 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field pwm4 fault value description value the pwm4 output signal is driven high during fault conditions if the fault4 bit in the pwmfault register is set. 1 the pwm4 output signal is driven low during fault conditions if the fault4 bit in the pwmfault register is set. 0 0 r/w pwm4 4 pwm3 fault value description value the pwm3 output signal is driven high during fault conditions if the fault3 bit in the pwmfault register is set. 1 the pwm3 output signal is driven low during fault conditions if the fault3 bit in the pwmfault register is set. 0 0 r/w pwm3 3 pwm2 fault value description value the pwm2 output signal is driven high during fault conditions if the fault2 bit in the pwmfault register is set. 1 the pwm2 output signal is driven low during fault conditions if the fault2 bit in the pwmfault register is set. 0 0 r/w pwm2 2 pwm1 fault value description value the pwm1 output signal is driven high during fault conditions if the fault1 bit in the pwmfault register is set. 1 the pwm1 output signal is driven low during fault conditions if the fault1 bit in the pwmfault register is set. 0 0 r/w pwm1 1 pwm0 fault value description value the pwm0 output signal is driven high during fault conditions if the fault0 bit in the pwmfault register is set. 1 the pwm0 output signal is driven low during fault conditions if the fault0 bit in the pwmfault register is set. 0 0 r/w pwm0 0 july 03, 2014 1146 texas instruments-production data pulse width modulator (pwm) register 11: pwm enable update (pwmenupd), offset 0x028 this register specifies when updates to the pwmnen bit in the pwmenable register are performed. the pwmnen bit enables the pwma' or pwmb' output to be passed to the microcontroller's pin. updates can be immediate or locally or globally synchronized to the next synchronous update. pwm enable update (pwmenupd) pwm0 base: 0x4002.8000 offset 0x028 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 enupd0 enupd1 enupd2 enupd3 enupd4 enupd5 enupd6 enupd7 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:16 pwm7 enable update mode description value immediate writes to the pwm7en bit in the pwmenable register are used by the pwm generator immediately. 0x0 reserved 0x1 locally synchronized writes to the pwm7en bit in the pwmenable register are used by the pwm generator the next time the counter is 0. 0x2 globally synchronized writes to the pwm7en bit in the pwmenable register are used by the pwm generator the next time the counter is 0 after a synchronous update has been requested through the pwm master control ( pwmctl ) register. 0x3 0 r/w enupd7 15:14 1147 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field pwm6 enable update mode description value immediate writes to the pwm6en bit in the pwmenable register are used by the pwm generator immediately. 0x0 reserved 0x1 locally synchronized writes to the pwm6en bit in the pwmenable register are used by the pwm generator the next time the counter is 0. 0x2 globally synchronized writes to the pwm6en bit in the pwmenable register are used by the pwm generator the next time the counter is 0 after a synchronous update has been requested through the pwm master control ( pwmctl ) register. 0x3 0 r/w enupd6 13:12 pwm5 enable update mode description value immediate writes to the pwm5en bit in the pwmenable register are used by the pwm generator immediately. 0x0 reserved 0x1 locally synchronized writes to the pwm5en bit in the pwmenable register are used by the pwm generator the next time the counter is 0. 0x2 globally synchronized writes to the pwm5en bit in the pwmenable register are used by the pwm generator the next time the counter is 0 after a synchronous update has been requested through the pwm master control ( pwmctl ) register. 0x3 0 r/w enupd5 11:10 pwm4 enable update mode description value immediate writes to the pwm4en bit in the pwmenable register are used by the pwm generator immediately. 0x0 reserved 0x1 locally synchronized writes to the pwm4en bit in the pwmenable register are used by the pwm generator the next time the counter is 0. 0x2 globally synchronized writes to the pwm4en bit in the pwmenable register are used by the pwm generator the next time the counter is 0 after a synchronous update has been requested through the pwm master control ( pwmctl ) register. 0x3 0 r/w enupd4 9:8 july 03, 2014 1148 texas instruments-production data pulse width modulator (pwm) description reset type name bit/field pwm3 enable update mode description value immediate writes to the pwm3en bit in the pwmenable register are used by the pwm generator immediately. 0x0 reserved 0x1 locally synchronized writes to the pwm3en bit in the pwmenable register are used by the pwm generator the next time the counter is 0. 0x2 globally synchronized writes to the pwm3en bit in the pwmenable register are used by the pwm generator the next time the counter is 0 after a synchronous update has been requested through the pwm master control ( pwmctl ) register. 0x3 0 r/w enupd3 7:6 pwm2 enable update mode description value immediate writes to the pwm2en bit in the pwmenable register are used by the pwm generator immediately. 0x0 reserved 0x1 locally synchronized writes to the pwm2en bit in the pwmenable register are used by the pwm generator the next time the counter is 0. 0x2 globally synchronized writes to the pwm2en bit in the pwmenable register are used by the pwm generator the next time the counter is 0 after a synchronous update has been requested through the pwm master control ( pwmctl ) register. 0x3 0 r/w enupd2 5:4 pwm1 enable update mode description value immediate writes to the pwm1en bit in the pwmenable register are used by the pwm generator immediately. 0x0 reserved 0x1 locally synchronized writes to the pwm1en bit in the pwmenable register are used by the pwm generator the next time the counter is 0. 0x2 globally synchronized writes to the pwm1en bit in the pwmenable register are used by the pwm generator the next time the counter is 0 after a synchronous update has been requested through the pwm master control ( pwmctl ) register. 0x3 0 r/w enupd1 3:2 1149 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field pwm0 enable update mode description value immediate writes to the pwm0en bit in the pwmenable register are used by the pwm generator immediately. 0x0 reserved 0x1 locally synchronized writes to the pwm0en bit in the pwmenable register are used by the pwm generator the next time the counter is 0. 0x2 globally synchronized writes to the pwm0en bit in the pwmenable register are used by the pwm generator the next time the counter is 0 after a synchronous update has been requested through the pwm master control ( pwmctl ) register. 0x3 0 r/w enupd0 1:0 july 03, 2014 1150 texas instruments-production data pulse width modulator (pwm) register 12: pwm0 control (pwm0ctl), offset 0x040 register 13: pwm1 control (pwm1ctl), offset 0x080 register 14: pwm2 control (pwm2ctl), offset 0x0c0 register 15: pwm3 control (pwm3ctl), offset 0x100 these registers configure the pwm signal generation blocks (pwm0ctl controls the pwm generator 0 block, and so on). the register update mode, debug mode, counting mode, and block enable mode are all controlled via these registers. the blocks produce the pwm signals, which can be either two independent pwm signals (from the same counter), or a paired set of pwm signals with dead-band delays added. the pwm0 block produces the pwm0 and pwm1 outputs, the pwm1 block produces the pwm2 and pwm3 outputs, the pwm2 block produces the pwm4 and pwm5 outputs, and the pwm3 block produces the pwm6 and pwm7 outputs. pwm0 control (pwm0ctl) pwm0 base: 0x4002.8000 offset 0x040 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 fltsrc minfltper latch reserved r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 enable mode debug loadupd cmpaupd cmpbupd genaupd genbupd dbctlupd dbriseupd dbfallupd r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 31:19 latch fault input description value fault condition not latched a fault condition is in effect for as long as the generating source is asserting. 0 fault condition latched a fault condition is set as the result of the assertion of the faulting source and is held (latched) while the pwmisc intfaultn bit is set. clearing the intfaultn bit clears the fault condition. 1 0 r/w latch 18 1151 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field minimum fault period this bit specifies that the pwm generator enables a one-shot counter to provide a minimum fault condition period. the timer begins counting on the rising edge of the fault condition to extend the condition for a minimum duration of the count value. the timer ignores the state of the fault condition while counting. the minimum fault delay is in effect only when the minfltper bit is set. if a detected fault is in the process of being extended when the minfltper bit is cleared, the fault condition extension is aborted. the delay time is specified by the pwmnminfltper register mfp field value. the effect of this is to pulse stretch the fault condition input. the delay value is defined by the pwm clock period. because the fault input is not synchronized to the pwm clock, the period of the time is pwmclock * (mfp value + 1) or pwmclock * (mfp value + 2). the delay function makes sense only if the fault source is unlatched. a latched fault source makes the fault condition appear asserted until cleared by software and negates the utility of the extend feature. it applies to all fault condition sources as specified in the fltsrc field. description value the fault input deassertion is unaffected. 0 the pwmnminfltper one-shot counter is active and extends the period of the fault condition to a minimum period. 1 0 r/w minfltper 17 fault condition source description value the fault condition is determined by the fault0 input. 0 the fault condition is determined by the configuration of the pwmnfltsrc0 and pwmnfltsrc1 registers. 1 0 r/w fltsrc 16 pwmndbfall update mode description value immediate the pwmndbfall register value is immediately updated on a write. 0x0 reserved 0x1 locally synchronized updates to the register are reflected to the generator the next time the counter is 0. 0x2 globally synchronized updates to the register are delayed until the next time the counter is 0 after a synchronous update has been requested through the pwmctl register. 0x3 0x0 r/w dbfallupd 15:14 july 03, 2014 1152 texas instruments-production data pulse width modulator (pwm) description reset type name bit/field pwmndbrise update mode description value immediate the pwmndbrise register value is immediately updated on a write. 0x0 reserved 0x1 locally synchronized updates to the register are reflected to the generator the next time the counter is 0. 0x2 globally synchronized updates to the register are delayed until the next time the counter is 0 after a synchronous update has been requested through the pwmctl register. 0x3 0x0 r/w dbriseupd 13:12 pwmndbctl update mode description value immediate the pwmndbctl register value is immediately updated on a write. 0x0 reserved 0x1 locally synchronized updates to the register are reflected to the generator the next time the counter is 0. 0x2 globally synchronized updates to the register are delayed until the next time the counter is 0 after a synchronous update has been requested through the pwmctl register. 0x3 0x0 r/w dbctlupd 11:10 pwmngenb update mode description value immediate the pwmngenb register value is immediately updated on a write. 0x0 reserved 0x1 locally synchronized updates to the register are reflected to the generator the next time the counter is 0. 0x2 globally synchronized updates to the register are delayed until the next time the counter is 0 after a synchronous update has been requested through the pwmctl register. 0x3 0x0 r/w genbupd 9:8 1153 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field pwmngena update mode description value immediate the pwmngena register value is immediately updated on a write. 0x0 reserved 0x1 locally synchronized updates to the register are reflected to the generator the next time the counter is 0. 0x2 globally synchronized updates to the register are delayed until the next time the counter is 0 after a synchronous update has been requested through the pwmctl register. 0x3 0x0 r/w genaupd 7:6 comparator b update mode description value locally synchronized updates to the pwmncmpb register are reflected to the generator the next time the counter is 0. 0 globally synchronized updates to the register are delayed until the next time the counter is 0 after a synchronous update has been requested through the pwmctl register. 1 0 r/w cmpbupd 5 comparator a update mode description value locally synchronized updates to the pwmncmpa register are reflected to the generator the next time the counter is 0. 0 globally synchronized updates to the register are delayed until the next time the counter is 0 after a synchronous update has been requested through the pwmctl register. 1 0 r/w cmpaupd 4 load register update mode description value locally synchronized updates to the pwmnload register are reflected to the generator the next time the counter is 0. 0 globally synchronized updates to the register are delayed until the next time the counter is 0 after a synchronous update has been requested through the pwmctl register. 1 0 r/w loadupd 3 july 03, 2014 1154 texas instruments-production data pulse width modulator (pwm) description reset type name bit/field debug mode description value the counter stops running when it next reaches 0 and continues running again when no longer in debug mode. 0 the counter always runs when in debug mode. 1 0 r/w debug 2 counter mode description value the counter counts down from the load value to 0 and then wraps back to the load value (count-down mode). 0 the counter counts up from 0 to the load value, back down to 0, and then repeats (count-up/down mode). 1 0 r/w mode 1 pwm block enable description value the entire pwm generation block is disabled and not clocked. 0 the pwm generation block is enabled and produces pwm signals. 1 0 r/w enable 0 1155 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 16: pwm0 interrupt and trigger enable (pwm0inten), offset 0x044 register 17: pwm1 interrupt and trigger enable (pwm1inten), offset 0x084 register 18: pwm2 interrupt and trigger enable (pwm2inten), offset 0x0c4 register 19: pwm3 interrupt and trigger enable (pwm3inten), offset 0x104 these registers control the interrupt and adc trigger generation capabilities of the pwm generators (pwm0inten controls the pwm generator 0 block, and so on). the events that can cause an interrupt,or an adc trigger are: the counter being equal to the load register the counter being equal to zero the counter being equal to the pwmncmpa register while counting up the counter being equal to the pwmncmpa register while counting down the counter being equal to the pwmncmpb register while counting up the counter being equal to the pwmncmpb register while counting down any combination of these events can generate either an interrupt or an adc trigger, though no determination can be made as to the actual event that caused an adc trigger if more than one is specified. the pwmnris register provides information about which events have caused raw interrupts. pwm0 interrupt and trigger enable (pwm0inten) pwm0 base: 0x4002.8000 offset 0x044 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 intcntzero intcntload intcmpau intcmpad intcmpbu intcmpbd reserved trcntzero trcntload trcmpau trcmpad trcmpbu trcmpbd reserved r/w r/w r/w r/w r/w r/w ro ro r/w r/w r/w r/w r/w r/w ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:14 trigger for counter= pwmncmpb down description value an adc trigger pulse is output when the counter matches the value in the pwmncmpb register value while counting down. 1 no adc trigger is output. 0 0 r/w trcmpbd 13 july 03, 2014 1156 texas instruments-production data pulse width modulator (pwm) description reset type name bit/field trigger for counter= pwmncmpb up description value an adc trigger pulse is output when the counter matches the value in the pwmncmpb register value while counting up. 1 no adc trigger is output. 0 0 r/w trcmpbu 12 trigger for counter= pwmncmpa down description value an adc trigger pulse is output when the counter matches the value in the pwmncmpa register value while counting down. 1 no adc trigger is output. 0 0 r/w trcmpad 11 trigger for counter= pwmncmpa up description value an adc trigger pulse is output when the counter matches the value in the pwmncmpa register value while counting up. 1 no adc trigger is output. 0 0 r/w trcmpau 10 trigger for counter= pwmnload description value an adc trigger pulse is output when the counter matches the pwmnload register. 1 no adc trigger is output. 0 0 r/w trcntload 9 trigger for counter=0 description value an adc trigger pulse is output when the counter is 0. 1 no adc trigger is output. 0 0 r/w trcntzero 8 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 7:6 interrupt for counter= pwmncmpb down description value a raw interrupt occurs when the counter matches the value in the pwmncmpb register value while counting down. 1 no interrupt. 0 0 r/w intcmpbd 5 1157 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field interrupt for counter= pwmncmpb up description value a raw interrupt occurs when the counter matches the value in the pwmncmpb register value while counting up. 1 no interrupt. 0 0 r/w intcmpbu 4 interrupt for counter= pwmncmpa down description value a raw interrupt occurs when the counter matches the value in the pwmncmpa register value while counting down. 1 no interrupt. 0 0 r/w intcmpad 3 interrupt for counter= pwmncmpa up description value a raw interrupt occurs when the counter matches the value in the pwmncmpa register value while counting up. 1 no interrupt. 0 0 r/w intcmpau 2 interrupt for counter= pwmnload description value a raw interrupt occurs when the counter matches the value in the pwmnload register value. 1 no interrupt. 0 0 r/w intcntload 1 interrupt for counter=0 description value a raw interrupt occurs when the counter is zero. 1 no interrupt. 0 0 r/w intcntzero 0 july 03, 2014 1158 texas instruments-production data pulse width modulator (pwm) register 20: pwm0 raw interrupt status (pwm0ris), offset 0x048 register 21: pwm1 raw interrupt status (pwm1ris), offset 0x088 register 22: pwm2 raw interrupt status (pwm2ris), offset 0x0c8 register 23: pwm3 raw interrupt status (pwm3ris), offset 0x108 these registers provide the current set of interrupt sources that are asserted, regardless of whether they cause an interrupt to be asserted to the controller ( pwm0ris controls the pwm generator 0 block, and so on). if a bit is set, the event has occurred; if a bit is clear, the event has not occurred. bits in this register are cleared by writing a 1 to the corresponding bit in the pwmnisc register. pwm0 raw interrupt status (pwm0ris) pwm0 base: 0x4002.8000 offset 0x048 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 intcntzero intcntload intcmpau intcmpad intcmpbu intcmpbd reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:6 comparator b down interrupt status description value the counter has matched the value in the pwmncmpb register while counting down. 1 an interrupt has not occurred. 0 this bit is cleared by writing a 1 to the intcmpbd bit in the pwmnisc register. 0 ro intcmpbd 5 comparator b up interrupt status description value the counter has matched the value in the pwmncmpb register while counting up. 1 an interrupt has not occurred. 0 this bit is cleared by writing a 1 to the intcmpbu bit in the pwmnisc register. 0 ro intcmpbu 4 1159 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field comparator a down interrupt status description value the counter has matched the value in the pwmncmpa register while counting down. 1 an interrupt has not occurred. 0 this bit is cleared by writing a 1 to the intcmpad bit in the pwmnisc register. 0 ro intcmpad 3 comparator a up interrupt status description value the counter has matched the value in the pwmncmpa register while counting up. 1 an interrupt has not occurred. 0 this bit is cleared by writing a 1 to the intcmpau bit in the pwmnisc register. 0 ro intcmpau 2 counter=load interrupt status description value the counter has matched the value in the pwmnload register. 1 an interrupt has not occurred. 0 this bit is cleared by writing a 1 to the intcntload bit in the pwmnisc register. 0 ro intcntload 1 counter=0 interrupt status description value the counter has matched zero. 1 an interrupt has not occurred. 0 this bit is cleared by writing a 1 to the intcntzero bit in the pwmnisc register. 0 ro intcntzero 0 july 03, 2014 1160 texas instruments-production data pulse width modulator (pwm) register 24: pwm0 interrupt status and clear (pwm0isc), offset 0x04c register 25: pwm1 interrupt status and clear (pwm1isc), offset 0x08c register 26: pwm2 interrupt status and clear (pwm2isc), offset 0x0cc register 27: pwm3 interrupt status and clear (pwm3isc), offset 0x10c these registers provide the current set of interrupt sources that are asserted to the interrupt controller (pwm0isc controls the pwm generator 0 block, and so on). a bit is set if the event has occurred and is enabled in the pwmninten register; if a bit is clear, the event has not occurred or is not enabled. these are r/w1c registers; writing a 1 to a bit position clears the corresponding interrupt reason. pwm0 interrupt status and clear (pwm0isc) pwm0 base: 0x4002.8000 offset 0x04c type r/w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 intcntzero intcntload intcmpau intcmpad intcmpbu intcmpbd reserved r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:6 comparator b down interrupt description value the intcmpbd bits in the pwmnris and pwmninten registers are set, providing an interrupt to the interrupt controller. 1 no interrupt has occurred or the interrupt is masked. 0 this bit is cleared by writing a 1. clearing this bit also clears the intcmpbd bit in the pwmnris register. 0 r/w1c intcmpbd 5 comparator b up interrupt description value the intcmpbu bits in the pwmnris and pwmninten registers are set, providing an interrupt to the interrupt controller. 1 no interrupt has occurred or the interrupt is masked. 0 this bit is cleared by writing a 1. clearing this bit also clears the intcmpbu bit in the pwmnris register. 0 r/w1c intcmpbu 4 1161 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field comparator a down interrupt description value the intcmpad bits in the pwmnris and pwmninten registers are set, providing an interrupt to the interrupt controller. 1 no interrupt has occurred or the interrupt is masked. 0 this bit is cleared by writing a 1. clearing this bit also clears the intcmpad bit in the pwmnris register. 0 r/w1c intcmpad 3 comparator a up interrupt description value the intcmpau bits in the pwmnris and pwmninten registers are set, providing an interrupt to the interrupt controller. 1 no interrupt has occurred or the interrupt is masked. 0 this bit is cleared by writing a 1. clearing this bit also clears the intcmpau bit in the pwmnris register. 0 r/w1c intcmpau 2 counter=load interrupt description value the intcntload bits in the pwmnris and pwmninten registers are set, providing an interrupt to the interrupt controller. 1 no interrupt has occurred or the interrupt is masked. 0 this bit is cleared by writing a 1. clearing this bit also clears the intcntload bit in the pwmnris register. 0 r/w1c intcntload 1 counter=0 interrupt description value the intcntzero bits in the pwmnris and pwmninten registers are set, providing an interrupt to the interrupt controller. 1 no interrupt has occurred or the interrupt is masked. 0 this bit is cleared by writing a 1. clearing this bit also clears the intcntzero bit in the pwmnris register. 0 r/w1c intcntzero 0 july 03, 2014 1162 texas instruments-production data pulse width modulator (pwm) register 28: pwm0 load (pwm0load), offset 0x050 register 29: pwm1 load (pwm1load), offset 0x090 register 30: pwm2 load (pwm2load), offset 0x0d0 register 31: pwm3 load (pwm3load), offset 0x110 these registers contain the load value for the pwm counter ( pwm0load controls the pwm generator 0 block, and so on). based on the counter mode configured by the mode bit in the pwmnctl register, this value is either loaded into the counter after it reaches zero or is the limit of up-counting after which the counter decrements back to zero. when this value matches the counter, a pulse is output which can be configured to drive the generation of the pwma and/or pwmb signal (via the pwmngena / pwmngenb register) or drive an interruptor adc trigger (via the pwmninten register). if the load value update mode is locally synchronized (based on the loadupd field encoding in the pwmnctl register), the 16-bit load value is used the next time the counter reaches zero. if the update mode is globally synchronized, it is used the next time the counter reaches zero after a synchronous update has been requested through the pwm master control (pwmctl) register (see page 1126). if this register is re-written before the actual update occurs, the previous value is never used and is lost. pwm0 load (pwm0load) pwm0 base: 0x4002.8000 offset 0x050 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 load r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 counter load value the counter load value. 0x0000 r/w load 15:0 1163 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 32: pwm0 counter (pwm0count), offset 0x054 register 33: pwm1 counter (pwm1count), offset 0x094 register 34: pwm2 counter (pwm2count), offset 0x0d4 register 35: pwm3 counter (pwm3count), offset 0x114 these registers contain the current value of the pwm counter ( pwm0count is the value of the pwm generator 0 block, and so on). when this value matches zero or the value in the pwmnload , pwmncmpa , or pwmncmpb registers, a pulse is output which can be configured to drive the generation of a pwm signal or drive an interrupt or adc trigger. pwm0 counter (pwm0count) pwm0 base: 0x4002.8000 offset 0x054 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 count ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 counter value the current value of the counter. 0x0000 ro count 15:0 july 03, 2014 1164 texas instruments-production data pulse width modulator (pwm) register 36: pwm0 compare a (pwm0cmpa), offset 0x058 register 37: pwm1 compare a (pwm1cmpa), offset 0x098 register 38: pwm2 compare a (pwm2cmpa), offset 0x0d8 register 39: pwm3 compare a (pwm3cmpa), offset 0x118 these registers contain a value to be compared against the counter ( pwm0cmpa controls the pwm generator 0 block, and so on). when this value matches the counter, a pulse is output which can be configured to drive the generation of the pwma and pwmb signals (via the pwmngena and pwmngenb registers) or drive an interrupt or adc trigger (via the pwmninten register). if the value of this register is greater than the pwmnload register (see page 1163), then no pulse is ever output. if the comparator a update mode is locally synchronized (based on the cmpaupd bit in the pwmnctl register), the 16-bit compa value is used the next time the counter reaches zero. if the update mode is globally synchronized, it is used the next time the counter reaches zero after a synchronous update has been requested through the pwm master control (pwmctl) register (see page 1126). if this register is rewritten before the actual update occurs, the previous value is never used and is lost. pwm0 compare a (pwm0cmpa) pwm0 base: 0x4002.8000 offset 0x058 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 compa r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:16 comparator a value the value to be compared against the counter. 0x00 r/w compa 15:0 1165 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 40: pwm0 compare b (pwm0cmpb), offset 0x05c register 41: pwm1 compare b (pwm1cmpb), offset 0x09c register 42: pwm2 compare b (pwm2cmpb), offset 0x0dc register 43: pwm3 compare b (pwm3cmpb), offset 0x11c these registers contain a value to be compared against the counter ( pwm0cmpb controls the pwm generator 0 block, and so on). when this value matches the counter, a pulse is output which can be configured to drive the generation of the pwma and pwmb signals (via the pwmngena and pwmngenb registers) or drive an interrupt or adc trigger (via the pwmninten register). if the value of this register is greater than the pwmnload register, no pulse is ever output. if the comparator b update mode is locally synchronized (based on the cmpbupd bit in the pwmnctl register), the 16-bit compb value is used the next time the counter reaches zero. if the update mode is globally synchronized, it is used the next time the counter reaches zero after a synchronous update has been requested through the pwm master control (pwmctl) register (see page 1126). if this register is rewritten before the actual update occurs, the previous value is never used and is lost. pwm0 compare b (pwm0cmpb) pwm0 base: 0x4002.8000 offset 0x05c type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 compb r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 comparator b value the value to be compared against the counter. 0x0000 r/w compb 15:0 july 03, 2014 1166 texas instruments-production data pulse width modulator (pwm) register 44: pwm0 generator a control (pwm0gena), offset 0x060 register 45: pwm1 generator a control (pwm1gena), offset 0x0a0 register 46: pwm2 generator a control (pwm2gena), offset 0x0e0 register 47: pwm3 generator a control (pwm3gena), offset 0x120 these registers control the generation of the pwma signal based on the load and zero output pulses from the counter, as well as the compare a and compare b pulses from the comparators (pwm0gena controls the pwm generator 0 block, and so on). when the counter is running in count-down mode, only four of these events occur; when running in count-up/down mode, all six occur. these events provide great flexibility in the positioning and duty cycle of the resulting pwm signal. the pwm0gena register controls generation of the pwm0a signal; pwm1gena , the pwm1a signal; pwm2gena , the pwm2a signal; and pwm3gena , the pwm3a signal. if a zero or load event coincides with a compare a or compare b event, the zero or load action is taken and the compare a or compare b action is ignored. if a compare a event coincides with a compare b event, the compare a action is taken and the compare b action is ignored. if the generator a update mode is immediate (based on the genaupd field encoding in the pwmnctl register), the actcmpbd, actcmpbu, actcmpad, actcmpau, actload , and actzero values are used immediately. if the update mode is locally synchronized, these values are used the next time the counter reaches zero. if the update mode is globally synchronized, these values are used the next time the counter reaches zero after a synchronous update has been requested through the pwm master control (pwmctl) register (see page 1126). if this register is rewritten before the actual update occurs, the previous value is never used and is lost. pwm0 generator a control (pwm0gena) pwm0 base: 0x4002.8000 offset 0x060 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 actzero actload actcmpau actcmpad actcmpbu actcmpbd reserved r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0 ro reserved 31:12 1167 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field action for comparator b down this field specifies the action to be taken when the counter matches comparator b while counting down. description value do nothing. 0x0 invert pwma. 0x1 drive pwma low. 0x2 drive pwma high. 0x3 0x0 r/w actcmpbd 11:10 action for comparator b up this field specifies the action to be taken when the counter matches comparator b while counting up. this action can only occur when the mode bit in the pwmnctl register is set. description value do nothing. 0x0 invert pwma. 0x1 drive pwma low. 0x2 drive pwma high. 0x3 0x0 r/w actcmpbu 9:8 action for comparator a down this field specifies the action to be taken when the counter matches comparator a while counting down. description value do nothing. 0x0 invert pwma. 0x1 drive pwma low. 0x2 drive pwma high. 0x3 0x0 r/w actcmpad 7:6 action for comparator a up this field specifies the action to be taken when the counter matches comparator a while counting up. this action can only occur when the mode bit in the pwmnctl register is set. description value do nothing. 0x0 invert pwma. 0x1 drive pwma low. 0x2 drive pwma high. 0x3 0x0 r/w actcmpau 5:4 july 03, 2014 1168 texas instruments-production data pulse width modulator (pwm) description reset type name bit/field action for counter= load this field specifies the action to be taken when the counter matches the value in the pwmnload register. description value do nothing. 0x0 invert pwma. 0x1 drive pwma low. 0x2 drive pwma high. 0x3 0x0 r/w actload 3:2 action for counter=0 this field specifies the action to be taken when the counter is zero. description value do nothing. 0x0 invert pwma. 0x1 drive pwma low. 0x2 drive pwma high. 0x3 0x0 r/w actzero 1:0 1169 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 48: pwm0 generator b control (pwm0genb), offset 0x064 register 49: pwm1 generator b control (pwm1genb), offset 0x0a4 register 50: pwm2 generator b control (pwm2genb), offset 0x0e4 register 51: pwm3 generator b control (pwm3genb), offset 0x124 these registers control the generation of the pwmb signal based on the load and zero output pulses from the counter, as well as the compare a and compare b pulses from the comparators (pwm0genb controls the pwm generator 0 block, and so on). when the counter is running in count-down mode, only four of these events occur; when running in count-up/down mode, all six occur. these events provide great flexibility in the positioning and duty cycle of the resulting pwm signal. the pwm0genb register controls generation of the pwm0b signal; pwm1genb , the pwm1b signal; pwm2genb , the pwm2b signal; and pwm3genb , the pwm3b signal. if a zero or load event coincides with a compare a or compare b event, the zero or load action is taken and the compare a or compare b action is ignored. if a compare a event coincides with a compare b event, the compare b action is taken and the compare a action is ignored. if the generator b update mode is immediate (based on the genbupd field encoding in the pwmnctl register), the actcmpbd, actcmpbu, actcmpad, actcmpau, actload , and actzero values are used immediately. if the update mode is locally synchronized, these values are used the next time the counter reaches zero. if the update mode is globally synchronized, these values are used the next time the counter reaches zero after a synchronous update has been requested through the pwm master control (pwmctl) register (see page 1126). if this register is rewritten before the actual update occurs, the previous value is never used and is lost. pwm0 generator b control (pwm0genb) pwm0 base: 0x4002.8000 offset 0x064 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 actzero actload actcmpau actcmpad actcmpbu actcmpbd reserved r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0 ro reserved 31:12 july 03, 2014 1170 texas instruments-production data pulse width modulator (pwm) description reset type name bit/field action for comparator b down this field specifies the action to be taken when the counter matches comparator b while counting down. description value do nothing. 0x0 invert pwmb. 0x1 drive pwmb low. 0x2 drive pwmb high. 0x3 0x0 r/w actcmpbd 11:10 action for comparator b up this field specifies the action to be taken when the counter matches comparator b while counting up. this action can only occur when the mode bit in the pwmnctl register is set. description value do nothing. 0x0 invert pwmb. 0x1 drive pwmb low. 0x2 drive pwmb high. 0x3 0x0 r/w actcmpbu 9:8 action for comparator a down this field specifies the action to be taken when the counter matches comparator a while counting down. description value do nothing. 0x0 invert pwmb. 0x1 drive pwmb low. 0x2 drive pwmb high. 0x3 0x0 r/w actcmpad 7:6 action for comparator a up this field specifies the action to be taken when the counter matches comparator a while counting up. this action can only occur when the mode bit in the pwmnctl register is set. description value do nothing. 0x0 invert pwmb. 0x1 drive pwmb low. 0x2 drive pwmb high. 0x3 0x0 r/w actcmpau 5:4 1171 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field action for counter= load this field specifies the action to be taken when the counter matches the load value. description value do nothing. 0x0 invert pwmb. 0x1 drive pwmb low. 0x2 drive pwmb high. 0x3 0x0 r/w actload 3:2 action for counter=0 this field specifies the action to be taken when the counter is 0. description value do nothing. 0x0 invert pwmb. 0x1 drive pwmb low. 0x2 drive pwmb high. 0x3 0x0 r/w actzero 1:0 july 03, 2014 1172 texas instruments-production data pulse width modulator (pwm) register 52: pwm0 dead-band control (pwm0dbctl), offset 0x068 register 53: pwm1 dead-band control (pwm1dbctl), offset 0x0a8 register 54: pwm2 dead-band control (pwm2dbctl), offset 0x0e8 register 55: pwm3 dead-band control (pwm3dbctl), offset 0x128 the pwmndbctl register controls the dead-band generator, which produces the pwmn signals based on the pwma and pwmb signals. when disabled, the pwma signal passes through to the pwma' signal and the pwmb signal passes through to the pwmb' signal. when dead-band control is enabled, the pwmb signal is ignored, the pwma' signal is generated by delaying the rising edge(s) of the pwma signal by the value in the pwmndbrise register (see page 1174), and the pwmb' signal is generated by inverting the pwma signal and delaying the falling edge(s) of the pwma signal by the value in the pwmndbfall register (see page 1175). the output control block outputs the pwm0a' signal on the pwm0 signal and the pwm0b' signal on the pwm1 signal. in a similar manner, pwm2 and pwm3 are produced from the pwm1a' and pwm1b' signals, pwm4 and pwm5 are produced from the pwm2a' and pwm2b' signals, and pwm6 and pwm7 are produced from the pwm3a' and pwm3b' signals. if the dead-band control mode is immediate (based on the dbctlupd field encoding in the pwmnctl register), the enable bit value is used immediately. if the update mode is locally synchronized, this value is used the next time the counter reaches zero. if the update mode is globally synchronized, this value is used the next time the counter reaches zero after a synchronous update has been requested through the pwm master control (pwmctl) register (see page 1126). if this register is rewritten before the actual update occurs, the previous value is never used and is lost. pwm0 dead-band control (pwm0dbctl) pwm0 base: 0x4002.8000 offset 0x068 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 enable reserved r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:1 dead-band generator enable description value the dead-band generator modifies the pwma signal by inserting dead bands into the pwma' and pwmb' signals. 1 the pwma and pwmb signals pass through to the pwma' and pwmb' signals unmodified. 0 0 r/w enable 0 1173 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 56: pwm0 dead-band rising-edge delay (pwm0dbrise), offset 0x06c register 57: pwm1 dead-band rising-edge delay (pwm1dbrise), offset 0x0ac register 58: pwm2 dead-band rising-edge delay (pwm2dbrise), offset 0x0ec register 59: pwm3 dead-band rising-edge delay (pwm3dbrise), offset 0x12c the pwmndbrise register contains the number of clock cycles to delay the rising edge of the pwma signal when generating the pwma' signal. if the dead-band generator is disabled through the pwmndbctl register, this register is ignored. if the value of this register is larger than the width of a high pulse on the pwma signal, the rising-edge delay consumes the entire high time of the signal, resulting in no high time on the output. care must be taken to ensure that the pwma high time always exceeds the rising-edge delay. if the dead-band rising-edge delay mode is immediate (based on the dbriseupd field encoding in the pwmnctl register), the 12-bit risedelay value is used immediately. if the update mode is locally synchronized, this value is used the next time the counter reaches zero. if the update mode is globally synchronized, this value is used the next time the counter reaches zero after a synchronous update has been requested through the pwm master control (pwmctl) register (see page 1126). if this register is rewritten before the actual update occurs, the previous value is never used and is lost. pwm0 dead-band rising-edge delay (pwm0dbrise) pwm0 base: 0x4002.8000 offset 0x06c type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 risedelay reserved r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0 ro reserved 31:12 dead-band rise delay the number of clock cycles to delay the rising edge of pwma' after the rising edge of pwma. 0x000 r/w risedelay 11:0 july 03, 2014 1174 texas instruments-production data pulse width modulator (pwm) register 60: pwm0 dead-band falling-edge-delay (pwm0dbfall), offset 0x070 register 61: pwm1 dead-band falling-edge-delay (pwm1dbfall), offset 0x0b0 register 62: pwm2 dead-band falling-edge-delay (pwm2dbfall), offset 0x0f0 register 63: pwm3 dead-band falling-edge-delay (pwm3dbfall), offset 0x130 the pwmndbfall register contains the number of clock cycles to delay the rising edge of the pwmb' signal from the falling edge of the pwma signal. if the dead-band generator is disabled through the pwmndbctl register, this register is ignored. if the value of this register is larger than the width of a low pulse on the pwma signal, the falling-edge delay consumes the entire low time of the signal, resulting in no low time on the output. care must be taken to ensure that the pwma low time always exceeds the falling-edge delay. if the dead-band falling-edge-delay mode is immediate (based on the dbfallup field encoding in the pwmnctl register), the 12-bit falldelay value is used immediately. if the update mode is locally synchronized, this value is used the next time the counter reaches zero. if the update mode is globally synchronized, this value is used the next time the counter reaches zero after a synchronous update has been requested through the pwm master control (pwmctl) register (see page 1126). if this register is rewritten before the actual update occurs, the previous value is never used and is lost. pwm0 dead-band falling-edge-delay (pwm0dbfall) pwm0 base: 0x4002.8000 offset 0x070 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 falldelay reserved r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0 ro reserved 31:12 dead-band fall delay the number of clock cycles to delay the falling edge of pwmb' from the rising edge of pwma. 0x000 r/w falldelay 11:0 1175 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 64: pwm0 fault source 0 (pwm0fltsrc0), offset 0x074 register 65: pwm1 fault source 0 (pwm1fltsrc0), offset 0x0b4 register 66: pwm2 fault source 0 (pwm2fltsrc0), offset 0x0f4 register 67: pwm3 fault source 0 (pwm3fltsrc0), offset 0x134 this register specifies which fault pin inputs are used to generate a fault condition. each bit in the following register indicates whether the corresponding fault pin is included in the fault condition. all enabled fault pins are ored together to form the pwmnfltsrc0 portion of the fault condition. the pwmnfltsrc0 fault condition is then ored with the pwmnfltsrc1 fault condition to generate the final fault condition for the pwm generator. if the fltsrc bit in the pwmnctl register (see page 1151) is clear, only the fault0 signal affects the fault condition generated. otherwise, sources defined in pwmnfltsrc0 and pwmnfltsrc1 affect the fault condition generated. pwm0 fault source 0 (pwm0fltsrc0) pwm0 base: 0x4002.8000 offset 0x074 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 fault0 fault1 fault2 fault3 reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:4 fault3 input description value the fault3 signal is suppressed and cannot generate a fault condition. 0 the fault3 signal value is ored with all other fault condition generation inputs ( faultn signals and digital comparators). 1 note: the fltsrc bit in the pwmnctl register must be set for this bit to affect fault condition generation. 0 r/w fault3 3 july 03, 2014 1176 texas instruments-production data pulse width modulator (pwm) description reset type name bit/field fault2 input description value the fault2 signal is suppressed and cannot generate a fault condition. 0 the fault2 signal value is ored with all other fault condition generation inputs ( faultn signals and digital comparators). 1 note: the fltsrc bit in the pwmnctl register must be set for this bit to affect fault condition generation. 0 r/w fault2 2 fault1 input description value the fault1 signal is suppressed and cannot generate a fault condition. 0 the fault1 signal value is ored with all other fault condition generation inputs ( faultn signals and digital comparators). 1 note: the fltsrc bit in the pwmnctl register must be set for this bit to affect fault condition generation. 0 r/w fault1 1 fault0 input description value the fault0 signal is suppressed and cannot generate a fault condition. 0 the fault0 signal value is ored with all other fault condition generation inputs ( faultn signals and digital comparators). 1 note: the fltsrc bit in the pwmnctl register must be set for this bit to affect fault condition generation. 0 r/w fault0 0 1177 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 68: pwm0 fault source 1 (pwm0fltsrc1), offset 0x078 register 69: pwm1 fault source 1 (pwm1fltsrc1), offset 0x0b8 register 70: pwm2 fault source 1 (pwm2fltsrc1), offset 0x0f8 register 71: pwm3 fault source 1 (pwm3fltsrc1), offset 0x138 this register specifies which digital comparator triggers from the adc are used to generate a fault condition. each bit in the following register indicates whether the corresponding digital comparator trigger is included in the fault condition. all enabled digital comparator triggers are ored together to form the pwmnfltsrc1 portion of the fault condition. the pwmnfltsrc1 fault condition is then ored with the pwmnfltsrc0 fault condition to generate the final fault condition for the pwm generator. if the fltsrc bit in the pwmnctl register (see page 1151) is clear, only the pwm fault0 pin affects the fault condition generated. otherwise, sources defined in pwmnfltsrc0 and pwmnfltsrc1 affect the fault condition generated. pwm0 fault source 1 (pwm0fltsrc1) pwm0 base: 0x4002.8000 offset 0x078 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dcmp0 dcmp1 dcmp2 dcmp3 dcmp4 dcmp5 dcmp6 dcmp7 reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 digital comparator 7 description value the trigger from digital comparator 7 is suppressed and cannot generate a fault condition. 0 the trigger from digital comparator 7 is ored with all other fault condition generation inputs ( faultn signals and digital comparators). 1 note: the fltsrc bit in the pwmnctl register must be set for this bit to affect fault condition generation. 0 r/w dcmp7 7 july 03, 2014 1178 texas instruments-production data pulse width modulator (pwm) description reset type name bit/field digital comparator 6 description value the trigger from digital comparator 6 is suppressed and cannot generate a fault condition. 0 the trigger from digital comparator 6 is ored with all other fault condition generation inputs ( faultn signals and digital comparators). 1 note: the fltsrc bit in the pwmnctl register must be set for this bit to affect fault condition generation. 0 r/w dcmp6 6 digital comparator 5 description value the trigger from digital comparator 5 is suppressed and cannot generate a fault condition. 0 the trigger from digital comparator 5 is ored with all other fault condition generation inputs ( faultn signals and digital comparators). 1 note: the fltsrc bit in the pwmnctl register must be set for this bit to affect fault condition generation. 0 r/w dcmp5 5 digital comparator 4 description value the trigger from digital comparator 4 is suppressed and cannot generate a fault condition. 0 the trigger from digital comparator 4 is ored with all other fault condition generation inputs ( faultn signals and digital comparators). 1 note: the fltsrc bit in the pwmnctl register must be set for this bit to affect fault condition generation. 0 r/w dcmp4 4 digital comparator 3 description value the trigger from digital comparator 3 is suppressed and cannot generate a fault condition. 0 the trigger from digital comparator 3 is ored with all other fault condition generation inputs ( faultn signals and digital comparators). 1 note: the fltsrc bit in the pwmnctl register must be set for this bit to affect fault condition generation. 0 r/w dcmp3 3 1179 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field digital comparator 2 description value the trigger from digital comparator 2 is suppressed and cannot generate a fault condition. 0 the trigger from digital comparator 2 is ored with all other fault condition generation inputs ( faultn signals and digital comparators). 1 note: the fltsrc bit in the pwmnctl register must be set for this bit to affect fault condition generation. 0 r/w dcmp2 2 digital comparator 1 description value the trigger from digital comparator 1 is suppressed and cannot generate a fault condition. 0 the trigger from digital comparator 1 is ored with all other fault condition generation inputs ( faultn signals and digital comparators). 1 note: the fltsrc bit in the pwmnctl register must be set for this bit to affect fault condition generation. 0 r/w dcmp1 1 digital comparator 0 description value the trigger from digital comparator 0 is suppressed and cannot generate a fault condition. 0 the trigger from digital comparator 0 is ored with all other fault condition generation inputs ( faultn signals and digital comparators). 1 note: the fltsrc bit in the pwmnctl register must be set for this bit to affect fault condition generation. 0 r/w dcmp0 0 july 03, 2014 1180 texas instruments-production data pulse width modulator (pwm) register 72: pwm0 minimum fault period (pwm0minfltper), offset 0x07c register 73: pwm1 minimum fault period (pwm1minfltper), offset 0x0bc register 74: pwm2 minimum fault period (pwm2minfltper), offset 0x0fc register 75: pwm3 minimum fault period (pwm3minfltper), offset 0x13c if the minfltper bit in the pwmnctl register is set, this register specifies the 16-bit time-extension value to be used in extending the fault condition. the value is loaded into a 16-bit down counter, and the counter value is used to extend the fault condition. the fault condition is released in the clock immediately after the counter value reaches 0. the fault condition is asynchronous to the pwm clock; and the delay value is the product of the pwm clock period and the (mfp field value + 1) or (mfp field value + 2) depending on when the fault condition asserts with respect to the pwm clock. the counter decrements at the pwm clock rate, without pause or condition. pwm0 minimum fault period (pwm0minfltper) pwm0 base: 0x4002.8000 offset 0x07c type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mfp r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 minimum fault period the number of pwm clocks by which a fault condition is extended when the delay is enabled by pwmnctl minfltper. 0x0000 r/w mfp 15:0 1181 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 76: pwm0 fault pin logic sense (pwm0fltsen), offset 0x800 register 77: pwm1 fault pin logic sense (pwm1fltsen), offset 0x880 register 78: pwm2 fault pin logic sense (pwm2fltsen), offset 0x900 register 79: pwm3 fault pin logic sense (pwm3fltsen), offset 0x980 this register defines the pwm fault pin logic sense. pwm0 fault pin logic sense (pwm0fltsen) pwm0 base: 0x4002.8000 offset 0x800 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 fault0 fault1 fault2 fault3 reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:4 fault3 sense description value an error is indicated if the fault3 signal is high. 0 an error is indicated if the fault3 signal is low. 1 0 r/w fault3 3 fault2 sense description value an error is indicated if the fault2 signal is high. 0 an error is indicated if the fault2 signal is low. 1 0 r/w fault2 2 fault1 sense description value an error is indicated if the fault1 signal is high. 0 an error is indicated if the fault1 signal is low. 1 0 r/w fault1 1 fault0 sense description value an error is indicated if the fault0 signal is high. 0 an error is indicated if the fault0 signal is low. 1 0 r/w fault0 0 july 03, 2014 1182 texas instruments-production data pulse width modulator (pwm) register 80: pwm0 fault status 0 (pwm0fltstat0), offset 0x804 register 81: pwm1 fault status 0 (pwm1fltstat0), offset 0x884 register 82: pwm2 fault status 0 (pwm2fltstat0), offset 0x904 register 83: pwm3 fault status 0 (pwm3fltstat0), offset 0x984 along with the pwmnfltstat1 register, this register provides status regarding the fault condition inputs. if the latch bit in the pwmnctl register is clear, the contents of the pwmnfltstat0 register are read-only (ro) and provide the current state of the faultn inputs. if the latch bit in the pwmnctl register is set, the contents of the pwmnfltstat0 register are read / write 1 to clear (r/w1c) and provide a latched version of the faultn inputs. in this mode, the register bits are cleared by writing a 1 to a set bit. the faultn inputs are recorded after their sense is adjusted in the generator. the contents of this register can only be written if the fault source extensions are enabled (the fltsrc bit in the pwmnctl register is set). pwm0 fault status 0 (pwm0fltstat0) pwm0 base: 0x4002.8000 offset 0x804 type -, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 fault0 fault1 fault2 fault3 reserved - - - - ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:4 fault input 3 if the pwmnctl register latch bit is clear, this bit is ro and represents the current state of the fault3 input signal after the logic sense adjustment. if the pwmnctl register latch bit is set, this bit is r/w1c and represents a sticky version of the fault3 input signal after the logic sense adjustment. if fault3 is set, the input transitioned to the active state previously. if fault3 is clear, the input has not transitioned to the active state since the last time it was cleared. the fault3 bit is cleared by writing it with the value 1. 0 - fault3 3 1183 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field fault input 2 if the pwmnctl register latch bit is clear, this bit is ro and represents the current state of the fault2 input signal after the logic sense adjustment. if the pwmnctl register latch bit is set, this bit is r/w1c and represents a sticky version of the fault2 input signal after the logic sense adjustment. if fault2 is set, the input transitioned to the active state previously. if fault2 is clear, the input has not transitioned to the active state since the last time it was cleared. the fault2 bit is cleared by writing it with the value 1. 0 - fault2 2 fault input 1 if the pwmnctl register latch bit is clear, this bit is ro and represents the current state of the fault1 input signal after the logic sense adjustment. if the pwmnctl register latch bit is set, this bit is r/w1c and represents a sticky version of the fault1 input signal after the logic sense adjustment. if fault1 is set, the input transitioned to the active state previously. if fault1 is clear, the input has not transitioned to the active state since the last time it was cleared. the fault1 bit is cleared by writing it with the value 1. 0 - fault1 1 fault input 0 if the pwmnctl register latch bit is clear, this bit is ro and represents the current state of the input signal after the logic sense adjustment. if the pwmnctl register latch bit is set, this bit is r/w1c and represents a sticky version of the input signal after the logic sense adjustment. if fault0 is set, the input transitioned to the active state previously. if fault0 is clear, the input has not transitioned to the active state since the last time it was cleared. the fault0 bit is cleared by writing it with the value 1. 0 - fault0 0 july 03, 2014 1184 texas instruments-production data pulse width modulator (pwm) register 84: pwm0 fault status 1 (pwm0fltstat1), offset 0x808 register 85: pwm1 fault status 1 (pwm1fltstat1), offset 0x888 register 86: pwm2 fault status 1 (pwm2fltstat1), offset 0x908 register 87: pwm3 fault status 1 (pwm3fltstat1), offset 0x988 along with the pwmnfltstat0 register, this register provides status regarding the fault condition inputs. if the latch bit in the pwmnctl register is clear, the contents of the pwmnfltstat1 register are read-only (ro) and provide the current state of the digital comparator triggers. if the latch bit in the pwmnctl register is set, the contents of the pwmnfltstat1 register are read / write 1 to clear (r/w1c) and provide a latched version of the digital comparator triggers. in this mode, the register bits are cleared by writing a 1 to a set bit. the contents of this register can only be written if the fault source extensions are enabled (the fltsrc bit in the pwmnctl register is set). pwm0 fault status 1 (pwm0fltstat1) pwm0 base: 0x4002.8000 offset 0x808 type -, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dcmp0 dcmp1 dcmp2 dcmp3 dcmp4 dcmp5 dcmp6 dcmp7 reserved - - - - - - - - ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00 ro reserved 31:8 digital comparator 7 trigger if the pwmnctl register latch bit is clear, this bit represents the current state of the digital comparator 7 trigger input. if the pwmnctl register latch bit is set, this bit represents a sticky version of the trigger. if dcmp7 is set, the trigger transitioned to the active state previously. if dcmp7 is clear, the trigger has not transitioned to the active state since the last time it was cleared. the dcmp7 bit is cleared by writing it with the value 1. 0 - dcmp7 7 1185 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field digital comparator 6 trigger if the pwmnctl register latch bit is clear, this bit represents the current state of the digital comparator 6 trigger input. if the pwmnctl register latch bit is set, this bit represents a sticky version of the trigger. if dcmp6 is set, the trigger transitioned to the active state previously. if dcmp6 is clear, the trigger has not transitioned to the active state since the last time it was cleared. the dcmp6 bit is cleared by writing it with the value 1. 0 - dcmp6 6 digital comparator 5 trigger if the pwmnctl register latch bit is clear, this bit represents the current state of the digital comparator 5 trigger input. if the pwmnctl register latch bit is set, this bit represents a sticky version of the trigger. if dcmp5 is set, the trigger transitioned to the active state previously. if dcmp5 is clear, the trigger has not transitioned to the active state since the last time it was cleared. the dcmp5 bit is cleared by writing it with the value 1. 0 - dcmp5 5 digital comparator 4 trigger if the pwmnctl register latch bit is clear, this bit represents the current state of the digital comparator 4 trigger input. if the pwmnctl register latch bit is set, this bit represents a sticky version of the trigger. if dcmp4 is set, the trigger transitioned to the active state previously. if dcmp4 is clear, the trigger has not transitioned to the active state since the last time it was cleared. the dcmp4 bit is cleared by writing it with the value 1. 0 - dcmp4 4 digital comparator 3 trigger if the pwmnctl register latch bit is clear, this bit represents the current state of the digital comparator 3 trigger input. if the pwmnctl register latch bit is set, this bit represents a sticky version of the trigger. if dcmp3 is set, the trigger transitioned to the active state previously. if dcmp3 is clear, the trigger has not transitioned to the active state since the last time it was cleared. the dcmp3 bit is cleared by writing it with the value 1. 0 - dcmp3 3 july 03, 2014 1186 texas instruments-production data pulse width modulator (pwm) description reset type name bit/field digital comparator 2 trigger if the pwmnctl register latch bit is clear, this bit represents the current state of the digital comparator 2 trigger input. if the pwmnctl register latch bit is set, this bit represents a sticky version of the trigger. if dcmp2 is set, the trigger transitioned to the active state previously. if dcmp2 is clear, the trigger has not transitioned to the active state since the last time it was cleared. the dcmp2 bit is cleared by writing it with the value 1. 0 - dcmp2 2 digital comparator 1 trigger if the pwmnctl register latch bit is clear, this bit represents the current state of the digital comparator 1 trigger input. if the pwmnctl register latch bit is set, this bit represents a sticky version of the trigger. if dcmp1 is set, the trigger transitioned to the active state previously. if dcmp1 is clear, the trigger has not transitioned to the active state since the last time it was cleared. the dcmp1 bit is cleared by writing it with the value 1. 0 - dcmp1 1 digital comparator 0 trigger if the pwmnctl register latch bit is clear, this bit represents the current state of the digital comparator 0 trigger input. if the pwmnctl register latch bit is set, this bit represents a sticky version of the trigger. if dcmp0 is set, the trigger transitioned to the active state previously. if dcmp0 is clear, the trigger has not transitioned to the active state since the last time it was cleared. the dcmp0 bit is cleared by writing it with the value 1. 0 - dcmp0 0 1187 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 22 quadrature encoder interface (qei) a quadrature encoder, also known as a 2-channel incremental encoder, converts linear displacement into a pulse signal. by monitoring both the number of pulses and the relative phase of the two signals, you can track the position, direction of rotation, and speed. in addition, a third channel, or index signal, can be used to reset the position counter. the lm3s9gn5 microcontroller includes two quadrature encoder interface (qei) modules. each qei module interprets the code produced by a quadrature encoder wheel to integrate position over time and determine direction of rotation. in addition, it can capture a running estimate of the velocity of the encoder wheel. the stellaris ? lm3s9gn5 microcontroller includes two qei modules providing control of two motors at the same time with the following features: position integrator that tracks the encoder position programmable noise filter on the inputs velocity capture using built-in timer the input frequency of the qei inputs may be as high as 1/4 of the processor frequency (for example, 12.5 mhz for a 50-mhz system) interrupt generation on: C index pulse C velocity-timer expiration C direction change C quadrature error detection 22.1 block diagram figure 22-1 on page 1189 provides a block diagram of a stellaris qei module. july 03, 2014 1188 texas instruments-production data quadrature encoder interface (qei) figure 22-1. qei block diagram 22.2 signal description the following table lists the external signals of the qei module and describes the function of each. the qei signals are alternate functions for some gpio signals and default to be gpio signals at reset. the column in the table below titled "pin mux/pin assignment" lists the possible gpio pin placements for these qei signals. the afsel bit in the gpio alternate function select (gpioafsel) register (page 429) should be set to choose the qei function. the number in parentheses is the encoding that must be programmed into the pmcn field in the gpio port control (gpiopctl) register (page 447) to assign the qei signal to the specified gpio port pin. for more information on configuring gpios, see general-purpose input/outputs (gpios) on page 405. table 22-1. qei signals (100lqfp) description buffer type a pin type pin mux / pin assignment pin number pin name qei module 0 index. ttl i pd0 (3) pg5 (4) pb2 (2) pb6 (5) pb4 (6) pd7 (1) 10 40 72 90 92 100 idx0 qei module 1 index. ttl i pg2 (8) pf1 (2) ph2 (1) 17 61 84 idx1 qei module 0 phase a. ttl i pd1 (3) pc4 (2) pf6 (4) pe2 (4) 11 25 43 95 pha0 qei module 1 phase a. ttl i pg6 (1) pe3 (3) 37 96 pha1 1189 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 4 x d g u d w x u h ( q f r g h u 9 h o r f l w \ 3 u h g l y l g h u , q w h u u x s w & r q w u r o 4 ( , , 1 7 ( 1 4 ( , 5 , 6 4 ( , , 6 & 3 r v l w l r q , q w h j u d w r u 4 ( , 0 $ ; 3 2 6 4 ( , 3 2 6 9 h o r f l w \ $ f f x p x o d w r u 4 ( , & 2 8 1 7 4 ( , 6 3 ( ( ' 9 h o r f l w \ 7 l p h u 4 ( , / 2 $ ' 4 ( , 7 , 0 ( 3 k $ 3 k % , ' ; f o n g l u , q w h u u x s w & r q w u r o 6 w d w x v 4 ( , & 7 / 4 ( , 6 7 $ 7 table 22-1. qei signals (100lqfp) (continued) description buffer type a pin type pin mux / pin assignment pin number pin name qei module 0 phase b. ttl i pc7 (2) pc6 (2) pf7 (4) pf0 (2) ph3 (1) pe3 (4) 22 23 42 47 83 96 phb0 qei module 1 phase b. ttl i pd1 (11) pg7 (1) pe2 (3) 11 36 95 phb1 a. the ttl designation indicates the pin has ttl-compatible voltage levels. table 22-2. qei signals (108bga) description buffer type a pin type pin mux / pin assignment pin number pin name qei module 0 index. ttl i pd0 (3) pg5 (4) pb2 (2) pb6 (5) pb4 (6) pd7 (1) g1 m7 a11 a7 a6 a2 idx0 qei module 1 index. ttl i pg2 (8) pf1 (2) ph2 (1) j1 h12 d11 idx1 qei module 0 phase a. ttl i pd1 (3) pc4 (2) pf6 (4) pe2 (4) g2 l1 m8 a4 pha0 qei module 1 phase a. ttl i pg6 (1) pe3 (3) l7 b4 pha1 qei module 0 phase b. ttl i pc7 (2) pc6 (2) pf7 (4) pf0 (2) ph3 (1) pe3 (4) l2 m2 k4 m9 d10 b4 phb0 qei module 1 phase b. ttl i pd1 (11) pg7 (1) pe2 (3) g2 c10 a4 phb1 a. the ttl designation indicates the pin has ttl-compatible voltage levels. 22.3 functional description the qei module interprets the two-bit gray code produced by a quadrature encoder wheel to integrate position over time and determine direction of rotation. in addition, it can capture a running estimate of the velocity of the encoder wheel. the position integrator and velocity capture can be independently enabled, though the position integrator must be enabled before the velocity capture can be enabled. the two phase signals, pha and phb , can be swapped before being interpreted by the qei module to change the meaning of forward and backward and to correct for miswiring of the system. alternatively, the phase signals can be interpreted as a clock and direction signal as output by some encoders. july 03, 2014 1190 texas instruments-production data quadrature encoder interface (qei) the qei module input signals have a digital noise filter on them that can be enabled to prevent spurious operation. the noise filter requires that the inputs be stable for a specified number of consecutive clock cycles before updating the edge detector. the filter is enabled by the filten bit in the qei control (qeictl) register. the frequency of the input update is programmable using the filtcnt bit field in the qeictl register. the qei module supports two modes of signal operation: quadrature phase mode and clock/direction mode. in quadrature phase mode, the encoder produces two clocks that are 90 degrees out of phase; the edge relationship is used to determine the direction of rotation. in clock/direction mode, the encoder produces a clock signal to indicate steps and a direction signal to indicate the direction of rotation. this mode is determined by the sigmode bit of the qeictl register (see page 1195). when the qei module is set to use the quadrature phase mode ( sigmode bit is clear), the capture mode for the position integrator can be set to update the position counter on every edge of the pha signal or to update on every edge of both pha and phb . updating the position counter on every pha and phb edge provides more positional resolution at the cost of less range in the positional counter. when edges on pha lead edges on phb , the position counter is incremented. when edges on phb lead edges on pha , the position counter is decremented. when a rising and falling edge pair is seen on one of the phases without any edges on the other, the direction of rotation has changed. the positional counter is automatically reset on one of two conditions: sensing the index pulse or reaching the maximum position value. the reset mode is determined by the resmode bit of the qeictl register. when resmode is set, the positional counter is reset when the index pulse is sensed. this mode limits the positional counter to the values [0:n-1], where n is the number of phase edges in a full revolution of the encoder wheel. the qei maximum position (qeimaxpos) register must be programmed with n-1 so that the reverse direction from position 0 can move the position counter to n-1. in this mode, the position register contains the absolute position of the encoder relative to the index (or home) position once an index pulse has been seen. when resmode is clear, the positional counter is constrained to the range [0:m], where m is the programmable maximum value. the index pulse is ignored by the positional counter in this mode. velocity capture uses a configurable timer and a count register. the timer counts the number of phase edges (using the same configuration as for the position integrator) in a given time period. the edge count from the previous time period is available to the controller via the qei velocity (qeispeed) register, while the edge count for the current time period is being accumulated in the qei velocity counter (qeicount) register. as soon as the current time period is complete, the total number of edges counted in that time period is made available in the qeispeed register (overwriting the previous value), the qeicount register is cleared, and counting commences on a new time period. the number of edges counted in a given time period is directly proportional to the velocity of the encoder. figure 22-2 on page 1192 shows how the stellaris quadrature encoder converts the phase input signals into clock pulses, the direction signal, and how the velocity predivider operates (in divide by 4 mode). 1191 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller figure 22-2. quadrature encoder and velocity predivider operation the period of the timer is configurable by specifying the load value for the timer in the qei timer load (qeiload) register. when the timer reaches zero, an interrupt can be triggered, and the hardware reloads the timer with the qeiload value and continues to count down. at lower encoder speeds, a longer timer period is required to be able to capture enough edges to have a meaningful result. at higher encoder speeds, both a shorter timer period and/or the velocity predivider can be used. the following equation converts the velocity counter value into an rpm value: rpm = (clock * (2 ^ veldiv) * speed * 60) (load * ppr * edges) where: clock is the controller clock rate ppr is the number of pulses per revolution of the physical encoder edges is 2 or 4, based on the capture mode set in the qeictl register (2 for capmode clear and 4 for capmode set) for example, consider a motor running at 600 rpm. a 2048 pulse per revolution quadrature encoder is attached to the motor, producing 8192 phase edges per revolution. with a velocity predivider of 1 ( veldiv is clear) and clocking on both pha and phb edges, this results in 81,920 pulses per second (the motor turns 10 times per second). if the timer were clocked at 10,000 hz, and the load value was 2,500 (? of a second), it would count 20,480 pulses per update. using the above equation: rpm = (10000 * 1 * 20480 * 60) (2500 * 2048 * 4) = 600 rpm now, consider that the motor is sped up to 3000 rpm. this results in 409,600 pulses per second, or 102,400 every ? of a second. again, the above equation gives: rpm = (10000 * 1 * 102400 * 60) (2500 * 2048 * 4) = 3000 rpm care must be taken when evaluating this equation because intermediate values may exceed the capacity of a 32-bit integer. in the above examples, the clock is 10,000 and the divider is 2,500; both could be predivided by 100 (at compile time if they are constants) and therefore be 100 and 25. in fact, if they were compile-time constants, they could also be reduced to a simple multiply by 4, cancelled by the 4 for the edge-count factor. important: reducing constant factors at compile time is the best way to control the intermediate values of this equation and reduce the processing requirement of computing this equation. the division can be avoided by selecting a timer load value such that the divisor is a power of 2; a simple shift can therefore be done in place of the division. for encoders with a power of 2 pulses per revolution, the load value can be a power of 2. for other encoders, a load value must be selected such that the product is very close to a power of 2. for example, a 100 pulse-per-revolution encoder july 03, 2014 1192 texas instruments-production data quadrature encoder interface (qei) 3 k % f o n f o n g l y g l u s r v 3 k $ u h o could use a load value of 82, resulting in 32,800 as the divisor, which is 0.09% above 2 14 . in this case a shift by 15 would be an adequate approximation of the divide in most cases. if absolute accuracy were required, the microcontrollers divide instruction could be used. the qei module can produce a controller interrupt on several events: phase error, direction change, reception of the index pulse, and expiration of the velocity timer. standard masking, raw interrupt status, interrupt status, and interrupt clear capabilities are provided. 22.4 initialization and configuration the following example shows how to configure the quadrature encoder module to read back an absolute position: 1. enable the qei clock by writing a value of 0x0000.0100 to the rcgc1 register in the system control module (see page 270). 2. enable the clock to the appropriate gpio module via the rcgc2 register in the system control module (see page 282). 3. in the gpio module, enable the appropriate pins for their alternate function using the gpioafsel register. to determine which gpios to configure, see table 24-4 on page 1239. 4. configure the pmcn fields in the gpiopctl register to assign the qei signals to the appropriate pins (see page 447 and table 24-5 on page 1248). 5. configure the quadrature encoder to capture edges on both signals and maintain an absolute position by resetting on index pulses. a 1000-line encoder with four edges per line, results in 4000 pulses per revolution; therefore, set the maximum position to 3999 (0xf9f) as the count is zero-based. write the qeictl register with the value of 0x0000.0018. write the qeimaxpos register with the value of 0x0000.0f9f. 6. enable the quadrature encoder by setting bit 0 of the qeictl register. 7. delay until the encoder position is required. 8. read the encoder position by reading the qei position (qeipos) register value. 22.5 register map table 22-3 on page 1194 lists the qei registers. the offset listed is a hexadecimal increment to the registers address, relative to the modules base address: qei0: 0x4002.c000 qei1: 0x4002.d000 note that the qei module clock must be enabled before the registers can be programmed (see page 270). there must be a delay of 3 system clocks after the qei module clock is enabled before any qei module registers are accessed. 1193 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 22-3. qei register map see page description reset type name offset 1195 qei control 0x0000.0000 r/w qeictl 0x000 1198 qei status 0x0000.0000 ro qeistat 0x004 1199 qei position 0x0000.0000 r/w qeipos 0x008 1200 qei maximum position 0x0000.0000 r/w qeimaxpos 0x00c 1201 qei timer load 0x0000.0000 r/w qeiload 0x010 1202 qei timer 0x0000.0000 ro qeitime 0x014 1203 qei velocity counter 0x0000.0000 ro qeicount 0x018 1204 qei velocity 0x0000.0000 ro qeispeed 0x01c 1205 qei interrupt enable 0x0000.0000 r/w qeiinten 0x020 1207 qei raw interrupt status 0x0000.0000 ro qeiris 0x024 1209 qei interrupt status and clear 0x0000.0000 r/w1c qeiisc 0x028 22.6 register descriptions the remainder of this section lists and describes the qei registers, in numerical order by address offset. july 03, 2014 1194 texas instruments-production data quadrature encoder interface (qei) register 1: qei control (qeictl), offset 0x000 this register contains the configuration of the qei module. separate enables are provided for the quadrature encoder and the velocity capture blocks; the quadrature encoder must be enabled in order to capture the velocity, but the velocity does not need to be captured in applications that do not need it. the phase signal interpretation, phase swap, position update mode, position reset mode, and velocity predivider are all set via this register. qei control (qeictl) qei0 base: 0x4002.c000 qei1 base: 0x4002.d000 offset 0x000 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 filtcnt reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 enable swap sigmode capmode resmode velen veldiv inva invb invi stallen filten reserved r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 31:20 input filter prescale count this field controls the frequency of the input update. when this field is clear, the input is sampled after 2 system clocks. when this field ix 0x1, the input is sampled after 3 system clocks. similarly, when this field is 0xf, the input is sampled after 17 clocks. 0x0 r/w filtcnt 19:16 software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 15:14 enable input filter description value the qei inputs are not filtered. 0 enables the digital noise filter on the qei input signals. inputs must be stable for 3 consecutive clock edges before the edge detector is updated. 1 0 r/w filten 13 stall qei description value the qei module does not stall when the microcontroller is stopped by a debugger. 0 the qei module stalls when the microcontroller is stopped by a debugger. 1 0 r/w stallen 12 1195 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field invert index pulse description value no effect. 0 inverts the idx input. 1 0 r/w invi 11 invert phb description value no effect. 0 inverts the phb input. 1 0 r/w invb 10 invert pha description value no effect. 0 inverts the pha input. 1 0 r/w inva 9 predivide velocity this field defines the predivider of the input quadrature pulses before being applied to the qeicount accumulator. predivider value 10x0 20x1 40x2 80x3 160x4 320x5 640x6 128 0x7 0x0 r/w veldiv 8:6 capture velocity description value no effect. 0 enables capture of the velocity of the quadrature encoder. 1 0 r/w velen 5 reset mode description value the position counter is reset when it reaches the maximum as defined by the maxpos field in the qeimaxpos register. 0 the position counter is reset when the index pulse is captured. 1 0 r/w resmode 4 july 03, 2014 1196 texas instruments-production data quadrature encoder interface (qei) description reset type name bit/field capture mode description value only the pha edges are counted. 0 the pha and phb edges are counted, providing twice the positional resolution but half the range. 1 0 r/w capmode 3 signal mode description value the pha and phb signals operate as quadrature phase signals. 0 the pha and phb signals operate as clock and direction. 1 0 r/w sigmode 2 swap signals description value no effect. 0 swaps the pha and phb signals. 1 0 r/w swap 1 enable qei description value no effect. 0 enables the quadrature encoder module. 1 0 r/w enable 0 1197 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 2: qei status (qeistat), offset 0x004 this register provides status about the operation of the qei module. qei status (qeistat) qei0 base: 0x4002.c000 qei1 base: 0x4002.d000 offset 0x004 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 error direction reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:2 direction of rotation indicates the direction the encoder is rotating. description value the encoder is rotating forward. 0 the encoder is rotating in reverse. 1 0 ro direction 1 error detected description value no error. 0 an error was detected in the gray code sequence (that is, both signals changing at the same time). 1 0 ro error 0 july 03, 2014 1198 texas instruments-production data quadrature encoder interface (qei) register 3: qei position (qeipos), offset 0x008 this register contains the current value of the position integrator. the value is updated by the status of the qei phase inputs and can be set to a specific value by writing to it. qei position (qeipos) qei0 base: 0x4002.c000 qei1 base: 0x4002.d000 offset 0x008 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 position r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 position r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field current position integrator value the current value of the position integrator. 0x0000.0000 r/w position 31:0 1199 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 4: qei maximum position (qeimaxpos), offset 0x00c this register contains the maximum value of the position integrator. when moving forward, the position register resets to zero when it increments past this value. when moving in reverse, the position register resets to this value when it decrements from zero. qei maximum position (qeimaxpos) qei0 base: 0x4002.c000 qei1 base: 0x4002.d000 offset 0x00c type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 maxpos r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 maxpos r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field maximum position integrator value the maximum value of the position integrator. 0x0000.0000 r/w maxpos 31:0 july 03, 2014 1200 texas instruments-production data quadrature encoder interface (qei) register 5: qei timer load (qeiload), offset 0x010 this register contains the load value for the velocity timer. because this value is loaded into the timer on the clock cycle after the timer is zero, this value should be one less than the number of clocks in the desired period. so, for example, to have 2000 decimal clocks per timer period, this register should contain 1999 decimal. qei timer load (qeiload) qei0 base: 0x4002.c000 qei1 base: 0x4002.d000 offset 0x010 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 load r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 load r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field velocity timer load value the load value for the velocity timer. 0x0000.0000 r/w load 31:0 1201 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 6: qei timer (qeitime), offset 0x014 this register contains the current value of the velocity timer. this counter does not increment when the velen bit in the qeictl register is clear. qei timer (qeitime) qei0 base: 0x4002.c000 qei1 base: 0x4002.d000 offset 0x014 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 time ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 time ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field velocity timer current value the current value of the velocity timer. 0x0000.0000 ro time 31:0 july 03, 2014 1202 texas instruments-production data quadrature encoder interface (qei) register 7: qei velocity counter (qeicount), offset 0x018 this register contains the running count of velocity pulses for the current time period. because this count is a running total, the time period to which it applies cannot be known with precision (that is, a read of this register does not necessarily correspond to the time returned by the qeitime register because there is a small window of time between the two reads, during which either value may have changed). the qeispeed register should be used to determine the actual encoder velocity; this register is provided for information purposes only. this counter does not increment when the velen bit in the qeictl register is clear. qei velocity counter (qeicount) qei0 base: 0x4002.c000 qei1 base: 0x4002.d000 offset 0x018 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 count ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 count ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field velocity pulse count the running total of encoder pulses during this velocity timer period. 0x0000.0000 ro count 31:0 1203 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller register 8: qei velocity (qeispeed), offset 0x01c this register contains the most recently measured velocity of the quadrature encoder. this value corresponds to the number of velocity pulses counted in the previous velocity timer period. this register does not update when the velen bit in the qeictl register is clear. qei velocity (qeispeed) qei0 base: 0x4002.c000 qei1 base: 0x4002.d000 offset 0x01c type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 speed ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 speed ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field velocity the measured speed of the quadrature encoder in pulses per period. 0x0000.0000 ro speed 31:0 july 03, 2014 1204 texas instruments-production data quadrature encoder interface (qei) register 9: qei interrupt enable (qeiinten), offset 0x020 this register contains enables for each of the qei module interrupts. an interrupt is asserted to the interrupt controller if the corresponding bit in this register is set. qei interrupt enable (qeiinten) qei0 base: 0x4002.c000 qei1 base: 0x4002.d000 offset 0x020 type r/w, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 intindex inttimer intdir interror reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:4 phase error interrupt enable description value an interrupt is sent to the interrupt controller when the interror bit in the qeiris register is set. 1 the interror interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w interror 3 direction change interrupt enable description value an interrupt is sent to the interrupt controller when the intdir bit in the qeiris register is set. 1 the intdir interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w intdir 2 timer expires interrupt enable description value an interrupt is sent to the interrupt controller when the inttimer bit in the qeiris register is set. 1 the inttimer interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w inttimer 1 1205 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field index pulse detected interrupt enable description value an interrupt is sent to the interrupt controller when the intindex bit in the qeiris register is set. 1 the intindex interrupt is suppressed and not sent to the interrupt controller. 0 0 r/w intindex 0 july 03, 2014 1206 texas instruments-production data quadrature encoder interface (qei) register 10: qei raw interrupt status (qeiris), offset 0x024 this register provides the current set of interrupt sources that are asserted, regardless of whether they cause an interrupt to be asserted to the controller (configured through the qeiinten register). if a bit is set, the latched event has occurred; if a bit is clear, the event in question has not occurred. qei raw interrupt status (qeiris) qei0 base: 0x4002.c000 qei1 base: 0x4002.d000 offset 0x024 type ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 intindex inttimer intdir interror reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:4 phase error detected description value a phase error has been detected. 1 an interrupt has not occurred. 0 this bit is cleared by writing a 1 to the interror bit in the qeiisc register. 0 ro interror 3 direction change detected description value the rotation direction has changed 1 an interrupt has not occurred. 0 this bit is cleared by writing a 1 to the intdir bit in the qeiisc register. 0 ro intdir 2 velocity timer expired description value the velocity timer has expired. 1 an interrupt has not occurred. 0 this bit is cleared by writing a 1 to the inttimer bit in the qeiisc register. 0 ro inttimer 1 1207 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field index pulse asserted description value the index pulse has occurred. 1 an interrupt has not occurred. 0 this bit is cleared by writing a 1 to the intindex bit in the qeiisc register. 0 ro intindex 0 july 03, 2014 1208 texas instruments-production data quadrature encoder interface (qei) register 11: qei interrupt status and clear (qeiisc), offset 0x028 this register provides the current set of interrupt sources that are asserted to the controller. if a bit is set, the latched event has occurred and is enabled to generate an interrupt; if a bit is clear the event in question has not occurred or is not enabled to generate an interrupt. this register is r/w1c; writing a 1 to a bit position clears the bit and the corresponding interrupt reason. qei interrupt status and clear (qeiisc) qei0 base: 0x4002.c000 qei1 base: 0x4002.d000 offset 0x028 type r/w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 intindex inttimer intdir interror reserved r/w1c r/w1c r/w1c r/w1c ro ro ro ro ro ro ro ro ro ro ro ro type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset type name bit/field software should not rely on the value of a reserved bit. to provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000 ro reserved 31:4 phase error interrupt description value the interror bits in the qeiris register and the qeiinten registers are set, providing an interrupt to the interrupt controller. 1 no interrupt has occurred or the interrupt is masked. 0 this bit is cleared by writing a 1. clearing this bit also clears the interror bit in the qeiris register. 0 r/w1c interror 3 direction change interrupt description value the intdir bits in the qeiris register and the qeiinten registers are set, providing an interrupt to the interrupt controller. 1 no interrupt has occurred or the interrupt is masked. 0 this bit is cleared by writing a 1. clearing this bit also clears the intdir bit in the qeiris register. 0 r/w1c intdir 2 velocity timer expired interrupt description value the inttimer bits in the qeiris register and the qeiinten registers are set, providing an interrupt to the interrupt controller. 1 no interrupt has occurred or the interrupt is masked. 0 this bit is cleared by writing a 1. clearing this bit also clears the inttimer bit in the qeiris register. 0 r/w1c inttimer 1 1209 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller description reset type name bit/field index pulse interrupt description value the intindex bits in the qeiris register and the qeiinten registers are set, providing an interrupt to the interrupt controller. 1 no interrupt has occurred or the interrupt is masked. 0 this bit is cleared by writing a 1. clearing this bit also clears the intindex bit in the qeiris register. 0 r/w1c intindex 0 july 03, 2014 1210 texas instruments-production data quadrature encoder interface (qei) 23 pin diagram the lm3s9gn5 microcontroller pin diagram is shown below. each gpio signal is identified by its gpio port unless it defaults to an alternate function on reset. in this case, the gpio port name is followed by the default alternate function. to see a complete list of possible functions for each pin, see table 24-5 on page 1248. figure 23-1. 100-pin lqfp package pin diagram 1211 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller figure 23-2. 108-ball bga package pin diagram (top view) july 03, 2014 1212 texas instruments-production data pin diagram 24 signal tables the following tables list the signals available for each pin. signals are configured as gpios on reset, except for those noted below. use the gpioamsel register (see page 445) to select analog mode. for a gpio pin to be used for an alternate digital function, the corresponding bit in the gpioafsel register (see page 429) must be set. further pin muxing options are provided through the pmcx bit field in the gpiopctl register (see page 447), which selects one of several available peripheral functions for that gpio. important: all gpio pins are configured as gpios by default with the exception of the pins shown in the table below. a power-on-reset ( por ) or asserting rst puts the pins back to their default state. table 24-1. gpio pins with default alternate functions gpiopctl pmcx bit field gpioafsel bit default state gpio pin 0x1 0 uart0 pa[1:0] 0x1 0 ssi0 pa[5:2] 0x1 0 i 2 c0 pb[3:2] 0x3 1 jtag/swd pc[3:0] table 24-2 on page 1214 shows the pin-to-signal-name mapping, including functional characteristics of the signals. each possible alternate analog and digital function is listed for each pin. table 24-3 on page 1227 lists the signals in alphabetical order by signal name. if it is possible for a signal to be on multiple pins, each possible pin assignment is listed. the "pin mux" column indicates the gpio and the encoding needed in the pmcx bit field in the gpiopctl register. table 24-4 on page 1239 groups the signals by functionality, except for gpios. if it is possible for a signal to be on multiple pins, each possible pin assignment is listed. table 24-5 on page 1248 lists the gpio pins and their analog and digital alternate functions. the ainx and vrefa analog signals are not 5-v tolerant and go through an isolation circuit before reaching their circuitry. these signals are configured by clearing the corresponding den bit in the gpio digital enable (gpioden) register and setting the corresponding amsel bit in the gpio analog mode select (gpioamsel) register. other analog signals are 5-v tolerant and are connected directly to their circuitry ( c0-, c0+, c1-, c1+, c2-, c2+, usb0vbus, usb0id ). these signals are configured by clearing the den bit in the gpio digital enable (gpioden) register. the digital signals are enabled by setting the appropriate bit in the gpio alternate function select (gpioafsel) and gpioden registers and configuring the pmcx bit field in the gpio port control (gpiopctl) register to the numeric enoding shown in the table below. table entries that are shaded gray are the default values for the corresponding gpio pin. table 24-6 on page 1251 lists the signals based on number of possible pin assignments. this table can be used to plan how to configure the pins for a particular functionality. application note an01274 configuring stellaris ? microcontrollers with pin multiplexing provides an overview of the pin muxing implementation, an explanation of how a system designer defines a pin configuration, and examples of the pin configuration process. note: all digital inputs are schmitt triggered. 1213 july 03, 2014 texas instruments-production data stellaris lm3s9gn5 microcontroller 24.1 100-pin lqfp package pin tables 24.1.1 signals by pin number table 24-2. signals by pin number description buffer type a pin type pin name pin number gpio port e bit 7. ttl i/o pe7 1 analog-to-digital converter input 0. analog i ain0 analog comparator 2 output. ttl o c2o pwm 5. this signal is controlled by pwm generator 2. ttl o pwm5 uart module 1 data carrier detect modem status input signal. ttl i u1dcd gpio port e bit 6. ttl i/o pe6 2 analog-to-digital converter input 1. analog i ain1 analog comparator 1 output. ttl o c1o pwm 4. this signal is controlled by pwm generator 2. ttl o pwm4 uart module 1 clear to send modem flow control input signal. ttl i u1cts the positive supply for the analog circuits (adc, analog comparators, etc.). these are separated from vdd to minimize the electrical noise contained on vdd from affecting the analog functions. vdda pins must be supplied with a voltage that meets the specification in table 26-2 on page 1298 , regardless of system implementation. power - vdda 3 the ground reference for the analog circuits (adc, analog comparators, etc.). these are separated from gnd to minimize the electrical noise contained on vdd from affecting the analog functions. power - gnda 4 gpio port e bit 5. ttl i/o pe5 5 analog-to-digital converter input 2. analog i ain2 capture/compare/pwm 5. ttl i/o ccp5 i 2 s module 0 transmit data. ttl i/o i2s0txsd gpio port e bit 4. ttl i/o pe4 6 analog-to-digital converter input 3. analog i ain3 capture/compare/pwm 2. ttl i/o ccp2 capture/compare/pwm 3. ttl i/o ccp3 pwm fault 0. ttl i fault0 i 2 s module 0 transmit word select. ttl i/o i2s0txws mii receive data 0. ttl i rxd0 uart module 2 transmit. when in irda mode, this signal has irda modulation. ttl o u2tx low drop-out regulator output voltage. this pin requires an external capacitor between the pin and gnd of 1 f or greater. the ldo pin must also be connected to the vddc pins at the board level in addition to the decoupling capacitor(s). power - ldo 7 positive supply for i/o and some logic. power - vdd 8 ground reference for logic and i/o pins. power - gnd 9 july 03, 2014 1214 texas instruments-production data signal tables table 24-2. signals by pin number (continued) description buffer type a pin type pin name pin number gpio port d bit 0. ttl i/o pd0 10 analog-to-digital converter input 15. analog i ain15 can module 0 receive. ttl i can0rx capture/compare/pwm 6. ttl i/o ccp6 i 2 s module 0 receive clock. ttl i/o i2s0rxsck qei module 0 index. ttl i idx0 pwm 0. this signal is controlled by pwm generator 0. ttl o pwm0 mii receive data valid. ttl i rxdv uart module 1 clear to send modem flow control input signal. ttl i u1cts uart module 1 receive. when in irda mode, this signal has irda modulation. ttl i u1rx uart module 2 receive. when in irda mode, this signal has irda modulation. ttl i u2rx gpio port d bit 1. ttl i/o pd1 11 analog-to-digital converter input 14. analog i ain14 can module 0 transmit. ttl o can0tx capture/compare/pwm 2. ttl i/o ccp2 capture/compare/pwm 7. ttl i/o ccp7 i 2 s module 0 receive word select. ttl i/o i2s0rxws pwm 1. this signal is controlled by pwm generator 0. ttl o pwm1 qei module 0 phase a. ttl i pha0 qei module 1 phase b. ttl i phb1 mii transmit error. ttl o txer uart module 1 data carrier detect modem status input signal. ttl i u1dcd uart module 1 transmit. when in irda mode, this signal has irda modulation. ttl o u1tx uart module 2 transmit. when in irda mode, this signal has irda modulation. ttl o u2tx gpio port d bit 2. ttl i/o pd2 12 analog-to-digital converter input 13. analog i ain13 capture/compare/pwm 5. ttl i/o ccp5 capture/compare/pwm 6. ttl i/o ccp6 epi module 0 signal 20. ttl i/o epi0s20 pwm 2. this signal is controlled by pwm generator 1. ttl o pwm2 uart module 1 receive. when in irda mode, this signal has irda modulation. ttl i u1rx 1215 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 24-2. signals by pin number (continued) description buffer type a pin type pin name pin number gpio port d bit 3. ttl i/o pd3 13 analog-to-digital converter input 12. analog i ain12 capture/compare/pwm 0. ttl i/o ccp0 capture/compare/pwm 7. ttl i/o ccp7 epi module 0 signal 21. ttl i/o epi0s21 pwm 3. this signal is controlled by pwm generator 1. ttl o pwm3 uart module 1 transmit. when in irda mode, this signal has irda modulation. ttl o u1tx gpio port j bit 0. ttl i/o pj0 14 epi module 0 signal 16. ttl i/o epi0s16 i 2 c module 1 clock. od i/o i2c1scl pwm 0. this signal is controlled by pwm generator 0. ttl o pwm0 mii receive error. ttl i rxer gpio port h bit 7. ttl i/o ph7 15 epi module 0 signal 27. ttl i/o epi0s27 pwm 5. this signal is controlled by pwm generator 2. ttl o pwm5 mii receive clock. 25 mhz in 100base-tx mode. 2.5 mhz in 10base-t mode. ttl i rxck ssi module 1 transmit. ttl o ssi1tx gpio port g bit 3. ttl i/o pg3 16 mii carrier sense. ttl i crs pwm fault 0. ttl i fault0 pwm fault 2. ttl i fault2 i 2 s module 0 receive master clock. ttl i/o i2s0rxmclk pwm 1. this signal is controlled by pwm generator 0. ttl o pwm1 gpio port g bit 2. ttl i/o pg2 17 mii collision detect. ttl i col pwm fault 0. ttl i fault0 i 2 s module 0 receive data. ttl i/o i2s0rxsd qei module 1 index. ttl i idx1 pwm 0. this signal is controlled by pwm generator 0. ttl o pwm0 gpio port g bit 1. ttl i/o pg1 18 epi module 0 signal 14. ttl i/o epi0s14 i 2 c module 1 data. od i/o i2c1sda pwm 1. this signal is controlled by pwm generator 0. ttl o pwm1 pwm 5. this signal is controlled by pwm generator 2. ttl o pwm5 uart module 2 transmit. when in irda mode, this signal has irda modulation. ttl o u2tx july 03, 2014 1216 texas instruments-production data signal tables table 24-2. signals by pin number (continued) description buffer type a pin type pin name pin number gpio port g bit 0. ttl i/o pg0 19 epi module 0 signal 13. ttl i/o epi0s13 i 2 c module 1 clock. od i/o i2c1scl pwm 0. this signal is controlled by pwm generator 0. ttl o pwm0 pwm 4. this signal is controlled by pwm generator 2. ttl o pwm4 uart module 2 receive. when in irda mode, this signal has irda modulation. ttl i u2rx optionally used in host mode to control an external power source to supply power to the usb bus. ttl o usb0epen positive supply for i/o and some logic. power - vdd 20 ground reference for logic and i/o pins. power - gnd 21 gpio port c bit 7. ttl i/o pc7 22 analog comparator 1 output. ttl o c1o analog comparator 2 negative input. analog i c2- capture/compare/pwm 0. ttl i/o ccp0 capture/compare/pwm 4. ttl i/o ccp4 epi module 0 signal 5. ttl i/o epi0s5 qei module 0 phase b. ttl i phb0 uart module 1 transmit. when in irda mode, this signal has irda modulation. ttl o u1tx optionally used in host mode by an external power source to indicate an error state by that power source. ttl i usb0pflt gpio port c bit 6. ttl i/o pc6 23 analog comparator 2 positive input. analog i c2+ analog comparator 2 output. ttl o c2o capture/compare/pwm 0. ttl i/o ccp0 capture/compare/pwm 3. ttl i/o ccp3 epi module 0 signal 4. ttl i/o epi0s4 pwm 7. this signal is controlled by pwm generator 3. ttl o pwm7 qei module 0 phase b. ttl i phb0 uart module 1 receive. when in irda mode, this signal has irda modulation. ttl i u1rx optionally used in host mode by an external power source to indicate an error state by that power source. ttl i usb0pflt 1217 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 24-2. signals by pin number (continued) description buffer type a pin type pin name pin number gpio port c bit 5. ttl i/o pc5 24 analog comparator 0 output. ttl o c0o analog comparator 1 positive input. analog i c1+ analog comparator 1 output. ttl o c1o capture/compare/pwm 1. ttl i/o ccp1 capture/compare/pwm 3. ttl i/o ccp3 epi module 0 signal 3. ttl i/o epi0s3 pwm fault 2. ttl i fault2 optionally used in host mode to control an external power source to supply power to the usb bus. ttl o usb0epen gpio port c bit 4. ttl i/o pc4 25 capture/compare/pwm 1. ttl i/o ccp1 capture/compare/pwm 2. ttl i/o ccp2 capture/compare/pwm 4. ttl i/o ccp4 capture/compare/pwm 5. ttl i/o ccp5 epi module 0 signal 2. ttl i/o epi0s2 pwm 6. this signal is controlled by pwm generator 3. ttl o pwm6 qei module 0 phase a. ttl i pha0 ethernet mii transmit data 3. ttl o txd3 gpio port a bit 0. ttl i/o pa0 26 i 2 c module 1 clock. od i/o i2c1scl uart module 0 receive. when in irda mode, this signal has irda modulation. ttl i u0rx uart module 1 receive. when in irda mode, this signal has irda modulation. ttl i u1rx gpio port a bit 1. ttl i/o pa1 27 i 2 c module 1 data. od i/o i2c1sda uart module 0 transmit. when in irda mode, this signal has irda modulation. ttl o u0tx uart module 1 transmit. when in irda mode, this signal has irda modulation. ttl o u1tx gpio port a bit 2. ttl i/o pa2 28 i 2 s module 0 receive data. ttl i/o i2s0rxsd pwm 4. this signal is controlled by pwm generator 2. ttl o pwm4 ssi module 0 clock. ttl i/o ssi0clk mii transmit data 2. ttl o txd2 gpio port a bit 3. ttl i/o pa3 29 i 2 s module 0 receive master clock. ttl i/o i2s0rxmclk pwm 5. this signal is controlled by pwm generator 2. ttl o pwm5 ssi module 0 frame signal. ttl i/o ssi0fss ethernet mii transmit data 1. ttl o txd1 july 03, 2014 1218 texas instruments-production data signal tables table 24-2. signals by pin number (continued) description buffer type a pin type pin name pin number gpio port a bit 4. ttl i/o pa4 30 can module 0 receive. ttl i can0rx i 2 s module 0 transmit clock. ttl i/o i2s0txsck pwm 6. this signal is controlled by pwm generator 3. ttl o pwm6 ssi module 0 receive. ttl i ssi0rx mii transmit data 0. ttl o txd0 gpio port a bit 5. ttl i/o pa5 31 can module 0 transmit. ttl o can0tx i 2 s module 0 transmit word select. ttl i/o i2s0txws pwm 7. this signal is controlled by pwm generator 3. ttl o pwm7 mii receive data valid. ttl i rxdv ssi module 0 transmit. ttl o ssi0tx positive supply for i/o and some logic. power - vdd 32 ground reference for logic and i/o pins. power - gnd 33 gpio port a bit 6. ttl i/o pa6 34 can module 0 receive. ttl i can0rx capture/compare/pwm 1. ttl i/o ccp1 i 2 c module 1 clock. od i/o i2c1scl pwm 0. this signal is controlled by pwm generator 0. ttl o pwm0 pwm 4. this signal is controlled by pwm generator 2. ttl o pwm4 mii receive clock. 25 mhz in 100base-tx mode. 2.5 mhz in 10base-t mode. ttl i rxck uart module 1 clear to send modem flow control input signal. ttl i u1cts optionally used in host mode to control an external power source to supply power to the usb bus. ttl o usb0epen gpio port a bit 7. ttl i/o pa7 35 can module 0 transmit. ttl o can0tx capture/compare/pwm 3. ttl i/o ccp3 capture/compare/pwm 4. ttl i/o ccp4 i 2 c module 1 data. od i/o i2c1sda pwm 1. this signal is controlled by pwm generator 0. ttl o pwm1 pwm 5. this signal is controlled by pwm generator 2. ttl o pwm5 mii receive error. ttl i rxer uart module 1 data carrier detect modem status input signal. ttl i u1dcd optionally used in host mode by an external power source to indicate an error state by that power source. ttl i usb0pflt gpio port g bit 7. ttl i/o pg7 36 capture/compare/pwm 5. ttl i/o ccp5 epi module 0 signal 31. ttl i/o epi0s31 pwm 7. this signal is controlled by pwm generator 3. ttl o pwm7 qei module 1 phase b. ttl i phb1 mii transmit error. ttl o txer 1219 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 24-2. signals by pin number (continued) description buffer type a pin type pin name pin number gpio port g bit 6. ttl i/o pg6 37 pwm fault 1. ttl i fault1 i 2 s module 0 receive word select. ttl i/o i2s0rxws pwm 6. this signal is controlled by pwm generator 3. ttl o pwm6 qei module 1 phase a. ttl i pha1 mii transmit clock. 25 mhz in 100base-tx mode. 2.5 mhz in 10base-t mode. ttl i txck uart module 1 ring indicator modem status input signal. ttl i u1ri positive supply for most of the logic function, including the processor core and most peripherals. the voltage on this pin is 1.3 v and is supplied by the on-chip ldo. the vddc pins should only be connected to the ldo pin and an external capacitor as specified in table 26-6 on page 1303 . power - vddc 38 gpio port j bit 2. ttl i/o pj2 39 capture/compare/pwm 0. ttl i/o ccp0 epi module 0 signal 18. ttl i/o epi0s18 pwm fault 0. ttl i fault0 gpio port g bit 5. ttl i/o pg5 40 capture/compare/pwm 5. ttl i/o ccp5 pwm fault 1. ttl i fault1 i 2 s module 0 receive clock. ttl i/o i2s0rxsck qei module 0 index. ttl i idx0 pwm 7. this signal is controlled by pwm generator 3. ttl o pwm7 mii transmit enable. ttl o txen uart module 1 data terminal ready modem status input signal. ttl o u1dtr gpio port g bit 4. ttl i/o pg4 41 capture/compare/pwm 3. ttl i/o ccp3 epi module 0 signal 15. ttl i/o epi0s15 pwm fault 1. ttl i fault1 pwm 6. this signal is controlled by pwm generator 3. ttl o pwm6 mii receive data 0. ttl i rxd0 uart module 1 ring indicator modem status input signal. ttl i u1ri gpio port f bit 7. ttl i/o pf7 42 capture/compare/pwm 4. ttl i/o ccp4 epi module 0 signal 12. ttl i/o epi0s12 pwm fault 1. ttl i fault1 qei module 0 phase b. ttl i phb0 mii receive data 1. ttl i rxd1 july 03, 2014 1220 texas instruments-production data signal tables table 24-2. signals by pin number (continued) description buffer type a pin type pin name pin number gpio port f bit 6. ttl i/o pf6 43 analog comparator 2 output. ttl o c2o capture/compare/pwm 1. ttl i/o ccp1 i 2 s module 0 transmit master clock. ttl i/o i2s0txmclk qei module 0 phase a. ttl i pha0 mii receive data 2. ttl i rxd2 uart module 1 request to send modem flow control output line. ttl o u1rts positive supply for i/o and some logic. power - vdd 44 ground reference for logic and i/o pins. power - gnd 45 gpio port f bit 5. ttl i/o pf5 46 analog comparator 1 output. ttl o c1o capture/compare/pwm 2. ttl i/o ccp2 epi module 0 signal 15. ttl i/o epi0s15 mii receive data 3. ttl i rxd3 ssi module 1 transmit. ttl o ssi1tx gpio port f bit 0. ttl i/o pf0 47 can module 1 receive. ttl i can1rx i 2 s module 0 transmit data. ttl i/o i2s0txsd pwm 0. this signal is controlled by pwm generator 0. ttl o pwm0 qei module 0 phase b. ttl i phb0 mii receive clock. 25 mhz in 100base-tx mode. 2.5 mhz in 10base-t mode. ttl i rxck uart module 1 data set ready modem output control line. ttl i u1dsr main oscillator crystal input or an external clock reference input. analog i osc0 48 main oscillator crystal output. leave unconnected when using a single-ended clock source. analog o osc1 49 gpio port j bit 3. ttl i/o pj3 50 capture/compare/pwm 6. ttl i/o ccp6 epi module 0 signal 19. ttl i/o epi0s19 uart module 1 clear to send modem flow control input signal. ttl i u1cts no connect. leave the pin electrically unconnected/isolated. - - nc 51 gpio port j bit 4. ttl i/o pj4 52 capture/compare/pwm 4. ttl i/o ccp4 epi module 0 signal 28. ttl i/o epi0s28 uart module 1 data carrier detect modem status input signal. ttl i u1dcd gpio port j bit 5. ttl i/o pj5 53 capture/compare/pwm 2. ttl i/o ccp2 epi module 0 signal 29. ttl i/o epi0s29 uart module 1 data set ready modem output control line. ttl i u1dsr 1221 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 24-2. signals by pin number (continued) description buffer type a pin type pin name pin number gpio port j bit 6. ttl i/o pj6 54 capture/compare/pwm 1. ttl i/o ccp1 epi module 0 signal 30. ttl i/o epi0s30 uart module 1 request to send modem flow control output line. ttl o u1rts gpio port j bit 7. ttl i/o pj7 55 capture/compare/pwm 0. ttl i/o ccp0 uart module 1 data terminal ready modem status input signal. ttl o u1dtr positive supply for i/o and some logic. power - vdd 56 ground reference for logic and i/o pins. power - gnd 57 gpio port f bit 4. ttl i/o pf4 58 analog comparator 0 output. ttl o c0o capture/compare/pwm 0. ttl i/o ccp0 epi module 0 signal 12. ttl i/o epi0s12 pwm fault 0. ttl i fault0 mdio of the ethernet phy. od i/o mdio ssi module 1 receive. ttl i ssi1rx gpio port f bit 3. ttl i/o pf3 59 mii management clock. ttl o mdc pwm 3. this signal is controlled by pwm generator 1. ttl o pwm3 pwm 5. this signal is controlled by pwm generator 2. ttl o pwm5 ssi module 1 frame signal. ttl i/o ssi1fss gpio port f bit 2. ttl i/o pf2 60 phy interrupt. ttl i phyint pwm 2. this signal is controlled by pwm generator 1. ttl o pwm2 pwm 4. this signal is controlled by pwm generator 2. ttl o pwm4 ssi module 1 clock. ttl i/o ssi1clk gpio port f bit 1. ttl i/o pf1 61 can module 1 transmit. ttl o can1tx capture/compare/pwm 3. ttl i/o ccp3 i 2 s module 0 transmit master clock. ttl i/o i2s0txmclk qei module 1 index. ttl i idx1 pwm 1. this signal is controlled by pwm generator 0. ttl o pwm1 mii receive error. ttl i rxer uart module 1 request to send modem flow control output line. ttl o u1rts gpio port h bit 6. ttl i/o ph6 62 epi module 0 signal 26. ttl i/o epi0s26 pwm 4. this signal is controlled by pwm generator 2. ttl o pwm4 mii receive data valid. ttl i rxdv ssi module 1 receive. ttl i ssi1rx july 03, 2014 1222 texas instruments-production data signal tables table 24-2. signals by pin number (continued) description buffer type a pin type pin name pin number gpio port h bit 5. ttl i/o ph5 63 epi module 0 signal 11. ttl i/o epi0s11 pwm fault 2. ttl i fault2 ssi module 1 frame signal. ttl i/o ssi1fss mii transmit data 0. ttl o txd0 system reset input. ttl i rst 64 gpio port b bit 3. ttl i/o pb3 65 pwm fault 0. ttl i fault0 pwm fault 3. ttl i fault3 i 2 c module 0 data. od i/o i2c0sda optionally used in host mode by an external power source to indicate an error state by that power source. ttl i usb0pflt gpio port b bit 0. this pin is not 5-v tolerant. ttl i/o pb0 66 capture/compare/pwm 0. ttl i/o ccp0 pwm 2. this signal is controlled by pwm generator 1. ttl o pwm2 uart module 1 receive. when in irda mode, this signal has irda modulation. ttl i u1rx this signal senses the state of the usb id signal. the usb phy enables an integrated pull-up, and an external element (usb connector) indicates the initial state of the usb controller (pulled down is the a side of the cable and pulled up is the b side). analog i usb0id gpio port b bit 1. this pin is not 5-v tolerant. ttl i/o pb1 67 capture/compare/pwm 1. ttl i/o ccp1 capture/compare/pwm 2. ttl i/o ccp2 pwm 3. this signal is controlled by pwm generator 1. ttl o pwm3 uart module 1 transmit. when in irda mode, this signal has irda modulation. ttl o u1tx this signal is used during the session request protocol. this signal allows the usb phy to both sense the voltage level of vbus, and pull up vbus momentarily during vbus pulsing. analog i/o usb0vbus positive supply for i/o and some logic. power - vdd 68 ground reference for logic and i/o pins. power - gnd 69 bidirectional differential data pin (d- per usb specification) for usb0. analog i/o usb0dm 70 bidirectional differential data pin (d+ per usb specification) for usb0. analog i/o usb0dp 71 gpio port b bit 2. ttl i/o pb2 72 capture/compare/pwm 0. ttl i/o ccp0 capture/compare/pwm 3. ttl i/o ccp3 i 2 c module 0 clock. od i/o i2c0scl qei module 0 index. ttl i idx0 optionally used in host mode to control an external power source to supply power to the usb bus. ttl o usb0epen 9.1-k resistor (1% precision) used internally for usb analog circuitry. analog o usb0rbias 73 1223 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 24-2. signals by pin number (continued) description buffer type a pin type pin name pin number gpio port e bit 0. ttl i/o pe0 74 capture/compare/pwm 3. ttl i/o ccp3 epi module 0 signal 8. ttl i/o epi0s8 pwm 4. this signal is controlled by pwm generator 2. ttl o pwm4 ssi module 1 clock. ttl i/o ssi1clk optionally used in host mode by an external power source to indicate an error state by that power source. ttl i usb0pflt gpio port e bit 1. ttl i/o pe1 75 capture/compare/pwm 2. ttl i/o ccp2 capture/compare/pwm 6. ttl i/o ccp6 epi module 0 signal 9. ttl i/o epi0s9 pwm fault 0. ttl i fault0 pwm 5. this signal is controlled by pwm generator 2. ttl o pwm5 ssi module 1 frame signal. ttl i/o ssi1fss gpio port h bit 4. ttl i/o ph4 76 epi module 0 signal 10. ttl i/o epi0s10 ssi module 1 clock. ttl i/o ssi1clk ethernet mii transmit data 1. ttl o txd1 optionally used in host mode by an external power source to indicate an error state by that power source. ttl i usb0pflt gpio port c bit 3. ttl i/o pc3 77 jtag tdo and swo. ttl o swo jtag tdo and swo. ttl o tdo gpio port c bit 2. ttl i/o pc2 78 jtag tdi. ttl i tdi gpio port c bit 1. ttl i/o pc1 79 jtag tms and swdio. ttl i/o swdio jtag tms and swdio. ttl i tms gpio port c bit 0. ttl i/o pc0 80 jtag/swd clk. ttl i swclk jtag/swd clk. ttl i tck positive supply for i/o and some logic. power - vdd 81 ground reference for logic and i/o pins. power - gnd 82 gpio port h bit 3. ttl i/o ph3 83 epi module 0 signal 0. ttl i/o epi0s0 pwm fault 0. ttl i fault0 qei module 0 phase b. ttl i phb0 mii transmit data 2. ttl o txd2 optionally used in host mode to control an external power source to supply power to the usb bus. ttl o usb0epen july 03, 2014 1224 texas instruments-production data signal tables table 24-2. signals by pin number (continued) description buffer type a pin type pin name pin number gpio port h bit 2. ttl i/o ph2 84 analog comparator 1 output. ttl o c1o epi module 0 signal 1. ttl i/o epi0s1 pwm fault 3. ttl i fault3 qei module 1 index. ttl i idx1 ethernet mii transmit data 3. ttl o txd3 gpio port h bit 1. ttl i/o ph1 85 capture/compare/pwm 7. ttl i/o ccp7 epi module 0 signal 7. ttl i/o epi0s7 pwm 3. this signal is controlled by pwm generator 1. ttl o pwm3 pwm 5. this signal is controlled by pwm generator 2. ttl o pwm5 gpio port h bit 0. ttl i/o ph0 86 capture/compare/pwm 6. ttl i/o ccp6 epi module 0 signal 6. ttl i/o epi0s6 pwm 2. this signal is controlled by pwm generator 1. ttl o pwm2 pwm 4. this signal is controlled by pwm generator 2. ttl o pwm4 gpio port j bit 1. ttl i/o pj1 87 epi module 0 signal 17. ttl i/o epi0s17 i 2 c module 1 data. od i/o i2c1sda pwm 1. this signal is controlled by pwm generator 0. ttl o pwm1 optionally used in host mode by an external power source to indicate an error state by that power source. ttl i usb0pflt positive supply for most of the logic function, including the processor core and most peripherals. the voltage on this pin is 1.3 v and is supplied by the on-chip ldo. the vddc pins should only be connected to the ldo pin and an external capacitor as specified in table 26-6 on page 1303 . power - vddc 88 gpio port b bit 7. ttl i/o pb7 89 non-maskable interrupt. ttl i nmi mii receive data 1. ttl i rxd1 gpio port b bit 6. ttl i/o pb6 90 analog comparator 0 positive input. analog i c0+ analog comparator 0 output. ttl o c0o capture/compare/pwm 1. ttl i/o ccp1 capture/compare/pwm 5. ttl i/o ccp5 capture/compare/pwm 7. ttl i/o ccp7 pwm fault 1. ttl i fault1 i 2 s module 0 transmit clock. ttl i/o i2s0txsck qei module 0 index. ttl i idx0 this input provides a reference voltage used to specify the input voltage at which the adc converts to a maximum value. in other words, the voltage that is applied to vrefa is the voltage with which an ainn signal is converted to 4095. the vrefa input is limited to the range specified in table 26-23 on page 1314 . analog i vrefa 1225 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 24-2. signals by pin number (continued) description buffer type a pin type pin name pin number gpio port b bit 5. ttl i/o pb5 91 analog-to-digital converter input 11. analog i ain11 analog comparator 0 output. ttl o c0o analog comparator 1 negative input. analog i c1- can module 0 transmit. ttl o can0tx capture/compare/pwm 0. ttl i/o ccp0 capture/compare/pwm 2. ttl i/o ccp2 capture/compare/pwm 5. ttl i/o ccp5 capture/compare/pwm 6. ttl i/o ccp6 epi module 0 signal 22. ttl i/o epi0s22 uart module 1 transmit. when in irda mode, this signal has irda modulation. ttl o u1tx gpio port b bit 4. ttl i/o pb4 92 analog-to-digital converter input 10. analog i ain10 analog comparator 0 negative input. analog i c0- can module 0 receive. ttl i can0rx epi module 0 signal 23. ttl i/o epi0s23 qei module 0 index. ttl i idx0 uart module 1 receive. when in irda mode, this signal has irda modulation. ttl i u1rx uart module 2 receive. when in irda mode, this signal has irda modulation. ttl i u2rx positive supply for i/o and some logic. power - vdd 93 ground reference for logic and i/o pins. power - gnd 94 gpio port e bit 2. ttl i/o pe2 95 analog-to-digital converter input 9. analog i ain9 capture/compare/pwm 2. ttl i/o ccp2 capture/compare/pwm 4. ttl i/o ccp4 epi module 0 signal 24. ttl i/o epi0s24 qei module 0 phase a. ttl i pha0 qei module 1 phase b. ttl i phb1 ssi module 1 receive. ttl i ssi1rx gpio port e bit 3. ttl i/o pe3 96 analog-to-digital converter input 8. analog i ain8 capture/compare/pwm 1. ttl i/o ccp1 capture/compare/pwm 7. ttl i/o ccp7 epi module 0 signal 25. ttl i/o epi0s25 qei module 1 phase a. ttl i pha1 qei module 0 phase b. ttl i phb0 ssi module 1 transmit. ttl o ssi1tx july 03, 2014 1226 texas instruments-production data signal tables table 24-2. signals by pin number (continued) description buffer type a pin type pin name pin number gpio port d bit 4. ttl i/o pd4 97 analog-to-digital converter input 7. analog i ain7 capture/compare/pwm 0. ttl i/o ccp0 capture/compare/pwm 3. ttl i/o ccp3 epi module 0 signal 19. ttl i/o epi0s19 i 2 s module 0 receive data. ttl i/o i2s0rxsd ethernet mii transmit data 3. ttl o txd3 uart module 1 ring indicator modem status input signal. ttl i u1ri gpio port d bit 5. ttl i/o pd5 98 analog-to-digital converter input 6. analog i ain6 capture/compare/pwm 2. ttl i/o ccp2 capture/compare/pwm 4. ttl i/o ccp4 epi module 0 signal 28. ttl i/o epi0s28 i 2 s module 0 receive master clock. ttl i/o i2s0rxmclk mii transmit data 2. ttl o txd2 uart module 2 receive. when in irda mode, this signal has irda modulation. ttl i u2rx gpio port d bit 6. ttl i/o pd6 99 analog-to-digital converter input 5. analog i ain5 epi module 0 signal 29. ttl i/o epi0s29 pwm fault 0. ttl i fault0 i 2 s module 0 transmit clock. ttl i/o i2s0txsck ethernet mii transmit data 1. ttl o txd1 uart module 2 transmit. when in irda mode, this signal has irda modulation. ttl o u2tx gpio port d bit 7. ttl i/o pd7 100 analog-to-digital converter input 4. analog i ain4 analog comparator 0 output. ttl o c0o capture/compare/pwm 1. ttl i/o ccp1 epi module 0 signal 30. ttl i/o epi0s30 i 2 s module 0 transmit word select. ttl i/o i2s0txws qei module 0 index. ttl i idx0 mii transmit data 0. ttl o txd0 uart module 1 data terminal ready modem status input signal. ttl o u1dtr a. the ttl designation indicates the pin has ttl-compatible voltage levels. 24.1.2 signals by signal name table 24-3. signals by signal name description buffer type a pin type pin mux / pin assignment pin number pin name analog-to-digital converter input 0. analog i pe7 1 ain0 analog-to-digital converter input 1. analog i pe6 2 ain1 1227 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 24-3. signals by signal name (continued) description buffer type a pin type pin mux / pin assignment pin number pin name analog-to-digital converter input 2. analog i pe5 5 ain2 analog-to-digital converter input 3. analog i pe4 6 ain3 analog-to-digital converter input 4. analog i pd7 100 ain4 analog-to-digital converter input 5. analog i pd6 99 ain5 analog-to-digital converter input 6. analog i pd5 98 ain6 analog-to-digital converter input 7. analog i pd4 97 ain7 analog-to-digital converter input 8. analog i pe3 96 ain8 analog-to-digital converter input 9. analog i pe2 95 ain9 analog-to-digital converter input 10. analog i pb4 92 ain10 analog-to-digital converter input 11. analog i pb5 91 ain11 analog-to-digital converter input 12. analog i pd3 13 ain12 analog-to-digital converter input 13. analog i pd2 12 ain13 analog-to-digital converter input 14. analog i pd1 11 ain14 analog-to-digital converter input 15. analog i pd0 10 ain15 analog comparator 0 positive input. analog i pb6 90 c0+ analog comparator 0 negative input. analog i pb4 92 c0- analog comparator 0 output. ttl o pc5 (3) pf4 (2) pb6 (3) pb5 (1) pd7 (2) 24 58 90 91 100 c0o analog comparator 1 positive input. analog i pc5 24 c1+ analog comparator 1 negative input. analog i pb5 91 c1- analog comparator 1 output. ttl o pe6 (2) pc7 (7) pc5 (2) pf5 (2) ph2 (2) 2 22 24 46 84 c1o analog comparator 2 positive input. analog i pc6 23 c2+ analog comparator 2 negative input. analog i pc7 22 c2- analog comparator 2 output. ttl o pe7 (2) pc6 (3) pf6 (2) 1 23 43 c2o can module 0 receive. ttl i pd0 (2) pa4 (5) pa6 (6) pb4 (5) 10 30 34 92 can0rx can module 0 transmit. ttl o pd1 (2) pa5 (5) pa7 (6) pb5 (5) 11 31 35 91 can0tx can module 1 receive. ttl i pf0 (1) 47 can1rx can module 1 transmit. ttl o pf1 (1) 61 can1tx july 03, 2014 1228 texas instruments-production data signal tables table 24-3. signals by signal name (continued) description buffer type a pin type pin mux / pin assignment pin number pin name capture/compare/pwm 0. ttl i/o pd3 (4) pc7 (4) pc6 (6) pj2 (9) pj7 (10) pf4 (1) pb0 (1) pb2 (5) pb5 (4) pd4 (1) 13 22 23 39 55 58 66 72 91 97 ccp0 capture/compare/pwm 1. ttl i/o pc5 (1) pc4 (9) pa6 (2) pf6 (1) pj6 (10) pb1 (4) pb6 (1) pe3 (1) pd7 (3) 24 25 34 43 54 67 90 96 100 ccp1 capture/compare/pwm 2. ttl i/o pe4 (6) pd1 (10) pc4 (5) pf5 (1) pj5 (10) pb1 (1) pe1 (4) pb5 (6) pe2 (5) pd5 (1) 6 11 25 46 53 67 75 91 95 98 ccp2 capture/compare/pwm 3. ttl i/o pe4 (1) pc6 (1) pc5 (5) pa7 (7) pg4 (1) pf1 (10) pb2 (4) pe0 (3) pd4 (2) 6 23 24 35 41 61 72 74 97 ccp3 capture/compare/pwm 4. ttl i/o pc7 (1) pc4 (6) pa7 (2) pf7 (1) pj4 (10) pe2 (1) pd5 (2) 22 25 35 42 52 95 98 ccp4 capture/compare/pwm 5. ttl i/o pe5 (1) pd2 (4) pc4 (1) pg7 (8) pg5 (1) pb6 (6) pb5 (2) 5 12 25 36 40 90 91 ccp5 1229 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 24-3. signals by signal name (continued) description buffer type a pin type pin mux / pin assignment pin number pin name capture/compare/pwm 6. ttl i/o pd0 (6) pd2 (2) pj3 (10) pe1 (5) ph0 (1) pb5 (3) 10 12 50 75 86 91 ccp6 capture/compare/pwm 7. ttl i/o pd1 (6) pd3 (2) ph1 (1) pb6 (2) pe3 (5) 11 13 85 90 96 ccp7 mii collision detect. ttl i pg2 (3) 17 col mii carrier sense. ttl i pg3 (3) 16 crs epi module 0 signal 0. ttl i/o ph3 (8) 83 epi0s0 epi module 0 signal 1. ttl i/o ph2 (8) 84 epi0s1 epi module 0 signal 2. ttl i/o pc4 (8) 25 epi0s2 epi module 0 signal 3. ttl i/o pc5 (8) 24 epi0s3 epi module 0 signal 4. ttl i/o pc6 (8) 23 epi0s4 epi module 0 signal 5. ttl i/o pc7 (8) 22 epi0s5 epi module 0 signal 6. ttl i/o ph0 (8) 86 epi0s6 epi module 0 signal 7. ttl i/o ph1 (8) 85 epi0s7 epi module 0 signal 8. ttl i/o pe0 (8) 74 epi0s8 epi module 0 signal 9. ttl i/o pe1 (8) 75 epi0s9 epi module 0 signal 10. ttl i/o ph4 (8) 76 epi0s10 epi module 0 signal 11. ttl i/o ph5 (8) 63 epi0s11 epi module 0 signal 12. ttl i/o pf7 (8) pf4 (8) 42 58 epi0s12 epi module 0 signal 13. ttl i/o pg0 (8) 19 epi0s13 epi module 0 signal 14. ttl i/o pg1 (8) 18 epi0s14 epi module 0 signal 15. ttl i/o pg4 (8) pf5 (8) 41 46 epi0s15 epi module 0 signal 16. ttl i/o pj0 (8) 14 epi0s16 epi module 0 signal 17. ttl i/o pj1 (8) 87 epi0s17 epi module 0 signal 18. ttl i/o pj2 (8) 39 epi0s18 epi module 0 signal 19. ttl i/o pj3 (8) pd4 (10) 50 97 epi0s19 epi module 0 signal 20. ttl i/o pd2 (8) 12 epi0s20 epi module 0 signal 21. ttl i/o pd3 (8) 13 epi0s21 epi module 0 signal 22. ttl i/o pb5 (8) 91 epi0s22 epi module 0 signal 23. ttl i/o pb4 (8) 92 epi0s23 epi module 0 signal 24. ttl i/o pe2 (8) 95 epi0s24 epi module 0 signal 25. ttl i/o pe3 (8) 96 epi0s25 epi module 0 signal 26. ttl i/o ph6 (8) 62 epi0s26 epi module 0 signal 27. ttl i/o ph7 (8) 15 epi0s27 july 03, 2014 1230 texas instruments-production data signal tables table 24-3. signals by signal name (continued) description buffer type a pin type pin mux / pin assignment pin number pin name epi module 0 signal 28. ttl i/o pj4 (8) pd5 (10) 52 98 epi0s28 epi module 0 signal 29. ttl i/o pj5 (8) pd6 (10) 53 99 epi0s29 epi module 0 signal 30. ttl i/o pj6 (8) pd7 (10) 54 100 epi0s30 epi module 0 signal 31. ttl i/o pg7 (9) 36 epi0s31 pwm fault 0. ttl i pe4 (4) pg3 (8) pg2 (4) pj2 (10) pf4 (4) pb3 (2) pe1 (3) ph3 (2) pd6 (1) 6 16 17 39 58 65 75 83 99 fault0 pwm fault 1. ttl i pg6 (8) pg5 (5) pg4 (4) pf7 (9) pb6 (4) 37 40 41 42 90 fault1 pwm fault 2. ttl i pg3 (4) pc5 (4) ph5 (10) 16 24 63 fault2 pwm fault 3. ttl i pb3 (4) ph2 (4) 65 84 fault3 ground reference for logic and i/o pins. power - fixed 9 21 33 45 57 69 82 94 gnd the ground reference for the analog circuits (adc, analog comparators, etc.). these are separated from gnd to minimize the electrical noise contained on vdd from affecting the analog functions. power - fixed 4 gnda i 2 c module 0 clock. od i/o pb2 (1) 72 i2c0scl i 2 c module 0 data. od i/o pb3 (1) 65 i2c0sda i 2 c module 1 clock. od i/o pj0 (11) pg0 (3) pa0 (8) pa6 (1) 14 19 26 34 i2c1scl i 2 c module 1 data. od i/o pg1 (3) pa1 (8) pa7 (1) pj1 (11) 18 27 35 87 i2c1sda i 2 s module 0 receive master clock. ttl i/o pg3 (9) pa3 (9) pd5 (8) 16 29 98 i2s0rxmclk 1231 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 24-3. signals by signal name (continued) description buffer type a pin type pin mux / pin assignment pin number pin name i 2 s module 0 receive clock. ttl i/o pd0 (8) pg5 (9) 10 40 i2s0rxsck i 2 s module 0 receive data. ttl i/o pg2 (9) pa2 (9) pd4 (8) 17 28 97 i2s0rxsd i 2 s module 0 receive word select. ttl i/o pd1 (8) pg6 (9) 11 37 i2s0rxws i 2 s module 0 transmit master clock. ttl i/o pf6 (9) pf1 (8) 43 61 i2s0txmclk i 2 s module 0 transmit clock. ttl i/o pa4 (9) pb6 (9) pd6 (8) 30 90 99 i2s0txsck i 2 s module 0 transmit data. ttl i/o pe5 (9) pf0 (8) 5 47 i2s0txsd i 2 s module 0 transmit word select. ttl i/o pe4 (9) pa5 (9) pd7 (8) 6 31 100 i2s0txws qei module 0 index. ttl i pd0 (3) pg5 (4) pb2 (2) pb6 (5) pb4 (6) pd7 (1) 10 40 72 90 92 100 idx0 qei module 1 index. ttl i pg2 (8) pf1 (2) ph2 (1) 17 61 84 idx1 low drop-out regulator output voltage. this pin requires an external capacitor between the pin and gnd of 1 f or greater. the ldo pin must also be connected to the vddc pins at the board level in addition to the decoupling capacitor(s). power - fixed 7 ldo mii management clock. ttl o pf3 (3) 59 mdc mdio of the ethernet phy. od i/o pf4 (3) 58 mdio no connect. leave the pin electrically unconnected/isolated. - - fixed 51 nc non-maskable interrupt. ttl i pb7 (4) 89 nmi main oscillator crystal input or an external clock reference input. analog i fixed 48 osc0 main oscillator crystal output. leave unconnected when using a single-ended clock source. analog o fixed 49 osc1 gpio port a bit 0. ttl i/o - 26 pa0 gpio port a bit 1. ttl i/o - 27 pa1 gpio port a bit 2. ttl i/o - 28 pa2 gpio port a bit 3. ttl i/o - 29 pa3 gpio port a bit 4. ttl i/o - 30 pa4 gpio port a bit 5. ttl i/o - 31 pa5 gpio port a bit 6. ttl i/o - 34 pa6 gpio port a bit 7. ttl i/o - 35 pa7 july 03, 2014 1232 texas instruments-production data signal tables table 24-3. signals by signal name (continued) description buffer type a pin type pin mux / pin assignment pin number pin name gpio port b bit 0. this pin is not 5-v tolerant. ttl i/o - 66 pb0 gpio port b bit 1. this pin is not 5-v tolerant. ttl i/o - 67 pb1 gpio port b bit 2. ttl i/o - 72 pb2 gpio port b bit 3. ttl i/o - 65 pb3 gpio port b bit 4. ttl i/o - 92 pb4 gpio port b bit 5. ttl i/o - 91 pb5 gpio port b bit 6. ttl i/o - 90 pb6 gpio port b bit 7. ttl i/o - 89 pb7 gpio port c bit 0. ttl i/o - 80 pc0 gpio port c bit 1. ttl i/o - 79 pc1 gpio port c bit 2. ttl i/o - 78 pc2 gpio port c bit 3. ttl i/o - 77 pc3 gpio port c bit 4. ttl i/o - 25 pc4 gpio port c bit 5. ttl i/o - 24 pc5 gpio port c bit 6. ttl i/o - 23 pc6 gpio port c bit 7. ttl i/o - 22 pc7 gpio port d bit 0. ttl i/o - 10 pd0 gpio port d bit 1. ttl i/o - 11 pd1 gpio port d bit 2. ttl i/o - 12 pd2 gpio port d bit 3. ttl i/o - 13 pd3 gpio port d bit 4. ttl i/o - 97 pd4 gpio port d bit 5. ttl i/o - 98 pd5 gpio port d bit 6. ttl i/o - 99 pd6 gpio port d bit 7. ttl i/o - 100 pd7 gpio port e bit 0. ttl i/o - 74 pe0 gpio port e bit 1. ttl i/o - 75 pe1 gpio port e bit 2. ttl i/o - 95 pe2 gpio port e bit 3. ttl i/o - 96 pe3 gpio port e bit 4. ttl i/o - 6 pe4 gpio port e bit 5. ttl i/o - 5 pe5 gpio port e bit 6. ttl i/o - 2 pe6 gpio port e bit 7. ttl i/o - 1 pe7 gpio port f bit 0. ttl i/o - 47 pf0 gpio port f bit 1. ttl i/o - 61 pf1 gpio port f bit 2. ttl i/o - 60 pf2 gpio port f bit 3. ttl i/o - 59 pf3 gpio port f bit 4. ttl i/o - 58 pf4 gpio port f bit 5. ttl i/o - 46 pf5 gpio port f bit 6. ttl i/o - 43 pf6 gpio port f bit 7. ttl i/o - 42 pf7 gpio port g bit 0. ttl i/o - 19 pg0 1233 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 24-3. signals by signal name (continued) description buffer type a pin type pin mux / pin assignment pin number pin name gpio port g bit 1. ttl i/o - 18 pg1 gpio port g bit 2. ttl i/o - 17 pg2 gpio port g bit 3. ttl i/o - 16 pg3 gpio port g bit 4. ttl i/o - 41 pg4 gpio port g bit 5. ttl i/o - 40 pg5 gpio port g bit 6. ttl i/o - 37 pg6 gpio port g bit 7. ttl i/o - 36 pg7 gpio port h bit 0. ttl i/o - 86 ph0 gpio port h bit 1. ttl i/o - 85 ph1 gpio port h bit 2. ttl i/o - 84 ph2 gpio port h bit 3. ttl i/o - 83 ph3 gpio port h bit 4. ttl i/o - 76 ph4 gpio port h bit 5. ttl i/o - 63 ph5 gpio port h bit 6. ttl i/o - 62 ph6 gpio port h bit 7. ttl i/o - 15 ph7 qei module 0 phase a. ttl i pd1 (3) pc4 (2) pf6 (4) pe2 (4) 11 25 43 95 pha0 qei module 1 phase a. ttl i pg6 (1) pe3 (3) 37 96 pha1 qei module 0 phase b. ttl i pc7 (2) pc6 (2) pf7 (4) pf0 (2) ph3 (1) pe3 (4) 22 23 42 47 83 96 phb0 qei module 1 phase b. ttl i pd1 (11) pg7 (1) pe2 (3) 11 36 95 phb1 phy interrupt. ttl i pf2 (3) 60 phyint gpio port j bit 0. ttl i/o - 14 pj0 gpio port j bit 1. ttl i/o - 87 pj1 gpio port j bit 2. ttl i/o - 39 pj2 gpio port j bit 3. ttl i/o - 50 pj3 gpio port j bit 4. ttl i/o - 52 pj4 gpio port j bit 5. ttl i/o - 53 pj5 gpio port j bit 6. ttl i/o - 54 pj6 gpio port j bit 7. ttl i/o - 55 pj7 pwm 0. this signal is controlled by pwm generator 0. ttl o pd0 (1) pj0 (10) pg2 (1) pg0 (2) pa6 (4) pf0 (3) 10 14 17 19 34 47 pwm0 july 03, 2014 1234 texas instruments-production data signal tables table 24-3. signals by signal name (continued) description buffer type a pin type pin mux / pin assignment pin number pin name pwm 1. this signal is controlled by pwm generator 0. ttl o pd1 (1) pg3 (1) pg1 (2) pa7 (4) pf1 (3) pj1 (10) 11 16 18 35 61 87 pwm1 pwm 2. this signal is controlled by pwm generator 1. ttl o pd2 (3) pf2 (4) pb0 (2) ph0 (2) 12 60 66 86 pwm2 pwm 3. this signal is controlled by pwm generator 1. ttl o pd3 (3) pf3 (4) pb1 (2) ph1 (2) 13 59 67 85 pwm3 pwm 4. this signal is controlled by pwm generator 2. ttl o pe6 (1) pg0 (4) pa2 (4) pa6 (5) pf2 (2) ph6 (10) pe0 (1) ph0 (9) 2 19 28 34 60 62 74 86 pwm4 pwm 5. this signal is controlled by pwm generator 2. ttl o pe7 (1) ph7 (10) pg1 (4) pa3 (4) pa7 (5) pf3 (2) pe1 (1) ph1 (9) 1 15 18 29 35 59 75 85 pwm5 pwm 6. this signal is controlled by pwm generator 3. ttl o pc4 (4) pa4 (4) pg6 (4) pg4 (9) 25 30 37 41 pwm6 pwm 7. this signal is controlled by pwm generator 3. ttl o pc6 (4) pa5 (4) pg7 (4) pg5 (8) 23 31 36 40 pwm7 system reset input. ttl i fixed 64 rst mii receive clock. 25 mhz in 100base-tx mode. 2.5 mhz in 10base-t mode. ttl i ph7 (3) pa6 (3) pf0 (4) 15 34 47 rxck mii receive data 0. ttl i pe4 (7) pg4 (3) 6 41 rxd0 mii receive data 1. ttl i pf7 (3) pb7 (7) 42 89 rxd1 mii receive data 2. ttl i pf6 (3) 43 rxd2 mii receive data 3. ttl i pf5 (3) 46 rxd3 mii receive data valid. ttl i pd0 (7) pa5 (3) ph6 (9) 10 31 62 rxdv 1235 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 24-3. signals by signal name (continued) description buffer type a pin type pin mux / pin assignment pin number pin name mii receive error. ttl i pj0 (3) pa7 (3) pf1 (4) 14 35 61 rxer ssi module 0 clock. ttl i/o pa2 (1) 28 ssi0clk ssi module 0 frame signal. ttl i/o pa3 (1) 29 ssi0fss ssi module 0 receive. ttl i pa4 (1) 30 ssi0rx ssi module 0 transmit. ttl o pa5 (1) 31 ssi0tx ssi module 1 clock. ttl i/o pf2 (9) pe0 (2) ph4 (11) 60 74 76 ssi1clk ssi module 1 frame signal. ttl i/o pf3 (9) ph5 (11) pe1 (2) 59 63 75 ssi1fss ssi module 1 receive. ttl i pf4 (9) ph6 (11) pe2 (2) 58 62 95 ssi1rx ssi module 1 transmit. ttl o ph7 (11) pf5 (9) pe3 (2) 15 46 96 ssi1tx jtag/swd clk. ttl i pc0 (3) 80 swclk jtag tms and swdio. ttl i/o pc1 (3) 79 swdio jtag tdo and swo. ttl o pc3 (3) 77 swo jtag/swd clk. ttl i pc0 (3) 80 tck jtag tdi. ttl i pc2 (3) 78 tdi jtag tdo and swo. ttl o pc3 (3) 77 tdo jtag tms and swdio. ttl i pc1 (3) 79 tms mii transmit clock. 25 mhz in 100base-tx mode. 2.5 mhz in 10base-t mode. ttl i pg6 (3) 37 txck mii transmit data 0. ttl o pa4 (3) ph5 (9) pd7 (4) 30 63 100 txd0 ethernet mii transmit data 1. ttl o pa3 (3) ph4 (9) pd6 (4) 29 76 99 txd1 mii transmit data 2. ttl o pa2 (3) ph3 (9) pd5 (4) 28 83 98 txd2 ethernet mii transmit data 3. ttl o pc4 (3) ph2 (9) pd4 (4) 25 84 97 txd3 mii transmit enable. ttl o pg5 (3) 40 txen mii transmit error. ttl o pd1 (7) pg7 (3) 11 36 txer uart module 0 receive. when in irda mode, this signal has irda modulation. ttl i pa0 (1) 26 u0rx uart module 0 transmit. when in irda mode, this signal has irda modulation. ttl o pa1 (1) 27 u0tx july 03, 2014 1236 texas instruments-production data signal tables table 24-3. signals by signal name (continued) description buffer type a pin type pin mux / pin assignment pin number pin name uart module 1 clear to send modem flow control input signal. ttl i pe6 (9) pd0 (9) pa6 (9) pj3 (9) 2 10 34 50 u1cts uart module 1 data carrier detect modem status input signal. ttl i pe7 (9) pd1 (9) pa7 (9) pj4 (9) 1 11 35 52 u1dcd uart module 1 data set ready modem output control line. ttl i pf0 (9) pj5 (9) 47 53 u1dsr uart module 1 data terminal ready modem status input signal. ttl o pg5 (10) pj7 (9) pd7 (9) 40 55 100 u1dtr uart module 1 ring indicator modem status input signal. ttl i pg6 (10) pg4 (10) pd4 (9) 37 41 97 u1ri uart module 1 request to send modem flow control output line. ttl o pf6 (10) pj6 (9) pf1 (9) 43 54 61 u1rts uart module 1 receive. when in irda mode, this signal has irda modulation. ttl i pd0 (5) pd2 (1) pc6 (5) pa0 (9) pb0 (5) pb4 (7) 10 12 23 26 66 92 u1rx uart module 1 transmit. when in irda mode, this signal has irda modulation. ttl o pd1 (5) pd3 (1) pc7 (5) pa1 (9) pb1 (5) pb5 (7) 11 13 22 27 67 91 u1tx uart module 2 receive. when in irda mode, this signal has irda modulation. ttl i pd0 (4) pg0 (1) pb4 (4) pd5 (9) 10 19 92 98 u2rx uart module 2 transmit. when in irda mode, this signal has irda modulation. ttl o pe4 (5) pd1 (4) pg1 (1) pd6 (9) 6 11 18 99 u2tx bidirectional differential data pin (d- per usb specification) for usb0. analog i/o fixed 70 usb0dm bidirectional differential data pin (d+ per usb specification) for usb0. analog i/o fixed 71 usb0dp optionally used in host mode to control an external power source to supply power to the usb bus. ttl o pg0 (7) pc5 (6) pa6 (8) pb2 (8) ph3 (4) 19 24 34 72 83 usb0epen this signal senses the state of the usb id signal. the usb phy enables an integrated pull-up, and an external element (usb connector) indicates the initial state of the usb controller (pulled down is the a side of the cable and pulled up is the b side). analog i pb0 66 usb0id 1237 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 24-3. signals by signal name (continued) description buffer type a pin type pin mux / pin assignment pin number pin name optionally used in host mode by an external power source to indicate an error state by that power source. ttl i pc7 (6) pc6 (7) pa7 (8) pb3 (8) pe0 (9) ph4 (4) pj1 (9) 22 23 35 65 74 76 87 usb0pflt 9.1-k resistor (1% precision) used internally for usb analog circuitry. analog o fixed 73 usb0rbias this signal is used during the session request protocol. this signal allows the usb phy to both sense the voltage level of vbus, and pull up vbus momentarily during vbus pulsing. analog i/o pb1 67 usb0vbus positive supply for i/o and some logic. power - fixed 8 20 32 44 56 68 81 93 vdd the positive supply for the analog circuits (adc, analog comparators, etc.). these are separated from vdd to minimize the electrical noise contained on vdd from affecting the analog functions. vdda pins must be supplied with a voltage that meets the specification in table 26-2 on page 1298 , regardless of system implementation. power - fixed 3 vdda positive supply for most of the logic function, including the processor core and most peripherals. the voltage on this pin is 1.3 v and is supplied by the on-chip ldo. the vddc pins should only be connected to the ldo pin and an external capacitor as specified in table 26-6 on page 1303 . power - fixed 38 88 vddc this input provides a reference voltage used to specify the input voltage at which the adc converts to a maximum value. in other words, the voltage that is applied to vrefa is the voltage with which an ainn signal is converted to 4095. the vrefa input is limited to the range specified in table 26-23 on page 1314 . analog i pb6 90 vrefa a. the ttl designation indicates the pin has ttl-compatible voltage levels. july 03, 2014 1238 texas instruments-production data signal tables 24.1.3 signals by function, except for gpio table 24-4. signals by function, except for gpio description buffer type a pin type pin number pin name function analog-to-digital converter input 0. analog i 1 ain0 adc analog-to-digital converter input 1. analog i 2 ain1 analog-to-digital converter input 2. analog i 5 ain2 analog-to-digital converter input 3. analog i 6 ain3 analog-to-digital converter input 4. analog i 100 ain4 analog-to-digital converter input 5. analog i 99 ain5 analog-to-digital converter input 6. analog i 98 ain6 analog-to-digital converter input 7. analog i 97 ain7 analog-to-digital converter input 8. analog i 96 ain8 analog-to-digital converter input 9. analog i 95 ain9 analog-to-digital converter input 10. analog i 92 ain10 analog-to-digital converter input 11. analog i 91 ain11 analog-to-digital converter input 12. analog i 13 ain12 analog-to-digital converter input 13. analog i 12 ain13 analog-to-digital converter input 14. analog i 11 ain14 analog-to-digital converter input 15. analog i 10 ain15 this input provides a reference voltage used to specify the input voltage at which the adc converts to a maximum value. in other words, the voltage that is applied to vrefa is the voltage with which an ainn signal is converted to 4095. the vrefa input is limited to the range specified in table 26-23 on page 1314 . analog i 90 vrefa analog comparator 0 positive input. analog i 90 c0+ analog comparators analog comparator 0 negative input. analog i 92 c0- analog comparator 0 output. ttl o 24 58 90 91 100 c0o analog comparator 1 positive input. analog i 24 c1+ analog comparator 1 negative input. analog i 91 c1- analog comparator 1 output. ttl o 2 22 24 46 84 c1o analog comparator 2 positive input. analog i 23 c2+ analog comparator 2 negative input. analog i 22 c2- analog comparator 2 output. ttl o 1 23 43 c2o 1239 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 24-4. signals by function, except for gpio (continued) description buffer type a pin type pin number pin name function can module 0 receive. ttl i 10 30 34 92 can0rx controller area network can module 0 transmit. ttl o 11 31 35 91 can0tx can module 1 receive. ttl i 47 can1rx can module 1 transmit. ttl o 61 can1tx mii collision detect. ttl i 17 col ethernet mii carrier sense. ttl i 16 crs mii management clock. ttl o 59 mdc mdio of the ethernet phy. od i/o 58 mdio phy interrupt. ttl i 60 phyint mii receive clock. 25 mhz in 100base-tx mode. 2.5 mhz in 10base-t mode. ttl i 15 34 47 rxck mii receive data 0. ttl i 6 41 rxd0 mii receive data 1. ttl i 42 89 rxd1 mii receive data 2. ttl i 43 rxd2 mii receive data 3. ttl i 46 rxd3 mii receive data valid. ttl i 10 31 62 rxdv mii receive error. ttl i 14 35 61 rxer mii transmit clock. 25 mhz in 100base-tx mode. 2.5 mhz in 10base-t mode. ttl i 37 txck mii transmit data 0. ttl o 30 63 100 txd0 ethernet mii transmit data 1. ttl o 29 76 99 txd1 mii transmit data 2. ttl o 28 83 98 txd2 ethernet mii transmit data 3. ttl o 25 84 97 txd3 mii transmit enable. ttl o 40 txen mii transmit error. ttl o 11 36 txer july 03, 2014 1240 texas instruments-production data signal tables table 24-4. signals by function, except for gpio (continued) description buffer type a pin type pin number pin name function epi module 0 signal 0. ttl i/o 83 epi0s0 external peripheral interface epi module 0 signal 1. ttl i/o 84 epi0s1 epi module 0 signal 2. ttl i/o 25 epi0s2 epi module 0 signal 3. ttl i/o 24 epi0s3 epi module 0 signal 4. ttl i/o 23 epi0s4 epi module 0 signal 5. ttl i/o 22 epi0s5 epi module 0 signal 6. ttl i/o 86 epi0s6 epi module 0 signal 7. ttl i/o 85 epi0s7 epi module 0 signal 8. ttl i/o 74 epi0s8 epi module 0 signal 9. ttl i/o 75 epi0s9 epi module 0 signal 10. ttl i/o 76 epi0s10 epi module 0 signal 11. ttl i/o 63 epi0s11 epi module 0 signal 12. ttl i/o 42 58 epi0s12 epi module 0 signal 13. ttl i/o 19 epi0s13 epi module 0 signal 14. ttl i/o 18 epi0s14 epi module 0 signal 15. ttl i/o 41 46 epi0s15 epi module 0 signal 16. ttl i/o 14 epi0s16 epi module 0 signal 17. ttl i/o 87 epi0s17 epi module 0 signal 18. ttl i/o 39 epi0s18 epi module 0 signal 19. ttl i/o 50 97 epi0s19 epi module 0 signal 20. ttl i/o 12 epi0s20 epi module 0 signal 21. ttl i/o 13 epi0s21 epi module 0 signal 22. ttl i/o 91 epi0s22 epi module 0 signal 23. ttl i/o 92 epi0s23 epi module 0 signal 24. ttl i/o 95 epi0s24 epi module 0 signal 25. ttl i/o 96 epi0s25 epi module 0 signal 26. ttl i/o 62 epi0s26 epi module 0 signal 27. ttl i/o 15 epi0s27 epi module 0 signal 28. ttl i/o 52 98 epi0s28 epi module 0 signal 29. ttl i/o 53 99 epi0s29 epi module 0 signal 30. ttl i/o 54 100 epi0s30 epi module 0 signal 31. ttl i/o 36 epi0s31 1241 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 24-4. signals by function, except for gpio (continued) description buffer type a pin type pin number pin name function capture/compare/pwm 0. ttl i/o 13 22 23 39 55 58 66 72 91 97 ccp0 general-purpose timers capture/compare/pwm 1. ttl i/o 24 25 34 43 54 67 90 96 100 ccp1 capture/compare/pwm 2. ttl i/o 6 11 25 46 53 67 75 91 95 98 ccp2 capture/compare/pwm 3. ttl i/o 6 23 24 35 41 61 72 74 97 ccp3 capture/compare/pwm 4. ttl i/o 22 25 35 42 52 95 98 ccp4 capture/compare/pwm 5. ttl i/o 5 12 25 36 40 90 91 ccp5 capture/compare/pwm 6. ttl i/o ccp6 july 03, 2014 1242 texas instruments-production data signal tables table 24-4. signals by function, except for gpio (continued) description buffer type a pin type pin number pin name function 10 12 50 75 86 91 capture/compare/pwm 7. ttl i/o 11 13 85 90 96 ccp7 i 2 c module 0 clock. od i/o 72 i2c0scl i2c i 2 c module 0 data. od i/o 65 i2c0sda i 2 c module 1 clock. od i/o 14 19 26 34 i2c1scl i 2 c module 1 data. od i/o 18 27 35 87 i2c1sda i 2 s module 0 receive master clock. ttl i/o 16 29 98 i2s0rxmclk i2s i 2 s module 0 receive clock. ttl i/o 10 40 i2s0rxsck i 2 s module 0 receive data. ttl i/o 17 28 97 i2s0rxsd i 2 s module 0 receive word select. ttl i/o 11 37 i2s0rxws i 2 s module 0 transmit master clock. ttl i/o 43 61 i2s0txmclk i 2 s module 0 transmit clock. ttl i/o 30 90 99 i2s0txsck i 2 s module 0 transmit data. ttl i/o 5 47 i2s0txsd i 2 s module 0 transmit word select. ttl i/o 6 31 100 i2s0txws jtag/swd clk. ttl i 80 swclk jtag/swd/swo jtag tms and swdio. ttl i/o 79 swdio jtag tdo and swo. ttl o 77 swo jtag/swd clk. ttl i 80 tck jtag tdi. ttl i 78 tdi jtag tdo and swo. ttl o 77 tdo jtag tms and swdio. ttl i 79 tms 1243 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 24-4. signals by function, except for gpio (continued) description buffer type a pin type pin number pin name function pwm fault 0. ttl i 6 16 17 39 58 65 75 83 99 fault0 pwm pwm fault 1. ttl i 37 40 41 42 90 fault1 pwm fault 2. ttl i 16 24 63 fault2 pwm fault 3. ttl i 65 84 fault3 pwm 0. this signal is controlled by pwm generator 0. ttl o 10 14 17 19 34 47 pwm0 pwm 1. this signal is controlled by pwm generator 0. ttl o 11 16 18 35 61 87 pwm1 pwm 2. this signal is controlled by pwm generator 1. ttl o 12 60 66 86 pwm2 pwm 3. this signal is controlled by pwm generator 1. ttl o 13 59 67 85 pwm3 pwm 4. this signal is controlled by pwm generator 2. ttl o 2 19 28 34 60 62 74 86 pwm4 pwm 5. this signal is controlled by pwm generator 2. ttl o 1 15 18 29 35 59 75 85 pwm5 july 03, 2014 1244 texas instruments-production data signal tables table 24-4. signals by function, except for gpio (continued) description buffer type a pin type pin number pin name function pwm6 pwm 6. this signal is controlled by pwm generator 3. ttl o 25 30 37 41 pwm 7. this signal is controlled by pwm generator 3. ttl o 23 31 36 40 pwm7 ground reference for logic and i/o pins. power - 9 21 33 45 57 69 82 94 gnd power the ground reference for the analog circuits (adc, analog comparators, etc.). these are separated from gnd to minimize the electrical noise contained on vdd from affecting the analog functions. power - 4 gnda low drop-out regulator output voltage. this pin requires an external capacitor between the pin and gnd of 1 f or greater. the ldo pin must also be connected to the vddc pins at the board level in addition to the decoupling capacitor(s). power - 7 ldo positive supply for i/o and some logic. power - 8 20 32 44 56 68 81 93 vdd the positive supply for the analog circuits (adc, analog comparators, etc.). these are separated from vdd to minimize the electrical noise contained on vdd from affecting the analog functions. vdda pins must be supplied with a voltage that meets the specification in table 26-2 on page 1298 , regardless of system implementation. power - 3 vdda positive supply for most of the logic function, including the processor core and most peripherals. the voltage on this pin is 1.3 v and is supplied by the on-chip ldo. the vddc pins should only be connected to the ldo pin and an external capacitor as specified in table 26-6 on page 1303 . power - 38 88 vddc 1245 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 24-4. signals by function, except for gpio (continued) description buffer type a pin type pin number pin name function qei module 0 index. ttl i 10 40 72 90 92 100 idx0 qei qei module 1 index. ttl i 17 61 84 idx1 qei module 0 phase a. ttl i 11 25 43 95 pha0 qei module 1 phase a. ttl i 37 96 pha1 qei module 0 phase b. ttl i 22 23 42 47 83 96 phb0 qei module 1 phase b. ttl i 11 36 95 phb1 ssi module 0 clock. ttl i/o 28 ssi0clk ssi ssi module 0 frame signal. ttl i/o 29 ssi0fss ssi module 0 receive. ttl i 30 ssi0rx ssi module 0 transmit. ttl o 31 ssi0tx ssi module 1 clock. ttl i/o 60 74 76 ssi1clk ssi module 1 frame signal. ttl i/o 59 63 75 ssi1fss ssi module 1 receive. ttl i 58 62 95 ssi1rx ssi module 1 transmit. ttl o 15 46 96 ssi1tx non-maskable interrupt. ttl i 89 nmi system control & clocks main oscillator crystal input or an external clock reference input. analog i 48 osc0 main oscillator crystal output. leave unconnected when using a single-ended clock source. analog o 49 osc1 system reset input. ttl i 64 rst july 03, 2014 1246 texas instruments-production data signal tables table 24-4. signals by function, except for gpio (continued) description buffer type a pin type pin number pin name function uart module 0 receive. when in irda mode, this signal has irda modulation. ttl i 26 u0rx uart uart module 0 transmit. when in irda mode, this signal has irda modulation. ttl o 27 u0tx uart module 1 clear to send modem flow control input signal. ttl i 2 10 34 50 u1cts uart module 1 data carrier detect modem status input signal. ttl i 1 11 35 52 u1dcd uart module 1 data set ready modem output control line. ttl i 47 53 u1dsr uart module 1 data terminal ready modem status input signal. ttl o 40 55 100 u1dtr uart module 1 ring indicator modem status input signal. ttl i 37 41 97 u1ri uart module 1 request to send modem flow control output line. ttl o 43 54 61 u1rts uart module 1 receive. when in irda mode, this signal has irda modulation. ttl i 10 12 23 26 66 92 u1rx uart module 1 transmit. when in irda mode, this signal has irda modulation. ttl o 11 13 22 27 67 91 u1tx uart module 2 receive. when in irda mode, this signal has irda modulation. ttl i 10 19 92 98 u2rx uart module 2 transmit. when in irda mode, this signal has irda modulation. ttl o 6 11 18 99 u2tx 1247 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 24-4. signals by function, except for gpio (continued) description buffer type a pin type pin number pin name function bidirectional differential data pin (d- per usb specification) for usb0. analog i/o 70 usb0dm usb bidirectional differential data pin (d+ per usb specification) for usb0. analog i/o 71 usb0dp optionally used in host mode to control an external power source to supply power to the usb bus. ttl o 19 24 34 72 83 usb0epen this signal senses the state of the usb id signal. the usb phy enables an integrated pull-up, and an external element (usb connector) indicates the initial state of the usb controller (pulled down is the a side of the cable and pulled up is the b side). analog i 66 usb0id optionally used in host mode by an external power source to indicate an error state by that power source. ttl i 22 23 35 65 74 76 87 usb0pflt 9.1-k resistor (1% precision) used internally for usb analog circuitry. analog o 73 usb0rbias this signal is used during the session request protocol. this signal allows the usb phy to both sense the voltage level of vbus, and pull up vbus momentarily during vbus pulsing. analog i/o 67 usb0vbus a. the ttl designation indicates the pin has ttl-compatible voltage levels. 24.1.4 gpio pins and alternate functions table 24-5. gpio pins and alternate functions digital function (gpiopctl pmcx bit field encoding) a analog function pinio 11 10 9 8 7 6 5 4 3 2 1 -- u1rx i2c1scl ------ u0rx -26 pa0 -- u1tx i2c1sda ------ u0tx -27 pa1 -- i2s0rxsd ---- pwm4 txd2 - ssi0clk -28 pa2 -- i2s0rxmclk ---- pwm5 txd1 - ssi0fss -29 pa3 -- i2s0txsck --- can0rx pwm6 txd0 - ssi0rx -30 pa4 -- i2s0txws --- can0tx pwm7 rxdv - ssi0tx -31 pa5 -- u1cts usb0epen - can0rx pwm4 pwm0 rxck ccp1 i2c1scl -34 pa6 -- u1dcd usb0pflt ccp3 can0tx pwm5 pwm1 rxer ccp4 i2c1sda -35 pa7 ------ u1rx -- pwm2 ccp0 usb0id 66 pb0 ------ u1tx ccp1 - pwm3 ccp2 usb0vbus 67 pb1 --- usb0epen -- ccp0 ccp3 - idx0 i2c0scl -72 pb2 --- usb0pflt --- fault3 - fault0 i2c0sda -65 pb3 --- epi0s23 u1rx idx0 can0rx u2rx --- ain10 c0- 92 pb4 july 03, 2014 1248 texas instruments-production data signal tables table 24-5. gpio pins and alternate functions (continued) digital function (gpiopctl pmcx bit field encoding) a analog function pinio 11 10 9 8 7 6 5 4 3 2 1 --- epi0s22 u1tx ccp2 can0tx ccp0 ccp6 ccp5 c0o ain11 c1- 91 pb5 -- i2s0txsck -- ccp5 idx0 fault1 c0o ccp7 ccp1 vrefa c0+ 90 pb6 ---- rxd1 -- nmi --- -89 pb7 -------- tck swclk -- -80 pc0 -------- tms swdio -- -79 pc1 -------- tdi -- -78 pc2 -------- tdo swo -- -77 pc3 -- ccp1 epi0s2 - ccp4 ccp2 pwm6 txd3 pha0 ccp5 -25 pc4 --- epi0s3 - usb0epen ccp3 fault2 c0o c1o ccp1 c1+ 24 pc5 --- epi0s4 usb0pflt ccp0 u1rx pwm7 c2o phb0 ccp3 c2+ 23 pc6 --- epi0s5 c1o usb0pflt u1tx ccp0 - phb0 ccp4 c2- 22 pc7 -- u1cts i2s0rxsck rxdv ccp6 u1rx u2rx idx0 can0rx pwm0 ain15 10 pd0 phb1 ccp2 u1dcd i2s0rxws txer ccp7 u1tx u2tx pha0 can0tx pwm1 ain14 11 pd1 --- epi0s20 --- ccp5 pwm2 ccp6 u1rx ain13 12 pd2 --- epi0s21 --- ccp0 pwm3 ccp7 u1tx ain12 13 pd3 - epi0s19 u1ri i2s0rxsd --- txd3 - ccp3 ccp0 ain7 97 pd4 - epi0s28 u2rx i2s0rxmclk --- txd2 - ccp4 ccp2 ain6 98 pd5 - epi0s29 u2tx i2s0txsck --- txd1 -- fault0 ain5 99 pd6 - epi0s30 u1dtr i2s0txws --- txd0 ccp1 c0o idx0 ain4 100 pd7 -- usb0pflt epi0s8 ---- ccp3 ssi1clk pwm4 -74 pe0 --- epi0s9 -- ccp6 ccp2 fault0 ssi1fss pwm5 -75 pe1 --- epi0s24 -- ccp2 pha0 phb1 ssi1rx ccp4 ain9 95 pe2 --- epi0s25 -- ccp7 phb0 pha1 ssi1tx ccp1 ain8 96 pe3 -- i2s0txws - rxd0 ccp2 u2tx fault0 -- ccp3 ain3 6 pe4 -- i2s0txsd ------- ccp5 ain2 5 pe5 -- u1cts ------ c1o pwm4 ain1 2 pe6 -- u1dcd ------ c2o pwm5 ain0 1 pe7 -- u1dsr i2s0txsd --- rxck pwm0 phb0 can1rx -47 pf0 - ccp3 u1rts i2s0txmclk --- rxer pwm1 idx1 can1tx -61 pf1 -- ssi1clk ---- pwm2 phyint pwm4 - -60 pf2 -- ssi1fss ---- pwm3 mdc pwm5 - -59 pf3 -- ssi1rx epi0s12 --- fault0 mdio c0o ccp0 -58 pf4 -- ssi1tx epi0s15 ---- rxd3 c1o ccp2 -46 pf5 - u1rts i2s0txmclk ---- pha0 rxd2 c2o ccp1 -43 pf6 -- fault1 epi0s12 --- phb0 rxd1 - ccp4 -42 pf7 --- epi0s13 usb0epen -- pwm4 i2c1scl pwm0 u2rx -19 pg0 --- epi0s14 --- pwm5 i2c1sda pwm1 u2tx -18 pg1 1249 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 24-5. gpio pins and alternate functions (continued) digital function (gpiopctl pmcx bit field encoding) a analog function pinio 11 10 9 8 7 6 5 4 3 2 1 -- i2s0rxsd idx1 --- fault0 col - pwm0 -17 pg2 -- i2s0rxmclk fault0 --- fault2 crs - pwm1 -16 pg3 - u1ri pwm6 epi0s15 --- fault1 rxd0 - ccp3 -41 pg4 - u1dtr i2s0rxsck pwm7 -- fault1 idx0 txen - ccp5 -40 pg5 - u1ri i2s0rxws fault1 --- pwm6 txck - pha1 -37 pg6 -- epi0s31 ccp5 --- pwm7 txer - phb1 -36 pg7 -- pwm4 epi0s6 ----- pwm2 ccp6 -86 ph0 -- pwm5 epi0s7 ----- pwm3 ccp7 -85 ph1 -- txd3 epi0s1 --- fault3 - c1o idx1 -84 ph2 -- txd2 epi0s0 --- usb0epen - fault0 phb0 -83 ph3 ssi1clk - txd1 epi0s10 --- usb0pflt --- -76 ph4 ssi1fss fault2 txd0 epi0s11 ------- -63 ph5 ssi1rx pwm4 rxdv epi0s26 ------- -62 ph6 ssi1tx pwm5 - epi0s27 ---- rxck -- -15 ph7 i2c1scl pwm0 - epi0s16 ---- rxer -- -14 pj0 i2c1sda pwm1 usb0pflt epi0s17 ------- -87 pj1 - fault0 ccp0 epi0s18 ------- -39 pj2 - ccp6 u1cts epi0s19 ------- -50 pj3 - ccp4 u1dcd epi0s28 ------- -52 pj4 - ccp2 u1dsr epi0s29 ------- -53 pj5 - ccp1 u1rts epi0s30 ------- -54 pj6 - ccp0 u1dtr -------- -55 pj7 a. the digital signals that are shaded gray are the power-on default values for the corresponding gpio pin. july 03, 2014 1250 texas instruments-production data signal tables 24.1.5 possible pin assignments for alternate functions table 24-6. possible pin assignments for alternate functions gpio function alternate function # of possible assignments pe7 ain0 one pe6 ain1 pb4 ain10 pb5 ain11 pd3 ain12 pd2 ain13 pd1 ain14 pd0 ain15 pe5 ain2 pe4 ain3 pd7 ain4 pd6 ain5 pd5 ain6 pd4 ain7 pe3 ain8 pe2 ain9 pb6 c0+ pb4 c0- pc5 c1+ pb5 c1- pc6 c2+ pc7 c2- pf0 can1rx pf1 can1tx pg2 col pg3 crs ph3 epi0s0 ph2 epi0s1 ph4 epi0s10 ph5 epi0s11 pg0 epi0s13 pg1 epi0s14 pj0 epi0s16 pj1 epi0s17 pj2 epi0s18 pc4 epi0s2 pd2 epi0s20 pd3 epi0s21 pb5 epi0s22 1251 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 24-6. possible pin assignments for alternate functions (continued) gpio function alternate function # of possible assignments epi0s23 pb4 pe2 epi0s24 pe3 epi0s25 ph6 epi0s26 ph7 epi0s27 pc5 epi0s3 pg7 epi0s31 pc6 epi0s4 pc7 epi0s5 ph0 epi0s6 ph1 epi0s7 pe0 epi0s8 pe1 epi0s9 pb2 i2c0scl pb3 i2c0sda pf3 mdc pf4 mdio pb7 nmi pf2 phyint pf6 rxd2 pf5 rxd3 pa2 ssi0clk pa3 ssi0fss pa4 ssi0rx pa5 ssi0tx pc0 swclk pc1 swdio pc3 swo pc0 tck pc2 tdi pc3 tdo pc1 tms pg6 txck pg5 txen pa0 u0rx pa1 u0tx pb0 usb0id pb1 usb0vbus pb6 vrefa july 03, 2014 1252 texas instruments-production data signal tables table 24-6. possible pin assignments for alternate functions (continued) gpio function alternate function # of possible assignments pf4 pf7 epi0s12 two pf5 pg4 epi0s15 pd4 pj3 epi0s19 pd5 pj4 epi0s28 pd6 pj5 epi0s29 pd7 pj6 epi0s30 pb3 ph2 fault3 pd0 pg5 i2s0rxsck pd1 pg6 i2s0rxws pf1 pf6 i2s0txmclk pe5 pf0 i2s0txsd pe3 pg6 pha1 pe4 pg4 rxd0 pb7 pf7 rxd1 pd1 pg7 txer pf0 pj5 u1dsr pc6 pe7 pf6 c2o three pc5 pg3 ph5 fault2 pa3 pd5 pg3 i2s0rxmclk pa2 pd4 pg2 i2s0rxsd pa4 pb6 pd6 i2s0txsck pa5 pd7 pe4 i2s0txws pf1 pg2 ph2 idx1 pd1 pe2 pg7 phb1 pa6 pf0 ph7 rxck pa5 pd0 ph6 rxdv pa7 pf1 pj0 rxer pe0 pf2 ph4 ssi1clk pe1 pf3 ph5 ssi1fss pe2 pf4 ph6 ssi1rx pe3 pf5 ph7 ssi1tx pa4 pd7 ph5 txd0 pa3 pd6 ph4 txd1 pa2 pd5 ph3 txd2 pc4 pd4 ph2 txd3 pd7 pg5 pj7 u1dtr pd4 pg4 pg6 u1ri pf1 pf6 pj6 u1rts 1253 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 24-6. possible pin assignments for alternate functions (continued) gpio function alternate function # of possible assignments pa4 pa6 pb4 pd0 can0rx four pa5 pa7 pb5 pd1 can0tx pa0 pa6 pg0 pj0 i2c1scl pa1 pa7 pg1 pj1 i2c1sda pb0 pd2 pf2 ph0 pwm2 pb1 pd3 pf3 ph1 pwm3 pa4 pc4 pg4 pg6 pwm6 pa5 pc6 pg5 pg7 pwm7 pc4 pd1 pe2 pf6 pha0 pa6 pd0 pe6 pj3 u1cts pa7 pd1 pe7 pj4 u1dcd pb4 pd0 pd5 pg0 u2rx pd1 pd6 pe4 pg1 u2tx pb5 pb6 pc5 pd7 pf4 c0o five pc5 pc7 pe6 pf5 ph2 c1o pb6 pd1 pd3 pe3 ph1 ccp7 pb6 pf7 pg4 pg5 pg6 fault1 pa6 pb2 pc5 pg0 ph3 usb0epen pb5 pd0 pd2 pe1 ph0 pj3 ccp6 six pb2 pb4 pb6 pd0 pd7 pg5 idx0 pa6 pd0 pf0 pg0 pg2 pj0 pwm0 pa7 pd1 pf1 pg1 pg3 pj1 pwm1 pc6 pc7 pe3 pf0 pf7 ph3 phb0 pa0 pb0 pb4 pc6 pd0 pd2 u1rx pa1 pb1 pb5 pc7 pd1 pd3 u1tx pa7 pc4 pc7 pd5 pe2 pf7 pj4 ccp4 seven pb5 pb6 pc4 pd2 pe5 pg5 pg7 ccp5 pa7 pb3 pc6 pc7 pe0 ph4 pj1 usb0pflt pa2 pa6 pe0 pe6 pf2 pg0 ph0 ph6 pwm4 eight pa3 pa7 pe1 pe7 pf3 pg1 ph1 ph7 pwm5 pa6 pb1 pb6 pc4 pc5 pd7 pe3 pf6 pj6 ccp1 nine pa7 pb2 pc5 pc6 pd4 pe0 pe4 pf1 pg4 ccp3 pb3 pd6 pe1 pe4 pf4 pg2 pg3 ph3 pj2 fault0 pb0 pb2 pb5 pc6 pc7 pd3 pd4 pf4 pj2 pj7 ccp0 ten pb1 pb5 pc4 pd1 pd5 pe1 pe2 pe4 pf5 pj5 ccp2 july 03, 2014 1254 texas instruments-production data signal tables 24.2 108-ball bga package pin tables 24.2.1 signals by pin number table 24-7. signals by pin number description buffer type a pin type pin name pin number gpio port e bit 6. ttl i/o pe6 a1 analog-to-digital converter input 1. analog i ain1 analog comparator 1 output. ttl o c1o pwm 4. this signal is controlled by pwm generator 2. ttl o pwm4 uart module 1 clear to send modem flow control input signal. ttl i u1cts gpio port d bit 7. ttl i/o pd7 a2 analog-to-digital converter input 4. analog i ain4 analog comparator 0 output. ttl o c0o capture/compare/pwm 1. ttl i/o ccp1 epi module 0 signal 30. ttl i/o epi0s30 i 2 s module 0 transmit word select. ttl i/o i2s0txws qei module 0 index. ttl i idx0 mii transmit data 0. ttl o txd0 uart module 1 data terminal ready modem status input signal. ttl o u1dtr gpio port d bit 6. ttl i/o pd6 a3 analog-to-digital converter input 5. analog i ain5 epi module 0 signal 29. ttl i/o epi0s29 pwm fault 0. ttl i fault0 i 2 s module 0 transmit clock. ttl i/o i2s0txsck ethernet mii transmit data 1. ttl o txd1 uart module 2 transmit. when in irda mode, this signal has irda modulation. ttl o u2tx gpio port e bit 2. ttl i/o pe2 a4 analog-to-digital converter input 9. analog i ain9 capture/compare/pwm 2. ttl i/o ccp2 capture/compare/pwm 4. ttl i/o ccp4 epi module 0 signal 24. ttl i/o epi0s24 qei module 0 phase a. ttl i pha0 qei module 1 phase b. ttl i phb1 ssi module 1 receive. ttl i ssi1rx the ground reference for the analog circuits (adc, analog comparators, etc.). these are separated from gnd to minimize the electrical noise contained on vdd from affecting the analog functions. power - gnda a5 1255 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 24-7. signals by pin number (continued) description buffer type a pin type pin name pin number gpio port b bit 4. ttl i/o pb4 a6 analog-to-digital converter input 10. analog i ain10 analog comparator 0 negative input. analog i c0- can module 0 receive. ttl i can0rx epi module 0 signal 23. ttl i/o epi0s23 qei module 0 index. ttl i idx0 uart module 1 receive. when in irda mode, this signal has irda modulation. ttl i u1rx uart module 2 receive. when in irda mode, this signal has irda modulation. ttl i u2rx gpio port b bit 6. ttl i/o pb6 a7 analog comparator 0 positive input. analog i c0+ analog comparator 0 output. ttl o c0o capture/compare/pwm 1. ttl i/o ccp1 capture/compare/pwm 5. ttl i/o ccp5 capture/compare/pwm 7. ttl i/o ccp7 pwm fault 1. ttl i fault1 i 2 s module 0 transmit clock. ttl i/o i2s0txsck qei module 0 index. ttl i idx0 this input provides a reference voltage used to specify the input voltage at which the adc converts to a maximum value. in other words, the voltage that is applied to vrefa is the voltage with which an ainn signal is converted to 4095. the vrefa input is limited to the range specified in table 26-23 on page 1314 . analog i vrefa gpio port b bit 7. ttl i/o pb7 a8 non-maskable interrupt. ttl i nmi mii receive data 1. ttl i rxd1 gpio port c bit 0. ttl i/o pc0 a9 jtag/swd clk. ttl i swclk jtag/swd clk. ttl i tck gpio port c bit 3. ttl i/o pc3 a10 jtag tdo and swo. ttl o swo jtag tdo and swo. ttl o tdo gpio port b bit 2. ttl i/o pb2 a11 capture/compare/pwm 0. ttl i/o ccp0 capture/compare/pwm 3. ttl i/o ccp3 i 2 c module 0 clock. od i/o i2c0scl qei module 0 index. ttl i idx0 optionally used in host mode to control an external power source to supply power to the usb bus. ttl o usb0epen july 03, 2014 1256 texas instruments-production data signal tables table 24-7. signals by pin number (continued) description buffer type a pin type pin name pin number gpio port e bit 1. ttl i/o pe1 a12 capture/compare/pwm 2. ttl i/o ccp2 capture/compare/pwm 6. ttl i/o ccp6 epi module 0 signal 9. ttl i/o epi0s9 pwm fault 0. ttl i fault0 pwm 5. this signal is controlled by pwm generator 2. ttl o pwm5 ssi module 1 frame signal. ttl i/o ssi1fss gpio port e bit 7. ttl i/o pe7 b1 analog-to-digital converter input 0. analog i ain0 analog comparator 2 output. ttl o c2o pwm 5. this signal is controlled by pwm generator 2. ttl o pwm5 uart module 1 data carrier detect modem status input signal. ttl i u1dcd gpio port e bit 4. ttl i/o pe4 b2 analog-to-digital converter input 3. analog i ain3 capture/compare/pwm 2. ttl i/o ccp2 capture/compare/pwm 3. ttl i/o ccp3 pwm fault 0. ttl i fault0 i 2 s module 0 transmit word select. ttl i/o i2s0txws mii receive data 0. ttl i rxd0 uart module 2 transmit. when in irda mode, this signal has irda modulation. ttl o u2tx gpio port e bit 5. ttl i/o pe5 b3 analog-to-digital converter input 2. analog i ain2 capture/compare/pwm 5. ttl i/o ccp5 i 2 s module 0 transmit data. ttl i/o i2s0txsd gpio port e bit 3. ttl i/o pe3 b4 analog-to-digital converter input 8. analog i ain8 capture/compare/pwm 1. ttl i/o ccp1 capture/compare/pwm 7. ttl i/o ccp7 epi module 0 signal 25. ttl i/o epi0s25 qei module 1 phase a. ttl i pha1 qei module 0 phase b. ttl i phb0 ssi module 1 transmit. ttl o ssi1tx gpio port d bit 4. ttl i/o pd4 b5 analog-to-digital converter input 7. analog i ain7 capture/compare/pwm 0. ttl i/o ccp0 capture/compare/pwm 3. ttl i/o ccp3 epi module 0 signal 19. ttl i/o epi0s19 i 2 s module 0 receive data. ttl i/o i2s0rxsd ethernet mii transmit data 3. ttl o txd3 uart module 1 ring indicator modem status input signal. ttl i u1ri 1257 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 24-7. signals by pin number (continued) description buffer type a pin type pin name pin number gpio port j bit 1. ttl i/o pj1 b6 epi module 0 signal 17. ttl i/o epi0s17 i 2 c module 1 data. od i/o i2c1sda pwm 1. this signal is controlled by pwm generator 0. ttl o pwm1 optionally used in host mode by an external power source to indicate an error state by that power source. ttl i usb0pflt gpio port b bit 5. ttl i/o pb5 b7 analog-to-digital converter input 11. analog i ain11 analog comparator 0 output. ttl o c0o analog comparator 1 negative input. analog i c1- can module 0 transmit. ttl o can0tx capture/compare/pwm 0. ttl i/o ccp0 capture/compare/pwm 2. ttl i/o ccp2 capture/compare/pwm 5. ttl i/o ccp5 capture/compare/pwm 6. ttl i/o ccp6 epi module 0 signal 22. ttl i/o epi0s22 uart module 1 transmit. when in irda mode, this signal has irda modulation. ttl o u1tx gpio port c bit 2. ttl i/o pc2 b8 jtag tdi. ttl i tdi gpio port c bit 1. ttl i/o pc1 b9 jtag tms and swdio. ttl i/o swdio jtag tms and swdio. ttl i tms gpio port h bit 4. ttl i/o ph4 b10 epi module 0 signal 10. ttl i/o epi0s10 ssi module 1 clock. ttl i/o ssi1clk ethernet mii transmit data 1. ttl o txd1 optionally used in host mode by an external power source to indicate an error state by that power source. ttl i usb0pflt gpio port e bit 0. ttl i/o pe0 b11 capture/compare/pwm 3. ttl i/o ccp3 epi module 0 signal 8. ttl i/o epi0s8 pwm 4. this signal is controlled by pwm generator 2. ttl o pwm4 ssi module 1 clock. ttl i/o ssi1clk optionally used in host mode by an external power source to indicate an error state by that power source. ttl i usb0pflt 9.1-k resistor (1% precision) used internally for usb analog circuitry. analog o usb0rbias b12 no connect. leave the pin electrically unconnected/isolated. - - nc c1 no connect. leave the pin electrically unconnected/isolated. - - nc c2 july 03, 2014 1258 texas instruments-production data signal tables table 24-7. signals by pin number (continued) description buffer type a pin type pin name pin number positive supply for most of the logic function, including the processor core and most peripherals. the voltage on this pin is 1.3 v and is supplied by the on-chip ldo. the vddc pins should only be connected to the ldo pin and an external capacitor as specified in table 26-6 on page 1303 . power - vddc c3 ground reference for logic and i/o pins. power - gnd c4 ground reference for logic and i/o pins. power - gnd c5 gpio port d bit 5. ttl i/o pd5 c6 analog-to-digital converter input 6. analog i ain6 capture/compare/pwm 2. ttl i/o ccp2 capture/compare/pwm 4. ttl i/o ccp4 epi module 0 signal 28. ttl i/o epi0s28 i 2 s module 0 receive master clock. ttl i/o i2s0rxmclk mii transmit data 2. ttl o txd2 uart module 2 receive. when in irda mode, this signal has irda modulation. ttl i u2rx the positive supply for the analog circuits (adc, analog comparators, etc.). these are separated from vdd to minimize the electrical noise contained on vdd from affecting the analog functions. vdda pins must be supplied with a voltage that meets the specification in table 26-2 on page 1298 , regardless of system implementation. power - vdda c7 gpio port h bit 1. ttl i/o ph1 c8 capture/compare/pwm 7. ttl i/o ccp7 epi module 0 signal 7. ttl i/o epi0s7 pwm 3. this signal is controlled by pwm generator 1. ttl o pwm3 pwm 5. this signal is controlled by pwm generator 2. ttl o pwm5 gpio port h bit 0. ttl i/o ph0 c9 capture/compare/pwm 6. ttl i/o ccp6 epi module 0 signal 6. ttl i/o epi0s6 pwm 2. this signal is controlled by pwm generator 1. ttl o pwm2 pwm 4. this signal is controlled by pwm generator 2. ttl o pwm4 gpio port g bit 7. ttl i/o pg7 c10 capture/compare/pwm 5. ttl i/o ccp5 epi module 0 signal 31. ttl i/o epi0s31 pwm 7. this signal is controlled by pwm generator 3. ttl o pwm7 qei module 1 phase b. ttl i phb1 mii transmit error. ttl o txer bidirectional differential data pin (d- per usb specification) for usb0. analog i/o usb0dm c11 bidirectional differential data pin (d+ per usb specification) for usb0. analog i/o usb0dp c12 no connect. leave the pin electrically unconnected/isolated. - - nc d1 no connect. leave the pin electrically unconnected/isolated. - - nc d2 1259 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 24-7. signals by pin number (continued) description buffer type a pin type pin name pin number positive supply for most of the logic function, including the processor core and most peripherals. the voltage on this pin is 1.3 v and is supplied by the on-chip ldo. the vddc pins should only be connected to the ldo pin and an external capacitor as specified in table 26-6 on page 1303 . power - vddc d3 gpio port h bit 3. ttl i/o ph3 d10 epi module 0 signal 0. ttl i/o epi0s0 pwm fault 0. ttl i fault0 qei module 0 phase b. ttl i phb0 mii transmit data 2. ttl o txd2 optionally used in host mode to control an external power source to supply power to the usb bus. ttl o usb0epen gpio port h bit 2. ttl i/o ph2 d11 analog comparator 1 output. ttl o c1o epi module 0 signal 1. ttl i/o epi0s1 pwm fault 3. ttl i fault3 qei module 1 index. ttl i idx1 ethernet mii transmit data 3. ttl o txd3 gpio port b bit 1. this pin is not 5-v tolerant. ttl i/o pb1 d12 capture/compare/pwm 1. ttl i/o ccp1 capture/compare/pwm 2. ttl i/o ccp2 pwm 3. this signal is controlled by pwm generator 1. ttl o pwm3 uart module 1 transmit. when in irda mode, this signal has irda modulation. ttl o u1tx this signal is used during the session request protocol. this signal allows the usb phy to both sense the voltage level of vbus, and pull up vbus momentarily during vbus pulsing. analog i/o usb0vbus no connect. leave the pin electrically unconnected/isolated. - - nc e1 no connect. leave the pin electrically unconnected/isolated. - - nc e2 low drop-out regulator output voltage. this pin requires an external capacitor between the pin and gnd of 1 f or greater. the ldo pin must also be connected to the vddc pins at the board level in addition to the decoupling capacitor(s). power - ldo e3 positive supply for i/o and some logic. power - vdd e10 gpio port b bit 3. ttl i/o pb3 e11 pwm fault 0. ttl i fault0 pwm fault 3. ttl i fault3 i 2 c module 0 data. od i/o i2c0sda optionally used in host mode by an external power source to indicate an error state by that power source. ttl i usb0pflt july 03, 2014 1260 texas instruments-production data signal tables table 24-7. signals by pin number (continued) description buffer type a pin type pin name pin number gpio port b bit 0. this pin is not 5-v tolerant. ttl i/o pb0 e12 capture/compare/pwm 0. ttl i/o ccp0 pwm 2. this signal is controlled by pwm generator 1. ttl o pwm2 uart module 1 receive. when in irda mode, this signal has irda modulation. ttl i u1rx this signal senses the state of the usb id signal. the usb phy enables an integrated pull-up, and an external element (usb connector) indicates the initial state of the usb controller (pulled down is the a side of the cable and pulled up is the b side). analog i usb0id no connect. leave the pin electrically unconnected/isolated. - - nc f1 no connect. leave the pin electrically unconnected/isolated. - - nc f2 gpio port j bit 0. ttl i/o pj0 f3 epi module 0 signal 16. ttl i/o epi0s16 i 2 c module 1 clock. od i/o i2c1scl pwm 0. this signal is controlled by pwm generator 0. ttl o pwm0 mii receive error. ttl i rxer gpio port h bit 5. ttl i/o ph5 f10 epi module 0 signal 11. ttl i/o epi0s11 pwm fault 2. ttl i fault2 ssi module 1 frame signal. ttl i/o ssi1fss mii transmit data 0. ttl o txd0 ground reference for logic and i/o pins. power - gnd f11 ground reference for logic and i/o pins. power - gnd f12 gpio port d bit 0. ttl i/o pd0 g1 analog-to-digital converter input 15. analog i ain15 can module 0 receive. ttl i can0rx capture/compare/pwm 6. ttl i/o ccp6 i 2 s module 0 receive clock. ttl i/o i2s0rxsck qei module 0 index. ttl i idx0 pwm 0. this signal is controlled by pwm generator 0. ttl o pwm0 mii receive data valid. ttl i rxdv uart module 1 clear to send modem flow control input signal. ttl i u1cts uart module 1 receive. when in irda mode, this signal has irda modulation. ttl i u1rx uart module 2 receive. when in irda mode, this signal has irda modulation. ttl i u2rx 1261 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 24-7. signals by pin number (continued) description buffer type a pin type pin name pin number gpio port d bit 1. ttl i/o pd1 g2 analog-to-digital converter input 14. analog i ain14 can module 0 transmit. ttl o can0tx capture/compare/pwm 2. ttl i/o ccp2 capture/compare/pwm 7. ttl i/o ccp7 i 2 s module 0 receive word select. ttl i/o i2s0rxws pwm 1. this signal is controlled by pwm generator 0. ttl o pwm1 qei module 0 phase a. ttl i pha0 qei module 1 phase b. ttl i phb1 mii transmit error. ttl o txer uart module 1 data carrier detect modem status input signal. ttl i u1dcd uart module 1 transmit. when in irda mode, this signal has irda modulation. ttl o u1tx uart module 2 transmit. when in irda mode, this signal has irda modulation. ttl o u2tx gpio port h bit 6. ttl i/o ph6 g3 epi module 0 signal 26. ttl i/o epi0s26 pwm 4. this signal is controlled by pwm generator 2. ttl o pwm4 mii receive data valid. ttl i rxdv ssi module 1 receive. ttl i ssi1rx positive supply for i/o and some logic. power - vdd g10 positive supply for i/o and some logic. power - vdd g11 positive supply for i/o and some logic. power - vdd g12 gpio port d bit 3. ttl i/o pd3 h1 analog-to-digital converter input 12. analog i ain12 capture/compare/pwm 0. ttl i/o ccp0 capture/compare/pwm 7. ttl i/o ccp7 epi module 0 signal 21. ttl i/o epi0s21 pwm 3. this signal is controlled by pwm generator 1. ttl o pwm3 uart module 1 transmit. when in irda mode, this signal has irda modulation. ttl o u1tx gpio port d bit 2. ttl i/o pd2 h2 analog-to-digital converter input 13. analog i ain13 capture/compare/pwm 5. ttl i/o ccp5 capture/compare/pwm 6. ttl i/o ccp6 epi module 0 signal 20. ttl i/o epi0s20 pwm 2. this signal is controlled by pwm generator 1. ttl o pwm2 uart module 1 receive. when in irda mode, this signal has irda modulation. ttl i u1rx july 03, 2014 1262 texas instruments-production data signal tables table 24-7. signals by pin number (continued) description buffer type a pin type pin name pin number gpio port h bit 7. ttl i/o ph7 h3 epi module 0 signal 27. ttl i/o epi0s27 pwm 5. this signal is controlled by pwm generator 2. ttl o pwm5 mii receive clock. 25 mhz in 100base-tx mode. 2.5 mhz in 10base-t mode. ttl i rxck ssi module 1 transmit. ttl o ssi1tx positive supply for i/o and some logic. power - vdd h10 system reset input. ttl i rst h11 gpio port f bit 1. ttl i/o pf1 h12 can module 1 transmit. ttl o can1tx capture/compare/pwm 3. ttl i/o ccp3 i 2 s module 0 transmit master clock. ttl i/o i2s0txmclk qei module 1 index. ttl i idx1 pwm 1. this signal is controlled by pwm generator 0. ttl o pwm1 mii receive error. ttl i rxer uart module 1 request to send modem flow control output line. ttl o u1rts gpio port g bit 2. ttl i/o pg2 j1 mii collision detect. ttl i col pwm fault 0. ttl i fault0 i 2 s module 0 receive data. ttl i/o i2s0rxsd qei module 1 index. ttl i idx1 pwm 0. this signal is controlled by pwm generator 0. ttl o pwm0 gpio port g bit 3. ttl i/o pg3 j2 mii carrier sense. ttl i crs pwm fault 0. ttl i fault0 pwm fault 2. ttl i fault2 i 2 s module 0 receive master clock. ttl i/o i2s0rxmclk pwm 1. this signal is controlled by pwm generator 0. ttl o pwm1 ground reference for logic and i/o pins. power - gnd j3 ground reference for logic and i/o pins. power - gnd j10 gpio port f bit 2. ttl i/o pf2 j11 phy interrupt. ttl i phyint pwm 2. this signal is controlled by pwm generator 1. ttl o pwm2 pwm 4. this signal is controlled by pwm generator 2. ttl o pwm4 ssi module 1 clock. ttl i/o ssi1clk gpio port f bit 3. ttl i/o pf3 j12 mii management clock. ttl o mdc pwm 3. this signal is controlled by pwm generator 1. ttl o pwm3 pwm 5. this signal is controlled by pwm generator 2. ttl o pwm5 ssi module 1 frame signal. ttl i/o ssi1fss 1263 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 24-7. signals by pin number (continued) description buffer type a pin type pin name pin number gpio port g bit 0. ttl i/o pg0 k1 epi module 0 signal 13. ttl i/o epi0s13 i 2 c module 1 clock. od i/o i2c1scl pwm 0. this signal is controlled by pwm generator 0. ttl o pwm0 pwm 4. this signal is controlled by pwm generator 2. ttl o pwm4 uart module 2 receive. when in irda mode, this signal has irda modulation. ttl i u2rx optionally used in host mode to control an external power source to supply power to the usb bus. ttl o usb0epen gpio port g bit 1. ttl i/o pg1 k2 epi module 0 signal 14. ttl i/o epi0s14 i 2 c module 1 data. od i/o i2c1sda pwm 1. this signal is controlled by pwm generator 0. ttl o pwm1 pwm 5. this signal is controlled by pwm generator 2. ttl o pwm5 uart module 2 transmit. when in irda mode, this signal has irda modulation. ttl o u2tx gpio port g bit 4. ttl i/o pg4 k3 capture/compare/pwm 3. ttl i/o ccp3 epi module 0 signal 15. ttl i/o epi0s15 pwm fault 1. ttl i fault1 pwm 6. this signal is controlled by pwm generator 3. ttl o pwm6 mii receive data 0. ttl i rxd0 uart module 1 ring indicator modem status input signal. ttl i u1ri gpio port f bit 7. ttl i/o pf7 k4 capture/compare/pwm 4. ttl i/o ccp4 epi module 0 signal 12. ttl i/o epi0s12 pwm fault 1. ttl i fault1 qei module 0 phase b. ttl i phb0 mii receive data 1. ttl i rxd1 ground reference for logic and i/o pins. power - gnd k5 gpio port j bit 2. ttl i/o pj2 k6 capture/compare/pwm 0. ttl i/o ccp0 epi module 0 signal 18. ttl i/o epi0s18 pwm fault 0. ttl i fault0 positive supply for i/o and some logic. power - vdd k7 positive supply for i/o and some logic. power - vdd k8 positive supply for i/o and some logic. power - vdd k9 ground reference for logic and i/o pins. power - gnd k10 gpio port j bit 4. ttl i/o pj4 k11 capture/compare/pwm 4. ttl i/o ccp4 epi module 0 signal 28. ttl i/o epi0s28 uart module 1 data carrier detect modem status input signal. ttl i u1dcd july 03, 2014 1264 texas instruments-production data signal tables table 24-7. signals by pin number (continued) description buffer type a pin type pin name pin number gpio port j bit 5. ttl i/o pj5 k12 capture/compare/pwm 2. ttl i/o ccp2 epi module 0 signal 29. ttl i/o epi0s29 uart module 1 data set ready modem output control line. ttl i u1dsr gpio port c bit 4. ttl i/o pc4 l1 capture/compare/pwm 1. ttl i/o ccp1 capture/compare/pwm 2. ttl i/o ccp2 capture/compare/pwm 4. ttl i/o ccp4 capture/compare/pwm 5. ttl i/o ccp5 epi module 0 signal 2. ttl i/o epi0s2 pwm 6. this signal is controlled by pwm generator 3. ttl o pwm6 qei module 0 phase a. ttl i pha0 ethernet mii transmit data 3. ttl o txd3 gpio port c bit 7. ttl i/o pc7 l2 analog comparator 1 output. ttl o c1o analog comparator 2 negative input. analog i c2- capture/compare/pwm 0. ttl i/o ccp0 capture/compare/pwm 4. ttl i/o ccp4 epi module 0 signal 5. ttl i/o epi0s5 qei module 0 phase b. ttl i phb0 uart module 1 transmit. when in irda mode, this signal has irda modulation. ttl o u1tx optionally used in host mode by an external power source to indicate an error state by that power source. ttl i usb0pflt gpio port a bit 0. ttl i/o pa0 l3 i 2 c module 1 clock. od i/o i2c1scl uart module 0 receive. when in irda mode, this signal has irda modulation. ttl i u0rx uart module 1 receive. when in irda mode, this signal has irda modulation. ttl i u1rx gpio port a bit 3. ttl i/o pa3 l4 i 2 s module 0 receive master clock. ttl i/o i2s0rxmclk pwm 5. this signal is controlled by pwm generator 2. ttl o pwm5 ssi module 0 frame signal. ttl i/o ssi0fss ethernet mii transmit data 1. ttl o txd1 gpio port a bit 4. ttl i/o pa4 l5 can module 0 receive. ttl i can0rx i 2 s module 0 transmit clock. ttl i/o i2s0txsck pwm 6. this signal is controlled by pwm generator 3. ttl o pwm6 ssi module 0 receive. ttl i ssi0rx mii transmit data 0. ttl o txd0 1265 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 24-7. signals by pin number (continued) description buffer type a pin type pin name pin number gpio port a bit 6. ttl i/o pa6 l6 can module 0 receive. ttl i can0rx capture/compare/pwm 1. ttl i/o ccp1 i 2 c module 1 clock. od i/o i2c1scl pwm 0. this signal is controlled by pwm generator 0. ttl o pwm0 pwm 4. this signal is controlled by pwm generator 2. ttl o pwm4 mii receive clock. 25 mhz in 100base-tx mode. 2.5 mhz in 10base-t mode. ttl i rxck uart module 1 clear to send modem flow control input signal. ttl i u1cts optionally used in host mode to control an external power source to supply power to the usb bus. ttl o usb0epen gpio port g bit 6. ttl i/o pg6 l7 pwm fault 1. ttl i fault1 i 2 s module 0 receive word select. ttl i/o i2s0rxws pwm 6. this signal is controlled by pwm generator 3. ttl o pwm6 qei module 1 phase a. ttl i pha1 mii transmit clock. 25 mhz in 100base-tx mode. 2.5 mhz in 10base-t mode. ttl i txck uart module 1 ring indicator modem status input signal. ttl i u1ri gpio port f bit 5. ttl i/o pf5 l8 analog comparator 1 output. ttl o c1o capture/compare/pwm 2. ttl i/o ccp2 epi module 0 signal 15. ttl i/o epi0s15 mii receive data 3. ttl i rxd3 ssi module 1 transmit. ttl o ssi1tx gpio port f bit 4. ttl i/o pf4 l9 analog comparator 0 output. ttl o c0o capture/compare/pwm 0. ttl i/o ccp0 epi module 0 signal 12. ttl i/o epi0s12 pwm fault 0. ttl i fault0 mdio of the ethernet phy. od i/o mdio ssi module 1 receive. ttl i ssi1rx gpio port j bit 6. ttl i/o pj6 l10 capture/compare/pwm 1. ttl i/o ccp1 epi module 0 signal 30. ttl i/o epi0s30 uart module 1 request to send modem flow control output line. ttl o u1rts main oscillator crystal input or an external clock reference input. analog i osc0 l11 gpio port j bit 7. ttl i/o pj7 l12 capture/compare/pwm 0. ttl i/o ccp0 uart module 1 data terminal ready modem status input signal. ttl o u1dtr july 03, 2014 1266 texas instruments-production data signal tables table 24-7. signals by pin number (continued) description buffer type a pin type pin name pin number gpio port c bit 5. ttl i/o pc5 m1 analog comparator 0 output. ttl o c0o analog comparator 1 positive input. analog i c1+ analog comparator 1 output. ttl o c1o capture/compare/pwm 1. ttl i/o ccp1 capture/compare/pwm 3. ttl i/o ccp3 epi module 0 signal 3. ttl i/o epi0s3 pwm fault 2. ttl i fault2 optionally used in host mode to control an external power source to supply power to the usb bus. ttl o usb0epen gpio port c bit 6. ttl i/o pc6 m2 analog comparator 2 positive input. analog i c2+ analog comparator 2 output. ttl o c2o capture/compare/pwm 0. ttl i/o ccp0 capture/compare/pwm 3. ttl i/o ccp3 epi module 0 signal 4. ttl i/o epi0s4 pwm 7. this signal is controlled by pwm generator 3. ttl o pwm7 qei module 0 phase b. ttl i phb0 uart module 1 receive. when in irda mode, this signal has irda modulation. ttl i u1rx optionally used in host mode by an external power source to indicate an error state by that power source. ttl i usb0pflt gpio port a bit 1. ttl i/o pa1 m3 i 2 c module 1 data. od i/o i2c1sda uart module 0 transmit. when in irda mode, this signal has irda modulation. ttl o u0tx uart module 1 transmit. when in irda mode, this signal has irda modulation. ttl o u1tx gpio port a bit 2. ttl i/o pa2 m4 i 2 s module 0 receive data. ttl i/o i2s0rxsd pwm 4. this signal is controlled by pwm generator 2. ttl o pwm4 ssi module 0 clock. ttl i/o ssi0clk mii transmit data 2. ttl o txd2 gpio port a bit 5. ttl i/o pa5 m5 can module 0 transmit. ttl o can0tx i 2 s module 0 transmit word select. ttl i/o i2s0txws pwm 7. this signal is controlled by pwm generator 3. ttl o pwm7 mii receive data valid. ttl i rxdv ssi module 0 transmit. ttl o ssi0tx 1267 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 24-7. signals by pin number (continued) description buffer type a pin type pin name pin number gpio port a bit 7. ttl i/o pa7 m6 can module 0 transmit. ttl o can0tx capture/compare/pwm 3. ttl i/o ccp3 capture/compare/pwm 4. ttl i/o ccp4 i 2 c module 1 data. od i/o i2c1sda pwm 1. this signal is controlled by pwm generator 0. ttl o pwm1 pwm 5. this signal is controlled by pwm generator 2. ttl o pwm5 mii receive error. ttl i rxer uart module 1 data carrier detect modem status input signal. ttl i u1dcd optionally used in host mode by an external power source to indicate an error state by that power source. ttl i usb0pflt gpio port g bit 5. ttl i/o pg5 m7 capture/compare/pwm 5. ttl i/o ccp5 pwm fault 1. ttl i fault1 i 2 s module 0 receive clock. ttl i/o i2s0rxsck qei module 0 index. ttl i idx0 pwm 7. this signal is controlled by pwm generator 3. ttl o pwm7 mii transmit enable. ttl o txen uart module 1 data terminal ready modem status input signal. ttl o u1dtr gpio port f bit 6. ttl i/o pf6 m8 analog comparator 2 output. ttl o c2o capture/compare/pwm 1. ttl i/o ccp1 i 2 s module 0 transmit master clock. ttl i/o i2s0txmclk qei module 0 phase a. ttl i pha0 mii receive data 2. ttl i rxd2 uart module 1 request to send modem flow control output line. ttl o u1rts gpio port f bit 0. ttl i/o pf0 m9 can module 1 receive. ttl i can1rx i 2 s module 0 transmit data. ttl i/o i2s0txsd pwm 0. this signal is controlled by pwm generator 0. ttl o pwm0 qei module 0 phase b. ttl i phb0 mii receive clock. 25 mhz in 100base-tx mode. 2.5 mhz in 10base-t mode. ttl i rxck uart module 1 data set ready modem output control line. ttl i u1dsr gpio port j bit 3. ttl i/o pj3 m10 capture/compare/pwm 6. ttl i/o ccp6 epi module 0 signal 19. ttl i/o epi0s19 uart module 1 clear to send modem flow control input signal. ttl i u1cts main oscillator crystal output. leave unconnected when using a single-ended clock source. analog o osc1 m11 no connect. leave the pin electrically unconnected/isolated. - - nc m12 a. the ttl designation indicates the pin has ttl-compatible voltage levels. july 03, 2014 1268 texas instruments-production data signal tables 24.2.2 signals by signal name table 24-8. signals by signal name description buffer type a pin type pin mux / pin assignment pin number pin name analog-to-digital converter input 0. analog i pe7 b1 ain0 analog-to-digital converter input 1. analog i pe6 a1 ain1 analog-to-digital converter input 2. analog i pe5 b3 ain2 analog-to-digital converter input 3. analog i pe4 b2 ain3 analog-to-digital converter input 4. analog i pd7 a2 ain4 analog-to-digital converter input 5. analog i pd6 a3 ain5 analog-to-digital converter input 6. analog i pd5 c6 ain6 analog-to-digital converter input 7. analog i pd4 b5 ain7 analog-to-digital converter input 8. analog i pe3 b4 ain8 analog-to-digital converter input 9. analog i pe2 a4 ain9 analog-to-digital converter input 10. analog i pb4 a6 ain10 analog-to-digital converter input 11. analog i pb5 b7 ain11 analog-to-digital converter input 12. analog i pd3 h1 ain12 analog-to-digital converter input 13. analog i pd2 h2 ain13 analog-to-digital converter input 14. analog i pd1 g2 ain14 analog-to-digital converter input 15. analog i pd0 g1 ain15 analog comparator 0 positive input. analog i pb6 a7 c0+ analog comparator 0 negative input. analog i pb4 a6 c0- analog comparator 0 output. ttl o pc5 (3) pf4 (2) pb6 (3) pb5 (1) pd7 (2) m1 l9 a7 b7 a2 c0o analog comparator 1 positive input. analog i pc5 m1 c1+ analog comparator 1 negative input. analog i pb5 b7 c1- analog comparator 1 output. ttl o pe6 (2) pc7 (7) pc5 (2) pf5 (2) ph2 (2) a1 l2 m1 l8 d11 c1o analog comparator 2 positive input. analog i pc6 m2 c2+ analog comparator 2 negative input. analog i pc7 l2 c2- analog comparator 2 output. ttl o pe7 (2) pc6 (3) pf6 (2) b1 m2 m8 c2o can module 0 receive. ttl i pd0 (2) pa4 (5) pa6 (6) pb4 (5) g1 l5 l6 a6 can0rx can module 0 transmit. ttl o pd1 (2) pa5 (5) pa7 (6) pb5 (5) g2 m5 m6 b7 can0tx can module 1 receive. ttl i pf0 (1) m9 can1rx 1269 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 24-8. signals by signal name (continued) description buffer type a pin type pin mux / pin assignment pin number pin name can module 1 transmit. ttl o pf1 (1) h12 can1tx capture/compare/pwm 0. ttl i/o pd3 (4) pc7 (4) pc6 (6) pj2 (9) pj7 (10) pf4 (1) pb0 (1) pb2 (5) pb5 (4) pd4 (1) h1 l2 m2 k6 l12 l9 e12 a11 b7 b5 ccp0 capture/compare/pwm 1. ttl i/o pc5 (1) pc4 (9) pa6 (2) pf6 (1) pj6 (10) pb1 (4) pb6 (1) pe3 (1) pd7 (3) m1 l1 l6 m8 l10 d12 a7 b4 a2 ccp1 capture/compare/pwm 2. ttl i/o pe4 (6) pd1 (10) pc4 (5) pf5 (1) pj5 (10) pb1 (1) pe1 (4) pb5 (6) pe2 (5) pd5 (1) b2 g2 l1 l8 k12 d12 a12 b7 a4 c6 ccp2 capture/compare/pwm 3. ttl i/o pe4 (1) pc6 (1) pc5 (5) pa7 (7) pg4 (1) pf1 (10) pb2 (4) pe0 (3) pd4 (2) b2 m2 m1 m6 k3 h12 a11 b11 b5 ccp3 capture/compare/pwm 4. ttl i/o pc7 (1) pc4 (6) pa7 (2) pf7 (1) pj4 (10) pe2 (1) pd5 (2) l2 l1 m6 k4 k11 a4 c6 ccp4 capture/compare/pwm 5. ttl i/o pe5 (1) pd2 (4) pc4 (1) pg7 (8) pg5 (1) pb6 (6) pb5 (2) b3 h2 l1 c10 m7 a7 b7 ccp5 july 03, 2014 1270 texas instruments-production data signal tables table 24-8. signals by signal name (continued) description buffer type a pin type pin mux / pin assignment pin number pin name capture/compare/pwm 6. ttl i/o pd0 (6) pd2 (2) pj3 (10) pe1 (5) ph0 (1) pb5 (3) g1 h2 m10 a12 c9 b7 ccp6 capture/compare/pwm 7. ttl i/o pd1 (6) pd3 (2) ph1 (1) pb6 (2) pe3 (5) g2 h1 c8 a7 b4 ccp7 mii collision detect. ttl i pg2 (3) j1 col mii carrier sense. ttl i pg3 (3) j2 crs epi module 0 signal 0. ttl i/o ph3 (8) d10 epi0s0 epi module 0 signal 1. ttl i/o ph2 (8) d11 epi0s1 epi module 0 signal 2. ttl i/o pc4 (8) l1 epi0s2 epi module 0 signal 3. ttl i/o pc5 (8) m1 epi0s3 epi module 0 signal 4. ttl i/o pc6 (8) m2 epi0s4 epi module 0 signal 5. ttl i/o pc7 (8) l2 epi0s5 epi module 0 signal 6. ttl i/o ph0 (8) c9 epi0s6 epi module 0 signal 7. ttl i/o ph1 (8) c8 epi0s7 epi module 0 signal 8. ttl i/o pe0 (8) b11 epi0s8 epi module 0 signal 9. ttl i/o pe1 (8) a12 epi0s9 epi module 0 signal 10. ttl i/o ph4 (8) b10 epi0s10 epi module 0 signal 11. ttl i/o ph5 (8) f10 epi0s11 epi module 0 signal 12. ttl i/o pf7 (8) pf4 (8) k4 l9 epi0s12 epi module 0 signal 13. ttl i/o pg0 (8) k1 epi0s13 epi module 0 signal 14. ttl i/o pg1 (8) k2 epi0s14 epi module 0 signal 15. ttl i/o pg4 (8) pf5 (8) k3 l8 epi0s15 epi module 0 signal 16. ttl i/o pj0 (8) f3 epi0s16 epi module 0 signal 17. ttl i/o pj1 (8) b6 epi0s17 epi module 0 signal 18. ttl i/o pj2 (8) k6 epi0s18 epi module 0 signal 19. ttl i/o pj3 (8) pd4 (10) m10 b5 epi0s19 epi module 0 signal 20. ttl i/o pd2 (8) h2 epi0s20 epi module 0 signal 21. ttl i/o pd3 (8) h1 epi0s21 epi module 0 signal 22. ttl i/o pb5 (8) b7 epi0s22 epi module 0 signal 23. ttl i/o pb4 (8) a6 epi0s23 epi module 0 signal 24. ttl i/o pe2 (8) a4 epi0s24 epi module 0 signal 25. ttl i/o pe3 (8) b4 epi0s25 epi module 0 signal 26. ttl i/o ph6 (8) g3 epi0s26 epi module 0 signal 27. ttl i/o ph7 (8) h3 epi0s27 1271 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 24-8. signals by signal name (continued) description buffer type a pin type pin mux / pin assignment pin number pin name epi module 0 signal 28. ttl i/o pj4 (8) pd5 (10) k11 c6 epi0s28 epi module 0 signal 29. ttl i/o pj5 (8) pd6 (10) k12 a3 epi0s29 epi module 0 signal 30. ttl i/o pj6 (8) pd7 (10) l10 a2 epi0s30 epi module 0 signal 31. ttl i/o pg7 (9) c10 epi0s31 pwm fault 0. ttl i pe4 (4) pg3 (8) pg2 (4) pj2 (10) pf4 (4) pb3 (2) pe1 (3) ph3 (2) pd6 (1) b2 j2 j1 k6 l9 e11 a12 d10 a3 fault0 pwm fault 1. ttl i pg6 (8) pg5 (5) pg4 (4) pf7 (9) pb6 (4) l7 m7 k3 k4 a7 fault1 pwm fault 2. ttl i pg3 (4) pc5 (4) ph5 (10) j2 m1 f10 fault2 pwm fault 3. ttl i pb3 (4) ph2 (4) e11 d11 fault3 ground reference for logic and i/o pins. power - fixed c4 c5 j3 k5 k10 j10 f11 f12 gnd the ground reference for the analog circuits (adc, analog comparators, etc.). these are separated from gnd to minimize the electrical noise contained on vdd from affecting the analog functions. power - fixed a5 gnda i 2 c module 0 clock. od i/o pb2 (1) a11 i2c0scl i 2 c module 0 data. od i/o pb3 (1) e11 i2c0sda i 2 c module 1 clock. od i/o pj0 (11) pg0 (3) pa0 (8) pa6 (1) f3 k1 l3 l6 i2c1scl i 2 c module 1 data. od i/o pg1 (3) pa1 (8) pa7 (1) pj1 (11) k2 m3 m6 b6 i2c1sda i 2 s module 0 receive master clock. ttl i/o pg3 (9) pa3 (9) pd5 (8) j2 l4 c6 i2s0rxmclk july 03, 2014 1272 texas instruments-production data signal tables table 24-8. signals by signal name (continued) description buffer type a pin type pin mux / pin assignment pin number pin name i 2 s module 0 receive clock. ttl i/o pd0 (8) pg5 (9) g1 m7 i2s0rxsck i 2 s module 0 receive data. ttl i/o pg2 (9) pa2 (9) pd4 (8) j1 m4 b5 i2s0rxsd i 2 s module 0 receive word select. ttl i/o pd1 (8) pg6 (9) g2 l7 i2s0rxws i 2 s module 0 transmit master clock. ttl i/o pf6 (9) pf1 (8) m8 h12 i2s0txmclk i 2 s module 0 transmit clock. ttl i/o pa4 (9) pb6 (9) pd6 (8) l5 a7 a3 i2s0txsck i 2 s module 0 transmit data. ttl i/o pe5 (9) pf0 (8) b3 m9 i2s0txsd i 2 s module 0 transmit word select. ttl i/o pe4 (9) pa5 (9) pd7 (8) b2 m5 a2 i2s0txws qei module 0 index. ttl i pd0 (3) pg5 (4) pb2 (2) pb6 (5) pb4 (6) pd7 (1) g1 m7 a11 a7 a6 a2 idx0 qei module 1 index. ttl i pg2 (8) pf1 (2) ph2 (1) j1 h12 d11 idx1 low drop-out regulator output voltage. this pin requires an external capacitor between the pin and gnd of 1 f or greater. the ldo pin must also be connected to the vddc pins at the board level in addition to the decoupling capacitor(s). power - fixed e3 ldo mii management clock. ttl o pf3 (3) j12 mdc mdio of the ethernet phy. od i/o pf4 (3) l9 mdio no connect. leave the pin electrically unconnected/isolated. - - fixed m12 c1 c2 d2 d1 e1 e2 f1 f2 nc non-maskable interrupt. ttl i pb7 (4) a8 nmi main oscillator crystal input or an external clock reference input. analog i fixed l11 osc0 main oscillator crystal output. leave unconnected when using a single-ended clock source. analog o fixed m11 osc1 gpio port a bit 0. ttl i/o - l3 pa0 gpio port a bit 1. ttl i/o - m3 pa1 gpio port a bit 2. ttl i/o - m4 pa2 1273 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 24-8. signals by signal name (continued) description buffer type a pin type pin mux / pin assignment pin number pin name gpio port a bit 3. ttl i/o - l4 pa3 gpio port a bit 4. ttl i/o - l5 pa4 gpio port a bit 5. ttl i/o - m5 pa5 gpio port a bit 6. ttl i/o - l6 pa6 gpio port a bit 7. ttl i/o - m6 pa7 gpio port b bit 0. this pin is not 5-v tolerant. ttl i/o - e12 pb0 gpio port b bit 1. this pin is not 5-v tolerant. ttl i/o - d12 pb1 gpio port b bit 2. ttl i/o - a11 pb2 gpio port b bit 3. ttl i/o - e11 pb3 gpio port b bit 4. ttl i/o - a6 pb4 gpio port b bit 5. ttl i/o - b7 pb5 gpio port b bit 6. ttl i/o - a7 pb6 gpio port b bit 7. ttl i/o - a8 pb7 gpio port c bit 0. ttl i/o - a9 pc0 gpio port c bit 1. ttl i/o - b9 pc1 gpio port c bit 2. ttl i/o - b8 pc2 gpio port c bit 3. ttl i/o - a10 pc3 gpio port c bit 4. ttl i/o - l1 pc4 gpio port c bit 5. ttl i/o - m1 pc5 gpio port c bit 6. ttl i/o - m2 pc6 gpio port c bit 7. ttl i/o - l2 pc7 gpio port d bit 0. ttl i/o - g1 pd0 gpio port d bit 1. ttl i/o - g2 pd1 gpio port d bit 2. ttl i/o - h2 pd2 gpio port d bit 3. ttl i/o - h1 pd3 gpio port d bit 4. ttl i/o - b5 pd4 gpio port d bit 5. ttl i/o - c6 pd5 gpio port d bit 6. ttl i/o - a3 pd6 gpio port d bit 7. ttl i/o - a2 pd7 gpio port e bit 0. ttl i/o - b11 pe0 gpio port e bit 1. ttl i/o - a12 pe1 gpio port e bit 2. ttl i/o - a4 pe2 gpio port e bit 3. ttl i/o - b4 pe3 gpio port e bit 4. ttl i/o - b2 pe4 gpio port e bit 5. ttl i/o - b3 pe5 gpio port e bit 6. ttl i/o - a1 pe6 gpio port e bit 7. ttl i/o - b1 pe7 gpio port f bit 0. ttl i/o - m9 pf0 gpio port f bit 1. ttl i/o - h12 pf1 gpio port f bit 2. ttl i/o - j11 pf2 gpio port f bit 3. ttl i/o - j12 pf3 july 03, 2014 1274 texas instruments-production data signal tables table 24-8. signals by signal name (continued) description buffer type a pin type pin mux / pin assignment pin number pin name gpio port f bit 4. ttl i/o - l9 pf4 gpio port f bit 5. ttl i/o - l8 pf5 gpio port f bit 6. ttl i/o - m8 pf6 gpio port f bit 7. ttl i/o - k4 pf7 gpio port g bit 0. ttl i/o - k1 pg0 gpio port g bit 1. ttl i/o - k2 pg1 gpio port g bit 2. ttl i/o - j1 pg2 gpio port g bit 3. ttl i/o - j2 pg3 gpio port g bit 4. ttl i/o - k3 pg4 gpio port g bit 5. ttl i/o - m7 pg5 gpio port g bit 6. ttl i/o - l7 pg6 gpio port g bit 7. ttl i/o - c10 pg7 gpio port h bit 0. ttl i/o - c9 ph0 gpio port h bit 1. ttl i/o - c8 ph1 gpio port h bit 2. ttl i/o - d11 ph2 gpio port h bit 3. ttl i/o - d10 ph3 gpio port h bit 4. ttl i/o - b10 ph4 gpio port h bit 5. ttl i/o - f10 ph5 gpio port h bit 6. ttl i/o - g3 ph6 gpio port h bit 7. ttl i/o - h3 ph7 qei module 0 phase a. ttl i pd1 (3) pc4 (2) pf6 (4) pe2 (4) g2 l1 m8 a4 pha0 qei module 1 phase a. ttl i pg6 (1) pe3 (3) l7 b4 pha1 qei module 0 phase b. ttl i pc7 (2) pc6 (2) pf7 (4) pf0 (2) ph3 (1) pe3 (4) l2 m2 k4 m9 d10 b4 phb0 qei module 1 phase b. ttl i pd1 (11) pg7 (1) pe2 (3) g2 c10 a4 phb1 phy interrupt. ttl i pf2 (3) j11 phyint gpio port j bit 0. ttl i/o - f3 pj0 gpio port j bit 1. ttl i/o - b6 pj1 gpio port j bit 2. ttl i/o - k6 pj2 gpio port j bit 3. ttl i/o - m10 pj3 gpio port j bit 4. ttl i/o - k11 pj4 gpio port j bit 5. ttl i/o - k12 pj5 gpio port j bit 6. ttl i/o - l10 pj6 gpio port j bit 7. ttl i/o - l12 pj7 1275 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 24-8. signals by signal name (continued) description buffer type a pin type pin mux / pin assignment pin number pin name pwm 0. this signal is controlled by pwm generator 0. ttl o pd0 (1) pj0 (10) pg2 (1) pg0 (2) pa6 (4) pf0 (3) g1 f3 j1 k1 l6 m9 pwm0 pwm 1. this signal is controlled by pwm generator 0. ttl o pd1 (1) pg3 (1) pg1 (2) pa7 (4) pf1 (3) pj1 (10) g2 j2 k2 m6 h12 b6 pwm1 pwm 2. this signal is controlled by pwm generator 1. ttl o pd2 (3) pf2 (4) pb0 (2) ph0 (2) h2 j11 e12 c9 pwm2 pwm 3. this signal is controlled by pwm generator 1. ttl o pd3 (3) pf3 (4) pb1 (2) ph1 (2) h1 j12 d12 c8 pwm3 pwm 4. this signal is controlled by pwm generator 2. ttl o pe6 (1) pg0 (4) pa2 (4) pa6 (5) pf2 (2) ph6 (10) pe0 (1) ph0 (9) a1 k1 m4 l6 j11 g3 b11 c9 pwm4 pwm 5. this signal is controlled by pwm generator 2. ttl o pe7 (1) ph7 (10) pg1 (4) pa3 (4) pa7 (5) pf3 (2) pe1 (1) ph1 (9) b1 h3 k2 l4 m6 j12 a12 c8 pwm5 pwm 6. this signal is controlled by pwm generator 3. ttl o pc4 (4) pa4 (4) pg6 (4) pg4 (9) l1 l5 l7 k3 pwm6 pwm 7. this signal is controlled by pwm generator 3. ttl o pc6 (4) pa5 (4) pg7 (4) pg5 (8) m2 m5 c10 m7 pwm7 system reset input. ttl i fixed h11 rst mii receive clock. 25 mhz in 100base-tx mode. 2.5 mhz in 10base-t mode. ttl i ph7 (3) pa6 (3) pf0 (4) h3 l6 m9 rxck mii receive data 0. ttl i pe4 (7) pg4 (3) b2 k3 rxd0 mii receive data 1. ttl i pf7 (3) pb7 (7) k4 a8 rxd1 mii receive data 2. ttl i pf6 (3) m8 rxd2 july 03, 2014 1276 texas instruments-production data signal tables table 24-8. signals by signal name (continued) description buffer type a pin type pin mux / pin assignment pin number pin name mii receive data 3. ttl i pf5 (3) l8 rxd3 mii receive data valid. ttl i pd0 (7) pa5 (3) ph6 (9) g1 m5 g3 rxdv mii receive error. ttl i pj0 (3) pa7 (3) pf1 (4) f3 m6 h12 rxer ssi module 0 clock. ttl i/o pa2 (1) m4 ssi0clk ssi module 0 frame signal. ttl i/o pa3 (1) l4 ssi0fss ssi module 0 receive. ttl i pa4 (1) l5 ssi0rx ssi module 0 transmit. ttl o pa5 (1) m5 ssi0tx ssi module 1 clock. ttl i/o pf2 (9) pe0 (2) ph4 (11) j11 b11 b10 ssi1clk ssi module 1 frame signal. ttl i/o pf3 (9) ph5 (11) pe1 (2) j12 f10 a12 ssi1fss ssi module 1 receive. ttl i pf4 (9) ph6 (11) pe2 (2) l9 g3 a4 ssi1rx ssi module 1 transmit. ttl o ph7 (11) pf5 (9) pe3 (2) h3 l8 b4 ssi1tx jtag/swd clk. ttl i pc0 (3) a9 swclk jtag tms and swdio. ttl i/o pc1 (3) b9 swdio jtag tdo and swo. ttl o pc3 (3) a10 swo jtag/swd clk. ttl i pc0 (3) a9 tck jtag tdi. ttl i pc2 (3) b8 tdi jtag tdo and swo. ttl o pc3 (3) a10 tdo jtag tms and swdio. ttl i pc1 (3) b9 tms mii transmit clock. 25 mhz in 100base-tx mode. 2.5 mhz in 10base-t mode. ttl i pg6 (3) l7 txck mii transmit data 0. ttl o pa4 (3) ph5 (9) pd7 (4) l5 f10 a2 txd0 ethernet mii transmit data 1. ttl o pa3 (3) ph4 (9) pd6 (4) l4 b10 a3 txd1 mii transmit data 2. ttl o pa2 (3) ph3 (9) pd5 (4) m4 d10 c6 txd2 ethernet mii transmit data 3. ttl o pc4 (3) ph2 (9) pd4 (4) l1 d11 b5 txd3 mii transmit enable. ttl o pg5 (3) m7 txen mii transmit error. ttl o pd1 (7) pg7 (3) g2 c10 txer 1277 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 24-8. signals by signal name (continued) description buffer type a pin type pin mux / pin assignment pin number pin name uart module 0 receive. when in irda mode, this signal has irda modulation. ttl i pa0 (1) l3 u0rx uart module 0 transmit. when in irda mode, this signal has irda modulation. ttl o pa1 (1) m3 u0tx uart module 1 clear to send modem flow control input signal. ttl i pe6 (9) pd0 (9) pa6 (9) pj3 (9) a1 g1 l6 m10 u1cts uart module 1 data carrier detect modem status input signal. ttl i pe7 (9) pd1 (9) pa7 (9) pj4 (9) b1 g2 m6 k11 u1dcd uart module 1 data set ready modem output control line. ttl i pf0 (9) pj5 (9) m9 k12 u1dsr uart module 1 data terminal ready modem status input signal. ttl o pg5 (10) pj7 (9) pd7 (9) m7 l12 a2 u1dtr uart module 1 ring indicator modem status input signal. ttl i pg6 (10) pg4 (10) pd4 (9) l7 k3 b5 u1ri uart module 1 request to send modem flow control output line. ttl o pf6 (10) pj6 (9) pf1 (9) m8 l10 h12 u1rts uart module 1 receive. when in irda mode, this signal has irda modulation. ttl i pd0 (5) pd2 (1) pc6 (5) pa0 (9) pb0 (5) pb4 (7) g1 h2 m2 l3 e12 a6 u1rx uart module 1 transmit. when in irda mode, this signal has irda modulation. ttl o pd1 (5) pd3 (1) pc7 (5) pa1 (9) pb1 (5) pb5 (7) g2 h1 l2 m3 d12 b7 u1tx uart module 2 receive. when in irda mode, this signal has irda modulation. ttl i pd0 (4) pg0 (1) pb4 (4) pd5 (9) g1 k1 a6 c6 u2rx uart module 2 transmit. when in irda mode, this signal has irda modulation. ttl o pe4 (5) pd1 (4) pg1 (1) pd6 (9) b2 g2 k2 a3 u2tx bidirectional differential data pin (d- per usb specification) for usb0. analog i/o fixed c11 usb0dm bidirectional differential data pin (d+ per usb specification) for usb0. analog i/o fixed c12 usb0dp optionally used in host mode to control an external power source to supply power to the usb bus. ttl o pg0 (7) pc5 (6) pa6 (8) pb2 (8) ph3 (4) k1 m1 l6 a11 d10 usb0epen july 03, 2014 1278 texas instruments-production data signal tables table 24-8. signals by signal name (continued) description buffer type a pin type pin mux / pin assignment pin number pin name this signal senses the state of the usb id signal. the usb phy enables an integrated pull-up, and an external element (usb connector) indicates the initial state of the usb controller (pulled down is the a side of the cable and pulled up is the b side). analog i pb0 e12 usb0id optionally used in host mode by an external power source to indicate an error state by that power source. ttl i pc7 (6) pc6 (7) pa7 (8) pb3 (8) pe0 (9) ph4 (4) pj1 (9) l2 m2 m6 e11 b11 b10 b6 usb0pflt 9.1-k resistor (1% precision) used internally for usb analog circuitry. analog o fixed b12 usb0rbias this signal is used during the session request protocol. this signal allows the usb phy to both sense the voltage level of vbus, and pull up vbus momentarily during vbus pulsing. analog i/o pb1 d12 usb0vbus positive supply for i/o and some logic. power - fixed k7 g12 k8 k9 h10 g10 e10 g11 vdd the positive supply for the analog circuits (adc, analog comparators, etc.). these are separated from vdd to minimize the electrical noise contained on vdd from affecting the analog functions. vdda pins must be supplied with a voltage that meets the specification in table 26-2 on page 1298 , regardless of system implementation. power - fixed c7 vdda positive supply for most of the logic function, including the processor core and most peripherals. the voltage on this pin is 1.3 v and is supplied by the on-chip ldo. the vddc pins should only be connected to the ldo pin and an external capacitor as specified in table 26-6 on page 1303 . power - fixed d3 c3 vddc this input provides a reference voltage used to specify the input voltage at which the adc converts to a maximum value. in other words, the voltage that is applied to vrefa is the voltage with which an ainn signal is converted to 4095. the vrefa input is limited to the range specified in table 26-23 on page 1314 . analog i pb6 a7 vrefa a. the ttl designation indicates the pin has ttl-compatible voltage levels. 1279 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 24.2.3 signals by function, except for gpio table 24-9. signals by function, except for gpio description buffer type a pin type pin number pin name function analog-to-digital converter input 0. analog i b1 ain0 adc analog-to-digital converter input 1. analog i a1 ain1 analog-to-digital converter input 2. analog i b3 ain2 analog-to-digital converter input 3. analog i b2 ain3 analog-to-digital converter input 4. analog i a2 ain4 analog-to-digital converter input 5. analog i a3 ain5 analog-to-digital converter input 6. analog i c6 ain6 analog-to-digital converter input 7. analog i b5 ain7 analog-to-digital converter input 8. analog i b4 ain8 analog-to-digital converter input 9. analog i a4 ain9 analog-to-digital converter input 10. analog i a6 ain10 analog-to-digital converter input 11. analog i b7 ain11 analog-to-digital converter input 12. analog i h1 ain12 analog-to-digital converter input 13. analog i h2 ain13 analog-to-digital converter input 14. analog i g2 ain14 analog-to-digital converter input 15. analog i g1 ain15 this input provides a reference voltage used to specify the input voltage at which the adc converts to a maximum value. in other words, the voltage that is applied to vrefa is the voltage with which an ainn signal is converted to 4095. the vrefa input is limited to the range specified in table 26-23 on page 1314 . analog i a7 vrefa analog comparator 0 positive input. analog i a7 c0+ analog comparators analog comparator 0 negative input. analog i a6 c0- analog comparator 0 output. ttl o m1 l9 a7 b7 a2 c0o analog comparator 1 positive input. analog i m1 c1+ analog comparator 1 negative input. analog i b7 c1- analog comparator 1 output. ttl o a1 l2 m1 l8 d11 c1o analog comparator 2 positive input. analog i m2 c2+ analog comparator 2 negative input. analog i l2 c2- analog comparator 2 output. ttl o b1 m2 m8 c2o july 03, 2014 1280 texas instruments-production data signal tables table 24-9. signals by function, except for gpio (continued) description buffer type a pin type pin number pin name function can module 0 receive. ttl i g1 l5 l6 a6 can0rx controller area network can module 0 transmit. ttl o g2 m5 m6 b7 can0tx can module 1 receive. ttl i m9 can1rx can module 1 transmit. ttl o h12 can1tx mii collision detect. ttl i j1 col ethernet mii carrier sense. ttl i j2 crs mii management clock. ttl o j12 mdc mdio of the ethernet phy. od i/o l9 mdio phy interrupt. ttl i j11 phyint mii receive clock. 25 mhz in 100base-tx mode. 2.5 mhz in 10base-t mode. ttl i h3 l6 m9 rxck mii receive data 0. ttl i b2 k3 rxd0 mii receive data 1. ttl i k4 a8 rxd1 mii receive data 2. ttl i m8 rxd2 mii receive data 3. ttl i l8 rxd3 mii receive data valid. ttl i g1 m5 g3 rxdv mii receive error. ttl i f3 m6 h12 rxer mii transmit clock. 25 mhz in 100base-tx mode. 2.5 mhz in 10base-t mode. ttl i l7 txck mii transmit data 0. ttl o l5 f10 a2 txd0 ethernet mii transmit data 1. ttl o l4 b10 a3 txd1 mii transmit data 2. ttl o m4 d10 c6 txd2 ethernet mii transmit data 3. ttl o l1 d11 b5 txd3 mii transmit enable. ttl o m7 txen mii transmit error. ttl o g2 c10 txer 1281 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 24-9. signals by function, except for gpio (continued) description buffer type a pin type pin number pin name function epi module 0 signal 0. ttl i/o d10 epi0s0 external peripheral interface epi module 0 signal 1. ttl i/o d11 epi0s1 epi module 0 signal 2. ttl i/o l1 epi0s2 epi module 0 signal 3. ttl i/o m1 epi0s3 epi module 0 signal 4. ttl i/o m2 epi0s4 epi module 0 signal 5. ttl i/o l2 epi0s5 epi module 0 signal 6. ttl i/o c9 epi0s6 epi module 0 signal 7. ttl i/o c8 epi0s7 epi module 0 signal 8. ttl i/o b11 epi0s8 epi module 0 signal 9. ttl i/o a12 epi0s9 epi module 0 signal 10. ttl i/o b10 epi0s10 epi module 0 signal 11. ttl i/o f10 epi0s11 epi module 0 signal 12. ttl i/o k4 l9 epi0s12 epi module 0 signal 13. ttl i/o k1 epi0s13 epi module 0 signal 14. ttl i/o k2 epi0s14 epi module 0 signal 15. ttl i/o k3 l8 epi0s15 epi module 0 signal 16. ttl i/o f3 epi0s16 epi module 0 signal 17. ttl i/o b6 epi0s17 epi module 0 signal 18. ttl i/o k6 epi0s18 epi module 0 signal 19. ttl i/o m10 b5 epi0s19 epi module 0 signal 20. ttl i/o h2 epi0s20 epi module 0 signal 21. ttl i/o h1 epi0s21 epi module 0 signal 22. ttl i/o b7 epi0s22 epi module 0 signal 23. ttl i/o a6 epi0s23 epi module 0 signal 24. ttl i/o a4 epi0s24 epi module 0 signal 25. ttl i/o b4 epi0s25 epi module 0 signal 26. ttl i/o g3 epi0s26 epi module 0 signal 27. ttl i/o h3 epi0s27 epi module 0 signal 28. ttl i/o k11 c6 epi0s28 epi module 0 signal 29. ttl i/o k12 a3 epi0s29 epi module 0 signal 30. ttl i/o l10 a2 epi0s30 epi module 0 signal 31. ttl i/o c10 epi0s31 july 03, 2014 1282 texas instruments-production data signal tables table 24-9. signals by function, except for gpio (continued) description buffer type a pin type pin number pin name function capture/compare/pwm 0. ttl i/o h1 l2 m2 k6 l12 l9 e12 a11 b7 b5 ccp0 general-purpose timers capture/compare/pwm 1. ttl i/o m1 l1 l6 m8 l10 d12 a7 b4 a2 ccp1 capture/compare/pwm 2. ttl i/o b2 g2 l1 l8 k12 d12 a12 b7 a4 c6 ccp2 capture/compare/pwm 3. ttl i/o b2 m2 m1 m6 k3 h12 a11 b11 b5 ccp3 capture/compare/pwm 4. ttl i/o l2 l1 m6 k4 k11 a4 c6 ccp4 capture/compare/pwm 5. ttl i/o b3 h2 l1 c10 m7 a7 b7 ccp5 capture/compare/pwm 6. ttl i/o ccp6 1283 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 24-9. signals by function, except for gpio (continued) description buffer type a pin type pin number pin name function g1 h2 m10 a12 c9 b7 capture/compare/pwm 7. ttl i/o g2 h1 c8 a7 b4 ccp7 i 2 c module 0 clock. od i/o a11 i2c0scl i2c i 2 c module 0 data. od i/o e11 i2c0sda i 2 c module 1 clock. od i/o f3 k1 l3 l6 i2c1scl i 2 c module 1 data. od i/o k2 m3 m6 b6 i2c1sda i 2 s module 0 receive master clock. ttl i/o j2 l4 c6 i2s0rxmclk i2s i 2 s module 0 receive clock. ttl i/o g1 m7 i2s0rxsck i 2 s module 0 receive data. ttl i/o j1 m4 b5 i2s0rxsd i 2 s module 0 receive word select. ttl i/o g2 l7 i2s0rxws i 2 s module 0 transmit master clock. ttl i/o m8 h12 i2s0txmclk i 2 s module 0 transmit clock. ttl i/o l5 a7 a3 i2s0txsck i 2 s module 0 transmit data. ttl i/o b3 m9 i2s0txsd i 2 s module 0 transmit word select. ttl i/o b2 m5 a2 i2s0txws jtag/swd clk. ttl i a9 swclk jtag/swd/swo jtag tms and swdio. ttl i/o b9 swdio jtag tdo and swo. ttl o a10 swo jtag/swd clk. ttl i a9 tck jtag tdi. ttl i b8 tdi jtag tdo and swo. ttl o a10 tdo jtag tms and swdio. ttl i b9 tms july 03, 2014 1284 texas instruments-production data signal tables table 24-9. signals by function, except for gpio (continued) description buffer type a pin type pin number pin name function pwm fault 0. ttl i b2 j2 j1 k6 l9 e11 a12 d10 a3 fault0 pwm pwm fault 1. ttl i l7 m7 k3 k4 a7 fault1 pwm fault 2. ttl i j2 m1 f10 fault2 pwm fault 3. ttl i e11 d11 fault3 pwm 0. this signal is controlled by pwm generator 0. ttl o g1 f3 j1 k1 l6 m9 pwm0 pwm 1. this signal is controlled by pwm generator 0. ttl o g2 j2 k2 m6 h12 b6 pwm1 pwm 2. this signal is controlled by pwm generator 1. ttl o h2 j11 e12 c9 pwm2 pwm 3. this signal is controlled by pwm generator 1. ttl o h1 j12 d12 c8 pwm3 pwm 4. this signal is controlled by pwm generator 2. ttl o a1 k1 m4 l6 j11 g3 b11 c9 pwm4 pwm 5. this signal is controlled by pwm generator 2. ttl o b1 h3 k2 l4 m6 j12 a12 c8 pwm5 1285 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 24-9. signals by function, except for gpio (continued) description buffer type a pin type pin number pin name function pwm6 pwm 6. this signal is controlled by pwm generator 3. ttl o l1 l5 l7 k3 pwm 7. this signal is controlled by pwm generator 3. ttl o m2 m5 c10 m7 pwm7 ground reference for logic and i/o pins. power - c4 c5 j3 k5 k10 j10 f11 f12 gnd power the ground reference for the analog circuits (adc, analog comparators, etc.). these are separated from gnd to minimize the electrical noise contained on vdd from affecting the analog functions. power - a5 gnda low drop-out regulator output voltage. this pin requires an external capacitor between the pin and gnd of 1 f or greater. the ldo pin must also be connected to the vddc pins at the board level in addition to the decoupling capacitor(s). power - e3 ldo positive supply for i/o and some logic. power - k7 g12 k8 k9 h10 g10 e10 g11 vdd the positive supply for the analog circuits (adc, analog comparators, etc.). these are separated from vdd to minimize the electrical noise contained on vdd from affecting the analog functions. vdda pins must be supplied with a voltage that meets the specification in table 26-2 on page 1298 , regardless of system implementation. power - c7 vdda positive supply for most of the logic function, including the processor core and most peripherals. the voltage on this pin is 1.3 v and is supplied by the on-chip ldo. the vddc pins should only be connected to the ldo pin and an external capacitor as specified in table 26-6 on page 1303 . power - d3 c3 vddc july 03, 2014 1286 texas instruments-production data signal tables table 24-9. signals by function, except for gpio (continued) description buffer type a pin type pin number pin name function qei module 0 index. ttl i g1 m7 a11 a7 a6 a2 idx0 qei qei module 1 index. ttl i j1 h12 d11 idx1 qei module 0 phase a. ttl i g2 l1 m8 a4 pha0 qei module 1 phase a. ttl i l7 b4 pha1 qei module 0 phase b. ttl i l2 m2 k4 m9 d10 b4 phb0 qei module 1 phase b. ttl i g2 c10 a4 phb1 ssi module 0 clock. ttl i/o m4 ssi0clk ssi ssi module 0 frame signal. ttl i/o l4 ssi0fss ssi module 0 receive. ttl i l5 ssi0rx ssi module 0 transmit. ttl o m5 ssi0tx ssi module 1 clock. ttl i/o j11 b11 b10 ssi1clk ssi module 1 frame signal. ttl i/o j12 f10 a12 ssi1fss ssi module 1 receive. ttl i l9 g3 a4 ssi1rx ssi module 1 transmit. ttl o h3 l8 b4 ssi1tx non-maskable interrupt. ttl i a8 nmi system control & clocks main oscillator crystal input or an external clock reference input. analog i l11 osc0 main oscillator crystal output. leave unconnected when using a single-ended clock source. analog o m11 osc1 system reset input. ttl i h11 rst 1287 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 24-9. signals by function, except for gpio (continued) description buffer type a pin type pin number pin name function uart module 0 receive. when in irda mode, this signal has irda modulation. ttl i l3 u0rx uart uart module 0 transmit. when in irda mode, this signal has irda modulation. ttl o m3 u0tx uart module 1 clear to send modem flow control input signal. ttl i a1 g1 l6 m10 u1cts uart module 1 data carrier detect modem status input signal. ttl i b1 g2 m6 k11 u1dcd uart module 1 data set ready modem output control line. ttl i m9 k12 u1dsr uart module 1 data terminal ready modem status input signal. ttl o m7 l12 a2 u1dtr uart module 1 ring indicator modem status input signal. ttl i l7 k3 b5 u1ri uart module 1 request to send modem flow control output line. ttl o m8 l10 h12 u1rts uart module 1 receive. when in irda mode, this signal has irda modulation. ttl i g1 h2 m2 l3 e12 a6 u1rx uart module 1 transmit. when in irda mode, this signal has irda modulation. ttl o g2 h1 l2 m3 d12 b7 u1tx uart module 2 receive. when in irda mode, this signal has irda modulation. ttl i g1 k1 a6 c6 u2rx uart module 2 transmit. when in irda mode, this signal has irda modulation. ttl o b2 g2 k2 a3 u2tx july 03, 2014 1288 texas instruments-production data signal tables table 24-9. signals by function, except for gpio (continued) description buffer type a pin type pin number pin name function bidirectional differential data pin (d- per usb specification) for usb0. analog i/o c11 usb0dm usb bidirectional differential data pin (d+ per usb specification) for usb0. analog i/o c12 usb0dp optionally used in host mode to control an external power source to supply power to the usb bus. ttl o k1 m1 l6 a11 d10 usb0epen this signal senses the state of the usb id signal. the usb phy enables an integrated pull-up, and an external element (usb connector) indicates the initial state of the usb controller (pulled down is the a side of the cable and pulled up is the b side). analog i e12 usb0id optionally used in host mode by an external power source to indicate an error state by that power source. ttl i l2 m2 m6 e11 b11 b10 b6 usb0pflt 9.1-k resistor (1% precision) used internally for usb analog circuitry. analog o b12 usb0rbias this signal is used during the session request protocol. this signal allows the usb phy to both sense the voltage level of vbus, and pull up vbus momentarily during vbus pulsing. analog i/o d12 usb0vbus a. the ttl designation indicates the pin has ttl-compatible voltage levels. 24.2.4 gpio pins and alternate functions table 24-10. gpio pins and alternate functions digital function (gpiopctl pmcx bit field encoding) a analog function pinio 11 10 9 8 7 6 5 4 3 2 1 -- u1rx i2c1scl ------ u0rx -l3 pa0 -- u1tx i2c1sda ------ u0tx -m3 pa1 -- i2s0rxsd ---- pwm4 txd2 - ssi0clk -m4 pa2 -- i2s0rxmclk ---- pwm5 txd1 - ssi0fss -l4 pa3 -- i2s0txsck --- can0rx pwm6 txd0 - ssi0rx -l5 pa4 -- i2s0txws --- can0tx pwm7 rxdv - ssi0tx -m5 pa5 -- u1cts usb0epen - can0rx pwm4 pwm0 rxck ccp1 i2c1scl -l6 pa6 -- u1dcd usb0pflt ccp3 can0tx pwm5 pwm1 rxer ccp4 i2c1sda -m6 pa7 ------ u1rx -- pwm2 ccp0 usb0id e12 pb0 ------ u1tx ccp1 - pwm3 ccp2 usb0vbus d12 pb1 --- usb0epen -- ccp0 ccp3 - idx0 i2c0scl -a11 pb2 --- usb0pflt --- fault3 - fault0 i2c0sda -e11 pb3 --- epi0s23 u1rx idx0 can0rx u2rx --- ain10 c0- a6 pb4 1289 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 24-10. gpio pins and alternate functions (continued) digital function (gpiopctl pmcx bit field encoding) a analog function pinio 11 10 9 8 7 6 5 4 3 2 1 --- epi0s22 u1tx ccp2 can0tx ccp0 ccp6 ccp5 c0o ain11 c1- b7 pb5 -- i2s0txsck -- ccp5 idx0 fault1 c0o ccp7 ccp1 vrefa c0+ a7 pb6 ---- rxd1 -- nmi --- -a8 pb7 -------- tck swclk -- -a9 pc0 -------- tms swdio -- -b9 pc1 -------- tdi -- -b8 pc2 -------- tdo swo -- -a10 pc3 -- ccp1 epi0s2 - ccp4 ccp2 pwm6 txd3 pha0 ccp5 -l1 pc4 --- epi0s3 - usb0epen ccp3 fault2 c0o c1o ccp1 c1+ m1 pc5 --- epi0s4 usb0pflt ccp0 u1rx pwm7 c2o phb0 ccp3 c2+ m2 pc6 --- epi0s5 c1o usb0pflt u1tx ccp0 - phb0 ccp4 c2- l2 pc7 -- u1cts i2s0rxsck rxdv ccp6 u1rx u2rx idx0 can0rx pwm0 ain15 g1 pd0 phb1 ccp2 u1dcd i2s0rxws txer ccp7 u1tx u2tx pha0 can0tx pwm1 ain14 g2 pd1 --- epi0s20 --- ccp5 pwm2 ccp6 u1rx ain13 h2 pd2 --- epi0s21 --- ccp0 pwm3 ccp7 u1tx ain12 h1 pd3 - epi0s19 u1ri i2s0rxsd --- txd3 - ccp3 ccp0 ain7 b5 pd4 - epi0s28 u2rx i2s0rxmclk --- txd2 - ccp4 ccp2 ain6 c6 pd5 - epi0s29 u2tx i2s0txsck --- txd1 -- fault0 ain5 a3 pd6 - epi0s30 u1dtr i2s0txws --- txd0 ccp1 c0o idx0 ain4 a2 pd7 -- usb0pflt epi0s8 ---- ccp3 ssi1clk pwm4 -b11 pe0 --- epi0s9 -- ccp6 ccp2 fault0 ssi1fss pwm5 -a12 pe1 --- epi0s24 -- ccp2 pha0 phb1 ssi1rx ccp4 ain9 a4 pe2 --- epi0s25 -- ccp7 phb0 pha1 ssi1tx ccp1 ain8 b4 pe3 -- i2s0txws - rxd0 ccp2 u2tx fault0 -- ccp3 ain3 b2 pe4 -- i2s0txsd ------- ccp5 ain2 b3 pe5 -- u1cts ------ c1o pwm4 ain1 a1 pe6 -- u1dcd ------ c2o pwm5 ain0 b1 pe7 -- u1dsr i2s0txsd --- rxck pwm0 phb0 can1rx -m9 pf0 - ccp3 u1rts i2s0txmclk --- rxer pwm1 idx1 can1tx -h12 pf1 -- ssi1clk ---- pwm2 phyint pwm4 - -j11 pf2 -- ssi1fss ---- pwm3 mdc pwm5 - -j12 pf3 -- ssi1rx epi0s12 --- fault0 mdio c0o ccp0 -l9 pf4 -- ssi1tx epi0s15 ---- rxd3 c1o ccp2 -l8 pf5 - u1rts i2s0txmclk ---- pha0 rxd2 c2o ccp1 -m8 pf6 -- fault1 epi0s12 --- phb0 rxd1 - ccp4 -k4 pf7 --- epi0s13 usb0epen -- pwm4 i2c1scl pwm0 u2rx -k1 pg0 --- epi0s14 --- pwm5 i2c1sda pwm1 u2tx -k2 pg1 july 03, 2014 1290 texas instruments-production data signal tables table 24-10. gpio pins and alternate functions (continued) digital function (gpiopctl pmcx bit field encoding) a analog function pinio 11 10 9 8 7 6 5 4 3 2 1 -- i2s0rxsd idx1 --- fault0 col - pwm0 -j1 pg2 -- i2s0rxmclk fault0 --- fault2 crs - pwm1 -j2 pg3 - u1ri pwm6 epi0s15 --- fault1 rxd0 - ccp3 -k3 pg4 - u1dtr i2s0rxsck pwm7 -- fault1 idx0 txen - ccp5 -m7 pg5 - u1ri i2s0rxws fault1 --- pwm6 txck - pha1 -l7 pg6 -- epi0s31 ccp5 --- pwm7 txer - phb1 -c10 pg7 -- pwm4 epi0s6 ----- pwm2 ccp6 -c9 ph0 -- pwm5 epi0s7 ----- pwm3 ccp7 -c8 ph1 -- txd3 epi0s1 --- fault3 - c1o idx1 -d11 ph2 -- txd2 epi0s0 --- usb0epen - fault0 phb0 -d10 ph3 ssi1clk - txd1 epi0s10 --- usb0pflt --- -b10 ph4 ssi1fss fault2 txd0 epi0s11 ------- -f10 ph5 ssi1rx pwm4 rxdv epi0s26 ------- -g3 ph6 ssi1tx pwm5 - epi0s27 ---- rxck -- -h3 ph7 i2c1scl pwm0 - epi0s16 ---- rxer -- -f3 pj0 i2c1sda pwm1 usb0pflt epi0s17 ------- -b6 pj1 - fault0 ccp0 epi0s18 ------- -k6 pj2 - ccp6 u1cts epi0s19 ------- - m10 pj3 - ccp4 u1dcd epi0s28 ------- -k11 pj4 - ccp2 u1dsr epi0s29 ------- -k12 pj5 - ccp1 u1rts epi0s30 ------- -l10 pj6 - ccp0 u1dtr -------- -l12 pj7 a. the digital signals that are shaded gray are the power-on default values for the corresponding gpio pin. 1291 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 24.2.5 possible pin assignments for alternate functions table 24-11. possible pin assignments for alternate functions gpio function alternate function # of possible assignments pe7 ain0 one pe6 ain1 pb4 ain10 pb5 ain11 pd3 ain12 pd2 ain13 pd1 ain14 pd0 ain15 pe5 ain2 pe4 ain3 pd7 ain4 pd6 ain5 pd5 ain6 pd4 ain7 pe3 ain8 pe2 ain9 pb6 c0+ pb4 c0- pc5 c1+ pb5 c1- pc6 c2+ pc7 c2- pf0 can1rx pf1 can1tx pg2 col pg3 crs ph3 epi0s0 ph2 epi0s1 ph4 epi0s10 ph5 epi0s11 pg0 epi0s13 pg1 epi0s14 pj0 epi0s16 pj1 epi0s17 pj2 epi0s18 pc4 epi0s2 pd2 epi0s20 pd3 epi0s21 pb5 epi0s22 july 03, 2014 1292 texas instruments-production data signal tables table 24-11. possible pin assignments for alternate functions (continued) gpio function alternate function # of possible assignments epi0s23 pb4 pe2 epi0s24 pe3 epi0s25 ph6 epi0s26 ph7 epi0s27 pc5 epi0s3 pg7 epi0s31 pc6 epi0s4 pc7 epi0s5 ph0 epi0s6 ph1 epi0s7 pe0 epi0s8 pe1 epi0s9 pb2 i2c0scl pb3 i2c0sda pf3 mdc pf4 mdio pb7 nmi pf2 phyint pf6 rxd2 pf5 rxd3 pa2 ssi0clk pa3 ssi0fss pa4 ssi0rx pa5 ssi0tx pc0 swclk pc1 swdio pc3 swo pc0 tck pc2 tdi pc3 tdo pc1 tms pg6 txck pg5 txen pa0 u0rx pa1 u0tx pb0 usb0id pb1 usb0vbus pb6 vrefa 1293 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 24-11. possible pin assignments for alternate functions (continued) gpio function alternate function # of possible assignments pf7 pf4 epi0s12 two pg4 pf5 epi0s15 pj3 pd4 epi0s19 pj4 pd5 epi0s28 pj5 pd6 epi0s29 pj6 pd7 epi0s30 pb3 ph2 fault3 pd0 pg5 i2s0rxsck pd1 pg6 i2s0rxws pf6 pf1 i2s0txmclk pe5 pf0 i2s0txsd pg6 pe3 pha1 pe4 pg4 rxd0 pf7 pb7 rxd1 pd1 pg7 txer pf0 pj5 u1dsr pe7 pc6 pf6 c2o three pg3 pc5 ph5 fault2 pg3 pa3 pd5 i2s0rxmclk pg2 pa2 pd4 i2s0rxsd pa4 pb6 pd6 i2s0txsck pe4 pa5 pd7 i2s0txws pg2 pf1 ph2 idx1 pd1 pg7 pe2 phb1 ph7 pa6 pf0 rxck pd0 pa5 ph6 rxdv pj0 pa7 pf1 rxer pf2 pe0 ph4 ssi1clk pf3 ph5 pe1 ssi1fss pf4 ph6 pe2 ssi1rx ph7 pf5 pe3 ssi1tx pa4 ph5 pd7 txd0 pa3 ph4 pd6 txd1 pa2 ph3 pd5 txd2 pc4 ph2 pd4 txd3 pg5 pj7 pd7 u1dtr pg6 pg4 pd4 u1ri pf6 pj6 pf1 u1rts july 03, 2014 1294 texas instruments-production data signal tables table 24-11. possible pin assignments for alternate functions (continued) gpio function alternate function # of possible assignments pd0 pa4 pa6 pb4 can0rx four pd1 pa5 pa7 pb5 can0tx pj0 pg0 pa0 pa6 i2c1scl pg1 pa1 pa7 pj1 i2c1sda pd2 pf2 pb0 ph0 pwm2 pd3 pf3 pb1 ph1 pwm3 pc4 pa4 pg6 pg4 pwm6 pc6 pa5 pg7 pg5 pwm7 pd1 pc4 pf6 pe2 pha0 pe6 pd0 pa6 pj3 u1cts pe7 pd1 pa7 pj4 u1dcd pd0 pg0 pb4 pd5 u2rx pe4 pd1 pg1 pd6 u2tx pc5 pf4 pb6 pb5 pd7 c0o five pe6 pc7 pc5 pf5 ph2 c1o pd1 pd3 ph1 pb6 pe3 ccp7 pg6 pg5 pg4 pf7 pb6 fault1 pg0 pc5 pa6 pb2 ph3 usb0epen pd0 pd2 pj3 pe1 ph0 pb5 ccp6 six pd0 pg5 pb2 pb6 pb4 pd7 idx0 pd0 pj0 pg2 pg0 pa6 pf0 pwm0 pd1 pg3 pg1 pa7 pf1 pj1 pwm1 pc7 pc6 pf7 pf0 ph3 pe3 phb0 pd0 pd2 pc6 pa0 pb0 pb4 u1rx pd1 pd3 pc7 pa1 pb1 pb5 u1tx pc7 pc4 pa7 pf7 pj4 pe2 pd5 ccp4 seven pe5 pd2 pc4 pg7 pg5 pb6 pb5 ccp5 pc7 pc6 pa7 pb3 pe0 ph4 pj1 usb0pflt pe6 pg0 pa2 pa6 pf2 ph6 pe0 ph0 pwm4 eight pe7 ph7 pg1 pa3 pa7 pf3 pe1 ph1 pwm5 pc5 pc4 pa6 pf6 pj6 pb1 pb6 pe3 pd7 ccp1 nine pe4 pc6 pc5 pa7 pg4 pf1 pb2 pe0 pd4 ccp3 pe4 pg3 pg2 pj2 pf4 pb3 pe1 ph3 pd6 fault0 pd3 pc7 pc6 pj2 pj7 pf4 pb0 pb2 pb5 pd4 ccp0 ten pe4 pd1 pc4 pf5 pj5 pb1 pe1 pb5 pe2 pd5 ccp2 24.3 connections for unused signals table 24-12 on page 1296 shows how to handle signals for functions that are not used in a particular system implementation for devices that are in a 100-pin lqfp package. two options are shown in the table: an acceptable practice and a preferred practice for reduced power consumption and improved emc characteristics. if a module is not used in a system, and its inputs are grounded, it 1295 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller is important that the clock to the module is never enabled by setting the corresponding bit in the rcgcx register. table 24-12. connections for unused signals (100-pin lqfp) preferred practice acceptable practice pin number signal name function nc nc 58 mdio a ethernet gnd nc - all unused gpios gpio nc nc - nc no connects gnd nc 48 osc0 system control nc nc 49 osc1 connect through a capacitor to gnd as close to pin as possible pull up as shown in figure 5-1 on page 193 64 rst gnd nc 70 usb0dm usb gnd nc 71 usb0dp connect to gnd through 10-k? resistor. connect to gnd through 10-k? resistor. 73 usb0rbias a. note that the ethernet phy is powered up by default. the phy cannot be powered down unless a clock source is provided and the mdio pin is pulled up through a 10-k? resistor. table 24-13 on page 1296 shows how to handle signals for functions that are not used in a particular system implementation for devices that are in a 108-ball bga package. two options are shown in the table: an acceptable practice and a preferred practice for reduced power consumption and improved emc characteristics. if a module is not used in a system, and its inputs are grounded, it is important that the clock to the module is never enabled by setting the corresponding bit in the rcgcx register. table 24-13. connections for unused signals (108-ball bga) preferred practice acceptable practice pin number signal name function nc nc l9 mdio a ethernet gnd nc - all unused gpios gpio nc nc - nc no connects gnd nc l11 osc0 system control nc nc m11 osc1 connect through a capacitor to gnd as close to pin as possible pull up as shown in figure 5-1 on page 193 h11 rst connect to gnd through 10-k? resistor. connect to gnd through 10-k? resistor. b12 usb0rbias usb gnd nc c11 usb0dm gnd nc c12 usb0dp a. note that the ethernet phy is powered up by default. the phy cannot be powered down unless a clock source is provided and the mdio pin is pulled up through a 10-k? resistor. july 03, 2014 1296 texas instruments-production data signal tables 25 operating characteristics table 25-1. temperature characteristics unit value symbol characteristic c -40 to +85 t a industrial operating temperature range c -65 to +150 t s unpowered storage temperature range table 25-2. thermal characteristics unit value symbol characteristic c/w 33 (100lqfp) 31 (108bga) ja thermal resistance (junction to ambient) a c t a + (p ? ja ) t j junction temperature, -40 to +125 b a. junction to ambient thermal resistance ja numbers are determined by a package simulator. b. power dissipation is a function of temperature. table 25-3. esd absolute maximum ratings a unit max nom min parameter name kv 2.0 - - v esdhbm v 500 - - v esdcdm a. all stellaris ? parts are esd tested following the jedec standard. 1297 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 26 electrical characteristics 26.1 maximum ratings the maximum ratings are the limits to which the device can be subjected without permanently damaging the device. device reliability may be adversely affected by exposure to absolute-maximum ratings for extended periods. note: the device is not guaranteed to operate properly at the maximum ratings. table 26-1. maximum ratings unit value parameter name a parameter max min v 4 0 v dd supply voltage v dd v 4 0 v dda supply voltage v dda v 5.5 -0.3 input voltage b v in_gpio v v dd + 0.3 -0.3 input voltage for pb0 and pb1 when configured as gpio ma 25 - maximum current per output pin i gpiomax mv 300 - maximum input voltage on a non-power pin when the microcontroller is unpowered v non a. voltages are measured with respect to gnd. b. applies to static and dynamic signals including overshoot. important: this device contains circuitry to protect the inputs against damage due to high-static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (see connections for unused signals on page 1295). 26.2 recommended operating conditions for special high-current applications, the gpio output buffers may be used with the following restrictions. with the gpio pins configured as 8-ma output drivers, a total of four gpio outputs may be used to sink current loads up to 18 ma each. at 18-ma sink current loading, the v ol value is specified as 1.2 v. the high-current gpio package pins must be selected such that there are only a maximum of two per side of the physical package or bga pin group with the total number of high-current gpio outputs not exceeding four for the entire package. table 26-2. recommended dc operating conditions unit max nom min parameter name parameter v 3.6 3.3 3.0 v dd supply voltage v dd v 3.6 3.3 3.0 v dda supply voltage v dda v 1.365 1.3 1.235 v ddc supply voltage, run mode v ddc v 5.0 - 2.1 high-level input voltage v ih v 1.2 - -0.3 low-level input voltage v il v - - 2.4 high-level output voltage v oh july 03, 2014 1298 texas instruments-production data electrical characteristics table 26-2. recommended dc operating conditions (continued) unit max nom min parameter name parameter v 0.4 - - low-level output voltage v ol high-level source current, v oh =2.4 v a i oh ma - - -2.0 2-ma drive ma - - -4.0 4-ma drive ma - - -8.0 8-ma drive low-level sink current, v ol =0.4 v a i ol ma - - 2.0 2-ma drive ma - - 4.0 4-ma drive ma - - 8.0 8-ma drive ma - - 18.0 8-ma drive, v ol =1.2 v a. i o specifications reflect the maximum current where the corresponding output voltage meets the v oh /v ol thresholds. i o current can exceed these limits (subject to absolute maximum ratings). 26.3 load conditions unless otherwise specified, the following conditions are true for all timing measurements. figure 26-1. load conditions 26.4 jtag and boundary scan table 26-3. jtag characteristics unit max nom min parameter name parameter parameter no. mhz 10 -0 tck operational clock frequency a f tck j1 ns - - 100 tck operational clock period t tck j2 ns - t tck /2 - tck clock low time t tck_low j3 ns - t tck /2 - tck clock high time t tck_high j4 ns 10 -0 tck rise time t tck_r j5 ns 10 -0 tck fall time t tck_f j6 ns - - 20 tms setup time to tck rise t tms_su j7 ns - - 20 tms hold time from tck rise t tms_hld j8 ns - - 25 tdi setup time to tck rise t tdi_su j9 ns - - 25 tdi hold time from tck rise t tdi_hld j10 1299 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller & / * 1 ' s l q s ) i r u ( 3 , 6 > @ v l j q d o v s ) i r u r w k h u g l j l w d o , 2 v l j q d o v table 26-3. jtag characteristics (continued) unit max nom min parameter name parameter parameter no. ns 35 23 - tck fall to data valid from high-z, 2-ma drive t tdo_zdv j11 ns 26 15 tck fall to data valid from high-z, 4-ma drive ns 25 14 tck fall to data valid from high-z, 8-ma drive ns 29 18 tck fall to data valid from high-z, 8-ma drive with slew rate control ns 35 21 - tck fall to data valid from data valid, 2-ma drive t tdo_dv j12 ns 25 14 tck fall to data valid from data valid, 4-ma drive ns 24 13 tck fall to data valid from data valid, 8-ma drive ns 28 18 tck fall to data valid from data valid, 8-ma drive with slew rate control ns 11 9 - tck fall to high-z from data valid, 2-ma drive t tdo_dvz j13 ns 9 7 tck fall to high-z from data valid, 4-ma drive ns 8 6 tck fall to high-z from data valid, 8-ma drive ns 9 7 tck fall to high-z from data valid, 8-ma drive with slew rate control a. a ratio of at least 8:1 must be kept between the system clock and tck. figure 26-2. jtag test clock input timing figure 26-3. jtag test access port (tap) timing july 03, 2014 1300 texas instruments-production data electrical characteristics 7 & . - - - - - 7 ' 2 2 x w s x w 9 d o l g 7 & . 7 ' 2 2 x w s x w 9 d o l g - 7 ' 2 7 ' , 7 0 6 7 ' , , q s x w 9 d o l g 7 ' , , q s x w 9 d o l g - - - 7 0 6 , q s x w 9 d o l g - - 7 0 6 , q s x w 9 d o l g - - - - - 26.5 power and brown-out table 26-4. power characteristics unit max nom min parameter name parameter parameter no. v - 2- power-on reset threshold v th p1 v 2.95 2.9 2.85 brown-out reset threshold v bth p2 ms 18 -6 power-on reset timeout t por p3 s - 500 - brown-out timeout t bor p4 ms 2 -- internal reset timeout after por t irpor p5 ms 2 -- internal reset timeout after bor t irbor p6 ms 10 -- supply voltage (v dd ) rise time (0v-3.0v) t vddrise p7 ms 6 -- supply voltage (v dd ) rise time (2.0v-3.0v) t vdd2_3 p8 figure 26-4. power-on reset timing figure 26-5. brown-out reset timing 1301 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 9 ' ' 3 2 5 , q w h u q d o 5 h v h w , q w h u q d o 3 3 3 9 ' ' % 2 5 , q w h u q d o 5 h v h w , q w h u q d o 3 3 3 figure 26-6. power-on reset and voltage parameters 26.6 reset table 26-5. reset characteristics unit max nom min parameter name parameter parameter no. ms 2-- internal reset timeout after hardware reset ( rst pin) t irhwr r1 ms 2-- internal reset timeout after software-initiated system reset t irswr r2 ms 2-- internal reset timeout after watchdog reset t irwdr r3 ms 2-- internal reset timeout after mosc failure reset t irmfr r4 s --2 minimum rst pulse width a t min r5 a. this specification must be met in order to guarantee proper reset operation. figure 26-7. external reset timing (rst ) figure 26-8. software reset timing july 03, 2014 1302 texas instruments-production data electrical characteristics 9 ' ' 3 3 5 6 7 5 h v h w , q w h u q d o 5 5 5 5 6 : 5 h v h w 5 h v h w , q w h u q d o figure 26-9. watchdog reset timing figure 26-10. mosc failure reset timing 26.7 on-chip low drop-out (ldo) regulator table 26-6. ldo regulator characteristics unit max nom min parameter name parameter f 3.0 - 1.0 external filter capacitor size for internal power supply a c ldo v 1.365 1.3 1.235 ldo output voltage v ldo a. the capacitor should be connected as close as possible to pin 86. 26.8 clocks the following sections provide specifications on the various clock sources and mode. 26.8.1 pll specifications the following tables provide specifications for using the pll. table 26-7. phase locked loop (pll) characteristics unit max nom min parameter name parameter mhz 16.384 - 3.579545 crystal reference a f ref_xtal mhz 16.384 - 3.579545 external clock reference a f ref_ext mhz - 400 - pll frequency b f pll ms 1.38 d - 0.562 c pll lock time t ready a. the exact value is determined by the crystal value programmed into the xtal field of the run-mode clock configuration (rcc) register. b. pll frequency is automatically calculated by the hardware based on the xtal field of the rcc register. c. using a 16.384-mhz crystal d. using 3.5795-mhz crystal 1303 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller : ' 2 * 5 h v h w , q w h u q d o 5 h v h w , q w h u q d o 5 0 2 6 & ) d l o 5 h v h w , q w h u q d o 5 h v h w , q w h u q d o 5 table 26-8 on page 1304 shows the actual frequency of the pll based on the crystal frequency used (defined by the xtal field in the rcc register). table 26-8. actual pll frequency error pll frequency (mhz) crystal frequency (mhz) xtal 0.0023% 400.904 3.5795 0x04 0.0047% 398.1312 3.6864 0x05 - 400 4.0 0x06 0.0035% 401.408 4.096 0x07 0.0047% 398.1312 4.9152 0x08 - 400 5.0 0x09 0.0016% 399.36 5.12 0x0a - 400 6.0 0x0b 0.0016% 399.36 6.144 0x0c 0.0047% 398.1312 7.3728 0x0d - 400 8.0 0x0e 0.0033% 398.6773333 8.192 0x0f - 400 10.0 0x10 - 400 12.0 0x11 0.0035% 401.408 12.288 0x12 0.0056% 397.76 13.56 0x13 0.0023% 400.90904 14.318 0x14 - 400 16.0 0x15 0.010% 404.1386667 16.384 0x16 26.8.2 piosc specifications table 26-9. piosc clock characteristics unit max nom min parameter name parameter - 1% 0.25% - internal 16-mhz precision oscillator frequency variance, factory calibrated at 25 c f piosc25 - 3% - - internal 16-mhz precision oscillator frequency variance, factory calibrated at 25 c, across specified temperature range f piosct - 1% 0.25% - internal 16-mhz precision oscillator frequency variance, user calibrated at a chosen temperature f pioscucal 26.8.3 internal 30-khz oscillator specifications table 26-10. 30-khz clock characteristics unit max nom min parameter name parameter khz 45 30 15 internal 30-khz oscillator frequency f iosc30khz july 03, 2014 1304 texas instruments-production data electrical characteristics 26.8.4 main oscillator specifications table 26-11. main oscillator clock characteristics unit max nom min parameter name parameter mhz 16.384 - 1 main oscillator frequency f mosc ns 1000 - 61 main oscillator period t mosc_per ms 20 - 17.5 main oscillator settling time a t mosc_settle mhz 16.384 - 1 crystal reference using the main oscillator (pll in bypass mode) b f ref_xtal_bypass mhz 50 - 0 external clock reference (pll in bypass mode) b f ref_ext_bypass % 55 - 45 external clock reference duty cycle dc mosc_ext a. this parameter is highly sensitive to pcb layout and trace lengths, which may make this parameter time longer. care must be taken in pcb design to minimize trace lengths and rlc (resistance, inductance, capacitance). b. if the adc is used, the crystal reference must be 16 mhz .03% when the pll is bypassed. table 26-12. supported mosc crystal frequencies a crystal frequency (mhz) using the pll crystal frequency (mhz) not using the pll reserved 1.000 mhz reserved 1.8432 mhz reserved 2.000 mhz reserved 2.4576 mhz 3.579545 mhz 3.6864 mhz 4 mhz (usb) 4.096 mhz 4.9152 mhz 5 mhz (usb) 5.12 mhz 6 mhz (reset value)(usb) 6.144 mhz 7.3728 mhz 8 mhz (usb) 8.192 mhz 10.0 mhz (usb) 12.0 mhz (usb) 12.288 mhz 13.56 mhz 14.31818 mhz 16.0 mhz (usb) 16.384 mhz a. frequencies that may be used with the usb interface are indicated in the table. 1305 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 26.8.5 system clock specification with adc operation table 26-13. system clock characteristics with adc operation unit max nom min parameter name parameter mhz 16.0048 16 15.9952 system clock frequency when the adc module is operating (when pll is bypassed). a f sysadc a. clock frequency (plus jitter) must be stable inside specified range. adc can be clocked from the pll or directly from an external clock source, as long as frequency absolute precision is inside specified range. 26.8.6 system clock specification with usb operation table 26-14. system clock characteristics with usb operation unit max nom min parameter name parameter mhz - - 30 system clock frequency when the usb module is operating (note that mosc must be the clock source, either with or without using the pll) f sysusb 26.9 sleep modes table 26-15. sleep modes ac characteristics a unit max nom min parameter name parameter parameter no system clocks 2-- time to wake from interrupt in sleep mode, not using the pll b t wake_s d1 system clocks 7-- time to wake from interrupt deep-sleep mode, not using the pll b t wake_ds ms t ready -- time to wake from interrupt in sleep or deep-sleep mode when using the pll b t wake_pll_s d2 ms 35 c 0- time to enter deep-sleep mode from sleep request t enter_ds d3 a. values in this table assume the iosc is the clock source during sleep or deep-sleep mode. b. specified from registering the interrupt to first instruction. c. nominal specification occurs 99.9995% of the time. 26.10 flash memory table 26-16. flash memory characteristics unit max nom min parameter name parameter cycles - - 15,000 number of guaranteed program/erase cycles before failure a pe cyc years - - 10 data retention, -40?c to +85?c t ret ms 1 - - word program time t prog ms 1 - - buffer program time t bprog ms 12 - - page erase time t erase ms 16 - - mass erase time t me a. a program/erase cycle is defined as switching the bits from 1-> 0 -> 1. july 03, 2014 1306 texas instruments-production data electrical characteristics 26.11 input/output characteristics note: all gpio signals are 5-v tolerant when configured as inputs except for pb0 and pb1 , which are limited to 3.6 v. see signal description on page 405 for more information on gpio configuration. table 26-17. gpio module characteristics a unit max nom min parameter name parameter k? 300 - 100 gpio internal pull-up resistor r gpiopu k? 500 - 200 gpio internal pull-down resistor r gpiopd a 2 - - gpio input leakage current b i lkg ns 20 14 - gpio rise time, 2-ma drive c t gpior ns 10 7 gpio rise time, 4-ma drive c ns 5 4 gpio rise time, 8-ma drive c ns 8 6 gpio rise time, 8-ma drive with slew rate control c ns 21 14 - gpio fall time, 2-ma drive d t gpiof ns 11 7 gpio fall time, 4-ma drive d ns 6 4 gpio fall time, 8-ma drive d ns 8 6 gpio fall time, 8-ma drive with slew rate control d a. v dd must be within the range specified in table 26-2 on page 1298. b. the leakage current is measured with gnd or v dd applied to the corresponding pin(s). the leakage of digital port pins is measured individually. the port pin is configured as an input and the pullup/pulldown resistor is disabled. c. time measured from 20% to 80% of v dd . d. time measured from 80% to 20% of v dd . 26.12 external peripheral interface (epi) when the epi module is in sdram mode, the drive strength must be configured to 8 ma. table 26-18 on page 1307 shows the rise and fall times in sdram mode with 16 pf load conditions. when the epi module is in host-bus or general-purpose mode, the values in input/output characteristics on page 1307 should be used. table 26-18. epi sdram characteristics unit max nom min condition parameter name parameter ns 32- 8-ma drive, c l = 16 pf epi rise time (from 20% to 80% of v dd ) t sdramr ns 32- 8-ma drive, c l = 16 pf epi fall time (from 80% to 20% of v dd ) t sdramf table 26-19. epi sdram interface characteristics a unit max nom min parameter name parameter parameter no ns -- 20 sdram clock period t ck e1 ns -- 10 sdram clock high time t ch e2 ns -- 10 sdram clock low time t cl e3 ns 5- -5 clk to output valid t cov e4 ns 5- -5 clk to output invalid t coi e5 ns 5- -5 clk to output tristate t cot e6 1307 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 26-19. epi sdram interface characteristics (continued) unit max nom min parameter name parameter parameter no ns -- 10 input set up to clk t s e7 ns -- 0 clk to input hold t h e8 s -- 100 power-up time t pu e9 ns -- 20 precharge all banks t rp e10 ns -- 66 auto refresh t rfc e11 ns -- 40 program mode register t mrd e12 a. the epi sdram interface must use 8-ma drive. figure 26-11. sdram initialization and load mode register timing figure 26-12. sdram read timing july 03, 2014 1308 texas instruments-production data electrical characteristics & / . ( 3 , 6 & . ( ( 3 , 6 & r p p d q g ( 3 , 6 > @ ' 4 0 + ' 4 0 / ( 3 , 6 > @ $ ' $ ' > @ ( 3 , 6 > @ $ ' ( 3 , 6 > @ % $ ' > @ ( 3 , 6 > @ $ ' > @ ( 3 , 6 > @ 1 2 3 3 5 ( 1 2 3 $ 5 ( ) 1 2 3 3 5 ( 1 2 3 $ 5 ( ) 1 2 3 / 2 $ ' & r g h $ o o % d q n v 6 l q j o h % d q n & r g h 1 r w h v , i & 6 l v k l j k d w f o r f n k l j k w l p h d o o d s s o l h g f r p p d q g v d u h 1 2 3 7 k h 0 r g h u h j l v w h u p d \ e h o r d g h g s u l r u w r w k h d x w r u h i u h v k f \ f o h v l i g h v l u h g - ( ' ( & d q g 3 & v s h f l i \ w k u h h f o r f n v 2 x w s x w v d u h j x d u d q w h h g + l j k = d i w h u f r p p d q g l v l v v x h g ( ( ( ( ( ( ( 1 2 3 $ 5 ( ) 1 2 3 $ f w l y h 5 r z 5 r z % d q n 5 r z & r o x p q ' d w d ' d w d ' d w d q & / . ( 3 , 6 & . ( ( 3 , 6 & 6 q ( 3 , 6 : ( q ( 3 , 6 5 $ 6 q ( 3 , 6 & $ 6 q ( 3 , 6 ' 4 0 + ' 4 0 / ( 3 , 6 > @ $ ' > @ ( 3 , 6 > @ $ f w l y d w h 1 2 3 1 2 3 5 h d g 1 2 3 % x u v w 7 h u p $ ' > @ g u l y h q l q $ ' > @ g u l y h q r x w $ ' > @ g u l y h q r x w ( ( ( ( ( figure 26-13. sdram write timing table 26-20. epi host-bus 8 and host-bus 16 interface characteristics unit max nom min parameter name parameter parameter no ns --10 read data set up time t isu e14 ns --0 read data hold time t ih e15 ns 5-- wen to write data valid t dv e16 epi clocks --2 data hold from wen invalid t di e17 ns 5--5 csn to output valid t ov e18 ns 5--5 csn to output invalid t oinv e19 epi clocks --2 wen / rdn strobe width low t stlow e20 system clocks --2 fempty and ffull setup time to clock edge t fifo e21 epi clocks -1- ale width high t alehigh e22 epi clocks --4 csn width low t cslow e23 epi clocks --2 ale rising to wen / rdn strobe falling t alest e24 epi clocks --1 ale falling to adn tristate t aleadd e25 1309 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 5 r z & r o x p q ' d w d ' d w d ' d w d q & / . ( 3 , 6 & . ( ( 3 , 6 & 6 q ( 3 , 6 : ( q ( 3 , 6 5 $ 6 q ( 3 , 6 & $ 6 q ( 3 , 6 ' 4 0 + ' 4 0 / ( 3 , 6 > @ $ ' > @ ( 3 , 6 > @ $ f w l y d w h 1 2 3 1 2 3 : u l w h % x u v w 7 h u p $ ' > @ g u l y h q r x w $ ' > @ g u l y h q r x w ( ( ( figure 26-14. host-bus 8/16 mode read timing figure 26-15. host-bus 8/16 mode write timing july 03, 2014 1310 texas instruments-production data electrical characteristics ' d w d $ / ( ( 3 , 6 & 6 q ( 3 , 6 : 5 q ( 3 , 6 5 ' q 2 ( q ( 3 , 6 $ g g u h v v ' d w d ( ( ( ( ( ( ( ( ( % 6 ( / q % 6 ( / q d d % 6 ( / q d q g % 6 ( / q d u h d y d l o d e o h l q + r v w % x v p r g h r q o \ ' d w d $ / ( ( 3 , 6 & 6 q ( 3 , 6 : 5 q ( 3 , 6 5 ' q 2 h q ( 3 , 6 $ g g u h v v ' d w d ( ( ( ( ( ( ( ( % 6 ( / q % 6 ( / q d d % 6 ( / q d q g % 6 ( / q d u h d y d l o d e o h l q + r v w % x v p r g h r q o \ figure 26-16. host-bus 8/16 mode muxed read timing figure 26-17. host-bus 8/16 mode muxed write timing table 26-21. epi general-purpose interface characteristics unit max nom min parameter name parameter parameter no ns -- 20 general-purpose clock period t ck e25 ns -- 10 general-purpose clock high time t ch e26 ns -- 10 general-purpose clock low time t cl e27 ns -- 10 input signal set up time to rising clock edge t isu e28 ns --0 input signal hold time from rising clock edge t ih e29 ns 5- -5 falling clock edge to output valid t dv e30 ns 5- -5 falling clock edge to output invalid t di e31 ns -- 10 irdy assertion or deassertion set up time to falling clock edge t rdysu e32 1311 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller $ g g u h v v ' d w d $ / ( ( 3 , 6 & 6 q ( 3 , 6 : 5 q ( 3 , 6 5 ' q 2 ( q ( 3 , 6 ( ( ( ( ( ( ( ( % 6 ( / q % 6 ( / q d 0 x [ h g $ g g u h v v ' d w d ( ( d % 6 ( / q d q g % 6 ( / q d u h d y d l o d e o h l q + r v w % x v p r g h r q o \ $ / ( ( 3 , 6 & 6 q ( 3 , 6 : 5 q ( 3 , 6 5 ' q 2 h q ( 3 , 6 ( ( ( ( ( ( ( ( % 6 ( / q % 6 ( / q d ' d w d 0 x [ h g $ g g u h v v ' d w d $ g g u h v v d % 6 ( / q d q g % 6 ( / q d u h d y d l o d e o h l q + r v w % x v p r g h r q o \ figure 26-18. general-purpose mode read and write timing the above figure illustrates accesses where the frm50 bit is clear, the frmcnt field is 0x0, the rd2cyc bit is clear, and the wr2cyc bit is clear. figure 26-19. general-purpose mode irdy timing july 03, 2014 1312 texas instruments-production data electrical characteristics 5 h d g ' d w d ( ( ' d w d ( ( ( & o r f n ( 3 , 6 ) u d p h ( 3 , 6 5 ' ( 3 , 6 : 5 ( 3 , 6 $ g g u h v v ' d w d ( ( : u l w h & o r f n ( 3 , 6 ) u d p h ( 3 , 6 5 ' ( 3 , 6 l 5 ' < ( 3 , 6 $ g g u h v v ' d w d ( ( 26.13 analog-to-digital converter (adc) table 26-22. adc characteristics a unit max nom min parameter name parameter v 3.0 -- maximum single-ended, full-scale analog input voltage, using internal reference v adcin v v refa -- maximum single-ended, full-scale analog input voltage, using external reference v - - 0.0 minimum single-ended, full-scale analog input voltage v 1.5 -- maximum differential, full-scale analog input voltage, using internal reference v v refa /2 -- maximum differential, full-scale analog input voltage, using external reference v - - 0.0 minimum differential, full-scale analog input voltage bits 12 resolution n mhz 16.0048 16 15.9952 adc internal clock frequency b f adc s 1 conversion time c t adcconv k samples/s 1000 conversion rate c f adcconv ns - - 125 sample time t adcsamp system clocks - 2 - latency from trigger to start of conversion t lt a 2.0 -- adc input leakage i l k? 10 -- adc equivalent resistance r adc pf 1.1 1.0 0.9 adc equivalent capacitance c adc lsb 8 -- integral nonlinearity (inl) error, 12-bit mode e l lsb 2 -- integral nonlinearity (inl) error, 10-bit mode lsb 4 -- differential nonlinearity (dnl) error, 12-bit mode e d lsb 2 -- differential nonlinearity (dnl) error, 10-bit mode lsb 40 -- offset error, 12-bit mode e o lsb 10 -- offset error, 10-bit mode lsb 100 -- full-scale gain error, 12-bit mode e g lsb 25 -- full-scale gain error, 10-bit mode c 5 -- temperature sensor accuracy d e ts a. the adc reference voltage is 3.0 v. this reference voltage is internally generated from the 3.3 vdda supply by a band gap circuit. b. the adc must be clocked from the pll or directly from an external clock source to operate properly. c. the conversion time and rate scale from the specified number if the adc internal clock frequency is any value other than 16 mhz. d. note that this parameter does not include adc error. 1313 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller figure 26-20. adc input equivalency diagram table 26-23. adc module external reference characteristics a unit max nom min parameter name parameter v 3.03 - 2.97 external voltage reference for adc, when the vref field in the adcctl register is 0x1 b v refa v 1.01 - 0.99 external voltage reference for adc, when the vref field in the adcctl register is 0x3 c a 2.0 - - external voltage reference leakage current i l a. care must be taken to supply a reference voltage of acceptable quality. b. ground is always used as the reference level for the minimum conversion value. c. ground is always used as the reference level for the minimum conversion value. table 26-24. adc module internal reference characteristics unit max nom min parameter name parameter v - 3.0 - internal voltage reference for adc v refi 26.14 synchronous serial interface (ssi) table 26-25. ssi characteristics unit max nom min parameter name parameter parameter no. ns --40 ssiclk cycle time a t clk_per s1 t clk_per -0.5 - ssiclk high time t clk_high s2 t clk_per -0.5 - ssiclk low time t clk_low s3 ns 64- ssiclk rise/fall time b t clkrf s4 system clocks 1-0 data from master valid delay time t dmd s5 system clocks --1 data from master setup time t dms s6 system clocks --2 data from master hold time t dmh s7 july 03, 2014 1314 texas instruments-production data electrical characteristics 6 w h o o d u l v ? 0 l f u r f r q w u r o o h u 6 d p s o h d q g k r o g $ ' & f r q y h u w h u & $ ' & 5 $ ' & 9 ' ' e l w f r q y h u w h u , / 9 , 1 ( 6 ' & o d p s ( 6 ' & o d p s table 26-25. ssi characteristics (continued) unit max nom min parameter name parameter parameter no. system clocks --1 data from slave setup time t dss s8 system clocks --2 data from slave hold time t dsh s9 a. in master mode, the system clock must be at least twice as fast as the ssiclk; in slave mode, the system clock must be at least 12 times faster than the ssiclk. b. note that the delays shown are using 8-ma drive strength. figure 26-21. ssi timing for ti frame format (frf=01), single transfer timing measurement figure 26-22. ssi timing for microwire frame format (frf=10), single transfer 1315 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 6 6 , & o n 6 6 , ) v v 6 6 , 7 [ 6 6 , 5 [ 0 6 % / 6 % 6 6 6 6 w r e l w v 6 6 , & o n 6 6 , ) v v 6 6 , 7 [ 6 6 , 5 [ 0 6 % / 6 % 0 6 % / 6 % 6 6 6 e l w f r q w u r o w r e l w v r x w s x w g d w d figure 26-23. ssi timing for spi frame format (frf=00), with sph=1 26.15 inter-integrated circuit (i 2 c) interface table 26-26. i 2 c characteristics unit max nom min parameter name parameter parameter no. system clocks --36 start condition hold time t sch i1 a system clocks --36 clock low period t lp i2 a ns (see note b) -- i2cscl/ i2csda rise time (v il =0.5 v to v ih =2.4 v) t srt i3 b system clocks --2 data hold time t dh i4 a ns 10 9- i2cscl/ i2csda fall time (v ih =2.4 v to v il =0.5 v) t sft i5 c system clocks --24 clock high time t ht i6 a system clocks --18 data setup time t ds i7 a system clocks --36 start condition setup time (for repeated start condition only) t scsr i8 a system clocks --24 stop condition setup time t scs i9 a a. values depend on the value programmed into the tpr bit in the i 2 c master timer period (i2cmtpr) register; a tpr programmed for the maximum i2cscl frequency (tpr=0x2) results in a minimum output timing as shown in the table above. the i 2 c interface is designed to scale the actual data transition time to move it to the middle of the i2cscl low period. the actual position is affected by the value programmed into the tpr ; however, the numbers given in the above values are minimum values. b. because i2cscl and i2csda operate as open-drain-type signals, which the controller can only actively drive low, the time i2cscl or i2csda takes to reach a high level depends on external signal capacitance and pull-up resistor values. c. specified at a nominal 50 pf load. july 03, 2014 1316 texas instruments-production data electrical characteristics 6 6 , & o n 6 3 2 6 6 , 7 [ p d v w h u 6 6 , 5 [ v o d y h / 6 % 6 6 , & o n 6 3 2 6 6 6 6 6 , ) v v / 6 % 6 0 6 % 6 6 6 6 6 0 6 % figure 26-24. i 2 c timing 26.16 inter-integrated circuit sound (i 2 s) interface table 26-27. i 2 s master clock (receive and transmit) unit max nom min parameter name parameter parameter no. ns - - 20.3 cycle time t mclk_per m1 ns see input/output characteristics on page 1307. rise/fall time t mclkrf m2 ns - - 10 high time t mclk_high m3 ns - - 10 low time t mclk_low m4 % 52 - 48 duty cycle t mdc m5 ns 2.5 - - jitter t mjitter m6 table 26-28. i 2 s slave clock (receive and transmit) unit max nom min parameter name parameter parameter no. ns - - 80 cycle time t sclk_per m7 ns - - 40 high time t sclk_high m8 ns - - 40 low time t sclk_low m9 % - 50 - duty cycle t sdc m10 table 26-29. i 2 s master mode unit max nom min parameter name parameter parameter no. ns 10 -- sck fall to ws valid t msws m11 ns 10 -- sck fall to txsd valid t msd m12 ns -- 10 rxsd setup time to sck rise t msds m13 ns -- 10 rxsd hold time from sck rise t msdh m14 figure 26-25. i 2 s master mode transmit timing 1317 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller , & 6 & / , & 6 ' $ , , , , , , , , , ' d w d 6 & . : 6 7 ; 6 ' 0 0 figure 26-26. i 2 s master mode receive timing table 26-30. i 2 s slave mode unit max nom min parameter name parameter parameter no. ns -- 80 cycle time t sclk_per m15 ns -- 40 high time t sclk_high m16 ns -- 40 low time t sclk_low m17 % - 50 - duty cycle t sdc m18 ns 25 -- ws setup time to sck rise t ssetup m19 ns 10 -- ws hold time from sck rise t shold m20 ns 20 -- sck fall to txsd valid t ssd m21 ns 20 -- left-justified mode, ws to txsd t slsd m22 ns -- 10 rxsd setup time to sck rise t ssds m23 ns -- 10 rxsd hold time from sck rise t ssdh m24 figure 26-27. i 2 s slave mode transmit timing figure 26-28. i 2 s slave mode receive timing 26.17 ethernet controller table 26-31. ethernet station management unit max nom min parameter name parameter parameter no. ns -- 400 mdc cycle time t mdc n1 ns -- 160 mdc high time t mdch n2 july 03, 2014 1318 texas instruments-production data electrical characteristics ' d w d 6 & . 5 ; 6 ' 0 0 ' d w d 6 & . : 6 7 ; 6 ' 0 0 0 0 ' d w d 6 & . 5 ; 6 ' 0 0 table 26-31. ethernet station management (continued) unit max nom min parameter name parameter parameter no. ns -- 160 mdc low time t mdcl n3 ns -- 100 mdio write data valid time t mdio_val n4 ns 100 - - mdio write data invalid time t mdio_inv n5 ns -- 10 mdio read data set up time t mdio_su n6 ns -- 10 mdio read data hold time t mdio_h n7 table 26-32. 100base-tx transmitter characteristics a unit max nom min parameter name mvpk 1050 - 950 peak output amplitude % 102 - 98 output amplitude symmetry % 5 - - output overshoot ns 5 - 3 rise/fall time ps 500 - - rise/fall time imbalance ps 250 - - duty cycle distortion ns 1.4 - - jitter a. measured at the line side of the transformer. table 26-33. 100base-tx transmitter characteristics (informative) a unit max nom min parameter name db - - 16 return loss h - - 350 open-circuit inductance a. the specifications in this table are included for information only. they are mainly a function of the external transformer and termination resistors used for measurements. table 26-34. 100base-tx receiver characteristics unit max nom min parameter name mvppd - 700 600 signal detect assertion threshold mvppd - 425 350 signal detect de-assertion threshold k? - 3.6 - differential input resistance ns - - 4 jitter tolerance (pk-pk) % +80 - -80 baseline wander tracking s 1000 - - signal detect assertion time s 4 - - signal detect de-assertion time table 26-35. 10base-t transmitter characteristics a unit max nom min parameter name v 2.7 - 2.2 peak differential output signal db - - 27 harmonic content ns - 100 - link pulse width ns - 300 - start-of-idle pulse width, last bit 0 1319 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller table 26-35. 10base-t transmitter characteristics (continued) unit max nom min parameter name ns - 350 - start-of-idle pulse width, last bit 1 a. the manchester-encoded data pulses, the link pulse and the start-of-idle pulse are tested against the templates and using the procedures found in clause 14 of ieee 802.3 . table 26-36. 10base-t transmitter characteristics (informative) a unit max nom min parameter name db - - 15 output return loss db - - 29-17log(f/10) output impedance balance mv 50 - - peak common-mode output voltage mv 100 - - common-mode rejection ns 1 - - common-mode rejection jitter a. the specifications in this table are included for information only. they are mainly a function of the external transformer and termination resistors used for measurements. table 26-37. 10base-t receiver characteristics unit max nom min parameter name ns - 26 30 jitter tolerance (pk-pk) mvppd 540 440 340 input squelched threshold k? - 3.6 - differential input resistance v - - 25 common-mode rejection table 26-38. isolation transformers a condition value name +/- 5% 1 ct : 1 ct turns ratio @ 10 mv, 10 khz 350 uh (min) open-circuit inductance @ 1 mhz (min) 0.40 uh (max) leakage inductance 25 pf (max) inter-winding capacitance 0.9 ohm (max) dc resistance 0-65 mhz 0.4 db (typ) insertion loss vrms 1500 hipot a. two simple 1:1 isolation transformers are required at the line interface. transformers with integrated common-mode chokes are recommended for exceeding fcc requirements. this table gives the recommended line transformer characteristics. note: the 100base-tx amplitude specifications assume a transformer loss of 0.4 db. 26.18 universal serial bus (usb) controller the stellaris ? usb controller electrical specifications are compliant with the universal serial bus specification rev. 2.0 (full-speed and low-speed support) and the on-the-go supplement to the usb 2.0 specification rev. 1.0 . some components of the usb system are integrated within the lm3s9gn5 microcontroller and specific to the stellaris microcontroller design. an external component resistor is needed as specified in table 26-39. july 03, 2014 1320 texas instruments-production data electrical characteristics table 26-39. usb controller characteristics unit value parameter name parameter ? 9.1k 1 % value of the pull-down resistor on the usb0rbias pin r ubias 26.19 analog comparator table 26-40. analog comparator characteristics unit max nom min parameter name parameter v v dd - gnd input voltage range v inp ,v inn v v dd -1.5 - gnd input common mode voltage range v cm mv 25 10 - input offset voltage v os db - - 50 common mode rejection ratio c mrr s 1.0 - - response time t rt s 10 - - comparator mode change to output valid t mc table 26-41. analog comparator voltage reference characteristics unit max nom min parameter name parameter v - v dda /31 - resolution in high range r hr v - v dda /23 - resolution in low range r lr v r hr /2 - - absolute accuracy high range a hr v r lr /4 - - absolute accuracy low range a lr 26.20 current consumption this section provides information on typical and maximum power consumption under various conditions. unless otherwise indicated, current consumption numbers include use of the on-chip ldo regulator and therefore include i ddc . 26.20.1 nominal power consumption the following table provides nominal figures for current consumption. table 26-42. nominal power consumption unit nom conditions parameter name parameter ma 111 v dd = 3.3 v code= while(1){} executed out of flash peripherals = all on system clock = 80 mhz (with pll) temp = 25c run mode 1 (flash loop) i dd_run ma 20 v dd = 3.3 v peripherals = all clock gated system clock = 80 mhz (with pll) temp = 25c sleep mode i dd_sleep a 550 peripherals = all off system clock = iosc30khz/64 temp = 25c deep-sleep mode i dd_deepsleep 1321 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 26.20.2 maximum current consumption the current measurements specified in the table that follows are maximum values under the following conditions: v dd = 3.6 v v ddc = 1.3 v v dda = 3.6 v temperature = 25c clock source (mosc) = 16.348-mhz crystal oscillator table 26-43. detailed current specifications unit max conditions parameter name parameter ma 149 v dd = 3.6 v code= while(1){} executed out of flash peripherals = all on system clock = 80 mhz (with pll) temperature = 85c run mode 1 (flash loop) i dd_run ma 46 v dd = 3.6 v peripherals = all clock gated system clock = 80 mhz (with pll) temperature = 85c sleep mode i dd_sleep ma 1.8 v dd = 3.6 v peripherals = all clock gated system clock = iosc30/64 temperature = 85c deep-sleep mode i dd_deepsleep july 03, 2014 1322 texas instruments-production data electrical characteristics a register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 the cortex-m3 processor r0, type r/w, , reset - (see page 76) data data r1, type r/w, , reset - (see page 76) data data r2, type r/w, , reset - (see page 76) data data r3, type r/w, , reset - (see page 76) data data r4, type r/w, , reset - (see page 76) data data r5, type r/w, , reset - (see page 76) data data r6, type r/w, , reset - (see page 76) data data r7, type r/w, , reset - (see page 76) data data r8, type r/w, , reset - (see page 76) data data r9, type r/w, , reset - (see page 76) data data r10, type r/w, , reset - (see page 76) data data r11, type r/w, , reset - (see page 76) data data r12, type r/w, , reset - (see page 76) data data sp, type r/w, , reset - (see page 77) sp sp lr, type r/w, , reset 0xffff.ffff (see page 78) link link pc, type r/w, , reset - (see page 79) pc pc 1323 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 psr, type r/w, , reset 0x0100.0000 (see page 80) thumb ici / it q v c z n isrnum ici / it primask, type r/w, , reset 0x0000.0000 (see page 84) primask faultmask, type r/w, , reset 0x0000.0000 (see page 85) faultmask basepri, type r/w, , reset 0x0000.0000 (see page 86) basepri control, type r/w, , reset 0x0000.0000 (see page 87) tmpl asp cortex-m3 peripherals system timer (systick) registers base 0xe000.e000 stctrl, type r/w, offset 0x010, reset 0x0000.0004 count enable inten clk_src streload, type r/w, offset 0x014, reset 0x0000.0000 reload reload stcurrent, type r/wc, offset 0x018, reset 0x0000.0000 current current cortex-m3 peripherals nested vectored interrupt controller (nvic) registers base 0xe000.e000 en0, type r/w, offset 0x100, reset 0x0000.0000 int int en1, type r/w, offset 0x104, reset 0x0000.0000 int int dis0, type r/w, offset 0x180, reset 0x0000.0000 int int dis1, type r/w, offset 0x184, reset 0x0000.0000 int int pend0, type r/w, offset 0x200, reset 0x0000.0000 int int pend1, type r/w, offset 0x204, reset 0x0000.0000 int int unpend0, type r/w, offset 0x280, reset 0x0000.0000 int int july 03, 2014 1324 texas instruments-production data register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 unpend1, type r/w, offset 0x284, reset 0x0000.0000 int int active0, type ro, offset 0x300, reset 0x0000.0000 int int active1, type ro, offset 0x304, reset 0x0000.0000 int int pri0, type r/w, offset 0x400, reset 0x0000.0000 intc intd inta intb pri1, type r/w, offset 0x404, reset 0x0000.0000 intc intd inta intb pri2, type r/w, offset 0x408, reset 0x0000.0000 intc intd inta intb pri3, type r/w, offset 0x40c, reset 0x0000.0000 intc intd inta intb pri4, type r/w, offset 0x410, reset 0x0000.0000 intc intd inta intb pri5, type r/w, offset 0x414, reset 0x0000.0000 intc intd inta intb pri6, type r/w, offset 0x418, reset 0x0000.0000 intc intd inta intb pri7, type r/w, offset 0x41c, reset 0x0000.0000 intc intd inta intb pri8, type r/w, offset 0x420, reset 0x0000.0000 intc intd inta intb pri9, type r/w, offset 0x424, reset 0x0000.0000 intc intd inta intb pri10, type r/w, offset 0x428, reset 0x0000.0000 intc intd inta intb pri11, type r/w, offset 0x42c, reset 0x0000.0000 intc intd inta intb pri12, type r/w, offset 0x430, reset 0x0000.0000 intc intd inta intb pri13, type r/w, offset 0x434, reset 0x0000.0000 intc intd inta intb 1325 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 swtrig, type wo, offset 0xf00, reset 0x0000.0000 intid cortex-m3 peripherals system control block (scb) registers base 0xe000.e000 actlr, type r/w, offset 0x008, reset 0x0000.0000 dismcyc diswbuf disfold cpuid, type ro, offset 0xd00, reset 0x412f.c230 con var imp rev partno intctrl, type r/w, offset 0xd04, reset 0x0000.0000 vecpend isrpend isrpre pendstclr pendstset unpendsv pendsv nmiset vecact retbase vecpend vtable, type r/w, offset 0xd08, reset 0x0000.0000 offset base offset apint, type r/w, offset 0xd0c, reset 0xfa05.0000 vectkey vectreset vectclract sysresreq prigroup endianess sysctrl, type r/w, offset 0xd10, reset 0x0000.0000 sleepexit sleepdeep sevonpend cfgctrl, type r/w, offset 0xd14, reset 0x0000.0200 basethr mainpend unaligned div0 bfhfnmign stkalign syspri1, type r/w, offset 0xd18, reset 0x0000.0000 usage mem bus syspri2, type r/w, offset 0xd1c, reset 0x0000.0000 svc syspri3, type r/w, offset 0xd20, reset 0x0000.0000 pendsv tick debug syshndctrl, type r/w, offset 0xd24, reset 0x0000.0000 mem bus usage mema busa usga svca mon pndsv tick usagep memp busp svc faultstat, type r/w1c, offset 0xd28, reset 0x0000.0000 undef invstat invpc nocp unalign div0 ierr derr mustke mstke mmarv ibus precise impre bustke bstke bfarv hfaultstat, type r/w1c, offset 0xd2c, reset 0x0000.0000 forced dbg vect mmaddr, type r/w, offset 0xd34, reset - addr addr faultaddr, type r/w, offset 0xd38, reset - addr addr july 03, 2014 1326 texas instruments-production data register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cortex-m3 peripherals memory protection unit (mpu) registers base 0xe000.e000 mputype, type ro, offset 0xd90, reset 0x0000.0800 iregion separate dregion mpuctrl, type r/w, offset 0xd94, reset 0x0000.0000 enable hfnmiena privdefen mpunumber, type r/w, offset 0xd98, reset 0x0000.0000 number mpubase, type r/w, offset 0xd9c, reset 0x0000.0000 addr region valid addr mpubase1, type r/w, offset 0xda4, reset 0x0000.0000 addr region valid addr mpubase2, type r/w, offset 0xdac, reset 0x0000.0000 addr region valid addr mpubase3, type r/w, offset 0xdb4, reset 0x0000.0000 addr region valid addr mpuattr, type r/w, offset 0xda0, reset 0x0000.0000 b c s tex ap xn enable size srd mpuattr1, type r/w, offset 0xda8, reset 0x0000.0000 b c s tex ap xn enable size srd mpuattr2, type r/w, offset 0xdb0, reset 0x0000.0000 b c s tex ap xn enable size srd mpuattr3, type r/w, offset 0xdb8, reset 0x0000.0000 b c s tex ap xn enable size srd system control base 0x400f.e000 did0, type ro, offset 0x000, reset - (see page 208) class ver minor major pborctl, type r/w, offset 0x030, reset 0x0000.0002 (see page 210) borior ris, type ro, offset 0x050, reset 0x0000.0000 (see page 211) borris plllris usbplllris moscpupris imc, type r/w, offset 0x054, reset 0x0000.0000 (see page 213) borim plllim usbplllim moscpupim 1327 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 misc, type r/w1c, offset 0x058, reset 0x0000.0000 (see page 215) bormis plllmis usbplllmis moscpupmis resc, type r/w, offset 0x05c, reset - (see page 217) moscfail ext por bor wdt0 sw wdt1 rcc, type r/w, offset 0x060, reset 0x078e.3ad1 (see page 219) pwmdiv usepwmdiv usesysdiv sysdiv acg moscdis ioscdis oscsrc xtal bypass pwrdn pllcfg, type ro, offset 0x064, reset - (see page 224) r f gpiohbctl, type r/w, offset 0x06c, reset 0x0000.0000 (see page 225) porta portb portc portd porte portf portg porth portj rcc2, type r/w, offset 0x070, reset 0x07c0.6810 (see page 227) sysdiv2lsb sysdiv2 div400 usercc2 oscsrc2 bypass2 pwrdn2 usbpwrdn moscctl, type r/w, offset 0x07c, reset 0x0000.0000 (see page 230) cval dslpclkcfg, type r/w, offset 0x144, reset 0x0780.0000 (see page 231) dsdivoride dsoscsrc piosccal, type r/w, offset 0x150, reset 0x0000.0000 (see page 233) uten ut update i2smclkcfg, type r/w, offset 0x170, reset 0x0000.0000 (see page 234) rxf rxi rxen txf txi txen did1, type ro, offset 0x004, reset - (see page 236) partno fam ver qual rohs pkg temp pincount dc0, type ro, offset 0x008, reset 0x00ff.00bf (see page 238) sramsz flashsz dc1, type ro, offset 0x010, reset - (see page 239) adc0 adc1 pwm can0 can1 wdt1 jtag swd swo wdt0 pll tempsns mpu maxadc0spd maxadc1spd minsysdiv dc2, type ro, offset 0x014, reset 0x570f.5337 (see page 242) timer0 timer1 timer2 timer3 comp0 comp1 comp2 i2s0 epi0 uart0 uart1 uart2 ssi0 ssi1 qei0 qei1 i2c0 i2c1 dc3, type ro, offset 0x018, reset 0xbfff.ffff (see page 244) adc0ain0 adc0ain1 adc0ain2 adc0ain3 adc0ain4 adc0ain5 adc0ain6 adc0ain7 ccp0 ccp1 ccp2 ccp3 ccp4 ccp5 32khz pwm0 pwm1 pwm2 pwm3 pwm4 pwm5 c0minus c0plus c0o c1minus c1plus c1o c2minus c2plus c2o pwmfault dc4, type ro, offset 0x01c, reset 0x1104.f1ff (see page 247) pical e1588 emac0 gpioa gpiob gpioc gpiod gpioe gpiof gpiog gpioh gpioj rom udma ccp6 ccp7 dc5, type ro, offset 0x020, reset 0x0f30.00ff (see page 249) pwmesync pwmeflt pwmfault0 pwmfault1 pwmfault2 pwmfault3 pwm0 pwm1 pwm2 pwm3 pwm4 pwm5 pwm6 pwm7 july 03, 2014 1328 texas instruments-production data register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dc6, type ro, offset 0x024, reset 0x0000.0013 (see page 251) usb0 usb0phy dc7, type ro, offset 0x028, reset 0xffff.ffff (see page 252) dmach16 dmach17 dmach18 dmach19 dmach20 dmach21 dmach22 dmach23 dmach24 dmach25 dmach26 dmach27 dmach28 dmach29 dmach30 dmach0 dmach1 dmach2 dmach3 dmach4 dmach5 dmach6 dmach7 dmach8 dmach9 dmach10 dmach11 dmach12 dmach13 dmach14 dmach15 dc8, type ro, offset 0x02c, reset 0xffff.ffff (see page 256) adc1ain0 adc1ain1 adc1ain2 adc1ain3 adc1ain4 adc1ain5 adc1ain6 adc1ain7 adc1ain8 adc1ain9 adc1ain10 adc1ain11 adc1ain12 adc1ain13 adc1ain14 adc1ain15 adc0ain0 adc0ain1 adc0ain2 adc0ain3 adc0ain4 adc0ain5 adc0ain6 adc0ain7 adc0ain8 adc0ain9 adc0ain10 adc0ain11 adc0ain12 adc0ain13 adc0ain14 adc0ain15 dc9, type ro, offset 0x190, reset 0x00ff.00ff (see page 259) adc1dc0 adc1dc1 adc1dc2 adc1dc3 adc1dc4 adc1dc5 adc1dc6 adc1dc7 adc0dc0 adc0dc1 adc0dc2 adc0dc3 adc0dc4 adc0dc5 adc0dc6 adc0dc7 nvmstat, type ro, offset 0x1a0, reset 0x0000.0001 (see page 261) fwb rcgc0, type r/w, offset 0x100, reset 0x00000040 (see page 262) adc0 adc1 pwm can0 can1 wdt1 wdt0 maxadc0spd maxadc1spd scgc0, type r/w, offset 0x110, reset 0x00000040 (see page 265) adc0 adc1 pwm can0 can1 wdt1 wdt0 maxadc0spd maxadc1spd dcgc0, type r/w, offset 0x120, reset 0x00000040 (see page 268) adc0 adc1 pwm can0 can1 wdt1 wdt0 rcgc1, type r/w, offset 0x104, reset 0x00000000 (see page 270) timer0 timer1 timer2 timer3 comp0 comp1 comp2 i2s0 epi0 uart0 uart1 uart2 ssi0 ssi1 qei0 qei1 i2c0 i2c1 scgc1, type r/w, offset 0x114, reset 0x00000000 (see page 274) timer0 timer1 timer2 timer3 comp0 comp1 comp2 i2s0 epi0 uart0 uart1 uart2 ssi0 ssi1 qei0 qei1 i2c0 i2c1 dcgc1, type r/w, offset 0x124, reset 0x00000000 (see page 278) timer0 timer1 timer2 timer3 comp0 comp1 comp2 i2s0 epi0 uart0 uart1 uart2 ssi0 ssi1 qei0 qei1 i2c0 i2c1 rcgc2, type r/w, offset 0x108, reset 0x00000000 (see page 282) usb0 emac0 gpioa gpiob gpioc gpiod gpioe gpiof gpiog gpioh gpioj udma scgc2, type r/w, offset 0x118, reset 0x00000000 (see page 285) usb0 emac0 gpioa gpiob gpioc gpiod gpioe gpiof gpiog gpioh gpioj udma dcgc2, type r/w, offset 0x128, reset 0x00000000 (see page 288) usb0 emac0 gpioa gpiob gpioc gpiod gpioe gpiof gpiog gpioh gpioj udma srcr0, type r/w, offset 0x040, reset 0x00000000 (see page 291) adc0 adc1 pwm can0 can1 wdt1 wdt0 srcr1, type r/w, offset 0x044, reset 0x00000000 (see page 293) timer0 timer1 timer2 timer3 comp0 comp1 comp2 i2s0 epi0 uart0 uart1 uart2 ssi0 ssi1 qei0 qei1 i2c0 i2c1 srcr2, type r/w, offset 0x048, reset 0x00000000 (see page 296) usb0 emac0 gpioa gpiob gpioc gpiod gpioe gpiof gpiog gpioh gpioj udma 1329 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 internal memory flash memory registers (flash control offset) base 0x400f.d000 fma, type r/w, offset 0x000, reset 0x0000.0000 offset offset fmd, type r/w, offset 0x004, reset 0x0000.0000 data data fmc, type r/w, offset 0x008, reset 0x0000.0000 wrkey write erase merase comt fcris, type ro, offset 0x00c, reset 0x0000.0000 aris pris fcim, type r/w, offset 0x010, reset 0x0000.0000 amask pmask fcmisc, type r/w1c, offset 0x014, reset 0x0000.0000 amisc pmisc fmc2, type r/w, offset 0x020, reset 0x0000.0000 wrkey wrbuf fwbval, type r/w, offset 0x030, reset 0x0000.0000 fwb[n] fwb[n] fctl, type r/w, offset 0x0f8, reset 0x0000.0000 usdreq usdack fwbn, type r/w, offset 0x100 - 0x17c, reset 0x0000.0000 data data internal memory memory registers (system control offset) base 0x400f.e000 rmctl, type r/w1c, offset 0x0f0, reset - ba fmpre0, type r/w, offset 0x130 and 0x200, reset 0xffff.ffff read_enable read_enable fmppe0, type r/w, offset 0x134 and 0x400, reset 0xffff.ffff prog_enable prog_enable bootcfg, type r/w, offset 0x1d0, reset 0xffff.fffe nw dbg0 dbg1 en pol pin port user_reg0, type r/w, offset 0x1e0, reset 0xffff.ffff data nw data july 03, 2014 1330 texas instruments-production data register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 user_reg1, type r/w, offset 0x1e4, reset 0xffff.ffff data nw data user_reg2, type r/w, offset 0x1e8, reset 0xffff.ffff data nw data user_reg3, type r/w, offset 0x1ec, reset 0xffff.ffff data nw data fmpre1, type r/w, offset 0x204, reset 0xffff.ffff read_enable read_enable fmpre2, type r/w, offset 0x208, reset 0xffff.ffff read_enable read_enable fmpre3, type r/w, offset 0x20c, reset 0xffff.ffff read_enable read_enable fmpre4, type r/w, offset 0x210, reset 0xffff.ffff read_enable read_enable fmpre5, type r/w, offset 0x214, reset 0xffff.ffff read_enable read_enable fmpre6, type r/w, offset 0x218, reset 0x0000.0000 read_enable read_enable fmpre7, type r/w, offset 0x21c, reset 0x0000.0000 read_enable read_enable fmppe1, type r/w, offset 0x404, reset 0xffff.ffff prog_enable prog_enable fmppe2, type r/w, offset 0x408, reset 0xffff.ffff prog_enable prog_enable fmppe3, type r/w, offset 0x40c, reset 0xffff.ffff prog_enable prog_enable fmppe4, type r/w, offset 0x410, reset 0xffff.ffff prog_enable prog_enable fmppe5, type r/w, offset 0x414, reset 0xffff.ffff prog_enable prog_enable fmppe6, type r/w, offset 0x418, reset 0x0000.0000 prog_enable prog_enable fmppe7, type r/w, offset 0x41c, reset 0x0000.0000 prog_enable prog_enable 1331 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 micro direct memory access (dma) dma channel control structure (offset from channel control table base) base n/a dmasrcendp, type r/w, offset 0x000, reset - addr addr dmadstendp, type r/w, offset 0x004, reset - addr addr dmachctl, type r/w, offset 0x008, reset - arbsize srcsize srcinc dstsize dstinc xfermode nxtuseburst xfersize arbsize micro direct memory access (dma) dma registers (offset from dma base address) base 0x400f.f000 dmastat, type ro, offset 0x000, reset 0x001f.0000 dmachans masten state dmacfg, type wo, offset 0x004, reset - masten dmactlbase, type r/w, offset 0x008, reset 0x0000.0000 addr addr dmaaltbase, type ro, offset 0x00c, reset 0x0000.0200 addr addr dmawaitstat, type ro, offset 0x010, reset 0xffff.ffc0 waitreq[n] waitreq[n] dmaswreq, type wo, offset 0x014, reset - swreq[n] swreq[n] dmauseburstset, type r/w, offset 0x018, reset 0x0000.0000 set[n] set[n] dmauseburstclr, type wo, offset 0x01c, reset - clr[n] clr[n] dmareqmaskset, type r/w, offset 0x020, reset 0x0000.0000 set[n] set[n] dmareqmaskclr, type wo, offset 0x024, reset - clr[n] clr[n] dmaenaset, type r/w, offset 0x028, reset 0x0000.0000 set[n] set[n] july 03, 2014 1332 texas instruments-production data register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dmaenaclr, type wo, offset 0x02c, reset - clr[n] clr[n] dmaaltset, type r/w, offset 0x030, reset 0x0000.0000 set[n] set[n] dmaaltclr, type wo, offset 0x034, reset - clr[n] clr[n] dmaprioset, type r/w, offset 0x038, reset 0x0000.0000 set[n] set[n] dmaprioclr, type wo, offset 0x03c, reset - clr[n] clr[n] dmaerrclr, type r/w, offset 0x04c, reset 0x0000.0000 errclr dmachasgn, type r/w, offset 0x500, reset 0x0000.0000 chasgn[n] chasgn[n] dmachis, type r/w1c, offset 0x504, reset 0x0000.0000 chis[n] chis[n] dmaperiphid0, type ro, offset 0xfe0, reset 0x0000.0030 pid0 dmaperiphid1, type ro, offset 0xfe4, reset 0x0000.00b2 pid1 dmaperiphid2, type ro, offset 0xfe8, reset 0x0000.000b pid2 dmaperiphid3, type ro, offset 0xfec, reset 0x0000.0000 pid3 dmaperiphid4, type ro, offset 0xfd0, reset 0x0000.0004 pid4 dmapcellid0, type ro, offset 0xff0, reset 0x0000.000d cid0 dmapcellid1, type ro, offset 0xff4, reset 0x0000.00f0 cid1 dmapcellid2, type ro, offset 0xff8, reset 0x0000.0005 cid2 dmapcellid3, type ro, offset 0xffc, reset 0x0000.00b1 cid3 1333 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 general-purpose input/outputs (gpios) gpio port a (apb) base: 0x4000.4000 gpio port a (ahb) base: 0x4005.8000 gpio port b (apb) base: 0x4000.5000 gpio port b (ahb) base: 0x4005.9000 gpio port c (apb) base: 0x4000.6000 gpio port c (ahb) base: 0x4005.a000 gpio port d (apb) base: 0x4000.7000 gpio port d (ahb) base: 0x4005.b000 gpio port e (apb) base: 0x4002.4000 gpio port e (ahb) base: 0x4005.c000 gpio port f (apb) base: 0x4002.5000 gpio port f (ahb) base: 0x4005.d000 gpio port g (apb) base: 0x4002.6000 gpio port g (ahb) base: 0x4005.e000 gpio port h (apb) base: 0x4002.7000 gpio port h (ahb) base: 0x4005.f000 gpio port j (apb) base: 0x4003.d000 gpio port j (ahb) base: 0x4006.0000 gpiodata, type r/w, offset 0x000, reset 0x0000.0000 (see page 419) data gpiodir, type r/w, offset 0x400, reset 0x0000.0000 (see page 420) dir gpiois, type r/w, offset 0x404, reset 0x0000.0000 (see page 421) is gpioibe, type r/w, offset 0x408, reset 0x0000.0000 (see page 422) ibe gpioiev, type r/w, offset 0x40c, reset 0x0000.0000 (see page 423) iev gpioim, type r/w, offset 0x410, reset 0x0000.0000 (see page 424) ime gpioris, type ro, offset 0x414, reset 0x0000.0000 (see page 425) ris gpiomis, type ro, offset 0x418, reset 0x0000.0000 (see page 426) mis gpioicr, type w1c, offset 0x41c, reset 0x0000.0000 (see page 428) ic gpioafsel, type r/w, offset 0x420, reset - (see page 429) afsel gpiodr2r, type r/w, offset 0x500, reset 0x0000.00ff (see page 431) drv2 gpiodr4r, type r/w, offset 0x504, reset 0x0000.0000 (see page 432) drv4 gpiodr8r, type r/w, offset 0x508, reset 0x0000.0000 (see page 433) drv8 july 03, 2014 1334 texas instruments-production data register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 gpioodr, type r/w, offset 0x50c, reset 0x0000.0000 (see page 434) ode gpiopur, type r/w, offset 0x510, reset - (see page 435) pue gpiopdr, type r/w, offset 0x514, reset 0x0000.0000 (see page 437) pde gpioslr, type r/w, offset 0x518, reset 0x0000.0000 (see page 439) srl gpioden, type r/w, offset 0x51c, reset - (see page 440) den gpiolock, type r/w, offset 0x520, reset 0x0000.0001 (see page 442) lock lock gpiocr, type -, offset 0x524, reset - (see page 443) cr gpioamsel, type r/w, offset 0x528, reset 0x0000.0000 (see page 445) gpioamsel gpiopctl, type r/w, offset 0x52c, reset - (see page 447) pmc4 pmc5 pmc6 pmc7 pmc0 pmc1 pmc2 pmc3 gpioperiphid4, type ro, offset 0xfd0, reset 0x0000.0000 (see page 449) pid4 gpioperiphid5, type ro, offset 0xfd4, reset 0x0000.0000 (see page 450) pid5 gpioperiphid6, type ro, offset 0xfd8, reset 0x0000.0000 (see page 451) pid6 gpioperiphid7, type ro, offset 0xfdc, reset 0x0000.0000 (see page 452) pid7 gpioperiphid0, type ro, offset 0xfe0, reset 0x0000.0061 (see page 453) pid0 gpioperiphid1, type ro, offset 0xfe4, reset 0x0000.0000 (see page 454) pid1 gpioperiphid2, type ro, offset 0xfe8, reset 0x0000.0018 (see page 455) pid2 gpioperiphid3, type ro, offset 0xfec, reset 0x0000.0001 (see page 456) pid3 1335 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 gpiopcellid0, type ro, offset 0xff0, reset 0x0000.000d (see page 457) cid0 gpiopcellid1, type ro, offset 0xff4, reset 0x0000.00f0 (see page 458) cid1 gpiopcellid2, type ro, offset 0xff8, reset 0x0000.0005 (see page 459) cid2 gpiopcellid3, type ro, offset 0xffc, reset 0x0000.00b1 (see page 460) cid3 external peripheral interface (epi) base 0x400d.0000 epicfg, type r/w, offset 0x000, reset 0x0000.0000 (see page 493) mode blken epibaud, type r/w, offset 0x004, reset 0x0000.0000 (see page 494) count1 count0 episdramcfg, type r/w, offset 0x010, reset 0x82ee.0000 (see page 496) rfsh freq size sleep epihb8cfg, type r/w, offset 0x010, reset 0x0000.ff00 (see page 498) rdhigh wrhigh xfeen xffen mode rdws wrws maxwait epihb16cfg, type r/w, offset 0x010, reset 0x0000.ff00 (see page 501) rdhigh wrhigh xfeen xffen mode bsel rdws wrws maxwait epigpcfg, type r/w, offset 0x010, reset 0x0000.0000 (see page 505) rd2cyc wr2cyc rw frmcnt frm50 frmpin rdyen clkgate clkpin dsize asize maxwait epihb8cfg2, type r/w, offset 0x014, reset 0x0000.0000 (see page 510) rdhigh wrhigh cscfg csbaud word rdws wrws epihb16cfg2, type r/w, offset 0x014, reset 0x0000.0000 (see page 513) rdhigh wrhigh cscfg csbaud word wrws epigpcfg2, type r/w, offset 0x014, reset 0x0000.0000 (see page 516) word epiaddrmap, type r/w, offset 0x01c, reset 0x0000.0000 (see page 517) eradr ersz epadr epsz epirsize0, type r/w, offset 0x020, reset 0x0000.0003 (see page 519) size epirsize1, type r/w, offset 0x030, reset 0x0000.0003 (see page 519) size epiraddr0, type r/w, offset 0x024, reset 0x0000.0000 (see page 520) addr addr july 03, 2014 1336 texas instruments-production data register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 epiraddr1, type r/w, offset 0x034, reset 0x0000.0000 (see page 520) addr addr epirpstd0, type r/w, offset 0x028, reset 0x0000.0000 (see page 521) postcnt epirpstd1, type r/w, offset 0x038, reset 0x0000.0000 (see page 521) postcnt epistat, type ro, offset 0x060, reset 0x0000.0000 (see page 523) active nbrbusy wbusy initseq xfempty xffull celow epirfifocnt, type ro, offset 0x06c, reset - (see page 525) count epireadfifo, type ro, offset 0x070, reset - (see page 526) data data epireadfifo1, type ro, offset 0x074, reset - (see page 526) data data epireadfifo2, type ro, offset 0x078, reset - (see page 526) data data epireadfifo3, type ro, offset 0x07c, reset - (see page 526) data data epireadfifo4, type ro, offset 0x080, reset - (see page 526) data data epireadfifo5, type ro, offset 0x084, reset - (see page 526) data data epireadfifo6, type ro, offset 0x088, reset - (see page 526) data data epireadfifo7, type ro, offset 0x08c, reset - (see page 526) data data epififolvl, type r/w, offset 0x200, reset 0x0000.0033 (see page 527) rserr wferr rdfifo wrfifo epiwfifocnt, type ro, offset 0x204, reset 0x0000.0004 (see page 529) wtav epiim, type r/w, offset 0x210, reset 0x0000.0000 (see page 530) errim rdim wrim epiris, type ro, offset 0x214, reset 0x0000.0004 (see page 531) errris rdris wrris 1337 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 epimis, type ro, offset 0x218, reset 0x0000.0000 (see page 533) errmis rdmis wrmis epieisc, type r/w1c, offset 0x21c, reset 0x0000.0000 (see page 534) tout rstall wtfull general-purpose timers timer 0 base: 0x4003.0000 timer 1 base: 0x4003.1000 timer 2 base: 0x4003.2000 timer 3 base: 0x4003.3000 gptmcfg, type r/w, offset 0x000, reset 0x0000.0000 (see page 553) gptmcfg gptmtamr, type r/w, offset 0x004, reset 0x0000.0000 (see page 554) tamr tacmr taams tacdir tamie tawot tasnaps gptmtbmr, type r/w, offset 0x008, reset 0x0000.0000 (see page 556) tbmr tbcmr tbams tbcdir tbmie tbwot tbsnaps gptmctl, type r/w, offset 0x00c, reset 0x0000.0000 (see page 558) taen tastall taevent rtcen taote tapwml tben tbstall tbevent tbote tbpwml gptmimr, type r/w, offset 0x018, reset 0x0000.0000 (see page 561) tatoim camim caeim rtcim tamim tbtoim cbmim cbeim tbmim gptmris, type ro, offset 0x01c, reset 0x0000.0000 (see page 563) tatoris camris caeris rtcris tamris tbtoris cbmris cberis tbmris gptmmis, type ro, offset 0x020, reset 0x0000.0000 (see page 566) tatomis cammis caemis rtcmis tammis tbtomis cbmmis cbemis tbmmis gptmicr, type w1c, offset 0x024, reset 0x0000.0000 (see page 569) tatocint camcint caecint rtccint tamcint tbtocint cbmcint cbecint tbmcint gptmtailr, type r/w, offset 0x028, reset 0xffff.ffff (see page 571) tailr tailr gptmtbilr, type r/w, offset 0x02c, reset 0x0000.ffff (see page 572) tbilr tbilr gptmtamatchr, type r/w, offset 0x030, reset 0xffff.ffff (see page 573) tamr tamr gptmtbmatchr, type r/w, offset 0x034, reset 0x0000.ffff (see page 574) tbmr tbmr gptmtapr, type r/w, offset 0x038, reset 0x0000.0000 (see page 575) tapsr gptmtbpr, type r/w, offset 0x03c, reset 0x0000.0000 (see page 576) tbpsr july 03, 2014 1338 texas instruments-production data register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 gptmtapmr, type r/w, offset 0x040, reset 0x0000.0000 (see page 577) tapsmr gptmtbpmr, type r/w, offset 0x044, reset 0x0000.0000 (see page 578) tbpsmr gptmtar, type ro, offset 0x048, reset 0xffff.ffff (see page 579) tar tar gptmtbr, type ro, offset 0x04c, reset 0x0000.ffff (see page 580) tbr tbr gptmtav, type rw, offset 0x050, reset 0xffff.ffff (see page 581) tav tav gptmtbv, type rw, offset 0x054, reset 0x0000.ffff (see page 582) tbv tbv watchdog timers wdt0 base: 0x4000.0000 wdt1 base: 0x4000.1000 wdtload, type r/w, offset 0x000, reset 0xffff.ffff (see page 587) wdtload wdtload wdtvalue, type ro, offset 0x004, reset 0xffff.ffff (see page 588) wdtvalue wdtvalue wdtctl, type r/w, offset 0x008, reset 0x0000.0000 (wdt0) and 0x8000.0000 (wdt1) (see page 589) wrc inten resen wdticr, type wo, offset 0x00c, reset - (see page 591) wdtintclr wdtintclr wdtris, type ro, offset 0x010, reset 0x0000.0000 (see page 592) wdtris wdtmis, type ro, offset 0x014, reset 0x0000.0000 (see page 593) wdtmis wdttest, type r/w, offset 0x418, reset 0x0000.0000 (see page 594) stall wdtlock, type r/w, offset 0xc00, reset 0x0000.0000 (see page 595) wdtlock wdtlock wdtperiphid4, type ro, offset 0xfd0, reset 0x0000.0000 (see page 596) pid4 wdtperiphid5, type ro, offset 0xfd4, reset 0x0000.0000 (see page 597) pid5 1339 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 wdtperiphid6, type ro, offset 0xfd8, reset 0x0000.0000 (see page 598) pid6 wdtperiphid7, type ro, offset 0xfdc, reset 0x0000.0000 (see page 599) pid7 wdtperiphid0, type ro, offset 0xfe0, reset 0x0000.0005 (see page 600) pid0 wdtperiphid1, type ro, offset 0xfe4, reset 0x0000.0018 (see page 601) pid1 wdtperiphid2, type ro, offset 0xfe8, reset 0x0000.0018 (see page 602) pid2 wdtperiphid3, type ro, offset 0xfec, reset 0x0000.0001 (see page 603) pid3 wdtpcellid0, type ro, offset 0xff0, reset 0x0000.000d (see page 604) cid0 wdtpcellid1, type ro, offset 0xff4, reset 0x0000.00f0 (see page 605) cid1 wdtpcellid2, type ro, offset 0xff8, reset 0x0000.0006 (see page 606) cid2 wdtpcellid3, type ro, offset 0xffc, reset 0x0000.00b1 (see page 607) cid3 analog-to-digital converter (adc) adc0 base: 0x4003.8000 adc1 base: 0x4003.9000 adcactss, type r/w, offset 0x000, reset 0x0000.0000 (see page 631) asen0 asen1 asen2 asen3 adcris, type ro, offset 0x004, reset 0x0000.0000 (see page 632) inrdc inr0 inr1 inr2 inr3 adcim, type r/w, offset 0x008, reset 0x0000.0000 (see page 634) dconss0 dconss1 dconss2 dconss3 mask0 mask1 mask2 mask3 adcisc, type r/w1c, offset 0x00c, reset 0x0000.0000 (see page 636) dcinss0 dcinss1 dcinss2 dcinss3 in0 in1 in2 in3 adcostat, type r/w1c, offset 0x010, reset 0x0000.0000 (see page 639) ov0 ov1 ov2 ov3 adcemux, type r/w, offset 0x014, reset 0x0000.0000 (see page 641) em0 em1 em2 em3 july 03, 2014 1340 texas instruments-production data register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 adcustat, type r/w1c, offset 0x018, reset 0x0000.0000 (see page 646) uv0 uv1 uv2 uv3 adcsspri, type r/w, offset 0x020, reset 0x0000.3210 (see page 647) ss0 ss1 ss2 ss3 adcspc, type r/w, offset 0x024, reset 0x0000.0000 (see page 649) phase adcpssi, type r/w, offset 0x028, reset - (see page 651) syncwait gsync ss0 ss1 ss2 ss3 adcsac, type r/w, offset 0x030, reset 0x0000.0000 (see page 653) avg adcdcisc, type r/w1c, offset 0x034, reset 0x0000.0000 (see page 654) dcint0 dcint1 dcint2 dcint3 dcint4 dcint5 dcint6 dcint7 adcctl, type r/w, offset 0x038, reset 0x0000.0000 (see page 656) vref res adcssmux0, type r/w, offset 0x040, reset 0x0000.0000 (see page 657) mux4 mux5 mux6 mux7 mux0 mux1 mux2 mux3 adcssctl0, type r/w, offset 0x044, reset 0x0000.0000 (see page 659) d4 end4 ie4 ts4 d5 end5 ie5 ts5 d6 end6 ie6 ts6 d7 end7 ie7 ts7 d0 end0 ie0 ts0 d1 end1 ie1 ts1 d2 end2 ie2 ts2 d3 end3 ie3 ts3 adcssfifo0, type ro, offset 0x048, reset - (see page 662) data adcssfifo1, type ro, offset 0x068, reset - (see page 662) data adcssfifo2, type ro, offset 0x088, reset - (see page 662) data adcssfifo3, type ro, offset 0x0a8, reset - (see page 662) data adcssfstat0, type ro, offset 0x04c, reset 0x0000.0100 (see page 663) tptr hptr empty full adcssfstat1, type ro, offset 0x06c, reset 0x0000.0100 (see page 663) tptr hptr empty full adcssfstat2, type ro, offset 0x08c, reset 0x0000.0100 (see page 663) tptr hptr empty full adcssfstat3, type ro, offset 0x0ac, reset 0x0000.0100 (see page 663) tptr hptr empty full 1341 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 adcssop0, type r/w, offset 0x050, reset 0x0000.0000 (see page 665) s4dcop s5dcop s6dcop s7dcop s0dcop s1dcop s2dcop s3dcop adcssdc0, type r/w, offset 0x054, reset 0x0000.0000 (see page 667) s4dcsel s5dcsel s6dcsel s7dcsel s0dcsel s1dcsel s2dcsel s3dcsel adcssmux1, type r/w, offset 0x060, reset 0x0000.0000 (see page 669) mux0 mux1 mux2 mux3 adcssmux2, type r/w, offset 0x080, reset 0x0000.0000 (see page 669) mux0 mux1 mux2 mux3 adcssctl1, type r/w, offset 0x064, reset 0x0000.0000 (see page 670) d0 end0 ie0 ts0 d1 end1 ie1 ts1 d2 end2 ie2 ts2 d3 end3 ie3 ts3 adcssctl2, type r/w, offset 0x084, reset 0x0000.0000 (see page 670) d0 end0 ie0 ts0 d1 end1 ie1 ts1 d2 end2 ie2 ts2 d3 end3 ie3 ts3 adcssop1, type r/w, offset 0x070, reset 0x0000.0000 (see page 672) s0dcop s1dcop s2dcop s3dcop adcssop2, type r/w, offset 0x090, reset 0x0000.0000 (see page 672) s0dcop s1dcop s2dcop s3dcop adcssdc1, type r/w, offset 0x074, reset 0x0000.0000 (see page 673) s0dcsel s1dcsel s2dcsel s3dcsel adcssdc2, type r/w, offset 0x094, reset 0x0000.0000 (see page 673) s0dcsel s1dcsel s2dcsel s3dcsel adcssmux3, type r/w, offset 0x0a0, reset 0x0000.0000 (see page 675) mux0 adcssctl3, type r/w, offset 0x0a4, reset 0x0000.0002 (see page 676) d0 end0 ie0 ts0 adcssop3, type r/w, offset 0x0b0, reset 0x0000.0000 (see page 677) s0dcop adcssdc3, type r/w, offset 0x0b4, reset 0x0000.0000 (see page 678) s0dcsel adcdcric, type r/w, offset 0xd00, reset 0x0000.0000 (see page 679) dctrig0 dctrig1 dctrig2 dctrig3 dctrig4 dctrig5 dctrig6 dctrig7 dcint0 dcint1 dcint2 dcint3 dcint4 dcint5 dcint6 dcint7 adcdcctl0, type r/w, offset 0xe00, reset 0x0000.0000 (see page 684) cim cic cie ctm ctc cte adcdcctl1, type r/w, offset 0xe04, reset 0x0000.0000 (see page 684) cim cic cie ctm ctc cte july 03, 2014 1342 texas instruments-production data register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 adcdcctl2, type r/w, offset 0xe08, reset 0x0000.0000 (see page 684) cim cic cie ctm ctc cte adcdcctl3, type r/w, offset 0xe0c, reset 0x0000.0000 (see page 684) cim cic cie ctm ctc cte adcdcctl4, type r/w, offset 0xe10, reset 0x0000.0000 (see page 684) cim cic cie ctm ctc cte adcdcctl5, type r/w, offset 0xe14, reset 0x0000.0000 (see page 684) cim cic cie ctm ctc cte adcdcctl6, type r/w, offset 0xe18, reset 0x0000.0000 (see page 684) cim cic cie ctm ctc cte adcdcctl7, type r/w, offset 0xe1c, reset 0x0000.0000 (see page 684) cim cic cie ctm ctc cte adcdccmp0, type r/w, offset 0xe40, reset 0x0000.0000 (see page 687) comp1 comp0 adcdccmp1, type r/w, offset 0xe44, reset 0x0000.0000 (see page 687) comp1 comp0 adcdccmp2, type r/w, offset 0xe48, reset 0x0000.0000 (see page 687) comp1 comp0 adcdccmp3, type r/w, offset 0xe4c, reset 0x0000.0000 (see page 687) comp1 comp0 adcdccmp4, type r/w, offset 0xe50, reset 0x0000.0000 (see page 687) comp1 comp0 adcdccmp5, type r/w, offset 0xe54, reset 0x0000.0000 (see page 687) comp1 comp0 adcdccmp6, type r/w, offset 0xe58, reset 0x0000.0000 (see page 687) comp1 comp0 adcdccmp7, type r/w, offset 0xe5c, reset 0x0000.0000 (see page 687) comp1 comp0 universal asynchronous receivers/transmitters (uarts) uart0 base: 0x4000.c000 uart1 base: 0x4000.d000 uart2 base: 0x4000.e000 uartdr, type r/w, offset 0x000, reset 0x0000.0000 (see page 704) data fe pe be oe uartrsr/uartecr, type ro, offset 0x004, reset 0x0000.0000 (read-only status register) (see page 706) fe pe be oe 1343 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 uartrsr/uartecr, type wo, offset 0x004, reset 0x0000.0000 (write-only error clear register) (see page 706) data uartfr, type ro, offset 0x018, reset 0x0000.0090 (see page 709) cts dsr dcd busy rxfe txff rxff txfe ri uartilpr, type r/w, offset 0x020, reset 0x0000.0000 (see page 712) ilpdvsr uartibrd, type r/w, offset 0x024, reset 0x0000.0000 (see page 713) divint uartfbrd, type r/w, offset 0x028, reset 0x0000.0000 (see page 714) divfrac uartlcrh, type r/w, offset 0x02c, reset 0x0000.0000 (see page 715) brk pen eps stp2 fen wlen sps uartctl, type r/w, offset 0x030, reset 0x0000.0300 (see page 717) uarten siren sirlp smart eot hse lin lbe txe rxe dtr rts rtsen ctsen uartifls, type r/w, offset 0x034, reset 0x0000.0012 (see page 721) txiflsel rxiflsel uartim, type r/w, offset 0x038, reset 0x0000.0000 (see page 723) riim ctsim dcdim dsrim rxim txim rtim feim peim beim oeim lmsbim lme1im lme5im uartris, type ro, offset 0x03c, reset 0x0000.0000 (see page 727) riris ctsris dcdris dsrris rxris txris rtris feris peris beris oeris lmsbris lme1ris lme5ris uartmis, type ro, offset 0x040, reset 0x0000.0000 (see page 731) rimis ctsmis dcdmis dsrmis rxmis txmis rtmis femis pemis bemis oemis lmsbmis lme1mis lme5mis uarticr, type w1c, offset 0x044, reset 0x0000.0000 (see page 735) rimic ctsmic dcdmic dsrmic rxic txic rtic feic peic beic oeic lmsbic lme1ic lme5ic uartdmactl, type r/w, offset 0x048, reset 0x0000.0000 (see page 737) rxdmae txdmae dmaerr uartlctl, type r/w, offset 0x090, reset 0x0000.0000 (see page 738) master blen uartlss, type ro, offset 0x094, reset 0x0000.0000 (see page 739) tss uartltim, type ro, offset 0x098, reset 0x0000.0000 (see page 740) timer uartperiphid4, type ro, offset 0xfd0, reset 0x0000.0000 (see page 741) pid4 july 03, 2014 1344 texas instruments-production data register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 uartperiphid5, type ro, offset 0xfd4, reset 0x0000.0000 (see page 742) pid5 uartperiphid6, type ro, offset 0xfd8, reset 0x0000.0000 (see page 743) pid6 uartperiphid7, type ro, offset 0xfdc, reset 0x0000.0000 (see page 744) pid7 uartperiphid0, type ro, offset 0xfe0, reset 0x0000.0060 (see page 745) pid0 uartperiphid1, type ro, offset 0xfe4, reset 0x0000.0000 (see page 746) pid1 uartperiphid2, type ro, offset 0xfe8, reset 0x0000.0018 (see page 747) pid2 uartperiphid3, type ro, offset 0xfec, reset 0x0000.0001 (see page 748) pid3 uartpcellid0, type ro, offset 0xff0, reset 0x0000.000d (see page 749) cid0 uartpcellid1, type ro, offset 0xff4, reset 0x0000.00f0 (see page 750) cid1 uartpcellid2, type ro, offset 0xff8, reset 0x0000.0005 (see page 751) cid2 uartpcellid3, type ro, offset 0xffc, reset 0x0000.00b1 (see page 752) cid3 synchronous serial interface (ssi) ssi0 base: 0x4000.8000 ssi1 base: 0x4000.9000 ssicr0, type r/w, offset 0x000, reset 0x0000.0000 (see page 768) dss frf spo sph scr ssicr1, type r/w, offset 0x004, reset 0x0000.0000 (see page 770) lbm sse ms sod eot ssidr, type r/w, offset 0x008, reset 0x0000.0000 (see page 772) data ssisr, type ro, offset 0x00c, reset 0x0000.0003 (see page 773) tfe tnf rne rff bsy ssicpsr, type r/w, offset 0x010, reset 0x0000.0000 (see page 775) cpsdvsr 1345 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ssiim, type r/w, offset 0x014, reset 0x0000.0000 (see page 776) rorim rtim rxim txim ssiris, type ro, offset 0x018, reset 0x0000.0008 (see page 777) rorris rtris rxris txris ssimis, type ro, offset 0x01c, reset 0x0000.0000 (see page 779) rormis rtmis rxmis txmis ssiicr, type w1c, offset 0x020, reset 0x0000.0000 (see page 781) roric rtic ssidmactl, type r/w, offset 0x024, reset 0x0000.0000 (see page 782) rxdmae txdmae ssiperiphid4, type ro, offset 0xfd0, reset 0x0000.0000 (see page 783) pid4 ssiperiphid5, type ro, offset 0xfd4, reset 0x0000.0000 (see page 784) pid5 ssiperiphid6, type ro, offset 0xfd8, reset 0x0000.0000 (see page 785) pid6 ssiperiphid7, type ro, offset 0xfdc, reset 0x0000.0000 (see page 786) pid7 ssiperiphid0, type ro, offset 0xfe0, reset 0x0000.0022 (see page 787) pid0 ssiperiphid1, type ro, offset 0xfe4, reset 0x0000.0000 (see page 788) pid1 ssiperiphid2, type ro, offset 0xfe8, reset 0x0000.0018 (see page 789) pid2 ssiperiphid3, type ro, offset 0xfec, reset 0x0000.0001 (see page 790) pid3 ssipcellid0, type ro, offset 0xff0, reset 0x0000.000d (see page 791) cid0 ssipcellid1, type ro, offset 0xff4, reset 0x0000.00f0 (see page 792) cid1 ssipcellid2, type ro, offset 0xff8, reset 0x0000.0005 (see page 793) cid2 ssipcellid3, type ro, offset 0xffc, reset 0x0000.00b1 (see page 794) cid3 july 03, 2014 1346 texas instruments-production data register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 inter-integrated circuit (i 2 c) interface i 2 c master i2c 0 base: 0x4002.0000 i2c 1 base: 0x4002.1000 i2cmsa, type r/w, offset 0x000, reset 0x0000.0000 r/s sa i2cmcs, type ro, offset 0x004, reset 0x0000.0020 (read-only status register) busy error adrack datack arblst idle busbsy i2cmcs, type wo, offset 0x004, reset 0x0000.0020 (write-only control register) run start stop ack i2cmdr, type r/w, offset 0x008, reset 0x0000.0000 data i2cmtpr, type r/w, offset 0x00c, reset 0x0000.0001 tpr i2cmimr, type r/w, offset 0x010, reset 0x0000.0000 im i2cmris, type ro, offset 0x014, reset 0x0000.0000 ris i2cmmis, type ro, offset 0x018, reset 0x0000.0000 mis i2cmicr, type wo, offset 0x01c, reset 0x0000.0000 ic i2cmcr, type r/w, offset 0x020, reset 0x0000.0000 lpbk mfe sfe inter-integrated circuit (i 2 c) interface i 2 c slave i2c 0 base: 0x4002.0000 i2c 1 base: 0x4002.1000 i2csoar, type r/w, offset 0x800, reset 0x0000.0000 oar i2cscsr, type ro, offset 0x804, reset 0x0000.0000 (read-only status register) rreq treq fbr i2cscsr, type wo, offset 0x804, reset 0x0000.0000 (write-only control register) da i2csdr, type r/w, offset 0x808, reset 0x0000.0000 data i2csimr, type r/w, offset 0x80c, reset 0x0000.0000 dataim startim stopim 1347 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 i2csris, type ro, offset 0x810, reset 0x0000.0000 dataris startris stopris i2csmis, type ro, offset 0x814, reset 0x0000.0000 datamis startmis stopmis i2csicr, type wo, offset 0x818, reset 0x0000.0000 dataic startic stopic inter-integrated circuit sound (i 2 s) interface base 0x4005.4000 i2stxfifo, type wo, offset 0x000, reset 0x0000.0000 (see page 846) txfifo txfifo i2stxfifocfg, type r/w, offset 0x004, reset 0x0000.0000 (see page 847) lrs css i2stxcfg, type r/w, offset 0x008, reset 0x1400.7df0 (see page 848) msl fmt wm lrp scp dly jst sdsz ssz i2stxlimit, type r/w, offset 0x00c, reset 0x0000.0000 (see page 850) limit i2stxism, type r/w, offset 0x010, reset 0x0000.0000 (see page 851) ffi ffm i2stxlev, type ro, offset 0x018, reset 0x0000.0000 (see page 852) level i2srxfifo, type ro, offset 0x800, reset 0x0000.0000 (see page 853) rxfifo rxfifo i2srxfifocfg, type r/w, offset 0x804, reset 0x0000.0000 (see page 854) lrs css fmm i2srxcfg, type r/w, offset 0x808, reset 0x1400.7df0 (see page 855) msl rm lrp scp dly jst sdsz ssz i2srxlimit, type r/w, offset 0x80c, reset 0x0000.7fff (see page 858) limit i2srxism, type r/w, offset 0x810, reset 0x0000.0000 (see page 859) ffi ffm i2srxlev, type ro, offset 0x818, reset 0x0000.0000 (see page 860) level i2scfg, type r/w, offset 0xc00, reset 0x0000.0000 (see page 861) txen rxen txslv rxslv july 03, 2014 1348 texas instruments-production data register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 i2sim, type r/w, offset 0xc10, reset 0x0000.0000 (see page 863) txsrim txweim rxsrim rxreim i2sris, type ro, offset 0xc14, reset 0x0000.0000 (see page 865) txsrris txweris rxsrris rxreris i2smis, type ro, offset 0xc18, reset 0x0000.0000 (see page 867) txsrmis txwemis rxsrmis rxremis i2sic, type wo, offset 0xc1c, reset 0x0000.0000 (see page 869) txweic rxreic controller area network (can) module can0 base: 0x4004.0000 can1 base: 0x4004.1000 canctl, type r/w, offset 0x000, reset 0x0000.0001 (see page 892) init ie sie eie dar cce test cansts, type r/w, offset 0x004, reset 0x0000.0000 (see page 894) lec txok rxok epass ewarn boff canerr, type ro, offset 0x008, reset 0x0000.0000 (see page 897) tec rec rp canbit, type r/w, offset 0x00c, reset 0x0000.2301 (see page 898) brp sjw tseg1 tseg2 canint, type ro, offset 0x010, reset 0x0000.0000 (see page 899) intid cantst, type r/w, offset 0x014, reset 0x0000.0000 (see page 900) basic silent lback tx rx canbrpe, type r/w, offset 0x018, reset 0x0000.0000 (see page 902) brpe canif1crq, type r/w, offset 0x020, reset 0x0000.0001 (see page 903) mnum busy canif2crq, type r/w, offset 0x080, reset 0x0000.0001 (see page 903) mnum busy canif1cmsk, type r/w, offset 0x024, reset 0x0000.0000 (see page 904) datab dataa newdat / txrqst clrintpnd control arb mask wrnrd 1349 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 canif2cmsk, type r/w, offset 0x084, reset 0x0000.0000 (see page 904) datab dataa newdat / txrqst clrintpnd control arb mask wrnrd canif1msk1, type r/w, offset 0x028, reset 0x0000.ffff (see page 907) msk canif2msk1, type r/w, offset 0x088, reset 0x0000.ffff (see page 907) msk canif1msk2, type r/w, offset 0x02c, reset 0x0000.ffff (see page 908) msk mdir mxtd canif2msk2, type r/w, offset 0x08c, reset 0x0000.ffff (see page 908) msk mdir mxtd canif1arb1, type r/w, offset 0x030, reset 0x0000.0000 (see page 910) id canif2arb1, type r/w, offset 0x090, reset 0x0000.0000 (see page 910) id canif1arb2, type r/w, offset 0x034, reset 0x0000.0000 (see page 911) id dir xtd msgval canif2arb2, type r/w, offset 0x094, reset 0x0000.0000 (see page 911) id dir xtd msgval canif1mctl, type r/w, offset 0x038, reset 0x0000.0000 (see page 913) dlc eob txrqst rmten rxie txie umask intpnd msglst newdat canif2mctl, type r/w, offset 0x098, reset 0x0000.0000 (see page 913) dlc eob txrqst rmten rxie txie umask intpnd msglst newdat canif1da1, type r/w, offset 0x03c, reset 0x0000.0000 (see page 916) data canif1da2, type r/w, offset 0x040, reset 0x0000.0000 (see page 916) data canif1db1, type r/w, offset 0x044, reset 0x0000.0000 (see page 916) data canif1db2, type r/w, offset 0x048, reset 0x0000.0000 (see page 916) data canif2da1, type r/w, offset 0x09c, reset 0x0000.0000 (see page 916) data july 03, 2014 1350 texas instruments-production data register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 canif2da2, type r/w, offset 0x0a0, reset 0x0000.0000 (see page 916) data canif2db1, type r/w, offset 0x0a4, reset 0x0000.0000 (see page 916) data canif2db2, type r/w, offset 0x0a8, reset 0x0000.0000 (see page 916) data cantxrq1, type ro, offset 0x100, reset 0x0000.0000 (see page 917) txrqst cantxrq2, type ro, offset 0x104, reset 0x0000.0000 (see page 917) txrqst cannwda1, type ro, offset 0x120, reset 0x0000.0000 (see page 918) newdat cannwda2, type ro, offset 0x124, reset 0x0000.0000 (see page 918) newdat canmsg1int, type ro, offset 0x140, reset 0x0000.0000 (see page 919) intpnd canmsg2int, type ro, offset 0x144, reset 0x0000.0000 (see page 919) intpnd canmsg1val, type ro, offset 0x160, reset 0x0000.0000 (see page 920) msgval canmsg2val, type ro, offset 0x164, reset 0x0000.0000 (see page 920) msgval ethernet controller base 0x4004.8000 macris/maciack, type r/w1c, offset 0x000, reset 0x0000.0000 (see page 934) rxint txer txemp fov rxer mdint phyint macim, type r/w, offset 0x004, reset 0x0000.007f (see page 937) rxintm txerm txempm fovm rxerm mdintm phyintm macrctl, type r/w, offset 0x008, reset 0x0000.0008 (see page 939) rxen amul prms badcrc rstfifo mactctl, type r/w, offset 0x00c, reset 0x0000.0000 (see page 941) txen paden crc duplex macdata, type ro, offset 0x010, reset 0x0000.0000 (reads) (see page 943) rxdata rxdata macdata, type wo, offset 0x010, reset 0x0000.0000 (writes) (see page 943) txdata txdata 1351 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 macia0, type r/w, offset 0x014, reset 0x0000.0000 (see page 945) macoct3 macoct4 macoct1 macoct2 macia1, type r/w, offset 0x018, reset 0x0000.0000 (see page 946) macoct5 macoct6 macthr, type r/w, offset 0x01c, reset 0x0000.003f (see page 947) thresh macmctl, type r/w, offset 0x020, reset 0x0000.0000 (see page 949) start write regadr macmdv, type r/w, offset 0x024, reset 0x0000.0080 (see page 950) div macmadd, type ro, offset 0x028, reset 0x0000.0000 (see page 951) phyadr macmtxd, type r/w, offset 0x02c, reset 0x0000.0000 (see page 952) mdtx macmrxd, type r/w, offset 0x030, reset 0x0000.0000 (see page 953) mdrx macnp, type ro, offset 0x034, reset 0x0000.0000 (see page 954) npr mactr, type r/w, offset 0x038, reset 0x0000.0000 (see page 955) newtx macts, type r/w, offset 0x03c, reset 0x0000.0000 (see page 956) tsen universal serial bus (usb) controller base 0x4005.0000 usbfaddr, type r/w, offset 0x000, reset 0x00 (see page 985) funcaddr usbpower, type r/w, offset 0x001, reset 0x20 (otg a / host mode) (see page 986) pwrdnphy suspend resume reset usbpower, type r/w, offset 0x001, reset 0x20 (otg b / device mode) (see page 986) pwrdnphy suspend resume reset softconn isoup usbtxis, type ro, offset 0x002, reset 0x0000 (see page 989) ep0 ep1 ep2 ep3 ep4 ep5 ep6 ep7 ep8 ep9 ep10 ep11 ep12 ep13 ep14 ep15 usbrxis, type ro, offset 0x004, reset 0x0000 (see page 991) ep1 ep2 ep3 ep4 ep5 ep6 ep7 ep8 ep9 ep10 ep11 ep12 ep13 ep14 ep15 usbtxie, type r/w, offset 0x006, reset 0xffff (see page 993) ep0 ep1 ep2 ep3 ep4 ep5 ep6 ep7 ep8 ep9 ep10 ep11 ep12 ep13 ep14 ep15 usbrxie, type r/w, offset 0x008, reset 0xfffe (see page 995) ep1 ep2 ep3 ep4 ep5 ep6 ep7 ep8 ep9 ep10 ep11 ep12 ep13 ep14 ep15 usbis, type ro, offset 0x00a, reset 0x00 (otg a / host mode) (see page 997) resume babble sof conn discon sesreq vbuserr july 03, 2014 1352 texas instruments-production data register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 usbis, type ro, offset 0x00a, reset 0x00 (otg b / device mode) (see page 997) suspend resume reset sof discon usbie, type r/w, offset 0x00b, reset 0x06 (otg a / host mode) (see page 1000) resume babble sof conn discon sesreq vbuserr usbie, type r/w, offset 0x00b, reset 0x06 (otg b / device mode) (see page 1000) suspend resume reset sof discon usbframe, type ro, offset 0x00c, reset 0x0000 (see page 1003) frame usbepidx, type r/w, offset 0x00e, reset 0x00 (see page 1004) epidx usbtest, type r/w, offset 0x00f, reset 0x00 (otg a / host mode) (see page 1005) forcefs fifoacc forceh usbtest, type r/w, offset 0x00f, reset 0x00 (otg b / device mode) (see page 1005) fifoacc usbfifo0, type r/w, offset 0x020, reset 0x0000.0000 (see page 1007) epdata epdata usbfifo1, type r/w, offset 0x024, reset 0x0000.0000 (see page 1007) epdata epdata usbfifo2, type r/w, offset 0x028, reset 0x0000.0000 (see page 1007) epdata epdata usbfifo3, type r/w, offset 0x02c, reset 0x0000.0000 (see page 1007) epdata epdata usbfifo4, type r/w, offset 0x030, reset 0x0000.0000 (see page 1007) epdata epdata usbfifo5, type r/w, offset 0x034, reset 0x0000.0000 (see page 1007) epdata epdata usbfifo6, type r/w, offset 0x038, reset 0x0000.0000 (see page 1007) epdata epdata usbfifo7, type r/w, offset 0x03c, reset 0x0000.0000 (see page 1007) epdata epdata usbfifo8, type r/w, offset 0x040, reset 0x0000.0000 (see page 1007) epdata epdata usbfifo9, type r/w, offset 0x044, reset 0x0000.0000 (see page 1007) epdata epdata usbfifo10, type r/w, offset 0x048, reset 0x0000.0000 (see page 1007) epdata epdata usbfifo11, type r/w, offset 0x04c, reset 0x0000.0000 (see page 1007) epdata epdata 1353 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 usbfifo12, type r/w, offset 0x050, reset 0x0000.0000 (see page 1007) epdata epdata usbfifo13, type r/w, offset 0x054, reset 0x0000.0000 (see page 1007) epdata epdata usbfifo14, type r/w, offset 0x058, reset 0x0000.0000 (see page 1007) epdata epdata usbfifo15, type r/w, offset 0x05c, reset 0x0000.0000 (see page 1007) epdata epdata usbdevctl, type r/w, offset 0x060, reset 0x80 (see page 1009) session hostreq host vbus lsdev fsdev dev usbtxfifosz, type r/w, offset 0x062, reset 0x00 (see page 1011) size dpb usbrxfifosz, type r/w, offset 0x063, reset 0x00 (see page 1011) size dpb usbtxfifoadd, type r/w, offset 0x064, reset 0x0000 (see page 1012) addr usbrxfifoadd, type r/w, offset 0x066, reset 0x0000 (see page 1012) addr usbcontim, type r/w, offset 0x07a, reset 0x5c (see page 1013) wtid wtcon usbvplen, type r/w, offset 0x07b, reset 0x3c (see page 1014) vplen usbfseof, type r/w, offset 0x07d, reset 0x77 (see page 1015) fseofg usblseof, type r/w, offset 0x07e, reset 0x72 (see page 1016) lseofg usbtxfuncaddr0, type r/w, offset 0x080, reset 0x00 (see page 1017) addr usbtxfuncaddr1, type r/w, offset 0x088, reset 0x00 (see page 1017) addr usbtxfuncaddr2, type r/w, offset 0x090, reset 0x00 (see page 1017) addr usbtxfuncaddr3, type r/w, offset 0x098, reset 0x00 (see page 1017) addr usbtxfuncaddr4, type r/w, offset 0x0a0, reset 0x00 (see page 1017) addr usbtxfuncaddr5, type r/w, offset 0x0a8, reset 0x00 (see page 1017) addr usbtxfuncaddr6, type r/w, offset 0x0b0, reset 0x00 (see page 1017) addr usbtxfuncaddr7, type r/w, offset 0x0b8, reset 0x00 (see page 1017) addr usbtxfuncaddr8, type r/w, offset 0x0c0, reset 0x00 (see page 1017) addr usbtxfuncaddr9, type r/w, offset 0x0c8, reset 0x00 (see page 1017) addr usbtxfuncaddr10, type r/w, offset 0x0d0, reset 0x00 (see page 1017) addr july 03, 2014 1354 texas instruments-production data register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 usbtxfuncaddr11, type r/w, offset 0x0d8, reset 0x00 (see page 1017) addr usbtxfuncaddr12, type r/w, offset 0x0e0, reset 0x00 (see page 1017) addr usbtxfuncaddr13, type r/w, offset 0x0e8, reset 0x00 (see page 1017) addr usbtxfuncaddr14, type r/w, offset 0x0f0, reset 0x00 (see page 1017) addr usbtxfuncaddr15, type r/w, offset 0x0f8, reset 0x00 (see page 1017) addr usbtxhubaddr0, type r/w, offset 0x082, reset 0x00 (see page 1019) addr usbtxhubaddr1, type r/w, offset 0x08a, reset 0x00 (see page 1019) addr usbtxhubaddr2, type r/w, offset 0x092, reset 0x00 (see page 1019) addr usbtxhubaddr3, type r/w, offset 0x09a, reset 0x00 (see page 1019) addr usbtxhubaddr4, type r/w, offset 0x0a2, reset 0x00 (see page 1019) addr usbtxhubaddr5, type r/w, offset 0x0aa, reset 0x00 (see page 1019) addr usbtxhubaddr6, type r/w, offset 0x0b2, reset 0x00 (see page 1019) addr usbtxhubaddr7, type r/w, offset 0x0ba, reset 0x00 (see page 1019) addr usbtxhubaddr8, type r/w, offset 0x0c2, reset 0x00 (see page 1019) addr usbtxhubaddr9, type r/w, offset 0x0ca, reset 0x00 (see page 1019) addr usbtxhubaddr10, type r/w, offset 0x0d2, reset 0x00 (see page 1019) addr usbtxhubaddr11, type r/w, offset 0x0da, reset 0x00 (see page 1019) addr usbtxhubaddr12, type r/w, offset 0x0e2, reset 0x00 (see page 1019) addr usbtxhubaddr13, type r/w, offset 0x0ea, reset 0x00 (see page 1019) addr usbtxhubaddr14, type r/w, offset 0x0f2, reset 0x00 (see page 1019) addr usbtxhubaddr15, type r/w, offset 0x0fa, reset 0x00 (see page 1019) addr usbtxhubport0, type r/w, offset 0x083, reset 0x00 (see page 1021) port usbtxhubport1, type r/w, offset 0x08b, reset 0x00 (see page 1021) port usbtxhubport2, type r/w, offset 0x093, reset 0x00 (see page 1021) port usbtxhubport3, type r/w, offset 0x09b, reset 0x00 (see page 1021) port usbtxhubport4, type r/w, offset 0x0a3, reset 0x00 (see page 1021) port 1355 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 usbtxhubport5, type r/w, offset 0x0ab, reset 0x00 (see page 1021) port usbtxhubport6, type r/w, offset 0x0b3, reset 0x00 (see page 1021) port usbtxhubport7, type r/w, offset 0x0bb, reset 0x00 (see page 1021) port usbtxhubport8, type r/w, offset 0x0c3, reset 0x00 (see page 1021) port usbtxhubport9, type r/w, offset 0x0cb, reset 0x00 (see page 1021) port usbtxhubport10, type r/w, offset 0x0d3, reset 0x00 (see page 1021) port usbtxhubport11, type r/w, offset 0x0db, reset 0x00 (see page 1021) port usbtxhubport12, type r/w, offset 0x0e3, reset 0x00 (see page 1021) port usbtxhubport13, type r/w, offset 0x0eb, reset 0x00 (see page 1021) port usbtxhubport14, type r/w, offset 0x0f3, reset 0x00 (see page 1021) port usbtxhubport15, type r/w, offset 0x0fb, reset 0x00 (see page 1021) port usbrxfuncaddr1, type r/w, offset 0x08c, reset 0x00 (see page 1023) addr usbrxfuncaddr2, type r/w, offset 0x094, reset 0x00 (see page 1023) addr usbrxfuncaddr3, type r/w, offset 0x09c, reset 0x00 (see page 1023) addr usbrxfuncaddr4, type r/w, offset 0x0a4, reset 0x00 (see page 1023) addr usbrxfuncaddr5, type r/w, offset 0x0ac, reset 0x00 (see page 1023) addr usbrxfuncaddr6, type r/w, offset 0x0b4, reset 0x00 (see page 1023) addr usbrxfuncaddr7, type r/w, offset 0x0bc, reset 0x00 (see page 1023) addr usbrxfuncaddr8, type r/w, offset 0x0c4, reset 0x00 (see page 1023) addr usbrxfuncaddr9, type r/w, offset 0x0cc, reset 0x00 (see page 1023) addr usbrxfuncaddr10, type r/w, offset 0x0d4, reset 0x00 (see page 1023) addr usbrxfuncaddr11, type r/w, offset 0x0dc, reset 0x00 (see page 1023) addr usbrxfuncaddr12, type r/w, offset 0x0e4, reset 0x00 (see page 1023) addr usbrxfuncaddr13, type r/w, offset 0x0ec, reset 0x00 (see page 1023) addr usbrxfuncaddr14, type r/w, offset 0x0f4, reset 0x00 (see page 1023) addr usbrxfuncaddr15, type r/w, offset 0x0fc, reset 0x00 (see page 1023) addr july 03, 2014 1356 texas instruments-production data register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 usbrxhubaddr1, type r/w, offset 0x08e, reset 0x00 (see page 1025) addr usbrxhubaddr2, type r/w, offset 0x096, reset 0x00 (see page 1025) addr usbrxhubaddr3, type r/w, offset 0x09e, reset 0x00 (see page 1025) addr usbrxhubaddr4, type r/w, offset 0x0a6, reset 0x00 (see page 1025) addr usbrxhubaddr5, type r/w, offset 0x0ae, reset 0x00 (see page 1025) addr usbrxhubaddr6, type r/w, offset 0x0b6, reset 0x00 (see page 1025) addr usbrxhubaddr7, type r/w, offset 0x0be, reset 0x00 (see page 1025) addr usbrxhubaddr8, type r/w, offset 0x0c6, reset 0x00 (see page 1025) addr usbrxhubaddr9, type r/w, offset 0x0ce, reset 0x00 (see page 1025) addr usbrxhubaddr10, type r/w, offset 0x0d6, reset 0x00 (see page 1025) addr usbrxhubaddr11, type r/w, offset 0x0de, reset 0x00 (see page 1025) addr usbrxhubaddr12, type r/w, offset 0x0e6, reset 0x00 (see page 1025) addr usbrxhubaddr13, type r/w, offset 0x0ee, reset 0x00 (see page 1025) addr usbrxhubaddr14, type r/w, offset 0x0f6, reset 0x00 (see page 1025) addr usbrxhubaddr15, type r/w, offset 0x0fe, reset 0x00 (see page 1025) addr usbrxhubport1, type r/w, offset 0x08f, reset 0x00 (see page 1027) port usbrxhubport2, type r/w, offset 0x097, reset 0x00 (see page 1027) port usbrxhubport3, type r/w, offset 0x09f, reset 0x00 (see page 1027) port usbrxhubport4, type r/w, offset 0x0a7, reset 0x00 (see page 1027) port usbrxhubport5, type r/w, offset 0x0af, reset 0x00 (see page 1027) port usbrxhubport6, type r/w, offset 0x0b7, reset 0x00 (see page 1027) port usbrxhubport7, type r/w, offset 0x0bf, reset 0x00 (see page 1027) port usbrxhubport8, type r/w, offset 0x0c7, reset 0x00 (see page 1027) port usbrxhubport9, type r/w, offset 0x0cf, reset 0x00 (see page 1027) port usbrxhubport10, type r/w, offset 0x0d7, reset 0x00 (see page 1027) port usbrxhubport11, type r/w, offset 0x0df, reset 0x00 (see page 1027) port 1357 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 usbrxhubport12, type r/w, offset 0x0e7, reset 0x00 (see page 1027) port usbrxhubport13, type r/w, offset 0x0ef, reset 0x00 (see page 1027) port usbrxhubport14, type r/w, offset 0x0f7, reset 0x00 (see page 1027) port usbrxhubport15, type r/w, offset 0x0ff, reset 0x00 (see page 1027) port usbtxmaxp1, type r/w, offset 0x110, reset 0x0000 (see page 1029) maxload usbtxmaxp2, type r/w, offset 0x120, reset 0x0000 (see page 1029) maxload usbtxmaxp3, type r/w, offset 0x130, reset 0x0000 (see page 1029) maxload usbtxmaxp4, type r/w, offset 0x140, reset 0x0000 (see page 1029) maxload usbtxmaxp5, type r/w, offset 0x150, reset 0x0000 (see page 1029) maxload usbtxmaxp6, type r/w, offset 0x160, reset 0x0000 (see page 1029) maxload usbtxmaxp7, type r/w, offset 0x170, reset 0x0000 (see page 1029) maxload usbtxmaxp8, type r/w, offset 0x180, reset 0x0000 (see page 1029) maxload usbtxmaxp9, type r/w, offset 0x190, reset 0x0000 (see page 1029) maxload usbtxmaxp10, type r/w, offset 0x1a0, reset 0x0000 (see page 1029) maxload usbtxmaxp11, type r/w, offset 0x1b0, reset 0x0000 (see page 1029) maxload usbtxmaxp12, type r/w, offset 0x1c0, reset 0x0000 (see page 1029) maxload usbtxmaxp13, type r/w, offset 0x1d0, reset 0x0000 (see page 1029) maxload usbtxmaxp14, type r/w, offset 0x1e0, reset 0x0000 (see page 1029) maxload usbtxmaxp15, type r/w, offset 0x1f0, reset 0x0000 (see page 1029) maxload usbcsrl0, type w1c, offset 0x102, reset 0x00 (otg a / host mode) (see page 1031) rxrdy txrdy stalled setup error reqpkt status nakto usbcsrl0, type w1c, offset 0x102, reset 0x00 (otg b / device mode) (see page 1031) rxrdy txrdy stalled dataend setend stall rxrdyc setendc usbcsrh0, type w1c, offset 0x103, reset 0x00 (otg a / host mode) (see page 1035) flush dt dtwe usbcsrh0, type w1c, offset 0x103, reset 0x00 (otg b / device mode) (see page 1035) flush usbcount0, type ro, offset 0x108, reset 0x00 (see page 1037) count usbtype0, type r/w, offset 0x10a, reset 0x00 (see page 1038) speed usbnaklmt, type r/w, offset 0x10b, reset 0x00 (see page 1039) naklmt july 03, 2014 1358 texas instruments-production data register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 usbtxcsrl1, type r/w, offset 0x112, reset 0x00 (otg a / host mode) (see page 1040) txrdy fifone error flush setup stalled clrdt nakto usbtxcsrl2, type r/w, offset 0x122, reset 0x00 (otg a / host mode) (see page 1040) txrdy fifone error flush setup stalled clrdt nakto usbtxcsrl3, type r/w, offset 0x132, reset 0x00 (otg a / host mode) (see page 1040) txrdy fifone error flush setup stalled clrdt nakto usbtxcsrl4, type r/w, offset 0x142, reset 0x00 (otg a / host mode) (see page 1040) txrdy fifone error flush setup stalled clrdt nakto usbtxcsrl5, type r/w, offset 0x152, reset 0x00 (otg a / host mode) (see page 1040) txrdy fifone error flush setup stalled clrdt nakto usbtxcsrl6, type r/w, offset 0x162, reset 0x00 (otg a / host mode) (see page 1040) txrdy fifone error flush setup stalled clrdt nakto usbtxcsrl7, type r/w, offset 0x172, reset 0x00 (otg a / host mode) (see page 1040) txrdy fifone error flush setup stalled clrdt nakto usbtxcsrl8, type r/w, offset 0x182, reset 0x00 (otg a / host mode) (see page 1040) txrdy fifone error flush setup stalled clrdt nakto usbtxcsrl9, type r/w, offset 0x192, reset 0x00 (otg a / host mode) (see page 1040) txrdy fifone error flush setup stalled clrdt nakto usbtxcsrl10, type r/w, offset 0x1a2, reset 0x00 (otg a / host mode) (see page 1040) txrdy fifone error flush setup stalled clrdt nakto usbtxcsrl11, type r/w, offset 0x1b2, reset 0x00 (otg a / host mode) (see page 1040) txrdy fifone error flush setup stalled clrdt nakto usbtxcsrl12, type r/w, offset 0x1c2, reset 0x00 (otg a / host mode) (see page 1040) txrdy fifone error flush setup stalled clrdt nakto usbtxcsrl13, type r/w, offset 0x1d2, reset 0x00 (otg a / host mode) (see page 1040) txrdy fifone error flush setup stalled clrdt nakto usbtxcsrl14, type r/w, offset 0x1e2, reset 0x00 (otg a / host mode) (see page 1040) txrdy fifone error flush setup stalled clrdt nakto usbtxcsrl15, type r/w, offset 0x1f2, reset 0x00 (otg a / host mode) (see page 1040) txrdy fifone error flush setup stalled clrdt nakto usbtxcsrl1, type r/w, offset 0x112, reset 0x00 (otg b / device mode) (see page 1040) txrdy fifone undrn flush stall stalled clrdt usbtxcsrl2, type r/w, offset 0x122, reset 0x00 (otg b / device mode) (see page 1040) txrdy fifone undrn flush stall stalled clrdt usbtxcsrl3, type r/w, offset 0x132, reset 0x00 (otg b / device mode) (see page 1040) txrdy fifone undrn flush stall stalled clrdt usbtxcsrl4, type r/w, offset 0x142, reset 0x00 (otg b / device mode) (see page 1040) txrdy fifone undrn flush stall stalled clrdt usbtxcsrl5, type r/w, offset 0x152, reset 0x00 (otg b / device mode) (see page 1040) txrdy fifone undrn flush stall stalled clrdt usbtxcsrl6, type r/w, offset 0x162, reset 0x00 (otg b / device mode) (see page 1040) txrdy fifone undrn flush stall stalled clrdt usbtxcsrl7, type r/w, offset 0x172, reset 0x00 (otg b / device mode) (see page 1040) txrdy fifone undrn flush stall stalled clrdt usbtxcsrl8, type r/w, offset 0x182, reset 0x00 (otg b / device mode) (see page 1040) txrdy fifone undrn flush stall stalled clrdt usbtxcsrl9, type r/w, offset 0x192, reset 0x00 (otg b / device mode) (see page 1040) txrdy fifone undrn flush stall stalled clrdt usbtxcsrl10, type r/w, offset 0x1a2, reset 0x00 (otg b / device mode) (see page 1040) txrdy fifone undrn flush stall stalled clrdt usbtxcsrl11, type r/w, offset 0x1b2, reset 0x00 (otg b / device mode) (see page 1040) txrdy fifone undrn flush stall stalled clrdt 1359 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 usbtxcsrl12, type r/w, offset 0x1c2, reset 0x00 (otg b / device mode) (see page 1040) txrdy fifone undrn flush stall stalled clrdt usbtxcsrl13, type r/w, offset 0x1d2, reset 0x00 (otg b / device mode) (see page 1040) txrdy fifone undrn flush stall stalled clrdt usbtxcsrl14, type r/w, offset 0x1e2, reset 0x00 (otg b / device mode) (see page 1040) txrdy fifone undrn flush stall stalled clrdt usbtxcsrl15, type r/w, offset 0x1f2, reset 0x00 (otg b / device mode) (see page 1040) txrdy fifone undrn flush stall stalled clrdt usbtxcsrh1, type r/w, offset 0x113, reset 0x00 (otg a / host mode) (see page 1045) dt dtwe dmamod fdt dmaen mode autoset usbtxcsrh2, type r/w, offset 0x123, reset 0x00 (otg a / host mode) (see page 1045) dt dtwe dmamod fdt dmaen mode autoset usbtxcsrh3, type r/w, offset 0x133, reset 0x00 (otg a / host mode) (see page 1045) dt dtwe dmamod fdt dmaen mode autoset usbtxcsrh4, type r/w, offset 0x143, reset 0x00 (otg a / host mode) (see page 1045) dt dtwe dmamod fdt dmaen mode autoset usbtxcsrh5, type r/w, offset 0x153, reset 0x00 (otg a / host mode) (see page 1045) dt dtwe dmamod fdt dmaen mode autoset usbtxcsrh6, type r/w, offset 0x163, reset 0x00 (otg a / host mode) (see page 1045) dt dtwe dmamod fdt dmaen mode autoset usbtxcsrh7, type r/w, offset 0x173, reset 0x00 (otg a / host mode) (see page 1045) dt dtwe dmamod fdt dmaen mode autoset usbtxcsrh8, type r/w, offset 0x183, reset 0x00 (otg a / host mode) (see page 1045) dt dtwe dmamod fdt dmaen mode autoset usbtxcsrh9, type r/w, offset 0x193, reset 0x00 (otg a / host mode) (see page 1045) dt dtwe dmamod fdt dmaen mode autoset usbtxcsrh10, type r/w, offset 0x1a3, reset 0x00 (otg a / host mode) (see page 1045) dt dtwe dmamod fdt dmaen mode autoset usbtxcsrh11, type r/w, offset 0x1b3, reset 0x00 (otg a / host mode) (see page 1045) dt dtwe dmamod fdt dmaen mode autoset usbtxcsrh12, type r/w, offset 0x1c3, reset 0x00 (otg a / host mode) (see page 1045) dt dtwe dmamod fdt dmaen mode autoset usbtxcsrh13, type r/w, offset 0x1d3, reset 0x00 (otg a / host mode) (see page 1045) dt dtwe dmamod fdt dmaen mode autoset usbtxcsrh14, type r/w, offset 0x1e3, reset 0x00 (otg a / host mode) (see page 1045) dt dtwe dmamod fdt dmaen mode autoset usbtxcsrh15, type r/w, offset 0x1f3, reset 0x00 (otg a / host mode) (see page 1045) dt dtwe dmamod fdt dmaen mode autoset usbtxcsrh1, type r/w, offset 0x113, reset 0x00 (otg b / device mode) (see page 1045) dmamod fdt dmaen mode iso autoset usbtxcsrh2, type r/w, offset 0x123, reset 0x00 (otg b / device mode) (see page 1045) dmamod fdt dmaen mode iso autoset usbtxcsrh3, type r/w, offset 0x133, reset 0x00 (otg b / device mode) (see page 1045) dmamod fdt dmaen mode iso autoset usbtxcsrh4, type r/w, offset 0x143, reset 0x00 (otg b / device mode) (see page 1045) dmamod fdt dmaen mode iso autoset usbtxcsrh5, type r/w, offset 0x153, reset 0x00 (otg b / device mode) (see page 1045) dmamod fdt dmaen mode iso autoset usbtxcsrh6, type r/w, offset 0x163, reset 0x00 (otg b / device mode) (see page 1045) dmamod fdt dmaen mode iso autoset usbtxcsrh7, type r/w, offset 0x173, reset 0x00 (otg b / device mode) (see page 1045) dmamod fdt dmaen mode iso autoset july 03, 2014 1360 texas instruments-production data register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 usbtxcsrh8, type r/w, offset 0x183, reset 0x00 (otg b / device mode) (see page 1045) dmamod fdt dmaen mode iso autoset usbtxcsrh9, type r/w, offset 0x193, reset 0x00 (otg b / device mode) (see page 1045) dmamod fdt dmaen mode iso autoset usbtxcsrh10, type r/w, offset 0x1a3, reset 0x00 (otg b / device mode) (see page 1045) dmamod fdt dmaen mode iso autoset usbtxcsrh11, type r/w, offset 0x1b3, reset 0x00 (otg b / device mode) (see page 1045) dmamod fdt dmaen mode iso autoset usbtxcsrh12, type r/w, offset 0x1c3, reset 0x00 (otg b / device mode) (see page 1045) dmamod fdt dmaen mode iso autoset usbtxcsrh13, type r/w, offset 0x1d3, reset 0x00 (otg b / device mode) (see page 1045) dmamod fdt dmaen mode iso autoset usbtxcsrh14, type r/w, offset 0x1e3, reset 0x00 (otg b / device mode) (see page 1045) dmamod fdt dmaen mode iso autoset usbtxcsrh15, type r/w, offset 0x1f3, reset 0x00 (otg b / device mode) (see page 1045) dmamod fdt dmaen mode iso autoset usbrxmaxp1, type r/w, offset 0x114, reset 0x0000 (see page 1049) maxload usbrxmaxp2, type r/w, offset 0x124, reset 0x0000 (see page 1049) maxload usbrxmaxp3, type r/w, offset 0x134, reset 0x0000 (see page 1049) maxload usbrxmaxp4, type r/w, offset 0x144, reset 0x0000 (see page 1049) maxload usbrxmaxp5, type r/w, offset 0x154, reset 0x0000 (see page 1049) maxload usbrxmaxp6, type r/w, offset 0x164, reset 0x0000 (see page 1049) maxload usbrxmaxp7, type r/w, offset 0x174, reset 0x0000 (see page 1049) maxload usbrxmaxp8, type r/w, offset 0x184, reset 0x0000 (see page 1049) maxload usbrxmaxp9, type r/w, offset 0x194, reset 0x0000 (see page 1049) maxload usbrxmaxp10, type r/w, offset 0x1a4, reset 0x0000 (see page 1049) maxload usbrxmaxp11, type r/w, offset 0x1b4, reset 0x0000 (see page 1049) maxload usbrxmaxp12, type r/w, offset 0x1c4, reset 0x0000 (see page 1049) maxload usbrxmaxp13, type r/w, offset 0x1d4, reset 0x0000 (see page 1049) maxload usbrxmaxp14, type r/w, offset 0x1e4, reset 0x0000 (see page 1049) maxload usbrxmaxp15, type r/w, offset 0x1f4, reset 0x0000 (see page 1049) maxload usbrxcsrl1, type r/w, offset 0x116, reset 0x00 (otg a / host mode) (see page 1051) rxrdy full error dataerr / nakto flush reqpkt stalled clrdt 1361 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 usbrxcsrl2, type r/w, offset 0x126, reset 0x00 (otg a / host mode) (see page 1051) rxrdy full error dataerr / nakto flush reqpkt stalled clrdt usbrxcsrl3, type r/w, offset 0x136, reset 0x00 (otg a / host mode) (see page 1051) rxrdy full error dataerr / nakto flush reqpkt stalled clrdt usbrxcsrl4, type r/w, offset 0x146, reset 0x00 (otg a / host mode) (see page 1051) rxrdy full error dataerr / nakto flush reqpkt stalled clrdt usbrxcsrl5, type r/w, offset 0x156, reset 0x00 (otg a / host mode) (see page 1051) rxrdy full error dataerr / nakto flush reqpkt stalled clrdt usbrxcsrl6, type r/w, offset 0x166, reset 0x00 (otg a / host mode) (see page 1051) rxrdy full error dataerr / nakto flush reqpkt stalled clrdt usbrxcsrl7, type r/w, offset 0x176, reset 0x00 (otg a / host mode) (see page 1051) rxrdy full error dataerr / nakto flush reqpkt stalled clrdt usbrxcsrl8, type r/w, offset 0x186, reset 0x00 (otg a / host mode) (see page 1051) rxrdy full error dataerr / nakto flush reqpkt stalled clrdt usbrxcsrl9, type r/w, offset 0x196, reset 0x00 (otg a / host mode) (see page 1051) rxrdy full error dataerr / nakto flush reqpkt stalled clrdt usbrxcsrl10, type r/w, offset 0x1a6, reset 0x00 (otg a / host mode) (see page 1051) rxrdy full error dataerr / nakto flush reqpkt stalled clrdt july 03, 2014 1362 texas instruments-production data register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 usbrxcsrl11, type r/w, offset 0x1b6, reset 0x00 (otg a / host mode) (see page 1051) rxrdy full error dataerr / nakto flush reqpkt stalled clrdt usbrxcsrl12, type r/w, offset 0x1c6, reset 0x00 (otg a / host mode) (see page 1051) rxrdy full error dataerr / nakto flush reqpkt stalled clrdt usbrxcsrl13, type r/w, offset 0x1d6, reset 0x00 (otg a / host mode) (see page 1051) rxrdy full error dataerr / nakto flush reqpkt stalled clrdt usbrxcsrl14, type r/w, offset 0x1e6, reset 0x00 (otg a / host mode) (see page 1051) rxrdy full error dataerr / nakto flush reqpkt stalled clrdt usbrxcsrl15, type r/w, offset 0x1f6, reset 0x00 (otg a / host mode) (see page 1051) rxrdy full error dataerr / nakto flush reqpkt stalled clrdt usbrxcsrl1, type r/w, offset 0x116, reset 0x00 (otg b / device mode) (see page 1051) rxrdy full over dataerr flush stall stalled clrdt usbrxcsrl2, type r/w, offset 0x126, reset 0x00 (otg b / device mode) (see page 1051) rxrdy full over dataerr flush stall stalled clrdt usbrxcsrl3, type r/w, offset 0x136, reset 0x00 (otg b / device mode) (see page 1051) rxrdy full over dataerr flush stall stalled clrdt usbrxcsrl4, type r/w, offset 0x146, reset 0x00 (otg b / device mode) (see page 1051) rxrdy full over dataerr flush stall stalled clrdt usbrxcsrl5, type r/w, offset 0x156, reset 0x00 (otg b / device mode) (see page 1051) rxrdy full over dataerr flush stall stalled clrdt usbrxcsrl6, type r/w, offset 0x166, reset 0x00 (otg b / device mode) (see page 1051) rxrdy full over dataerr flush stall stalled clrdt usbrxcsrl7, type r/w, offset 0x176, reset 0x00 (otg b / device mode) (see page 1051) rxrdy full over dataerr flush stall stalled clrdt usbrxcsrl8, type r/w, offset 0x186, reset 0x00 (otg b / device mode) (see page 1051) rxrdy full over dataerr flush stall stalled clrdt usbrxcsrl9, type r/w, offset 0x196, reset 0x00 (otg b / device mode) (see page 1051) rxrdy full over dataerr flush stall stalled clrdt usbrxcsrl10, type r/w, offset 0x1a6, reset 0x00 (otg b / device mode) (see page 1051) rxrdy full over dataerr flush stall stalled clrdt usbrxcsrl11, type r/w, offset 0x1b6, reset 0x00 (otg b / device mode) (see page 1051) rxrdy full over dataerr flush stall stalled clrdt usbrxcsrl12, type r/w, offset 0x1c6, reset 0x00 (otg b / device mode) (see page 1051) rxrdy full over dataerr flush stall stalled clrdt 1363 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 usbrxcsrl13, type r/w, offset 0x1d6, reset 0x00 (otg b / device mode) (see page 1051) rxrdy full over dataerr flush stall stalled clrdt usbrxcsrl14, type r/w, offset 0x1e6, reset 0x00 (otg b / device mode) (see page 1051) rxrdy full over dataerr flush stall stalled clrdt usbrxcsrl15, type r/w, offset 0x1f6, reset 0x00 (otg b / device mode) (see page 1051) rxrdy full over dataerr flush stall stalled clrdt usbrxcsrh1, type r/w, offset 0x117, reset 0x00 (otg a / host mode) (see page 1056) dt dtwe dmamod piderr dmaen autorq autocl usbrxcsrh2, type r/w, offset 0x127, reset 0x00 (otg a / host mode) (see page 1056) dt dtwe dmamod piderr dmaen autorq autocl usbrxcsrh3, type r/w, offset 0x137, reset 0x00 (otg a / host mode) (see page 1056) dt dtwe dmamod piderr dmaen autorq autocl usbrxcsrh4, type r/w, offset 0x147, reset 0x00 (otg a / host mode) (see page 1056) dt dtwe dmamod piderr dmaen autorq autocl usbrxcsrh5, type r/w, offset 0x157, reset 0x00 (otg a / host mode) (see page 1056) dt dtwe dmamod piderr dmaen autorq autocl usbrxcsrh6, type r/w, offset 0x167, reset 0x00 (otg a / host mode) (see page 1056) dt dtwe dmamod piderr dmaen autorq autocl usbrxcsrh7, type r/w, offset 0x177, reset 0x00 (otg a / host mode) (see page 1056) dt dtwe dmamod piderr dmaen autorq autocl usbrxcsrh8, type r/w, offset 0x187, reset 0x00 (otg a / host mode) (see page 1056) dt dtwe dmamod piderr dmaen autorq autocl usbrxcsrh9, type r/w, offset 0x197, reset 0x00 (otg a / host mode) (see page 1056) dt dtwe dmamod piderr dmaen autorq autocl usbrxcsrh10, type r/w, offset 0x1a7, reset 0x00 (otg a / host mode) (see page 1056) dt dtwe dmamod piderr dmaen autorq autocl usbrxcsrh11, type r/w, offset 0x1b7, reset 0x00 (otg a / host mode) (see page 1056) dt dtwe dmamod piderr dmaen autorq autocl usbrxcsrh12, type r/w, offset 0x1c7, reset 0x00 (otg a / host mode) (see page 1056) dt dtwe dmamod piderr dmaen autorq autocl usbrxcsrh13, type r/w, offset 0x1d7, reset 0x00 (otg a / host mode) (see page 1056) dt dtwe dmamod piderr dmaen autorq autocl usbrxcsrh14, type r/w, offset 0x1e7, reset 0x00 (otg a / host mode) (see page 1056) dt dtwe dmamod piderr dmaen autorq autocl usbrxcsrh15, type r/w, offset 0x1f7, reset 0x00 (otg a / host mode) (see page 1056) dt dtwe dmamod piderr dmaen autorq autocl usbrxcsrh1, type r/w, offset 0x117, reset 0x00 (otg b / device mode) (see page 1056) dmamod disnyet / piderr dmaen iso autocl usbrxcsrh2, type r/w, offset 0x127, reset 0x00 (otg b / device mode) (see page 1056) dmamod disnyet / piderr dmaen iso autocl july 03, 2014 1364 texas instruments-production data register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 usbrxcsrh3, type r/w, offset 0x137, reset 0x00 (otg b / device mode) (see page 1056) dmamod disnyet / piderr dmaen iso autocl usbrxcsrh4, type r/w, offset 0x147, reset 0x00 (otg b / device mode) (see page 1056) dmamod disnyet / piderr dmaen iso autocl usbrxcsrh5, type r/w, offset 0x157, reset 0x00 (otg b / device mode) (see page 1056) dmamod disnyet / piderr dmaen iso autocl usbrxcsrh6, type r/w, offset 0x167, reset 0x00 (otg b / device mode) (see page 1056) dmamod disnyet / piderr dmaen iso autocl usbrxcsrh7, type r/w, offset 0x177, reset 0x00 (otg b / device mode) (see page 1056) dmamod disnyet / piderr dmaen iso autocl usbrxcsrh8, type r/w, offset 0x187, reset 0x00 (otg b / device mode) (see page 1056) dmamod disnyet / piderr dmaen iso autocl usbrxcsrh9, type r/w, offset 0x197, reset 0x00 (otg b / device mode) (see page 1056) dmamod disnyet / piderr dmaen iso autocl usbrxcsrh10, type r/w, offset 0x1a7, reset 0x00 (otg b / device mode) (see page 1056) dmamod disnyet / piderr dmaen iso autocl usbrxcsrh11, type r/w, offset 0x1b7, reset 0x00 (otg b / device mode) (see page 1056) dmamod disnyet / piderr dmaen iso autocl 1365 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 usbrxcsrh12, type r/w, offset 0x1c7, reset 0x00 (otg b / device mode) (see page 1056) dmamod disnyet / piderr dmaen iso autocl usbrxcsrh13, type r/w, offset 0x1d7, reset 0x00 (otg b / device mode) (see page 1056) dmamod disnyet / piderr dmaen iso autocl usbrxcsrh14, type r/w, offset 0x1e7, reset 0x00 (otg b / device mode) (see page 1056) dmamod disnyet / piderr dmaen iso autocl usbrxcsrh15, type r/w, offset 0x1f7, reset 0x00 (otg b / device mode) (see page 1056) dmamod disnyet / piderr dmaen iso autocl usbrxcount1, type ro, offset 0x118, reset 0x0000 (see page 1061) count usbrxcount2, type ro, offset 0x128, reset 0x0000 (see page 1061) count usbrxcount3, type ro, offset 0x138, reset 0x0000 (see page 1061) count usbrxcount4, type ro, offset 0x148, reset 0x0000 (see page 1061) count usbrxcount5, type ro, offset 0x158, reset 0x0000 (see page 1061) count usbrxcount6, type ro, offset 0x168, reset 0x0000 (see page 1061) count usbrxcount7, type ro, offset 0x178, reset 0x0000 (see page 1061) count usbrxcount8, type ro, offset 0x188, reset 0x0000 (see page 1061) count usbrxcount9, type ro, offset 0x198, reset 0x0000 (see page 1061) count usbrxcount10, type ro, offset 0x1a8, reset 0x0000 (see page 1061) count usbrxcount11, type ro, offset 0x1b8, reset 0x0000 (see page 1061) count usbrxcount12, type ro, offset 0x1c8, reset 0x0000 (see page 1061) count usbrxcount13, type ro, offset 0x1d8, reset 0x0000 (see page 1061) count usbrxcount14, type ro, offset 0x1e8, reset 0x0000 (see page 1061) count usbrxcount15, type ro, offset 0x1f8, reset 0x0000 (see page 1061) count july 03, 2014 1366 texas instruments-production data register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 usbtxtype1, type r/w, offset 0x11a, reset 0x00 (see page 1063) tep proto speed usbtxtype2, type r/w, offset 0x12a, reset 0x00 (see page 1063) tep proto speed usbtxtype3, type r/w, offset 0x13a, reset 0x00 (see page 1063) tep proto speed usbtxtype4, type r/w, offset 0x14a, reset 0x00 (see page 1063) tep proto speed usbtxtype5, type r/w, offset 0x15a, reset 0x00 (see page 1063) tep proto speed usbtxtype6, type r/w, offset 0x16a, reset 0x00 (see page 1063) tep proto speed usbtxtype7, type r/w, offset 0x17a, reset 0x00 (see page 1063) tep proto speed usbtxtype8, type r/w, offset 0x18a, reset 0x00 (see page 1063) tep proto speed usbtxtype9, type r/w, offset 0x19a, reset 0x00 (see page 1063) tep proto speed usbtxtype10, type r/w, offset 0x1aa, reset 0x00 (see page 1063) tep proto speed usbtxtype11, type r/w, offset 0x1ba, reset 0x00 (see page 1063) tep proto speed usbtxtype12, type r/w, offset 0x1ca, reset 0x00 (see page 1063) tep proto speed usbtxtype13, type r/w, offset 0x1da, reset 0x00 (see page 1063) tep proto speed usbtxtype14, type r/w, offset 0x1ea, reset 0x00 (see page 1063) tep proto speed usbtxtype15, type r/w, offset 0x1fa, reset 0x00 (see page 1063) tep proto speed usbtxinterval1, type r/w, offset 0x11b, reset 0x00 (see page 1065) txpoll / naklmt usbtxinterval2, type r/w, offset 0x12b, reset 0x00 (see page 1065) txpoll / naklmt usbtxinterval3, type r/w, offset 0x13b, reset 0x00 (see page 1065) txpoll / naklmt usbtxinterval4, type r/w, offset 0x14b, reset 0x00 (see page 1065) txpoll / naklmt usbtxinterval5, type r/w, offset 0x15b, reset 0x00 (see page 1065) txpoll / naklmt usbtxinterval6, type r/w, offset 0x16b, reset 0x00 (see page 1065) txpoll / naklmt usbtxinterval7, type r/w, offset 0x17b, reset 0x00 (see page 1065) txpoll / naklmt usbtxinterval8, type r/w, offset 0x18b, reset 0x00 (see page 1065) txpoll / naklmt usbtxinterval9, type r/w, offset 0x19b, reset 0x00 (see page 1065) txpoll / naklmt usbtxinterval10, type r/w, offset 0x1ab, reset 0x00 (see page 1065) txpoll / naklmt usbtxinterval11, type r/w, offset 0x1bb, reset 0x00 (see page 1065) txpoll / naklmt 1367 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 usbtxinterval12, type r/w, offset 0x1cb, reset 0x00 (see page 1065) txpoll / naklmt usbtxinterval13, type r/w, offset 0x1db, reset 0x00 (see page 1065) txpoll / naklmt usbtxinterval14, type r/w, offset 0x1eb, reset 0x00 (see page 1065) txpoll / naklmt usbtxinterval15, type r/w, offset 0x1fb, reset 0x00 (see page 1065) txpoll / naklmt usbrxtype1, type r/w, offset 0x11c, reset 0x00 (see page 1067) tep proto speed usbrxtype2, type r/w, offset 0x12c, reset 0x00 (see page 1067) tep proto speed usbrxtype3, type r/w, offset 0x13c, reset 0x00 (see page 1067) tep proto speed usbrxtype4, type r/w, offset 0x14c, reset 0x00 (see page 1067) tep proto speed usbrxtype5, type r/w, offset 0x15c, reset 0x00 (see page 1067) tep proto speed usbrxtype6, type r/w, offset 0x16c, reset 0x00 (see page 1067) tep proto speed usbrxtype7, type r/w, offset 0x17c, reset 0x00 (see page 1067) tep proto speed usbrxtype8, type r/w, offset 0x18c, reset 0x00 (see page 1067) tep proto speed usbrxtype9, type r/w, offset 0x19c, reset 0x00 (see page 1067) tep proto speed usbrxtype10, type r/w, offset 0x1ac, reset 0x00 (see page 1067) tep proto speed usbrxtype11, type r/w, offset 0x1bc, reset 0x00 (see page 1067) tep proto speed usbrxtype12, type r/w, offset 0x1cc, reset 0x00 (see page 1067) tep proto speed usbrxtype13, type r/w, offset 0x1dc, reset 0x00 (see page 1067) tep proto speed usbrxtype14, type r/w, offset 0x1ec, reset 0x00 (see page 1067) tep proto speed usbrxtype15, type r/w, offset 0x1fc, reset 0x00 (see page 1067) tep proto speed usbrxinterval1, type r/w, offset 0x11d, reset 0x00 (see page 1069) txpoll / naklmt usbrxinterval2, type r/w, offset 0x12d, reset 0x00 (see page 1069) txpoll / naklmt usbrxinterval3, type r/w, offset 0x13d, reset 0x00 (see page 1069) txpoll / naklmt usbrxinterval4, type r/w, offset 0x14d, reset 0x00 (see page 1069) txpoll / naklmt usbrxinterval5, type r/w, offset 0x15d, reset 0x00 (see page 1069) txpoll / naklmt usbrxinterval6, type r/w, offset 0x16d, reset 0x00 (see page 1069) txpoll / naklmt usbrxinterval7, type r/w, offset 0x17d, reset 0x00 (see page 1069) txpoll / naklmt july 03, 2014 1368 texas instruments-production data register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 usbrxinterval8, type r/w, offset 0x18d, reset 0x00 (see page 1069) txpoll / naklmt usbrxinterval9, type r/w, offset 0x19d, reset 0x00 (see page 1069) txpoll / naklmt usbrxinterval10, type r/w, offset 0x1ad, reset 0x00 (see page 1069) txpoll / naklmt usbrxinterval11, type r/w, offset 0x1bd, reset 0x00 (see page 1069) txpoll / naklmt usbrxinterval12, type r/w, offset 0x1cd, reset 0x00 (see page 1069) txpoll / naklmt usbrxinterval13, type r/w, offset 0x1dd, reset 0x00 (see page 1069) txpoll / naklmt usbrxinterval14, type r/w, offset 0x1ed, reset 0x00 (see page 1069) txpoll / naklmt usbrxinterval15, type r/w, offset 0x1fd, reset 0x00 (see page 1069) txpoll / naklmt usbrqpktcount1, type r/w, offset 0x304, reset 0x0000 (see page 1071) count usbrqpktcount2, type r/w, offset 0x308, reset 0x0000 (see page 1071) count usbrqpktcount3, type r/w, offset 0x30c, reset 0x0000 (see page 1071) count usbrqpktcount4, type r/w, offset 0x310, reset 0x0000 (see page 1071) count usbrqpktcount5, type r/w, offset 0x314, reset 0x0000 (see page 1071) count usbrqpktcount6, type r/w, offset 0x318, reset 0x0000 (see page 1071) count usbrqpktcount7, type r/w, offset 0x31c, reset 0x0000 (see page 1071) count usbrqpktcount8, type r/w, offset 0x320, reset 0x0000 (see page 1071) count usbrqpktcount9, type r/w, offset 0x324, reset 0x0000 (see page 1071) count usbrqpktcount10, type r/w, offset 0x328, reset 0x0000 (see page 1071) count usbrqpktcount11, type r/w, offset 0x32c, reset 0x0000 (see page 1071) count usbrqpktcount12, type r/w, offset 0x330, reset 0x0000 (see page 1071) count usbrqpktcount13, type r/w, offset 0x334, reset 0x0000 (see page 1071) count usbrqpktcount14, type r/w, offset 0x338, reset 0x0000 (see page 1071) count usbrqpktcount15, type r/w, offset 0x33c, reset 0x0000 (see page 1071) count usbrxdpktbufdis, type r/w, offset 0x340, reset 0x0000 (see page 1073) ep1 ep2 ep3 ep4 ep5 ep6 ep7 ep8 ep9 ep10 ep11 ep12 ep13 ep14 ep15 usbtxdpktbufdis, type r/w, offset 0x342, reset 0x0000 (see page 1075) ep1 ep2 ep3 ep4 ep5 ep6 ep7 ep8 ep9 ep10 ep11 ep12 ep13 ep14 ep15 1369 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 usbepc, type r/w, offset 0x400, reset 0x0000.0000 (see page 1077) epen epende pflten pfltsen pfltaen pfltact usbepcris, type ro, offset 0x404, reset 0x0000.0000 (see page 1080) pf usbepcim, type r/w, offset 0x408, reset 0x0000.0000 (see page 1081) pf usbepcisc, type r/w, offset 0x40c, reset 0x0000.0000 (see page 1082) pf usbdrris, type ro, offset 0x410, reset 0x0000.0000 (see page 1083) resume usbdrim, type r/w, offset 0x414, reset 0x0000.0000 (see page 1084) resume usbdrisc, type w1c, offset 0x418, reset 0x0000.0000 (see page 1085) resume usbgpcs, type r/w, offset 0x41c, reset 0x0000.0001 (see page 1086) devmod devmodotg usbvdc, type r/w, offset 0x430, reset 0x0000.0000 (see page 1087) vbden usbvdcris, type ro, offset 0x434, reset 0x0000.0000 (see page 1088) vd usbvdcim, type r/w, offset 0x438, reset 0x0000.0000 (see page 1089) vd usbvdcisc, type r/w, offset 0x43c, reset 0x0000.0000 (see page 1090) vd usbidvris, type ro, offset 0x444, reset 0x0000.0000 (see page 1091) id usbidvim, type r/w, offset 0x448, reset 0x0000.0000 (see page 1092) id usbidvisc, type r/w1c, offset 0x44c, reset 0x0000.0000 (see page 1093) id usbdmasel, type r/w, offset 0x450, reset 0x0033.2211 (see page 1094) dmacrx dmactx dmaarx dmaatx dmabrx dmabtx analog comparators base 0x4003.c000 acmis, type r/w1c, offset 0x000, reset 0x0000.0000 (see page 1103) in0 in1 in2 july 03, 2014 1370 texas instruments-production data register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 acris, type ro, offset 0x004, reset 0x0000.0000 (see page 1104) in0 in1 in2 acinten, type r/w, offset 0x008, reset 0x0000.0000 (see page 1105) in0 in1 in2 acrefctl, type r/w, offset 0x010, reset 0x0000.0000 (see page 1106) vref rng en acstat0, type ro, offset 0x020, reset 0x0000.0000 (see page 1107) oval acstat1, type ro, offset 0x040, reset 0x0000.0000 (see page 1107) oval acstat2, type ro, offset 0x060, reset 0x0000.0000 (see page 1107) oval acctl0, type r/w, offset 0x024, reset 0x0000.0000 (see page 1108) cinv isen islval tsen tslval asrcp toen acctl1, type r/w, offset 0x044, reset 0x0000.0000 (see page 1108) cinv isen islval tsen tslval asrcp toen acctl2, type r/w, offset 0x064, reset 0x0000.0000 (see page 1108) cinv isen islval tsen tslval asrcp toen pulse width modulator (pwm) pwm0 base: 0x4002.8000 pwmctl, type r/w, offset 0x000, reset 0x0000.0000 (see page 1126) globalsync0 globalsync1 globalsync2 globalsync3 pwmsync, type r/w, offset 0x004, reset 0x0000.0000 (see page 1128) sync0 sync1 sync2 sync3 pwmenable, type r/w, offset 0x008, reset 0x0000.0000 (see page 1129) pwm0en pwm1en pwm2en pwm3en pwm4en pwm5en pwm6en pwm7en pwminvert, type r/w, offset 0x00c, reset 0x0000.0000 (see page 1131) pwm0inv pwm1inv pwm2inv pwm3inv pwm4inv pwm5inv pwm6inv pwm7inv pwmfault, type r/w, offset 0x010, reset 0x0000.0000 (see page 1133) fault0 fault1 fault2 fault3 fault4 fault5 fault6 fault7 pwminten, type r/w, offset 0x014, reset 0x0000.0000 (see page 1135) intfault0 intfault1 intfault2 intfault3 intpwm0 intpwm1 intpwm2 intpwm3 pwmris, type ro, offset 0x018, reset 0x0000.0000 (see page 1137) intfault0 intfault1 intfault2 intfault3 intpwm0 intpwm1 intpwm2 intpwm3 1371 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pwmisc, type r/w1c, offset 0x01c, reset 0x0000.0000 (see page 1140) intfault0 intfault1 intfault2 intfault3 intpwm0 intpwm1 intpwm2 intpwm3 pwmstatus, type ro, offset 0x020, reset 0x0000.0000 (see page 1143) fault0 fault1 fault2 fault3 pwmfaultval, type r/w, offset 0x024, reset 0x0000.0000 (see page 1145) pwm0 pwm1 pwm2 pwm3 pwm4 pwm5 pwm6 pwm7 pwmenupd, type r/w, offset 0x028, reset 0x0000.0000 (see page 1147) enupd0 enupd1 enupd2 enupd3 enupd4 enupd5 enupd6 enupd7 pwm0ctl, type r/w, offset 0x040, reset 0x0000.0000 (see page 1151) fltsrc minfltper latch enable mode debug loadupd cmpaupd cmpbupd genaupd genbupd dbctlupd dbriseupd dbfallupd pwm1ctl, type r/w, offset 0x080, reset 0x0000.0000 (see page 1151) fltsrc minfltper latch enable mode debug loadupd cmpaupd cmpbupd genaupd genbupd dbctlupd dbriseupd dbfallupd pwm2ctl, type r/w, offset 0x0c0, reset 0x0000.0000 (see page 1151) fltsrc minfltper latch enable mode debug loadupd cmpaupd cmpbupd genaupd genbupd dbctlupd dbriseupd dbfallupd pwm3ctl, type r/w, offset 0x100, reset 0x0000.0000 (see page 1151) fltsrc minfltper latch enable mode debug loadupd cmpaupd cmpbupd genaupd genbupd dbctlupd dbriseupd dbfallupd pwm0inten, type r/w, offset 0x044, reset 0x0000.0000 (see page 1156) intcntzero intcntload intcmpau intcmpad intcmpbu intcmpbd trcntzero trcntload trcmpau trcmpad trcmpbu trcmpbd pwm1inten, type r/w, offset 0x084, reset 0x0000.0000 (see page 1156) intcntzero intcntload intcmpau intcmpad intcmpbu intcmpbd trcntzero trcntload trcmpau trcmpad trcmpbu trcmpbd pwm2inten, type r/w, offset 0x0c4, reset 0x0000.0000 (see page 1156) intcntzero intcntload intcmpau intcmpad intcmpbu intcmpbd trcntzero trcntload trcmpau trcmpad trcmpbu trcmpbd pwm3inten, type r/w, offset 0x104, reset 0x0000.0000 (see page 1156) intcntzero intcntload intcmpau intcmpad intcmpbu intcmpbd trcntzero trcntload trcmpau trcmpad trcmpbu trcmpbd pwm0ris, type ro, offset 0x048, reset 0x0000.0000 (see page 1159) intcntzero intcntload intcmpau intcmpad intcmpbu intcmpbd pwm1ris, type ro, offset 0x088, reset 0x0000.0000 (see page 1159) intcntzero intcntload intcmpau intcmpad intcmpbu intcmpbd pwm2ris, type ro, offset 0x0c8, reset 0x0000.0000 (see page 1159) intcntzero intcntload intcmpau intcmpad intcmpbu intcmpbd pwm3ris, type ro, offset 0x108, reset 0x0000.0000 (see page 1159) intcntzero intcntload intcmpau intcmpad intcmpbu intcmpbd pwm0isc, type r/w1c, offset 0x04c, reset 0x0000.0000 (see page 1161) intcntzero intcntload intcmpau intcmpad intcmpbu intcmpbd july 03, 2014 1372 texas instruments-production data register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pwm1isc, type r/w1c, offset 0x08c, reset 0x0000.0000 (see page 1161) intcntzero intcntload intcmpau intcmpad intcmpbu intcmpbd pwm2isc, type r/w1c, offset 0x0cc, reset 0x0000.0000 (see page 1161) intcntzero intcntload intcmpau intcmpad intcmpbu intcmpbd pwm3isc, type r/w1c, offset 0x10c, reset 0x0000.0000 (see page 1161) intcntzero intcntload intcmpau intcmpad intcmpbu intcmpbd pwm0load, type r/w, offset 0x050, reset 0x0000.0000 (see page 1163) load pwm1load, type r/w, offset 0x090, reset 0x0000.0000 (see page 1163) load pwm2load, type r/w, offset 0x0d0, reset 0x0000.0000 (see page 1163) load pwm3load, type r/w, offset 0x110, reset 0x0000.0000 (see page 1163) load pwm0count, type ro, offset 0x054, reset 0x0000.0000 (see page 1164) count pwm1count, type ro, offset 0x094, reset 0x0000.0000 (see page 1164) count pwm2count, type ro, offset 0x0d4, reset 0x0000.0000 (see page 1164) count pwm3count, type ro, offset 0x114, reset 0x0000.0000 (see page 1164) count pwm0cmpa, type r/w, offset 0x058, reset 0x0000.0000 (see page 1165) compa pwm1cmpa, type r/w, offset 0x098, reset 0x0000.0000 (see page 1165) compa pwm2cmpa, type r/w, offset 0x0d8, reset 0x0000.0000 (see page 1165) compa pwm3cmpa, type r/w, offset 0x118, reset 0x0000.0000 (see page 1165) compa pwm0cmpb, type r/w, offset 0x05c, reset 0x0000.0000 (see page 1166) compb pwm1cmpb, type r/w, offset 0x09c, reset 0x0000.0000 (see page 1166) compb 1373 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pwm2cmpb, type r/w, offset 0x0dc, reset 0x0000.0000 (see page 1166) compb pwm3cmpb, type r/w, offset 0x11c, reset 0x0000.0000 (see page 1166) compb pwm0gena, type r/w, offset 0x060, reset 0x0000.0000 (see page 1167) actzero actload actcmpau actcmpad actcmpbu actcmpbd pwm1gena, type r/w, offset 0x0a0, reset 0x0000.0000 (see page 1167) actzero actload actcmpau actcmpad actcmpbu actcmpbd pwm2gena, type r/w, offset 0x0e0, reset 0x0000.0000 (see page 1167) actzero actload actcmpau actcmpad actcmpbu actcmpbd pwm3gena, type r/w, offset 0x120, reset 0x0000.0000 (see page 1167) actzero actload actcmpau actcmpad actcmpbu actcmpbd pwm0genb, type r/w, offset 0x064, reset 0x0000.0000 (see page 1170) actzero actload actcmpau actcmpad actcmpbu actcmpbd pwm1genb, type r/w, offset 0x0a4, reset 0x0000.0000 (see page 1170) actzero actload actcmpau actcmpad actcmpbu actcmpbd pwm2genb, type r/w, offset 0x0e4, reset 0x0000.0000 (see page 1170) actzero actload actcmpau actcmpad actcmpbu actcmpbd pwm3genb, type r/w, offset 0x124, reset 0x0000.0000 (see page 1170) actzero actload actcmpau actcmpad actcmpbu actcmpbd pwm0dbctl, type r/w, offset 0x068, reset 0x0000.0000 (see page 1173) enable pwm1dbctl, type r/w, offset 0x0a8, reset 0x0000.0000 (see page 1173) enable pwm2dbctl, type r/w, offset 0x0e8, reset 0x0000.0000 (see page 1173) enable pwm3dbctl, type r/w, offset 0x128, reset 0x0000.0000 (see page 1173) enable pwm0dbrise, type r/w, offset 0x06c, reset 0x0000.0000 (see page 1174) risedelay pwm1dbrise, type r/w, offset 0x0ac, reset 0x0000.0000 (see page 1174) risedelay pwm2dbrise, type r/w, offset 0x0ec, reset 0x0000.0000 (see page 1174) risedelay july 03, 2014 1374 texas instruments-production data register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pwm3dbrise, type r/w, offset 0x12c, reset 0x0000.0000 (see page 1174) risedelay pwm0dbfall, type r/w, offset 0x070, reset 0x0000.0000 (see page 1175) falldelay pwm1dbfall, type r/w, offset 0x0b0, reset 0x0000.0000 (see page 1175) falldelay pwm2dbfall, type r/w, offset 0x0f0, reset 0x0000.0000 (see page 1175) falldelay pwm3dbfall, type r/w, offset 0x130, reset 0x0000.0000 (see page 1175) falldelay pwm0fltsrc0, type r/w, offset 0x074, reset 0x0000.0000 (see page 1176) fault0 fault1 fault2 fault3 pwm1fltsrc0, type r/w, offset 0x0b4, reset 0x0000.0000 (see page 1176) fault0 fault1 fault2 fault3 pwm2fltsrc0, type r/w, offset 0x0f4, reset 0x0000.0000 (see page 1176) fault0 fault1 fault2 fault3 pwm3fltsrc0, type r/w, offset 0x134, reset 0x0000.0000 (see page 1176) fault0 fault1 fault2 fault3 pwm0fltsrc1, type r/w, offset 0x078, reset 0x0000.0000 (see page 1178) dcmp0 dcmp1 dcmp2 dcmp3 dcmp4 dcmp5 dcmp6 dcmp7 pwm1fltsrc1, type r/w, offset 0x0b8, reset 0x0000.0000 (see page 1178) dcmp0 dcmp1 dcmp2 dcmp3 dcmp4 dcmp5 dcmp6 dcmp7 pwm2fltsrc1, type r/w, offset 0x0f8, reset 0x0000.0000 (see page 1178) dcmp0 dcmp1 dcmp2 dcmp3 dcmp4 dcmp5 dcmp6 dcmp7 pwm3fltsrc1, type r/w, offset 0x138, reset 0x0000.0000 (see page 1178) dcmp0 dcmp1 dcmp2 dcmp3 dcmp4 dcmp5 dcmp6 dcmp7 pwm0minfltper, type r/w, offset 0x07c, reset 0x0000.0000 (see page 1181) mfp pwm1minfltper, type r/w, offset 0x0bc, reset 0x0000.0000 (see page 1181) mfp pwm2minfltper, type r/w, offset 0x0fc, reset 0x0000.0000 (see page 1181) mfp pwm3minfltper, type r/w, offset 0x13c, reset 0x0000.0000 (see page 1181) mfp 1375 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pwm0fltsen, type r/w, offset 0x800, reset 0x0000.0000 (see page 1182) fault0 fault1 fault2 fault3 pwm1fltsen, type r/w, offset 0x880, reset 0x0000.0000 (see page 1182) fault0 fault1 fault2 fault3 pwm2fltsen, type r/w, offset 0x900, reset 0x0000.0000 (see page 1182) fault0 fault1 fault2 fault3 pwm3fltsen, type r/w, offset 0x980, reset 0x0000.0000 (see page 1182) fault0 fault1 fault2 fault3 pwm0fltstat0, type -, offset 0x804, reset 0x0000.0000 (see page 1183) fault0 fault1 fault2 fault3 pwm1fltstat0, type -, offset 0x884, reset 0x0000.0000 (see page 1183) fault0 fault1 fault2 fault3 pwm2fltstat0, type -, offset 0x904, reset 0x0000.0000 (see page 1183) fault0 fault1 fault2 fault3 pwm3fltstat0, type -, offset 0x984, reset 0x0000.0000 (see page 1183) fault0 fault1 fault2 fault3 pwm0fltstat1, type -, offset 0x808, reset 0x0000.0000 (see page 1185) dcmp0 dcmp1 dcmp2 dcmp3 dcmp4 dcmp5 dcmp6 dcmp7 pwm1fltstat1, type -, offset 0x888, reset 0x0000.0000 (see page 1185) dcmp0 dcmp1 dcmp2 dcmp3 dcmp4 dcmp5 dcmp6 dcmp7 pwm2fltstat1, type -, offset 0x908, reset 0x0000.0000 (see page 1185) dcmp0 dcmp1 dcmp2 dcmp3 dcmp4 dcmp5 dcmp6 dcmp7 pwm3fltstat1, type -, offset 0x988, reset 0x0000.0000 (see page 1185) dcmp0 dcmp1 dcmp2 dcmp3 dcmp4 dcmp5 dcmp6 dcmp7 quadrature encoder interface (qei) qei0 base: 0x4002.c000 qei1 base: 0x4002.d000 qeictl, type r/w, offset 0x000, reset 0x0000.0000 (see page 1195) filtcnt enable swap sigmode capmode resmode velen veldiv inva invb invi stallen filten qeistat, type ro, offset 0x004, reset 0x0000.0000 (see page 1198) error direction qeipos, type r/w, offset 0x008, reset 0x0000.0000 (see page 1199) position position qeimaxpos, type r/w, offset 0x00c, reset 0x0000.0000 (see page 1200) maxpos maxpos july 03, 2014 1376 texas instruments-production data register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 qeiload, type r/w, offset 0x010, reset 0x0000.0000 (see page 1201) load load qeitime, type ro, offset 0x014, reset 0x0000.0000 (see page 1202) time time qeicount, type ro, offset 0x018, reset 0x0000.0000 (see page 1203) count count qeispeed, type ro, offset 0x01c, reset 0x0000.0000 (see page 1204) speed speed qeiinten, type r/w, offset 0x020, reset 0x0000.0000 (see page 1205) intindex inttimer intdir interror qeiris, type ro, offset 0x024, reset 0x0000.0000 (see page 1207) intindex inttimer intdir interror qeiisc, type r/w1c, offset 0x028, reset 0x0000.0000 (see page 1209) intindex inttimer intdir interror 1377 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller b ordering and contact information b.1 ordering information the figure below defines the full set of potential orderable part numbers for all the stellaris ? lm3s microcontrollers. see the package option addendum for the valid orderable part numbers for the lm3s9gn5 microcontroller. b.2 part markings the stellaris microcontrollers are marked with an identifying number. this code contains the following information: the first line indicates the part number, for example, lm3s9b90. in the second line, the first eight characters indicate the temperature, package, speed, revision, and product status. for example in the figure below, iqc80c0x indicates an industrial temperature (i), 100-pin lqfp package (qc), 80-mhz (80), revision c0 (c0) device. the letter immediately following the revision indicates product status. an x indicates experimental and requires a waiver; an s indicates the part is fully qualified and released to production. the remaining characters contain internal tracking numbers. b.3 kits the stellaris family provides the hardware and software tools that engineers need to begin development quickly. july 03, 2014 1378 texas instruments-production data ordering and contact information / 0 6 q q q q j s s v v u u p 3 d u w 1 x p e h u 7 h p s h u d w x u h 3 d f n d j h 6 s h h g 5 h y l v l r q 6 k l s s l q j 0 h g l x p ( ? & w r ? & , ? & w r ? & 7 7 d s h d q g u h h o 2 p l w w h g ' h i d x o w v k l s s l q j w u d \ r u w x e h % = e d o o % * $ 4 & s l q / 4 ) 3 4 1 s l q / 4 ) 3 4 5 s l q / 4 ) 3 0 + ] 0 + ] 0 + ] 0 + ] q q q 6 d q g v w r u p f o d v v s d u w v q q q q $ o o r w k h u 6 w h o o d u l v ? s d u w v reference design kits accelerate product development by providing ready-to-run hardware and comprehensive documentation including hardware design files evaluation kits provide a low-cost and effective means of evaluating stellaris microcontrollers before purchase development kits provide you with all the tools you need to develop and prototype embedded applications right out of the box see the website at www.ti.com/stellaris for the latest tools available, or ask your distributor. b.4 support information for support on stellaris products, contact the ti worldwide product information center nearest you: http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm . 1379 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller c package information c.1 100-pin lqfp package c.1.1 package dimensions figure c-1. stellaris lm3s9gn5 100-pin lqfp package dimensions note: the following notes apply to the package drawing. 1. all dimensions shown in mm. 2. dimensions shown are nominal with tolerances indicated. 3. foot length 'l' is measured at gage plane 0.25 mm above seating plane. july 03, 2014 1380 texas instruments-production data package information body +2.00 mm footprint, 1.4 mm package thickness 100l leads symbols 1.60 max. a 0.05 min./0.15 max. - a 1 1.40 0.05 a 2 16.00 0.20 d 14.00 0.05 d 1 16.00 0.20 e 14.00 0.05 e 1 0.60 +0.15/-0.10 l 0.50 basic e 0.22 +0.05 b 0?-7? - 0.08 max. ddd 0.08 max. ccc ms-026 jedec reference drawing bed variation designator 1381 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller c.1.2 tray dimensions figure c-2. 100-pin lqfp tray dimensions c.1.3 tape and reel dimensions note: in the figure that follows, pin 1 is located in the top right corner of the device. july 03, 2014 1382 texas instruments-production data package information figure c-3. 100-pin lqfp tape and reel dimensions 1383 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller printed on must not be reproduced without written permission from sumicarrier (s) pte ltd 06.01.2003 this is a computer generated uncontrolled document 06.01.2003 06.01.2003 06.01.2003 06.01.2003 c.2 108-ball bga package c.2.1 package dimensions figure c-4. stellaris lm3s9gn5 108-ball bga package dimensions july 03, 2014 1384 texas instruments-production data package information note: the following notes apply to the package drawing. max nom min symbols 1.50 1.36 1.22 a 0.39 0.34 0.29 a1 0.75 0.70 0.65 a3 0.36 0.32 0.28 c 10.15 10.00 9.85 d 8.80 bsc d1 10.15 10.00 9.85 e 8.80 bsc e1 0.53 0.48 0.43 b .20 bbb .12 ddd 0.80 bsc e - 0.60 - f 12 m 108 n ref: jedec mo-219f 1385 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller c.2.2 tray dimensions figure c-5. 108-ball bga tray dimensions july 03, 2014 1386 texas instruments-production data package information c.2.3 tape and reel dimensions figure c-6. 108-ball bga tape and reel dimensions 1387 july 03, 2014 texas instruments-production data stellaris ? lm3s9gn5 microcontroller c-pak pte ltd package option addendum www.ti.com 1-nov-2015 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples lm3s9gn5-ibz80-a2 obsolete nfbga zcr 108 tbd call ti call ti -40 to 85 lm3s9gn5 ibz80 lm3s9gn5-ibz80-a2t obsolete nfbga zcr 108 tbd call ti call ti -40 to 85 lm3s9gn5 ibz80 lm3s9gn5-iqc80-a2 obsolete lqfp pz 100 tbd call ti call ti -40 to 85 lm3s9gn5 iqc80 LM3S9GN5-IQC80-A2T obsolete lqfp pz 100 tbd call ti call ti -40 to 85 lm3s9gn5 iqc80 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. package option addendum www.ti.com 1-nov-2015 addendum-page 2 important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. mechanical data mtqf013a october 1994 revised december 1996 1 post office box 655303 ? dallas, texas 75265 pz (s-pqfp-g100) plastic quad flatpack 4040149 /b 11/96 50 26 0,13 nom gage plane 0,25 0,45 0,75 0,05 min 0,27 51 25 75 1 12,00 typ 0,17 76 100 sq sq 15,80 16,20 13,80 1,35 1,45 1,60 max 14,20 0 7 seating plane 0,08 0,50 m 0,08 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec ms-026 important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per jesd46, latest issue, and to discontinue any product or service per jesd48, latest issue. buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all semiconductor products (also referred to herein as ? components ? ) are sold subject to ti ? s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in ti ? s terms and conditions of sale of semiconductor products. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. ti assumes no liability for applications assistance or the design of buyers ? products. buyers are responsible for their products and applications using ti components. to minimize the risks associated with buyers ? products and applications, buyers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which ti components or services are used. information published by ti regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of significant portions of ti information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. ti is not responsible or liable for such altered documentation. information of third parties may be subject to additional restrictions. resale of ti components or services with statements different from or beyond the parameters stated by ti for that component or service voids all express and any implied warranties for the associated ti component or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of ti components in its applications, notwithstanding any applications-related information or support that may be provided by ti. buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. buyer will fully indemnify ti and its representatives against any damages arising out of the use of any ti components in safety-critical applications. in some cases, ti components may be promoted specifically to facilitate safety-related applications. with such components, ti ? s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. nonetheless, such components are subject to these terms. no ti components are authorized for use in fda class iii (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. only those ti components which ti has specifically designated as military grade or ? enhanced plastic ? are designed and intended for use in military/aerospace applications or environments. buyer acknowledges and agrees that any military or aerospace use of ti components which have not been so designated is solely at the buyer ' s risk, and that buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. ti has specifically designated certain components as meeting iso/ts16949 requirements, mainly for automotive use. in any case of use of non-designated products, ti will not be responsible for any failure to meet iso/ts16949. products applications audio www.ti.com/audio automotive and transportation www.ti.com/automotive amplifiers amplifier.ti.com communications and telecom www.ti.com/communications data converters dataconverter.ti.com computers and peripherals www.ti.com/computers dlp ? products www.dlp.com consumer electronics www.ti.com/consumer-apps dsp dsp.ti.com energy and lighting www.ti.com/energy clocks and timers www.ti.com/clocks industrial www.ti.com/industrial interface interface.ti.com medical www.ti.com/medical logic logic.ti.com security www.ti.com/security power mgmt power.ti.com space, avionics and defense www.ti.com/space-avionics-defense microcontrollers microcontroller.ti.com video and imaging www.ti.com/video rfid www.ti-rfid.com omap applications processors www.ti.com/omap ti e2e community e2e.ti.com wireless connectivity www.ti.com/wirelessconnectivity mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2015, texas instruments incorporated |
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