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1 21421012fa ltc2142-12/ ltc2141-12/ltc2140-12 typical application features applications description 12-bit, 65msps/ 40msps/25msps low power dual adcs n communications n cellular base stations n software defined radios n portable medical imaging n multi-channel data acquisition n nondestructive testing n 2-channel simultaneously sampling adc n 70.8db snr n 89db sfdr n low power: 92mw/65mw/48mw total 46mw/33mw/24mw per channel n single 1.8v supply n cmos, ddr cmos, or ddr lvds outputs n selectable input ranges: 1v p-p to 2v p-p n 750mhz full power bandwidth s/h n optional data output randomizer n optional clock duty cycle stabilizer n shutdown and nap modes n serial spi port for configuration n 64-pin (9mm 9mm) qfn package the ltc ? 2142-12/ltc2141-12/ltc2140-12 are 2-channel simultaneous sampling 12-bit a/d converters designed for digitizing high frequency, wide dynamic range signals. they are perfect for demanding communications applica- tions with ac performance that includes 70.8db snr and 89db spurious free dynamic range (sfdr). ultralow jitter of 0.08ps rms allows undersampling of if frequencies with excellent noise performance. dc specs include 0.3lsb inl (typ), 0.1lsb dnl (typ) and no missing codes over temperature. the transition noise is 0.3lsb rms . the digital outputs can be either full rate cmos, double data rate cmos, or double data rate lvds. a separate output power supply allows the cmos output swing to range from 1.2v to 1.8v. the enc + and enc C inputs may be driven differentially or single-ended with a sine wave, pecl, lvds, ttl, or cmos inputs. an optional clock duty cycle stabilizer al- lows high performance at full speed for a wide range of clock duty cycles. l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. 2-tone fft, f in = 70mhz and 69mhz cmos, ddr cmos or ddr lvds outputs 1.8v v dd 1.8v ov dd clock control d1_11 d1_0 21421012 ta01a ch 1 analog input output drivers t t t gnd ognd s/h 12-bit adc core ch 2 analog input s/h 12-bit adc core d2_11 d2_0 t t t 65mhz clock frequency (mhz) C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 21821012 ta01b frequency ( mhz ) 2 1821012 ta01 b 0 10 20 30
ltc2142-12/ ltc2141-12/ltc2140-12 2 21421012fa absolute maximum ratings supply voltages (v dd , ov dd ) ....................... C0.3v to 2v analog input voltage (a in + , a in C , par/ ser , sense) (note 3) .......... C0.3v to (v dd + 0.2v) digital input voltage (enc + , enc C , cs , sdi, sck) (note 4) .................................... C0.3v to 3.9v sdo (note 4) ............................................. C0.3v to 3.9v (notes 1, 2) pin configurations digital output voltage ................ C0.3v to (ov dd + 0.3v) operating temperature range ltc2142c, ltc2141c, ltc2140c ............. 0c to 70c ltc2142i, ltc2141i, ltc2140i ............ C40c to 85c storage temperature range .................. C65c to 150c full rate cmos output mode double data rate cmos output mode top view up package 64-lead (9mm 9mm) plastic qfn v dd 1 v cm1 2 gnd 3 a in1 + 4 a in1 C 5 gnd 6 refh 7 refl 8 refh 9 refl 10 par/ ser 11 a in2 + 12 a in2 C 13 gnd 14 v cm2 15 v dd 16 48 d1_1 47 d1_0 46 dnc* 45 dnc* 44 dnc* 43 dnc* 42 ov dd 41 ognd 40 clkout + 39 clkout C 38 d2_11 37 d2_10 36 d2_9 35 d2_8 34 d2_7 33 d2_6 65 gnd 64 v dd 63 sense 62 v ref 61 sdo 60 of1 59 of2 58 d1_11 57 d1_10 56 d1_9 55 d1_8 54 d1_7 53 d1_6 52 d1_5 51 d1_4 50 d1_3 49 d1_2 v dd 17 enc + 18 enc C 19 cs 20 sck 21 sdi 22 dnc* 23 dnc* 24 dnc* 25 dnc* 26 d2_0 27 d2_1 28 d2_2 29 d2_3 30 d2_4 31 d2_5 32 t jmax = 150c, ja = 20c/w exposed pad (pin 65) is gnd, must be soldered to pcb top view up package 64-lead (9mm 9mm) plastic qfn v dd 1 v cm1 2 gnd 3 a in1 + 4 a in1 C 5 gnd 6 refh 7 refl 8 refh 9 refl 10 par/ ser 11 a in2 + 12 a in2 C 13 gnd 14 v cm2 15 v dd 16 48 d1_0_1 47 dnc 46 dnc* 45 dnc* 44 dnc* 43 dnc* 42 ov dd 41 ognd 40 clkout + 39 clkout C 38 d2_10_11 37 dnc 36 d2_8_9 35 dnc 34 d2_6_7 33 dnc 65 gnd 64 v dd 63 sense 62 v ref 61 sdo 60 of2_1 59 dnc 58 d1_10_11 57 dnc 56 d1_8_9 55 dnc 54 d1_6_7 53 dnc 52 d1_4_5 51 dnc 50 d1_2_3 49 dnc v dd 17 enc + 18 enc C 19 cs 20 sck 21 sdi 22 dnc* 23 dnc* 24 dnc* 25 dnc* 26 dnc 27 d2_0_1 28 dnc 29 d2_2_3 30 dnc 31 d2_4_5 32 t jmax = 150c, ja = 20c/w exposed pad (pin 65) is gnd, must be soldered to pcb
3 21421012fa ltc2142-12/ ltc2141-12/ltc2140-12 order information lead free finish tape and reel part marking* package description temperature range ltc2142cup-12#pbf ltc2142cup-12#trpbf ltc2142up-12 64-lead (9mm 9mm) plastic qfn 0c to 70c ltc2142iup-12#pbf ltc2142iup-12#trpbf ltc2142up-12 64-lead (9mm 9mm) plastic qfn C40c to 85c ltc2141cup-12#pbf ltc2141cup-12#trpbf ltc2141up-12 64-lead (9mm 9mm) plastic qfn 0c to 70c ltc2141iup-12#pbf ltc2141iup-12#trpbf ltc2141up-12 64-lead (9mm 9mm) plastic qfn C40c to 85c ltc2140cup-12#pbf ltc2140cup-12#trpbf ltc2140up-12 64-lead (9mm 9mm) plastic qfn 0c to 70c ltc2140iup-12#pbf ltc2140iup-12#trpbf ltc2140up-12 64-lead (9mm 9mm) plastic qfn C40c to 85c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a la bel on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ pin configurations double data rate lvds output mode top view up package 64-lead (9mm 9mm) plastic qfn v dd 1 v cm1 2 gnd 3 a in1 + 4 a in1 C 5 gnd 6 refh 7 refl 8 refh 9 refl 10 par/ ser 11 a in2 + 12 a in2 C 13 gnd 14 v cm2 15 v dd 16 48 d1_0_1 + 47 d1_0_1 C 46 dnc* 45 dnc* 44 dnc* 43 dnc* 42 ov dd 41 ognd 40 clkout + 39 clkout C 38 d2_10_11 + 37 d2_10_11 C 36 d2_8_9 + 35 d2_8_9 C 34 d2_6_7 + 33 d2_6_7 C 65 gnd 64 v dd 63 sense 62 v ref 61 sdo 60 of2_1 + 59 of2_1 C 58 d1_10_11 + 57 d1_10_11 C 56 d1_8_9 + 55 d1_8_9 C 54 d1_6_7 + 53 d1_6_7 C 52 d1_4_5 + 51 d1_4_5 C 50 d1_2_3 + 49 d1_2_3 C v dd 17 enc + 18 enc C 19 cs 20 sck 21 sdi 22 dnc* 23 dnc* 24 dnc* 25 dnc* 26 d2_0_1 C 27 d2_0_1 + 28 d2_2_3 C 29 d2_2_3 + 30 d2_4_5 C 31 d2_4_5 + 32 t jmax = 150c, ja = 20c/w exposed pad (pin 65) is gnd, must be soldered to pcb
ltc2142-12/ ltc2141-12/ltc2140-12 4 21421012fa analog input the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) symbol parameter conditions min typ max units v in analog input range (a in + C a in C ) 1.7v < v dd < 1.9v l 1 to 2 v p-p v in(cm) analog input common mode (a in + + a in C )/2 differential analog input (note 8) l 0.7 v cm 1.25 v v sense external voltage reference applied to sense external reference mode l 0.625 1.250 1.300 v i incm analog input common mode current per pin, 65msps per pin, 40msps per pin, 25msps 81 50 31 a a a i in1 analog input leakage current (no encode) 0 < a in + , a in C < v dd l C1.5 1.5 a i in2 par/ ser input leakage current 0 < par/ ser < v dd l C3 3 a i in3 sense input leakage current 0.625 < sense < 1.3v l C3 3 a t ap sample-and-hold acquisition delay time 0 ns t jitter sample-and-hold acquisition delay jitter single-ended encode differential encode 0.08 0.10 ps rms ps rms cmrr analog input common mode rejection ratio 80 db bw-3b full-power bandwidth figure 6 test circuit 750 mhz converter characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) parameter conditions ltc2142-12 ltc2141-12 ltc2140-12 units min typ max min typ max min typ max resolution (no missing codes) l 12 12 12 bits integral linearity error differential analog input (note 6) l C0.9 0.3 0.9 C0.9 0.3 0.9 C0.9 0.3 0.9 lsb differential linearity error differential analog input l C0.5 0.1 0.5 C0.5 0.1 0.5 C0.5 0.1 0.5 lsb offset error (note 7) l C9 1.5 9 C9 1.5 9 C9 1.5 9 mv gain error internal reference external reference l C1.7 1.5 C0.3 1.1 C1.7 1.5 C0.3 1.1 C1.7 1.5 C0.3 1.1 %fs %fs offset drift 10 10 10 v/c full-scale drift internal reference external reference 30 10 30 10 30 10 ppm/c ppm/c gain matching 0.2 0.2 0.2 %fs offset matching 1.5 1.5 1.5 mv transition noise 0.3 0.3 0.3 lsb rms
5 21421012fa ltc2142-12/ ltc2141-12/ltc2140-12 internal reference characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) parameter conditions min typ max units v cm output voltage i out = 0 0.5 ? v dd C 25mv 0.5 ? v dd 0.5 ? v dd + 25mv v v cm output temperature drift 25 ppm/c v cm output resistance C600a < i out < 1ma 4 v ref output voltage i out = 0 1.225 1.250 1.275 v v ref output temperature drift 25 ppm/c v ref output resistance C400a < i out < 1ma 7 v ref line regulation 1.7v < v dd < 1.9v 0.6 mv/v dynamic accuracy the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. a in = C1dbfs. (note 5) symbol parameter conditions ltc2142-12 ltc2141-12 ltc2140-12 units min typ max min typ max min typ max snr signal-to-noise ratio 5mhz input 30mhz input 70mhz input 140mhz input l 69.6 70.8 70.8 70.7 70.5 69.2 70.5 70.5 70.4 70.2 69.7 71 71 70.9 70.7 dbfs dbfs dbfs dbfs sfdr spurious free dynamic range 2nd harmonic 5mhz input 30mhz input 70mhz input 140mhz input l 78 89 89 88 84 80 89 89 88 84 80 89 89 88 84 dbfs dbfs dbfs dbfs spurious free dynamic range 3rd harmonic 5mhz input 30mhz input 70mhz input 140mhz input l 80 89 89 88 84 80 89 89 88 84 80 89 89 88 84 dbfs dbfs dbfs dbfs spurious free dynamic range 4th harmonic or higher 5mhz input 30mhz input 70mhz input 140mhz input l 85 95 95 95 95 85 95 95 95 95 85 95 95 95 95 dbfs dbfs dbfs dbfs s/(n+d) signal-to-noise plus distortion ratio 5mhz input 30mhz input 70mhz input 140mhz input l 69.4 70.7 70.7 70.6 70.2 69.1 70.4 70.4 70.3 69.9 69.6 70.9 70.9 70.8 70.4 dbfs dbfs dbfs dbfs crosstalk 10mhz input C110 C110 C110 dbc
ltc2142-12/ ltc2141-12/ltc2140-12 6 21421012fa digital inputs and outputs the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) symbol parameter conditions min typ max units encode inputs (enc + , enc C ) differential encode mode (enc C not tied to gnd) v id differential input voltage (note 8) l 0.2 v v icm common mode input voltage internally set externally set (note 8) l 1.1 1.2 1.6 v v v in input voltage range enc + , enc C to gnd l 0.2 3.6 v r in input resistance (see figure 10) 10 k c in input capacitance (note 8) 3.5 pf single-ended encode mode (enc C tied to gnd) v ih high level input voltage v dd = 1.8v l 1.2 v v il low level input voltage v dd = 1.8v l 0.6 v v in input voltage range enc + to gnd l 0 3.6 v r in input resistance (see figure 11) 30 k c in input capacitance (note 8) 3.5 pf digital inputs ( cs , sdi, sck in serial or parallel programming mode. sdo in parallel programming mode) v ih high level input voltage v dd = 1.8v l 1.3 v v il low level input voltage v dd = 1.8v l 0.6 v i in input current v in = 0v to 3.6v l C10 10 a c in input capacitance (note 8) 3 pf sdo output (serial programming mode. open-drain output. requires 2k pull-up resistor if sdo is used) r ol logic low output resistance to gnd v dd = 1.8v, sdo = 0v 200 i oh logic high output leakage current sdo = 0v to 3.6v l C10 10 a c out output capacitance (note 8) 3 pf digital data outputs (cmos modes: full data rate and double data rate) ov dd = 1.8v v oh high level output voltage i o = C500a l 1.750 1.790 v v ol low level output voltage i o = 500a l 0.010 0.050 v ov dd = 1.5v v oh high level output voltage i o = C500a 1.488 v v ol low level output voltage i o = 500a 0.010 v ov dd = 1.2v v oh high level output voltage i o = C500a 1.185 v v ol low level output voltage i o = 500a 0.010 v digital data outputs (lvds mode) v od differential output voltage 100 differential load, 3.5ma mode 100 differential load, 1.75ma mode l 247 350 175 454 mv mv v os common mode output voltage 100 differential load, 3.5ma mode 100 differential load, 1.75ma mode l 1.125 1.250 1.250 1.375 v v r term on-chip termination resistance termination enabled, ov dd = 1.8v 100
7 21421012fa ltc2142-12/ ltc2141-12/ltc2140-12 power requirements the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 9) symbol parameter conditions ltc2142-12 ltc2141-12 ltc2140-12 units min typ max min typ max min typ max cmos output modes: full data rate and double data rate v dd analog supply voltage (note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 v ov dd output supply voltage (note 10) l 1.1 1.8 1.9 1.1 1.8 1.9 1.1 1.8 1.9 v i vdd analog supply current dc input sine wave input l 50.9 51.3 57 35.9 36.2 41 26.9 27 32 ma ma i ovdd digital supply current sine wave input, ov dd = 1.2v 3.8 2.4 1.5 ma p diss power dissipation dc input sine wave input, ov dd = 1.2v l 91.6 96.9 103 64.6 68 74 48.4 50.4 57.6 mw mw lvds output mode v dd analog supply voltage (note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 v ov dd output supply voltage (note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 v i vdd analog supply current sine input, 1.75ma mode sine input, 3.5ma mode l 52.6 53.8 61 37.4 38.7 45 28.3 29.5 35.5 ma ma i ovdd digital supply current (0v dd = 1.8v) sine input, 1.75ma mode sine input, 3.5ma mode l 30 57.4 67 29.6 57.1 67 29.3 56.8 67 ma ma p diss power dissipation sine input, 1.75ma mode sine input, 3.5ma mode l 149 200 231 121 172 202 104 155 185 mw mw all output modes p sleep sleep mode power 1 1 1 mw p nap nap mode power 10 10 10 mw p diffclk power increase with differential encode mode enabled (no increase for nap or sleep modes) 20 20 20 mw timing characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) symbol parameter conditions ltc2142-12 ltc2141-12 ltc2140-12 units min typ max min typ max min typ max f s sampling frequency (note 10) l 1 65 1 40 1 25 mhz t l enc low time (note 8) duty cycle stabilizer off duty cycle stabilizer on l l 7.3 2 7.69 7.69 500 500 11.88 2 12.5 12.5 500 500 19 2 20 20 500 500 ns ns t h enc high time (note 8) duty cycle stabilizer off duty cycle stabilizer on l l 7.3 2 7.69 7.69 500 500 11.88 2 12.5 12.5 500 500 19 2 20 20 500 500 ns ns t ap sample-and-hold acquisition delay time 000ns symbol parameter conditions min typ max units digital data outputs (cmos modes: full data rate and double data rate) t d enc to data delay c l = 5pf (note 8) l 1.1 1.7 3.1 ns t c enc to clkout delay c l = 5pf (note 8) l 1 1.4 2.6 ns t skew data to clkout skew t d C t c (note 8) l 0 0.3 0.6 ns pipeline latency full data rate mode double data rate mode 6 6.5 cycles cycles
ltc2142-12/ ltc2141-12/ltc2140-12 8 21421012fa symbol parameter conditions min typ max units digital data outputs (lvds mode) t d enc to data delay c l = 5pf (note 8) l 1.1 1.8 3.2 ns t c enc to clkout delay c l = 5pf (note 8) l 1 1.5 2.7 ns t skew data to clkout skew t d C t c (note 8) l 0 0.3 0.6 ns pipeline latency 6.5 cycles spi port timing (note 8) t sck sck period write mode readback mode, c sdo = 20pf, r pullup = 2k l l 40 250 ns ns t s cs to sck setup time l 5ns t h sck to cs setup time l 5ns t ds sdi setup time l 5ns t dh sdi hold time l 5ns t do sck falling to sdo valid readback mode, c sdo = 20pf, r pullup = 2k l 125 ns timing characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to gnd with gnd and ognd shorted (unless otherwise noted). note 3: when these pin voltages are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd or above v dd without latchup. note 4: when these pin voltages are taken below gnd they will be clamped by internal diodes. when these pin voltages are taken above v dd they will not be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd without latchup. note 5: v dd = ov dd = 1.8v, f sample = 65mhz (ltc2142), 40mhz (ltc2141), or 25mhz (ltc2140), lvds outputs, differential enc + /enc C = 2v p-p sine wave, input range = 2v p-p with differential drive, unless otherwise noted. note 6: integral nonlinearity is defined as the deviation of a code from a best fit straight line to the transfer curve. the deviation is measured from the center of the quantization band. note 7: offset error is the offset voltage measured from C0.5 lsb when the output code flickers between 0000 0000 0000 and 1111 1111 1111 in 2s complement output mode. note 8: guaranteed by design, not subject to test. note 9: v dd = 1.8v, f sample = 65mhz (ltc2142), 40mhz (ltc2141), or 25mhz (ltc2140), cmos outputs, enc + = single-ended 1.8v square wave, enc C = 0v, input range = 2v p-p with differential drive, 5pf load on each digital output unless otherwise noted. the supply current and power dissipation specifications are totals for the entire ic, not per channel. note 10: recommended operating conditions.
9 21421012fa ltc2142-12/ ltc2141-12/ltc2140-12 typical performance characteristics ltc2142-12: integral non-linearity (inl) ltc2142-12: differential non-linearity (dnl) ltc2142-12: 64k point fft, f in = 5mhz, C1dbfs, 65msps output code 0 C1.0 C0.8 C0.6 C0.4 inl error (lsb) 0.2 0.0 1.0 0.6 0.8 0.2 0.4 1024 2048 3072 4096 21421012 g01 output code C1.0 C0.4 C0.2 C0.6 C0.8 dnl error (lsb) 0 0.4 0.2 0.6 0.8 1.0 21421012 g02 0 1024 2048 3072 4096 frequency (mhz) C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 21421012 g03 0 10 20 30 ltc2142-12: 64k point fft, f in = 30mhz, C1dbfs, 65msps ltc2142-12: 64k point fft, f in = 70mhz, C1dbfs, 65msps ltc2142-12: 64k point fft, f in = 140mhz, C1dbfs, 65msps ltc2142-12: 64k point 2-tone fft, f in = 69mhz, 70mhz, C7dbfs, 65msps ltc2142-12: shorted input histogram frequency (mhz) C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 21421012 g04 ltc2142-12: 64k point 2-tone fft f in = 69mhz 70mh z frequency (m hz) 21421012 g04 0 10 20 30 frequency (mhz) C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 21421012 g05 lt c 2142-12: s horted input histo g ram frequency (m hz) 21421012 g 0 5 0 10 20 30 frequency (mhz) C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 21421012 g06 frequency (m hz) 21421012 g 0 6 0 10 20 30 output code 2043 2044 2000 0 6000 4000 count 8000 10000 18000 16000 14000 12000 2045 2046 2047 21421012 g08 input frequency (mhz) 0 70 69 68 72 71 snr (dbfs) 50 100 150 200 250 300 21421012 g09 single-ended encode differential encode ltc2142-12: snr vs input frequency, C1dbfs, 65msps, 2v range frequency (mhz) C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 21421012 g07 frequency ( mhz ) 21421012 g 0 7 0 10 20 30
ltc2142-12/ ltc2141-12/ltc2140-12 10 21421012fa typical performance characteristics ltc2142-12: sfdr vs input level, f in = 70mhz, 65msps, 2v range ltc2142-12: i vdd vs sample rate, 5mhz, C1dbfs sine wave input on each channel input level (dbfs) C80 40 30 20 10 0 60 50 sfdr (dbc and dbfs) 70 80 110 100 90 C70 C60 C50 C40 C30 C20 C10 0 21421012 g12 dbfs dbc sample rate (msps) 0 50 40 45 35 55 i vdd (ma) 10 20 30 40 50 60 21421012 g13 cmos outputs lvds outputs 0 50 100 150 200 250 300 input frequency (mhz) 90 85 80 75 70 65 100 95 2nd and 3rd harmonic (dbfs) 21421012 g10 2nd 3rd ltc2142-12: 2nd, 3rd harmonic vs input frequency, C1dbfs, 65msps, 2v range ltc2142-12: io vdd vs sample rate, 5mhz, C1dbfs, sine wave on each channel ltc2142-12: snr vs sense, f in = 5mhz, C1dbfs ltc2141-12: integral non-linearity (inl) ltc2141-12: differential non-linearity (dnl) ltc2141-12: 64k point fft, f in = 5mhz, C1dbfs, 40msps sample rate (msps) 0 10 20 0 70 60 50 30 40 iov dd (ma) 10 20 30 40 50 60 21421012 g14 1.8v cmos 1.75ma lvds 3.5ma lvds sense pin (v) 0.6 67 66 68 69 72 71 70 snr (dbfs) 0.7 0.8 0.9 1.1 1.2 1.3 1 21421012 g15 output code 0 C1.0 C0.8 C0.6 C0.4 inl error (lsb) C0.2 0.0 0.2 1.0 0.6 0.8 0.4 1024 2048 3072 4096 21421012 g16 C1.0 C0.4 C0.2 C0.6 C0.8 dnl error (lsb) 0 0.4 0.2 0.6 0.8 1.0 21421012 g17 output code 0 1024 2048 3072 4096 frequency (mhz) 0 C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 5 101520 21421012 g18 214 210 12f fre q uen c y (mhz ) 0 5 1 0 15 20 21421012 g1 8 0 50 100 150 200 250 300 input frequency (mhz) 90 85 80 75 70 65 100 95 2nd and 3rd harmonic (dbfs) 21421012 g11 2nd 3rd ltc2142-12: 2nd, 3rd harmonic vs input frequency, C1dbfs, 65msps, 1v range
11 21421012fa ltc2142-12/ ltc2141-12/ltc2140-12 ltc2141-12: 64k point fft, f in = 140mhz, C1dbfs, 40msps typical performance characteristics ltc2141-12: 64k point fft, f in = 30mhz, C1dbfs, 40msps frequency (mhz) 0 C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 5 101520 21421012 g19 frequency (mhz ) 0 5 1 0 1 5 2 0 21421012 g 1 9 ltc2141-12: 64k point fft, f in = 70mhz, C1dbfs, 40msps frequency (mhz) 0 C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 5 101520 21421012 g20 frequency (mhz ) 0 5 10 15 20 2 1421012 g 2 0 frequency (mhz) 0 C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 5 101520 21421012 g21 ltc2141-12: 64k point 2-tone fft, f in = 69mhz, 70mhz, C7dbfs, 40msps frequency (mhz) 0 C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 5 101520 21421012 g22 frequency (m hz) 0 5 10 1 5 2 0 21421012 g 2 2 output code 2043 2044 2000 0 6000 4000 count 8000 10000 18000 16000 14000 12000 2045 2046 2047 21421012 g23 ltc2141-12: shorted input histogram input frequency (mhz) 0 69 68 72 71 70 snr (dbfs) 50 100 150 200 250 300 21421012 g24 single-ended encode differential encode ltc2141-12: snr vs input frequency, C1dbfs, 40msps, 2v range 0 50 100 150 200 250 300 input frequency (mhz) 90 85 80 75 70 65 100 95 2nd and 3rd harmonic (dbfs) 21421012 g25 2nd 3rd ltc2141-12: 2nd, 3rd harmonic vs input frequency, C1dbfs, 40msps, 2v range 0 50 100 150 200 250 300 input frequency (mhz) 90 85 80 75 70 65 100 95 2nd and 3rd harmonic (dbfs) 21421012 g26 2nd 3rd ltc2141-12: 2nd, 3rd harmonic vs input frequency, C1dbfs, 40msps, 1v range ltc2141-12: sfdr vs input level, f in = 70mhz, 40msps, 2v range input level (dbfs) C80 40 30 20 10 0 60 50 sfdr (dbc and dbfs) 70 80 110 100 90 C70 C60 C50 C40 C30 C20 C10 0 21421012 g27 dbfs dbc
ltc2142-12/ ltc2141-12/ltc2140-12 12 21421012fa typical performance characteristics ltc2140-12: 64k point fft, f in = 70mhz, C1dbfs, 25msps ltc2140-12: 64k point fft, f in = 140mhz, C1dbfs, 25msps ltc2140-12: 64k point fft, f in = 30mhz, C1dbfs, 25msps ltc2141-12: i vdd vs sample rate, 5mhz, C1dbfs sine wave input on each channel sample rate (msps) 0 35 30 25 40 i vdd (ma) 10 20 30 40 21421012 g28 lvds outputs cmos outputs ltc2141-12: io vdd vs sample rate, 5mhz, C1dbfs, sine wave input on each channel ltc2141-12: snr vs sense, f in = 5mhz, C1dbfs ltc2140-12: integral non-linearity (inl) ltc2140-12: differential non-linearity (dnl) ltc2140-12: 64k point fft, f in = 5mhz, C1dbfs, 25msps sample rate (msps) 10 20 0 70 60 50 30 40 io vdd (ma) 21421012 g29 0 10203040 1.8v cmos 1.75ma lvds 3.5ma lvds sense pin (v) 0.6 67 66 68 69 72 71 70 snr (dbfs) 0.7 0.8 0.9 1.1 1.2 1.3 1 21421012 g30 output code 0 C1.0 C0.8 C0.6 C0.4 inl error (lsb) C0.2 0.0 1.0 0.6 0.8 0.4 1024 2048 3072 4096 21421012 g31 C1.0 C0.4 C0.2 C0.6 C0.8 dnl error (lsb) 0 0.4 0.2 0.6 0.8 1.0 21421012 g32 output code 0 1024 2048 3072 4096 frequency (mhz) 0 C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 510 21421012 g33 lt c2 14 0- 12 : 64 k po in t ff t f requency (m hz) 0 5 10 21421012 g33 frequency (mhz) 0 C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 510 21421012 g36 frequency (mhz) 0 C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 510 21421012 g35 f requency (m hz) 0 5 10 21421012 g 3 5 frequency (mhz) 0 C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 510 21421012 g34 frequency (m hz) 0 5 10 21421012 g34
13 21421012fa ltc2142-12/ ltc2141-12/ltc2140-12 typical performance characteristics ltc2140-12: shorted input histogram ltc2140-12: 64k point 2-tone fft, f in = 69mhz, 70mhz, C7dbfs, 25msps frequency (mhz) 0 C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 510 21421012 g37 f requency ( mhz ) 0 5 10 21421 0 12 g 3 7 output code 2050 2051 2053 2000 0 6000 4000 count 8000 10000 18000 16000 14000 12000 2052 2054 21421012 g38 input frequency (mhz) 0 69 68 72 71 70 snr (dbfs) 50 100 150 200 250 300 21421012 g39 single-ended encode differential encode ltc2140-12: snr vs input frequency, C1dbfs, 25msps, 2v range 0 50 100 150 200 250 300 input frequency (mhz) 90 85 80 75 70 65 100 95 2nd and 3rd harmonic (dbfs) 21421012 g40 2nd 3rd ltc2140-12: 2nd, 3rd harmonic vs input frequency, C1dbfs, 25msps, 2v range 0 50 100 150 200 250 300 input frequency (mhz) 90 85 80 75 70 65 100 95 2nd and 3rd harmonic (dbfs) 21421012 g41 2nd 3rd ltc2140-12: 2nd, 3rd harmonic vs input frequency, C1dbfs, 25msps, 1v range ltc2140-12: sfdr vs input level, f in = 70mhz, 25msps, 2v range input level (dbfs) C80 40 30 20 10 0 60 50 sfdr (dbc and dbfs) 70 80 110 100 90 C70 C60 C50 C40 C30 C20 C10 0 21421012 g42 dbfs dbc ltc2140-12: i vdd vs sample rate, 5mhz, C1dbfs sine wave input on each channel sample rate (msps) 0 28 22 24 26 20 30 i vdd (ma) 5 10152025 21421012 g43 cmos outputs lvds outputs ltc2140-12: io vdd vs sample rate, 5mhz, C1dbfs, sine wave on each input ltc2140-12: snr vs sense, f in = 5mhz, C1dbfs sample rate (msps) 10 20 0 60 50 30 40 io vdd (ma) 21421012 g44 0 5 10 15 20 25 3.5ma lvds 1.75ma lvds 1.8v cmos sense pin (v) 0.6 67 66 68 69 72 71 70 snr (dbfs) 0.7 0.8 0.9 1.1 1.2 1.3 1 21421012 g45
ltc2142-12/ ltc2141-12/ltc2140-12 14 21421012fa pins that are the same for all digital output modes v dd (pins 1, 16, 17, 64): analog power supply, 1.7v to 1.9v. bypass to ground with 0.1f ceramic capacitors. adjacent pins can share a bypass capacitor. v cm1 (pin 2): common mode bias output, nominally equal to v dd /2. v cm1 should be used to bias the common mode of the analog inputs to channel 1. bypass to ground with a 0.1f ceramic capacitor. gnd (pins 3, 6, 14): adc power ground. a in1 + (pin 4): channel 1 positive differential analog input. a in1 C (pin 5): channel 1 negative differential analog input. refh (pins 7, 9): adc high reference. see the applica- tions information section for recommended bypassing circuits for refh and refl. refl (pins 8, 10): adc low reference. see the applica- tions information section for recommended bypassing circuits for refh and refl. par/ ser (pin 11): programming mode selection pin. con- nect to ground to enable the serial programming mode. cs , sck, sdi, sdo become a serial interface that control the a/d operating modes. connect to v dd to enable the parallel programming mode where cs , sck, sdi, sdo become parallel logic inputs that control a reduced set of the a/d operating modes. par/ ser should be connected directly to ground or v dd and not be driven by a logic signal. a in2 + (pin 12): channel 2 positive differential analog input. a in2 C (pin 13): channel 2 negative differential analog input. v cm2 (pin 15): common mode bias output, nominally equal to v dd /2. v cm2 should be used to bias the common mode of the analog inputs to channel 2. bypass to ground with a 0.1f ceramic capacitor. enc + (pin 18): encode input. conversion starts on the rising edge. enc C (pin 19): encode complement input. conversion starts on the falling edge. tie to gnd for single-ended encode mode. cs (pin 20): in serial programming mode, (par/ ser = 0v), cs is the serial interface chip select input. when cs is low, sck is enabled for shifting data on sdi into the mode control registers. in the parallel programming mode (par/ ser = v dd ), cs controls the clock duty cycle stabilizer (see table 2). cs can be driven with 1.8v to 3.3v logic. sck (pin 21): in serial programming mode, (par/ ser = 0v), sck is the serial interface clock input. in the parallel programming mode (par/ ser = v dd ), sck controls the digital output mode (see table 2). sck can be driven with 1.8v to 3.3v logic. sdi (pin 22): in serial programming mode, (par/ ser = 0v), sdi is the serial interface data input. data on sdi is clocked into the mode control registers on the rising edge of sck. in the parallel programming mode (par/ ser = v dd ), sdi can be used together with sdo to power down the part (see table 2). sdi can be driven with 1.8v to 3.3v logic. ognd (pin 41): output driver ground. must be shorted to the ground plane by a very low inductance path. use multiple vias close to the pin. ov dd (pin 42): output driver supply. bypass to ground with a 0.1f ceramic capacitor. sdo (pin 61): in serial programming mode, (par/ ser = 0v), sdo is the optional serial interface data output. data on sdo is read back from the mode control regis- ters and can be latched on the falling edge of sck. sdo is an open-drain nmos output that requires an external 2k pull-up resistor to 1.8v C 3.3v. if read back from the mode control registers is not needed, the pull-up resistor is not necessary and sdo can be left unconnected. in the parallel programming mode (par/ ser = v dd ), sdo can be used together with sdi to power down the part (see table 2). when used as an input, sdo can be driven with 1.8v to 3.3v logic through a 1k series resistor. v ref (pin 62): reference voltage output. bypass to ground with a 2.2f ceramic capacitor. the output voltage is nominally 1.25v. pin functions
15 21421012fa ltc2142-12/ ltc2141-12/ltc2140-12 pin functions sense (pin 63): reference programming pin. connecting sense to v dd selects the internal reference and a 1v input range. connecting sense to ground selects the internal reference and a 0.5v input range. an external reference between 0.625v and 1.3v applied to sense selects an input range of 0.8 ? v sense . ground (exposed pad pin 65): the exposed pad must be soldered to the pcb ground. dnc* (pins 23, 24, 25, 26, 43, 44, 45, 46): these pins are shorted to gnd inside the package. for most applica- tions they should be left unconnected. for pin compat- ibility with the 14-bit ltc2142-14 or the 16-bit ltc2182 they can be connected as digital outputs to make the bus width 14 or 16 bits. full rate cmos output mode all pins below have cmos output levels (ognd to ov dd ) d2_0 to d2_11 (pins 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38): channel 2 digital outputs. d2_11 is the msb. clkout C (pin 39): inverted version of clkout + . clkout + (pin 40): data output clock. the digital outputs normally transition at the same time as the falling edge of clkout + . the phase of clkout + can also be delayed relative to the digital outputs by programming the mode control registers. d1_0 to d1_11 (pins 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58): channel 1 digital outputs. d1_11 is the msb. of2 (pin 59): channel 2 over/underflow digital output. of2 is high when an overflow or underflow has occurred. of1 (pin 60): channel 1 over/underflow digital output. of1 is high when an overflow or underflow has occurred. double data rate cmos output mode all pins below have cmos output levels (ognd to ov dd ) d2_0_1 to d2_10_11 (pins 28, 30, 32, 34, 36, 38): channel 2 double data rate digital outputs. two data bits are multiplexed onto each output pin. the even data bits (d0, d2, d4, d6, d8, d10) appear when clkout + is low. the odd data bits (d1, d3, d5, d7, d9, d11) appear when clkout + is high. dnc (pins 27, 29, 31, 33, 35, 37, 47, 49, 51, 53, 55, 57, 59): do not connect these pins. clkout C (pin 39): inverted version of clkout + . clkout + (pin 40): data output clock. the digital outputs normally transition at the same time as the falling and rising edges of clkout + . the phase of clkout + can also be delayed relative to the digital outputs by programming the mode control registers. d1_0_1 to d1_10_11 (pins 48, 50, 52, 54, 56, 58): channel 1 double data rate digital outputs. two data bits are multiplexed onto each output pin. the even data bits (d0, d2, d4, d6, d8, d10) appear when clkout + is low. the odd data bits (d1, d3, d5, d7, d9, d11) appear when clkout + is high. of2_1 (pin 60): over/underflow digital output. of2_1 is high when an overflow or underflow has occurred. the over/underflow for both channels are multiplexed onto this pin. channel 2 appears when clkout + is low, and channel 1 appears when clkout + is high. double data rate lvds output mode all pins below have lvds output levels. the output current level is programmable. there is an optional internal 100 termination resistor between the pins of each lvds output pair. d2_0_1 C /d2_0_1 + to d2_10_11 C /d2_10_11 + (pins 27/28, 29/30, 31/32, 33/34, 35/36, 37/38): channel 2 double data rate digital outputs. two data bits are multiplexed onto each differential output pair. the even data bits (d0, d2, d4, d6, d8, d10) appear when clkout + is low. the odd data bits (d1, d3, d5, d7, d9, d11) appear when clkout + is high. clkout C /clkout + (pins 39/40): data output clock. the digital outputs normally transition at the same time as the falling and rising edges of clkout + . the phase of clkout + can also be delayed relative to the digital outputs by programming the mode control registers.
ltc2142-12/ ltc2141-12/ltc2140-12 16 21421012fa functional block diagram figure 1. functional block diagram d1_0_1 C /d1_0_1 + to d1_10_11 C /d1_10_11 + (pins 47/48, 49/50, 51/52, 53/54, 55/56, 57/58): channel 1 double data rate digital outputs. two data bits are multiplexed onto each differential output pair. the even data bits (d0, d2, d4, d6, d8, d10) appear when clkout + is low. the odd data bits (d1, d3, d5, d7, d9, d11) appear when clkout + is high. of2_1 C /of2_1 + (pins 59/60): over/underflow digital output. of2_1 + is high when an overflow or underflow has occurred. the over/underflow for both channels are multiplexed onto this pin. channel 2 appears when clkout + is low, and channel 1 appears when clkout + is high. diff ref amp ref buf 2.2f 0.1f 0.1f internal clock signals refh refl clock/duty cycle control range select 1.25v reference enc + refh refl enc C correction logic sdo cs ognd of1 ov dd d1_11 clkout C clkout + d1_0 21421012 f01 sense v ref ch 1 analog input 2.2f v cm1 0.1f v dd /2 output drivers mode control registers sck par/ ser sdi ? ? ? gnd s/h 12-bit adc core ch 2 analog input s/h 12-bit adc core v cm2 0.1f of2 d2_11 d2_0 ? ? ? v dd pin functions
17 21421012fa ltc2142-12/ ltc2141-12/ltc2140-12 full rate cmos output mode timing all outputs are single-ended and have cmos levels timing diagrams t h t d t c t l b C 6 b C 5 b C 4 b C 3 b C 2 t ap a + 1 a + 2 a + 4 a + 3 a ch 1 analog input enc C enc + clkout + clkout C d2_0 - d2_11, of2 t ap b + 1 b + 2 b + 4 b + 3 b ch 2 analog input a C 6 a C 5 a C 4 a C 3 a C 2 d1_0 - d1_11, of1 21421012 td01
ltc2142-12/ ltc2141-12/ltc2140-12 18 21421012fa double data rate cmos output mode timing all outputs are single-ended and have cmos levels t d ? ? ? t d t c t c t l bit 0 a-6 bit 1 a-6 bit 0 a-5 bit 1 a-5 bit 0 a-4 bit 1 a-4 bit 0 a-3 bit 1 a-3 bit 0 a-2 bit 10 a-6 bit 11 a-6 bit 10 a-5 bit 11 a-5 bit 10 a-4 bit 11 a-4 bit 10 a-3 bit 11 a-3 bit 10 a-2 enc C enc + d1_0_1 d1_10_11 ? ? ? bit 0 b-6 bit 1 b-6 bit 0 b-5 bit 1 b-5 bit 0 b-4 bit 1 b-4 bit 0 b-3 bit 1 b-3 bit 0 b-2 bit 10 b-6 bit 11 b-6 bit 10 b-5 bit 11 b-5 bit 10 b-4 bit 11 b-4 bit 10 b-3 bit 11 b-3 bit 10 b-2 of b-6 of a-6 of b-5 of a-5 of b-4 of a-4 of b-3 of a-3 of b-2 d2_0_1 d2_10_11 clkout + clkout C of2_1 21421012 td02 t h t ap a + 1 a + 2 a + 4 a + 3 a ch 1 analog input t ap b + 1 b + 2 b + 4 b + 3 b ch 2 analog input timing diagrams
19 21421012fa ltc2142-12/ ltc2141-12/ltc2140-12 timing diagrams double data rate lvds output mode timing all outputs are differential and have lvds levels t d ? ? ? t d t c t c t l bit 0 a-6 bit 1 a-6 bit 0 a-5 bit 1 a-5 bit 0 a-4 bit 1 a-4 bit 0 a-3 bit 1 a-3 bit 0 a-2 bit 10 a-6 bit 11 a-6 bit 10 a-5 bit 11 a-5 bit 10 a-4 bit 11 a-4 bit 10 a-3 bit 11 a-3 bit 10 a-2 enc C enc + d1_0_1 + d1_10_11 + ? ? ? bit 0 b-6 bit 1 b-6 bit 0 b-5 bit 1 b-5 bit 0 b-4 bit 1 b-4 bit 0 b-3 bit 1 b-3 bit 0 b-2 bit 10 b-6 bit 11 b-6 bit 10 b-5 bit 11 b-5 bit 10 b-4 bit 11 b-4 bit 10 b-3 bit 11 b-3 bit 10 b-2 of b-6 of a-6 of b-5 of a-5 of b-4 of a-4 of b-3 of a-3 of b-2 d2_0_1 + d2_10_11 + clkout + clkout C of2_1 + d1_0_1 C d1_10_11 C d2_0_1 C d2_10_11 C of2_1 C 21421012 td03 t h t ap a + 1 a + 2 a + 4 a + 3 a ch 1 analog input t ap b + 1 b + 2 b + 4 b + 3 b ch 2 analog input a6 t s t ds a5 a4 a3 a2 a1 a0 xx d7 d6 d5 d4 d3 d2 d1 d0 xx xx xx xx xx xx xx cs sck sdi r/ w sdo high impedance spi port timing (readback mode) spi port timing (write mode) t dh t do t sck t h a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 21421012 td04 cs sck sdi r/ w sdo high impedance
ltc2142-12/ ltc2141-12/ltc2140-12 20 21421012fa converter operation the ltc2142-12/ltc2141-12/ltc2140-12 are low power, 2-channel, 12-bit, 65msps/40msps/25msps a/d converters that are powered by a single 1.8v supply. the analog inputs should be driven differentially. the encode input can be driven differentially, or single ended for lower power consumption. the digital outputs can be cmos, double data rate cmos (to halve the number of output lines), or double data rate lvds (to reduce digital noise in the system.) many additional features can be chosen by programming the mode control registers through a serial spi port. analog input the analog inputs are differential cmos sample-and-hold circuits (figure 2). the inputs should be driven differen- tially around a common mode voltage set by the v cm1 or v cm2 output pins, which are nominally v dd /2. for the 2v input range, the inputs should swing from v cm C 0.5v to v cm + 0.5v. there should be 180 phase difference between the inputs. the two channels are simultaneously sampled by a shared encode circuit (figure 2). single-ended input for applications less sensitive to harmonic distortion, the a in + input can be driven single-ended with a 1v p-p signal centered around v cm . the a in C input should be connected to v cm . with a single-ended input the harmonic distortion and inl will degrade, but the noise and dnl will remain unchanged. input drive circuits input filtering if possible, there should be an rc lowpass filter right at the analog inputs. this lowpass filter isolates the drive circuitry from the a/d sample-and-hold switching, and also limits wideband noise from the drive circuitry. figure 3 shows an example of an input rc filter. the rc component values should be chosen based on the applications input frequency. transformer coupled circuits figure 3 shows the analog input being driven by an rf transformer with a center-tapped secondary. the center tap is biased with v cm , setting the a/d input at its opti- mal dc level. at higher input frequencies, a transmission line balun transformer (figure 4 to figure 6) has better balance, resulting in lower a/d distortion. c sample 5pf r on 15 r on 15 v dd v dd ltc2142-12 a in + 21421012 f02 c sample 5pf v dd a in C enc C enc + 1.2v 10k 1.2v 10k c parasitic 1.8pf c parasitic 1.8pf 10 10 25 25 25 25 50 0.1f a in + a in C 12pf 0.1f v cm ltc2142-12 analog input 0.1f t1 1:1 t1: ma/com mabaes0060 resistors, capacitors are 0402 package size 21421012 f03 figure 2. equivalent input circuit. only one of the two analog channels is shown figure 3. analog input circuit using a transformer. recommended for input frequencies from 5mhz to 70mhz applications information
21 21421012fa ltc2142-12/ ltc2141-12/ltc2140-12 applications information figure 5. recommended front-end circuit for input frequencies from 150mhz to 250mhz figure 6. recommended front-end circuit for input frequencies above 250mhz amplifier circuits figure 7 shows the analog input being driven by a high speed differential amplifier. the output of the amplifier is ac- coupled to the a/d so the amplifiers output common mode voltage can be optimally set to minimize distortion. at very high frequencies, an rf gain block will often have lower distortion than a differential amplifier. if the gain block is single-ended, then a transformer circuit (figure 4 to figure 6) should convert the signal to differential before driving the a/d. figure 4. recommended front-end circuit for input frequencies from 5mhz to 150mhz reference the ltc2142-12/ltc2141-12/ltc2140-12 has an internal 1.25v voltage reference. for a 2v input range using the internal reference, connect sense to v dd . for a 1v input range using the internal reference, connect sense to ground. for a 2v input range with an external reference, apply a 1.25v reference voltage to sense (figure 9). the input range can be adjusted by applying a voltage to sense that is between 0.625v and 1.30v. the input range will then be 1.6 ? v sense . the v ref , refh and refl pins should be bypassed, as shown in figure 8. a low inductance 2.2f interdigitated capacitor is recommended for the bypass between refh and refl. this type of capacitor is available at a low cost from multiple suppliers. 25 12 12 25 50 0.1f a in + a in C 8.2pf 0.1f v cm analog input 0.1f 0.1f t1 t2 t1: ma/com maba-007159-000000 t2: coilcraft wbc1-1tl resistors, capacitors are 0402 package size 21421012 f04 ltc2142-12 25 25 50 0.1f a in + a in C 1.8pf 0.1f v cm analog input 0.1f 0.1f t1 t2 t1: ma/com maba-007159-000000 t2: coilcraft wbc1-1tl resistors, capacitors are 0402 package size 21421012 f05 ltc2142-12 25 25 50 0.1f 4.7nh 4.7nh a in + a in C 0.1f v cm t1: ma/com etc1-1-13 resistors, capacitors are 0402 package size 21421012 f06 ltc2142-12 analog input 0.1f 0.1f t1 25 25 200 200 0.1f a in + a in C 0.1f 12pf 12pf v cm ltc2142-12 21421012 f07 C C + + analog input high speed differential amplifier 0.1f figure 7. front-end circuit using a high speed differential amplifier
ltc2142-12/ ltc2141-12/ltc2140-12 22 21421012fa applications information v ref refh refh sense c1 tie to v dd for 2v range; tie to gnd for 1v range; 3"/(&t7 sense for 0.625v < v sense < 1.300v 1.25v refl refl internal adc high reference buffer 21421012 f08a ltc2142-12 5 0.8x diff amp internal adc low reference c1: 2.2f low inductance interdigitated capacitor tdk clle1ax7s0g225m murata lla219c70g225m avx w2l14z225m or equivalent 1.25v bandgap reference 0.625v range detect and control 2.2f c2 0.1f c3 0.1f + + C C C C + + figure 8a. reference circuit sense 1.25v external reference 2.2f 1f v ref 21421012 f09 ltc2142-12 figure 9. using an external 1.25v reference refh refh refl refl 21421012 f08b ltc2142-12 capacitors are 0402 package size c3 0.1f c1 2.2f c2 0.1f figure 8b. alternative refh/refl bypass circuit figure 8c. recommended layout for the refh/refl bypass circuit in figure 8a alternatively c1 can be replaced by a standard 2.2f capacitor between refh and refl (see figure 8b). the capacitors should be as close to the pins as possible (not on the back side of the circuit board). figure 8c and figure 8d show the recommended circuit board layout for the refh/refl bypass capacitors. note that in figure 8c, every pin of the interdigitated capacitor (c1) is connected since the pins are not internally connected in some vendors capacitors. in figure 8d the refh and figure 8d. recommended layout for the refh/refl bypass circuit in figure 8b encode inputs the signal quality of the encode inputs strongly affects the a/d noise performance. the encode inputs should be treated as analog signals C do not route them next to digital traces on the circuit board. there are two modes of operation for the encode inputs: the differential encode mode (figure 10), and the single-ended encode mode (figure 11). the differential encode mode is recommended for si- nusoidal, pecl, or lvds encode inputs (figure 12 and figure 13). the encode inputs are internally biased to 1.2v through 10k equivalent resistance. the encode inputs can be taken above v dd (up to 3.6v), and the common mode range is from 1.1v to 1.6v. in the differential encode mode, refl pins are connected by short jumpers in an internal layer. to minimize the inductance of these jumpers they can be placed in a small hole in the gnd plane on the second board layer.
23 21421012fa ltc2142-12/ ltc2141-12/ltc2140-12 50 100 0.1f t1 = ma/com etc1-1-13 resistors and capacitors are 0402 package size 50 ltc2142-12 21421012 f12 enc C enc + 0.1f 0.1f t1 figure 12. sinusoidal encode drive enc + enc C pecl or lvds clock 0.1f 0.1f 21421012 f13 ltc2142-12 figure 13. pecl or lvds encode drive v dd ltc2142-12 21421012 f10 enc C enc + 15k v dd differential comparator 30k figure 10. equivalent encode input circuit for differential encode mode 30k enc + enc C 21421012 f11 0v 1.8v to 3.3v ltc2142-12 cmos logic buffer figure 11. equivalent encode input circuit for single-ended encode mode enc C should stay at least 200mv above ground to avoid falsely triggering the single ended encode mode. for good jitter performance enc + and enc C should have fast rise and fall times. the single-ended encode mode should be used with cmos encode inputs. to select this mode, enc C is connected to ground and enc + is driven with a square wave encode input. enc + can be taken above v dd (up to 3.6v) so 1.8v to 3.3v cmos logic levels can be used. the enc + threshold is 0.9v. for good jitter performance, enc + should have fast rise and fall times. if the encode signal is turned off or drops below approxi- mately 500khz, the a/d enters nap mode. clock duty cycle stabilizer for good performance the encode signal should have a 50% (5%) duty cycle. if the optional clock duty cycle stabilizer circuit is enabled, the encode duty cycle can vary from 30% to 70% and the duty cycle stabilizer will maintain a constant 50% internal duty cycle. if the encode signal changes frequency, the duty cycle stabilizer circuit requires one hundred clock cycles to lock onto the input clock. the duty cycle stabilizer is enabled by mode control register a2 (serial programming mode), or by cs (parallel programming mode). for applications where the sample rate needs to be changed quickly, the clock duty cycle stabilizer can be disabled. if the duty cycle stabilizer is disabled, care should be taken to make the sampling clock have a 50% (5%) duty cycle. the duty cycle stabilizer should not be used below 5msps. digital outputs digital output modes the ltc2142-12/ltc2141-12/ltc2140-12 can operate in three digital output modes: full rate cmos, double data rate cmos (to halve the number of output lines), or double data rate lvds (to reduce digital noise in the system.) the output mode is set by mode control register a3 (serial programming mode), or by sck (parallel programming mode). note that double data rate cmos cannot be selected in the parallel programming mode. applications information
ltc2142-12/ ltc2141-12/ltc2140-12 24 21421012fa applications information full rate cmos mode in full rate cmos mode the data outputs (d1_0 to d1_11 and d2_0 to d2_11), overflow (of2, of1), and the data output clocks (clkout + , clkout C ) have cmos output levels. the outputs are powered by ov dd and ognd which are isolated from the a/d core power and ground. ov dd can range from 1.1v to 1.9v, allowing 1.2v through 1.8v cmos logic outputs. for good performance, the digital outputs should drive minimal capacitive loads. if the load capacitance is larger than 10pf a digital buffer should be used. double data rate cmos mode in double data rate cmos mode, two data bits are multiplexed and output on each data pin. this reduces the number of digital lines by thirteen, simplifying board routing and reducing the number of input pins needed to receive the data. the data outputs (d1_0_1, d1_2_3, d1_4_5, d1_6_7, d1_8_9, d1_10_11, d2_0_1, d2_2_3, d2_4_5, d2_6_7, d2_8_9, d2_10_11), overflow (of2_1), and the data output clocks (clkout + , clkout C ) have cmos output levels. the outputs are powered by ov dd and ognd which are isolated from the a/d core power and ground. ov dd can range from 1.1v to 1.9v, allowing 1.2v through 1.8v cmos logic outputs. note that the overflow for both adc channels is multiplexed onto the of2_1 pin. for good performance, the digital outputs should drive minimal capacitive loads. if the load capacitance is larger than 10pf a digital buffer should be used. double data rate lvds mode in double data rate lvds mode, two data bits are multiplexed and output on each differential output pair. there are six lvds output pairs per adc channel (d1_0_1 + /d1_0_1 C through d1_10_11 + /d1_10_11 C and d2_0_1 + /d2_0_1 C through d2_10_11 + /d2_10_11 C ) for the digital output data. overflow (of2_1 + /of2_1 C ) and the data output clock (clkout + /clkout C ) each have an lvds output pair. note that the overflow for both adc channels is multiplexed onto the of2_1 + /of2_1 C output pair. by default the outputs are standard lvds levels: 3.5ma output current and a 1.25v output common mode volt- age. an external 100 differential termination resistor is required for each lvds output pair. the termination resistors should be located as close as possible to the lvds receiver. the outputs are powered by ov dd and ognd which are isolated from the a/d core power and ground. in lvds mode, ov dd must be 1.8v. programmable lvds output current in lvds mode, the default output driver current is 3.5ma. this current can be adjusted by serially programming mode control register a3. available current levels are 1.75ma, 2.1ma, 2.5ma, 3ma, 3.5ma, 4ma and 4.5ma. optional lvds driver internal termination in most cases, using just an external 100 termination resistor will give excellent lvds signal integrity. in addi- tion, an optional internal 100 termination resistor can be enabled by serially programming mode control register a3. the internal termination helps absorb any reflections caused by imperfect termination at the receiver. when the internal termination is enabled, the output driver current is doubled to maintain the same output voltage swing. overflow bit the overflow output bit outputs a logic high when the analog input is either overranged or underranged. the overflow bit has the same pipeline latency as the data bits. in full rate cmos mode each adc channel has its own overflow pin (of1 for channel 1, of2 for channel 2). in ddr cmos or ddr lvds mode the overflow for both adc channels is multiplexed onto the of2_1 output.
25 21421012fa ltc2142-12/ ltc2141-12/ltc2140-12 applications information phase shifting the output clock in full rate cmos mode the data output bits normally change at the same time as the falling edge of clkout + , so the rising edge of clkout + can be used to latch the output data. in double data rate cmos and lvds modes the data output bits normally change at the same time as the falling and rising edges of clkout + . to allow adequate set-up and hold time when latching the data, the clkout + signal may need to be phase shifted relative to the data output bits. most fpgas have this feature; this is generally the best place to adjust the timing. the ltc2142-12/ltc2141-12/ltc2140-12 can also phase shift the clkout + /clkout C signals by serially programming mode control register a2. the output clock can be shifted by 0, 45, 90, or 135. to use the phase shifting feature the clock duty cycle stabilizer must be turned on. another control register bit can invert the polarity of clkout + and clkout C , independently of the phase shift. the combination of these two features enables phase shifts of 45 up to 315 (figure 14). data format table 1 shows the relationship between the analog input voltage, the digital data output bits and the overflow bit. by default the output data format is offset binary. the 2s complement format can be selected by serially program- ming mode control register a4. table 1. output codes vs input voltage a in + C a in C (2v range) of d11-d0 (offset binary) d11-d0 (2s complement) >+1.000000v +0.999512v +0.999024v 1 0 0 1111 1111 1111 1111 1111 1111 1111 1111 1110 0111 1111 1111 0111 1111 1111 0111 1111 1110 +0.000488v 0.000000v C0.000488v C0.000976v 0 0 0 0 1000 0000 0001 1000 0000 0000 0111 1111 1111 0111 1111 1110 0000 0000 0001 0000 0000 0000 1111 1111 1111 1111 1111 1110 C0.999512v C1.000000v ?C1.000000v 0 0 1 0000 0000 0001 0000 0000 0000 0000 0000 0000 1000 0000 0001 1000 0000 0000 1000 0000 0000 clkout + d0-d11, of phase shift 0 45 90 135 180 225 270 315 clkinv 0 0 0 0 1 1 1 1 clkphase1 mode control bits 0 0 1 1 0 0 1 1 clkphase0 0 1 0 1 0 1 0 1 21421012 f14 enc + figure 14. phase shifting clkout
ltc2142-12/ ltc2141-12/ltc2140-12 26 21421012fa digital output randomizer interference from the a/d digital outputs is sometimes unavoidable. digital interference may be from capacitive or inductive coupling or coupling through the ground plane. even a tiny coupling factor can cause unwanted tones in the adc output spectrum. by randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized which reduces the unwanted tone amplitude. the digital output is randomized by applying an exclusive- or logic operation between the lsb and all other data output bits. to decode, the reverse operation is applied C an exclusive-or operation is applied between the lsb and all other bits. the lsb, of and clkout outputs are not affected. the output randomizer is enabled by serially programming mode control register a4. alternate bit polarity another feature that reduces digital feedback on the circuit board is the alternate bit polarity mode. when this mode is enabled, all of the odd bits (d1, d3, d5, d7, d9, d11) are inverted before the output buffers. the even bits (d0, d2, d4, d6, d8, d10), of and clkout are not affected. this can reduce digital currents in the circuit board ground plane and reduce digital noise, particularly for very small analog input signals. when there is a very small signal at the input of the a/d that is centered around mid-scale, the digital outputs toggle between mostly 1s and mostly 0s. this simultaneous switching of most of the bits will cause large currents in the ground plane. by inverting every other bit, the alternate bit polarity mode makes half of the bits transition high while half of the bits transition low. this cancels current flow in the ground plane, reducing the digital noise. the digital output is decoded at the receiver by inverting the odd bits (d1, d3, d5, d7, d9, d11). the alternate bit polarity mode is independent of the digital output randomizer C either, both or neither function can be on at the same time. the alternate bit polarity mode is enabled by serially programming mode control register a4. applications information clkout clkout of d11/d0 d10/d0 ? ? ? d2/d0 d1/d0 d0 21421012 f15 of d11 d10 d2 d1 d0 randomizer on d11 fpga pc board d10 t t t d2 d1 d0 21421012 f16 d0 d1/d0 d2/d0 d10/d0 d11/d0 of clkout ltc2142-12 figure 15. functional equivalent of digital output randomizer figure 16. unrandomizing a randomized digital output signal
27 21421012fa ltc2142-12/ ltc2141-12/ltc2140-12 slight temperature shift caused by the change in supply current as the a/d leaves nap mode. either channel 2 or both channels can be placed in nap mode; it is not possible to have channel 1 in nap mode and channel 2 operating normally. sleep mode and nap mode are enabled by mode control register a1 (serial programming mode), or by sdi and sdo (parallel programming mode). device programming modes the operating modes of the ltc2142-12/ltc2141-12/ ltc2140-12 can be programmed by either a parallel interface or a simple serial interface. the serial interface has more flexibility and can program all available modes. the parallel interface is more limited and can only program some of the more commonly used modes. parallel programming mode to use the parallel programming mode, par/ ser should be tied to v dd . the cs , sck, sdi and sdo pins are binary logic inputs that set certain operating modes. these pins can be tied to v dd or ground, or driven by 1.8v, 2.5v, or 3.3v cmos logic. when used as an input, sdo should be driven through a 1k series resistor. table 2 shows the modes set by cs , sck, sdi and sdo. table 2. parallel programming mode control bits (par/ ser = v dd ) pin description cs clock duty cycle stabilizer control bit 0 = clock duty cycle stabilizer off 1 = clock duty cycle stabilizer on sck digital output mode control bit 0 = full rate cmos output mode 1 = double data rate lvds output mode (3.5ma lvds current, internal termination off) sdi/sdo power down c ontrol bit 00 = normal operation 01 = channel 1 in normal operation, channel 2 in nap mode 10 = channel 1 and channel 2 in nap mode 11 = sleep mode (entire device powered down) applications information digital output test patterns to allow in-circuit testing of the digital interface to the a/d, there are several test modes that force the a/d data outputs (of, d11-d0) to known values: all 1s: all outputs are 1 all 0s: all outputs are 0 alternating: outputs change from all 1s to all 0s on alternating samples. checkerboard: outputs change from 1010101010101 to 0101010101010 on alternating samples. the digital output test patterns are enabled by serially programming mode control register a4. when enabled, the test patterns override all other formatting modes: 2s complement, randomizer, alternate bit polarity. output disable the digital outputs may be disabled by serially program- ming mode control register a3. all digital outputs including of and clkout are disabled. the high impedance disabled state is intended for in-circuit testing or long periods of inactivity C it is too slow to multiplex a data bus between multiple converters at full speed. when the outputs are disabled both channels should be put into either sleep or nap mode. sleep and nap modes the a/d may be placed in sleep or nap modes to conserve power. in sleep mode the entire device is powered down, resulting in 1mw power consumption. the amount of time required to recover from sleep mode depends on the size of the bypass capacitors on v ref , refh, and refl. for the suggested values in fig. 8, the a/d will stabilize after 2ms. in nap mode the a/d core is powered down while the internal reference circuits stay active, allowing faster wakeup than from sleep mode. recovering from nap mode requires at least 100 clock cycles. if the application demands very accurate dc settling then an additional 50s should be allowed so the on-chip references can settle from the
ltc2142-12/ ltc2141-12/ltc2140-12 28 21421012fa serial programming mode to use the serial programming mode, par/ ser should be tied to ground. the cs , sck, sdi and sdo pins become a serial interface that program the a/d mode control registers. data is written to a register with a 16-bit serial word. data can also be read back from a register to verify its contents. serial data transfer starts when cs is taken low. the data on the sdi pin is latched at the first 16 rising edges of sck. any sck rising edges after the first 16 are ignored. the data transfer ends when cs is taken high again. the first bit of the 16-bit input word is the r/ w bit. the next seven bits are the address of the register (a6:a0). the final eight bits are the register data (d7:d0). if the r/ w bit is low, the serial data (d7:d0) will be writ- ten to the register set by the address bits (a6:a0). if the r/ w bit is high, data in the register set by the address bits (a6:a0) will be read back on the sdo pin (see the timing diagrams). during a read back command the register is not updated and data on sdi is ignored. the sdo pin is an open drain output that pulls to ground with a 200 impedance. if register data is read back through sdo, an external 2k pull-up resistor is required. if serial data is only written and read back is not needed, then sdo can be left floating and no pull-up resistor is needed. table 3 shows a map of the mode control registers. software reset if serial programming is used, the mode control registers should be programmed as soon as possible after the power supplies turn on and are stable. the first serial command must be a software reset which will reset all register data bits to logic 0. to perform a software reset, bit d7 in the reset register is written with a logic 1. after the reset spi write command is complete, bit d7 is automatically set back to zero. grounding and bypassing the ltc2142-12/ltc2141-12/ltc2140-12 requires a printed circuit board with a clean unbroken ground plane. a multilayer board with an internal ground plane in the first layer beneath the adc is recommended. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track or underneath the adc. high quality ceramic bypass capacitors should be used at the v dd , ov dd , v cm , v ref , refh and refl pins. bypass capacitors must be located as close to the pins as possible. size 0402 ceramic capacitors are recommended. the traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. of particular importance is the capacitor between refh and refl. this capacitor should be on the same side of the circuit board as the a/d, and as close to the device as possible. the analog inputs, encode signals, and digital outputs should not be routed next to each other. ground fill and grounded vias should be used as barriers to isolate these signals from each other. heat transfer most of the heat generated by the ltc2142-12/ltc2141-12/ ltc2140-12 is transferred from the die through the bottom- side exposed pad and package leads onto the printed circuit board. for good electrical and thermal performance, the exposed pad must be soldered to a large grounded pad on the pc board. this pad should be connected to the internal ground planes by an array of vias. applications information
29 21421012fa ltc2142-12/ ltc2141-12/ltc2140-12 applications information table 3. serial programming mode register map (par/ ser = gnd) register a0: reset register (address 00h) d7 d6 d5 d4 d3 d2 d1 d0 resetxxxxxxx bit 7 reset software reset bit 0 = not used 1 = software reset. all mode control registers are reset to 00h. the adc is momentarily placed in sleep mode. this bit is automatically set back to zero at the end of the spi write command. the reset register is write-only. data read back from the reset register will be random. bits 6-0 unused, dont care bits. register a1: power-down register (address 01h) d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxp wroff1 pwroff0 bits 7-2 unused, dont care bits. bits 1-0 pwroff1:pwroff0 power down control bits 00 = normal operation 01 = channel 1 in normal operation, channel 2 in nap mode 10 = channel 1 and channel 2 in nap mode 11 = sleep mode register a2: timing register (address 02h) d7 d6 d5 d4 d3 d2 d1 d0 xxxxc lkinv clkphase1 clkphase0 dcs bits 7-4 unused, dont care bits. bit 3 clkinv output clock invert bit 0 = normal clkout polarity (as shown in the timing diagrams) 1 = inverted clkout polarity bits 2-1 clkphase1:clkphase0 output clock phase delay bits 00 = no clkout delay (as shown in the timing diagrams) 01 = clkout + /clkout C delayed by 45 (clock period ? 1/8) 10 = clkout + /clkout C delayed by 90 (clock period ? 1/4) 11 = clkout + /clkout C delayed by 135 (clock period ? 3/8) note: if the clkout phase delay feature is used, the clock duty cycle stabilizer must also be turned on bit 0 dcs clock duty cycle stabilizer bit 0 = clock duty cycle stabilizer off 1 = clock duty cycle stabilizer on
ltc2142-12/ ltc2141-12/ltc2140-12 30 21421012fa register a3: output mode register (address 03h) d7 d6 d5 d4 d3 d2 d1 d0 x ilvds2 ilvds1 ilvds0 termon outoff outmode1 outmode0 bit 7 unused, dont care bit. bits 6-4 ilvds2:ilvds0 lvds output current bits 000 = 3.5ma lvds output driver current 001 = 4.0ma lvds output driver current 010 = 4.5ma lvds output driver current 011 = not used 100 = 3.0ma lvds output driver current 101 = 2.5ma lvds output driver current 110 = 2.1ma lvds output driver current 111 = 1.75ma lvds output driver current bit 3 termon lvds internal termination bit 0 = internal termination off 1 = internal termination on. lvds output driver current is 2 the current set by ilvds2:ilvds0 bit 2 outoff output disable bit 0 = digital outputs are enabled 1 = digital outputs are disabled and have high output impedance note: if the digital outputs are disabled the part should also be put in sleep or nap mode (both channels). bits 1-0 outmode1:outmode0 digital output mode control bits 00 = full rate cmos output mode 01 = double data rate lvds output mode 10 = double data rate cmos output mode 11 = not used register a4: data format register (address 04h) d7 d6 d5 d4 d3 d2 d1 d0 x x outtest2 outtest1 outtest0 abp rand twoscomp bit 7-6 unused, dont care bits. bits 5-3 outtest2:outtest0 digital output test pattern bits 000 = digital output test patterns off 001 = all digital outputs = 0 011 = all digital outputs = 1 101 = checkerboard output pattern. of, d11-d0 alternate between 1 0101 0101 0101 and 0 1010 1010 1010 111 = alternating output pattern. of, d11-d0 alternate between 0 0000 0000 0000 and 1 1111 1111 1111 note: other bit combinations are not used bit 2 abp alternate bit polarity mode control bit 0 = alternate bit polarity mode off 1 = alternate bit polarity mode on. forces the output format to be offset binary bit 1 rand data output randomizer mode control bit 0 = data output randomizer mode off 1 = data output randomizer mode on bit 0 twoscomp twos complement mode control bit 0 = offset binary data format 1 = twos complement data format applications information
31 21421012fa ltc2142-12/ ltc2141-12/ltc2140-12 silkscreen top typical applications top side
ltc2142-12/ ltc2141-12/ltc2140-12 32 21421012fa typical applications inner layer 2 gnd inner layer 3
33 21421012fa ltc2142-12/ ltc2141-12/ltc2140-12 typical applications inner layer 4 inner layer 5 power
ltc2142-12/ ltc2141-12/ltc2140-12 34 21421012fa typical applications bottom side
35 21421012fa ltc2142-12/ ltc2141-12/ltc2140-12 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 d1_0_1 + d1_0_1 C dnc dnc dnc dnc ov dd ognd clkout + clkout C d2_10_11 + d2_10_11 C d2_8_9 + d2_8_9 C d2_6_7 + d2_6_7 C 65 pad 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 v dd sense v ref sdo of2_1 + of2_1 C d1_10_11 + d1_10_11 C d1_8_9 + d1_8_9 C d1_6_7 + d1_6_7 C d1_4_5 + d1_4_5 C d1_2_3 + d1_2_3 C 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 v dd enc + enc C cs sck sdi dnc dnc dnc dnc d2_1_0 C d2_1_0 + d2_2_3 C d2_2_3 + d2_4_5 C d2_4_5 + 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 c19 0.1f sdo sense v dd v dd v cm1 gnd a in1 + a in1 C gnd refh refl refh refl par/ ser a in2 + a in2 C gnd v cm2 v dd c20 0.1f c18 0.1f v dd par/ ser c17 1f c23 2.2f c37 0.1f digital outputs digital outputs ov dd spi bus c67 0.1f c78 0.1f c79 0.1f r51 100 ltc2142-12 encode clock cn1 a in2 + a in2 C a in1 + a in1 C c15 0.1f c21 0.1f + + C C C C + + 21821012 ta02 typical applications ltc2142 schematic
ltc2142-12/ ltc2141-12/ltc2140-12 36 21421012fa package description 9 .00 0.10 (4 sides) note: 1. drawing conforms to jedec package outline mo-220 variation wnjr-5 2. all dimensions are in millimeters 3. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side, if present 4. exposed pad shall be solder plated 5. shaded area is only a reference for pin 1 location on the top and bottom of package 6. drawing not to scale pin 1 top mark (see note 5) 0.40 0.10 64 63 1 2 bottom viewexposed pad 7.15 0.10 7.15 0.10 7.50 ref (4-sides) 0.75 0.05 r = 0.10 typ r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 C 0.05 (up64) qfn 0406 rev c recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 7.50 ref (4 sides) 7.15 0.05 7.15 0.05 8.10 0.05 9.50 0.05 0.25 0.05 0.50 bsc package outline pin 1 chamfer c = 0.35 up package 64-lead plastic qfn (9mm w 9mm) (reference ltc dwg # 05-08-1705 rev c) please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
37 21421012fa ltc2142-12/ ltc2141-12/ltc2140-12 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 07/12 corrected channel 1 data bus (d1_*) pin description to state channel 1 16
ltc2142-12/ ltc2141-12/ltc2140-12 38 21421012fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2011 lt 0712 rev a ? printed in usa related parts part number description comments adcs ltc2259-14/ltc2260-14/ ltc2261-14 14-bit, 80msps/105msps/125msps 1.8v adcs, ultralow power 89mw/106mw/127mw, 73.4db snr, 85db sfdr, ddr lvds/ddr cmos/cmos outputs, 6mm 6mm qfn-40 ltc2262-14 14-bit, 150msps 1.8v adc, ultralow power 149mw, 72.8db snr, 88db sfdr, ddr lvds/ddr cmos/cmos outputs, 6mm 6mm qfn-40 ltc2266-14/ltc2267-14/ ltc2268-14 14-bit, 80msps/105msps/125msps 1.8v dual adcs, ultralow power 216mw/250mw/293mw, 73.4db snr, 85db sfdr, serial lvds outputs, 6mm 6mm qfn-40 ltc2266-12/ltc2267-12/ ltc2268-12 12-bit, 80msps/105msps/125msps 1.8v dual adcs, ultralow power 216mw/250mw/293mw, 70.5db snr, 85db sfdr, serial lvds outputs, 6mm 6mm qfn-40 ltc2182/ltc2181/ ltc2180 16-bit 65msps/40msps/25msps 1.8v dual adcs, ultralow power 182mw/112mw/70mw, 76.8db snr, 90db sfdr, ddr wds/ddr cmos/ cmos outputs, 9mm 9mm qfn-64 ltc2142-14/ltc2141-14/ ltc2140-14 14-bit 65msps/40msps/25msps 1.8v dual adcs, ultralow power 104mw/68mw/48mw, 73db snr, 90db sfdr, ddr lvds/ddr cmos/ cmos outputs, 9mm 9mm qfn-64 rf mixers/demodulators ltc5517 40mhz to 900mhz direct conversion quadrature demodulator high iip3: 21dbm at 800mhz, integrated lo quadrature generator ltc5557 400mhz to 3.8ghz high linearity downconverting mixer 23.7dbm iip3 at 2.6ghz, 23.5dbm iip3 at 3.5ghz, nf = 13.2db, 3.3v supply operation, integrated transformer ltc5575 800mhz to 2.7ghz direct conversion quadrature demodulator high iip3: 28dbm at 900mhz, integrated lo quadrature generator, integrated rf and lo transformer amplifiers/filters ltc6412 800mhz, 31db range, analog-controlled variable gain amplifier continuously adjustable gain control, 35dbm oip3 at 240mhz, 10db noise figure, 4mm 4mm qfn-24 ltc6605-7/ltc6605-10/ ltc6605-14 dual matched 7mhz/10mhz/14mhz filters with adc drivers dual matched 2nd order lowpass filters with differential drivers, pin-programmable gain, 6mm 3mm dfn-22 signal chain receivers ltm9002 14-bit dual channel if/baseband receiver subsystem integrated high speed adc, passive filters and fixed gain differential amplifiers typical applications cmos, ddr cmos or ddr lvds outputs 1.8v v dd 1.8v ov dd clock control d1_11 d1_0 21421012 ta01a ch 1 analog input output drivers t t t gnd ognd s/h 12-bit adc core ch 2 analog input s/h 12-bit adc core d2_11 d2_0 t t t 65mhz clock frequency (mhz) C100 C110 C120 C70 C60 C80 C90 amplitude (dbfs) C50 C30 C40 C20 C10 0 21821012 ta01b f requency (m hz) 2 1821012 ta01 b 0 10 20 30 2-tone fft, f in = 70mhz and 69mhz

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