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max11166 16-bit, 500ksps, 5v sar adc with internal reference in tdfn general description the max11166 16-bit, 500ksps, sar adc offers excel - lent ac and dc performance with true bipolar input range, small size, and internal reference. the max11166 mea - sures a q 5v (10v p-p ) input range while operating from a single 5v supply. a patented charge-pump architecture allows direct sampling of high-impedance sources. the max11166 integrates an optional internal reference and buffer, saving additional cost and space. this adc achieves 92.9db snr and -103db thd. the max11166 guarantees 16-bit no-missing codes and q 0.4 lsb inl (typ). the max11166 communicates using an spi-compatible serial interface at 2.5v, 3v, 3.3v, or 5v logic. the serial interface can be used to daisy-chain multiple adcs in parallel for multichannel applications and provides a busy indicator option for simplified system synchronization and timing. the max11166 is offered in a 12-pin, 3mm x 3mm, tdfn package and is specified over the -40 n c to +85 n c tem - perature range. applications data acquisition systems industrial control systems/process control medical instrumentation automatic test equipment beneits and features high dc/ac accuracy improves measurement quality ? 16-bit resolution with no missing codes ? 500ksps throughput rates without pipeline delay/ latency ? 92.9db snr and -103db thd at 10khz ? 0.5 lsb rms transition noise ? 0.2 lsb dnl (typ) and 0.4 lsb inl (typ) highly integrated adc saves cost and space ? 6ppm/c internal reference ? internal reference buffer ? 5v bipolar analog input range wide supply range and low power simplify power- supply design ? 5v analog supply ? 2.3v to 5v digital supply ? 25.5mw power consumption at 500ksps ? 10a in shutdown mode multi-industry standard serial interface and small package reduce size ? spi/qspi?/microwire?/dsp-compatible serial interface ? 3mm x 3mm tiny 12-pin tdfn package 19-7673; rev 0; 7/15 typical operating circuit selector guide and ordering information appear at end of data sheet. qspi is a trademark of motorola, inc. microwire is a registered trademark of national semiconductor corporation. 14-bit to 18-bit sar adc family evaluation kit available 14-bit 500ksps 16-bit 250ksps 16-bit 500ksps 18-bit 500ksps 5v input internal reference max11167 max11169 max11166 max11168 max11156 max11158 0 to 5v input internal reference max11161 max11165 max11160 max11164 max11150 max11154 0 to 5v input external reference max11262 max11163 max11162 max11152 v ovdd (2.3v to 5v) v dd (5v) ain+ ref host c 10f 4.7nf max11166 internal reference refbuf gnd 16-bit adc ain- max9632 interface and control cnvst dout din sclk 1f 1f 5v 10 ? 0.1f agnds refio downloaded from: http:///
maxim integrated 2 max11166 16-bit, 500ksps, 5v sar adc with internal reference in tdfn www.maximintegrated.com v dd to gnd ............................................................ -0.3v to +6v ovdd to gnd ....... -0.3v to the lower of (v dd + 0.3v) and +6v ain+ to gnd ........................................................................ q 7v ain-, ref, refio, agnds to gnd ............... -0.3v to the lower of (v dd + 0.3v) and +6v sclk, din, dout, cnvst to gnd ............... -0.3v to the lower of (v dd + 0.3v) and +6v maximum current into any pin ...........................................50ma continuous power dissipation (t a = +70 n c) tdfn (derate 18.2mw/ n c above +70 n c) .................. 1349mw operating temperature range ........................... -40 n c to +85 n c junction temperature ...................................................... +150 n c storage temperature range ............................ -65 n c to +150 n c lead temperature (soldering, 10s) ................................. +300 n c soldering temperature (reflow) ....................................... +260 n c absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. electrical characteristics (v dd = 4.75v to 5.25v, v ovdd = 2.3v to 5.25v, f sample = 500ksps, v ref = 4.096v; reference mode 3, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 n c.) (note 2) note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . tdfn junction-to-ambient thermal resistance ( q ja ).......59.3 n c/w junction-to-case thermal resistance ( q jc ) ........... 22.5 n c/w package thermal characteristics (note 1) parameter symbol conditions min typ max units analog input (note 3) input voltage range ain+ to ain-, k = -k x v ref +k x v ref v absolute input voltage range ain+ to gnd -(v dd + 0.1) +(v dd + 0.1) v ain- to gnd -0.1 +0.1 input leakage current acquisition phase -10 +0.001 +10 a input capacitance 16 pf input-clamp protection current both inputs -20 +20 ma dc accuracy (note 4) resolution n 16 bits no missing codes 16 bits offset error -7.5 0.8 +7.5 lsb offset temperature coeficient 0.006 lsb/c gain error -4.3 1.2 +4.3 lsb gain error temperature coeficient 0.015 lsb/c integral nonlinearity inl t a = t min to t max -1.2 0.4 +1.2 lsb differential nonlinearity dnl guaranteed by design -0.5 0.2 +0.5 lsb positive full-scale error -8 +8 lsb 5.000 4.096 downloaded from: http:///
maxim integrated 3 max11166 16-bit, 500ksps, 5v sar adc with internal reference in tdfn www.maximintegrated.com electrical characteristics (continued) (v dd = 4.75v to 5.25v, v ovdd = 2.3v to 5.25v, f sample = 500ksps, v ref = 4.096v; reference mode 3, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 n c.) (note 2) parameter symbol conditions min typ max units negative full-scale error -8 +8 lsb analog input cmrr cmrr -1.1 lsb/v power-supply rejection (note 5) psr -4.5 lsb/v transition noise 0.5 lsb rms reference (note 7) ref output initial accuracy v ref reference mode 0 4.092 4.096 4.100 v ref output temperature coeficient tc ref reference mode 0 7.5 17 ppm/c refio output initial accuracy v refio reference modes 0 and 2 4.092 4.096 4.100 v refio output temperature coeficient tc refio reference modes 0 and 2 6 15 ppm/c refio output impedance reference modes 0 and 2 10 k refio input voltage range reference mode 1 3.00 4.096 4.25 v reference buffer initial offset reference modes 0 and 1 -500 +500 v reference buffer temperature coeficient reference modes 0 and 1 6 10 v/c external compensation capacitor c ext required for reference modes 0 and 1, recommended for reference modes 2 and 3 10 f ref voltage input range v ref reference modes 2 and 3 2.5 4.25 v ref input capacitance reference modes 2 and 3 20 pf ref load current i ref v ref = 4.096v, reference modes 2 and 3 146 a ac accuracy (note 6) signal-to-noise ratio (note 7) snr f in = 10khz v ref = 4.096v, reference mode 3 91.8 92.9 db v ref = 4.096v, reference mode 1 92.8 v ref = 2.5v, reference mode 3 89.8 internal reference, reference mode 0 92.9 signal-to-noise plus distortion (note 7) sinad f in = 10khz v ref = 4.096v, reference mode 3 91.1 92.1 db v ref = 4.096v, reference mode 1 92.1 v ref = 2.5v, reference mode 3 89.3 internal reference, reference mode 0 92.3 spurious-free dynamic range sfdr 99.0 -104.3 db total harmonic distortion thd -103.0 -97.5 db intermodulation distortion (note 8) imd -119.7 db downloaded from: http:///
maxim integrated 4 max11166 16-bit, 500ksps, 5v sar adc with internal reference in tdfn www.maximintegrated.com electrical characteristics (continued) (v dd = 4.75v to 5.25v, v ovdd = 2.3v to 5.25v, f sample = 500ksps, v ref = 4.096v; reference mode 3, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 n c.) (note 2) parameter symbol conditions min typ max units sampling dynamicsthroughput sample rate 0.01 500 ksps transient response full-scale step 400 ns full-power bandwidth -3db point 6 mhz -0.1db point > 0.2 aperture delay 2.5 ns aperture jitter < 50 ps rms power supplies analog supply voltage v dd 4.75 5.25 v interface supply voltage v ovdd 2.3 5.25 v analog supply current i vdd reference mode = 0, 1 5.0 6.0 7.0 ma reference mode = 2, 3 3.0 3.5 4.0 v dd shutdown current 6.1 10 a interface supply current i ovdd v ovdd = 2.3v 1.5 2.0 ma v ovdd = 5.25v 4.3 5.0 ovdd shutdown current 0.9 10 a power dissipation v dd = 5v, v ovdd = 3.3v, reference mode = 2, 3 25.5 mw v dd = 5v, v ovdd = 3.3v, reference mode = 0, 1 37.5 digital inputs (din, sclk, cnvst) input voltage high v ih 0.7 x v ovdd v input voltage low v il 0.3 x v ovdd v input hysteresis v hys 0.05 x v ovdd v input capacitance c in 10 pf input current i in v in = 0v or v ovdd -10 +10 a digital output (dout) output voltage high v oh i source = 2ma v ovdd - 0.4 v output voltage low v ol i sink = 2ma 0.4 v three-state leakage current -10 +10 a three-state output capacitance 15 pf downloaded from: http:///
maxim integrated 5 max11166 16-bit, 500ksps, 5v sar adc with internal reference in tdfn www.maximintegrated.com electrical characteristics (continued) (v dd = 4.75v to 5.25v, v ovdd = 2.3v to 5.25v, f sample = 500ksps, v ref = 4.096v; reference mode 3, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 n c.) (note 2) note 2: maximum and minimum limits are fully production tested over specified supply voltage range and at a temperature of +25c. limits over the operating temperature range are guaranteed by design and device characterization. note 3: see the analog inputs and overvoltage input clamps sections. note 4: static performance limits are guaranteed by design and device characterization. for definitions, see the definitions section. note 5: defined as the change in positive full-scale code transition caused by a q 5% variation in the v dd supply voltage. note 6: 10khz sine wave input, -0.1db below full scale. note 7: see table 4 for definition of the reference modes. note 8: f in1 ~ 9.4khz, f in2 ~ 10.7khz, each tone at -6.1db below full scale. note 9: c load = 65pf on dout. parameter symbol conditions min typ max units timing (note 9) time between conversions t cyc 2 100000 s conversion time t conv cnvst rising to data available 1.35 1.5 s acquisition time t acq t acq = t cyc - t conv 0.5 s cnvst pulse width t cnvpw cs mode 5 ns sclk period ( cs mode) t sclk v ovdd > 4.5v 14 ns v ovdd > 2.7v 20 v ovdd > 2.3v 26 sclk period (daisy-chain mode) t sclk v ovdd > 4.5v 16 ns v ovdd > 2.7v 24 v ovdd > 2.3v 30 sclk low time t sclkl 5 ns sclk high time t sclkh 5 ns sclk falling edge to data valid delay t ddo v ovdd > 4.5v 12 ns v ovdd > 2.7v 18 v ovdd > 2.3v 23 cnvst low to dout d15 msb valid ( cs mode) t en v ovdd > 2.7v 14 ns v ovdd < 2.7v 17 cnvst high or last sclk falling edge to dout high impedance t dis cs mode 20 ns din valid setup time from sclk falling edge t sdinsck v ovdd > 4.5v 3 ns v ovdd > 2.7v 5 v ovdd > 2.3v 6 din valid hold time from sclk falling edge t hdinsck 0 ns sclk valid setup time to cnvst falling edge t ssckcnf 3 ns sclk valid hold time to cnvst falling edge t hsckcnf 6 ns downloaded from: http:///
maxim integrated 6 www.maximintegrated.com max11166 16-bit, 500ksps, 5v sar adc with internal reference in tdfn (v dd = 5.0v, v ovdd = 3.3v, f sample = 500ksps; reference mode 3, t a = +25c, unless otherwise noted.) typical operating characteristics -4 -3 -2 -1 0 1 2 3 4 -40 -15 10 35 60 85 error (lsb) temperature ( c) offset error gain error offset and gain error vs. temperature average of 128 devices toc01 -4 -3 -2 -1 0 1 2 3 4 4.75 4.85 4.95 5.05 5.15 5.25 error (lsb) v dd (v) offset error gain error offset and gain error vs. v dd supply voltage average of 128 devices toc02 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 8192 16384 24576 32768 40960 49152 57344 65536 dnl (lsb) output code (decimal) differential nonlinearity vs. code single device toc03 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 -40 -15 10 35 60 85 dnl (lsb) temperature ( c) dnl vs. temperature max dnl min dnl average of 128 devices toc05 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 0 8192 16384 24576 32768 40960 49152 57344 65536 inl (lsb) output code (decimal) integral nonlinearity vs. code single device toc04 -4 -3 -2 -1 0 1 2 3 4 -40 -15 10 35 60 85 inl (lsb) temperature ( c) inl vs. temperature max inl min inl average of 128 devices toc06 downloaded from: http:///
maxim integrated 7 www.maximintegrated.com max11166 16-bit, 500ksps, 5v sar adc with internal reference in tdfn (v dd = 5.0v, v ovdd = 3.3v, f sample = 500ksps; reference mode 3, t a = +25c, unless otherwise noted.) typical operating characteristics (continued) -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 4.75 4.85 4.95 5.05 5.15 5.25 dnl (lsb) v dd (v) dnl vs. v dd supply voltage max dnl min dnl average of 128 devices toc07 -4 -3 -2 -1 0 1 2 3 4 4.75 4.85 4.95 5.05 5.15 5.25 inl (lsb) v dd (v) inl vs. v dd supply voltage max inl min inl average of 128 devices toc08 0 4000 8000 12000 16000 20000 24000 28000 32762 32763 32764 32765 32766 32767 32768 32769 32770 32771 32772 32773 32774 number of occurrences output code (decimal) output noise histogram no average single device stdev = 0.45 lsb rms toc09 4.090 4.092 4.094 4.096 4.098 4.100 4.102 4.104 -40 -15 10 35 60 85 v ref (v) temperature ( c) internal reference voltage (ref pin) vs. temperature 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 15 devices toc11 0 4000 8000 12000 16000 20000 24000 28000 32762 32763 32764 32765 32766 32767 32768 32769 32770 32771 32772 32773 32774 number of occurrences output code (decimal) output noise histogram with 4 sample average single device stdev = 0.23 lsb rms toc10 0 10 20 30 40 50 60 4.0990 4.0985 4.0980 4.0975 4.0970 4.0965 4.0960 4.0955 4.0950 4.0945 4.0940 4.0935 4.0930 number of occurrences ref pin voltage (v) initial error voltage on ref pin 303 devices mean = 4096.0mv stdev = 1.2mv stdev = 282ppm toc12 downloaded from: http:///
maxim integrated 8 www.maximintegrated.com max11166 16-bit, 500ksps, 5v sar adc with internal reference in tdfn typical operating characteristics (continued) (v dd = 5.0v, v ovdd = 3.3v, f sample = 500ksps; reference mode 3, t a = +25c, unless otherwise noted.) 0 10 20 30 40 50 60 70 12 10 86420 -2 -4 -6 -8 -10 -12 -14 -16 number of occurrences thermal drift (ppm/ c) 25c to -40c 25c to +85c ref pin thermal drift slope 303 devices mean = 2.1ppm/ c stdev = 1.9ppm/ c 303 devices mean = - 7.3ppm/ c stdev = 1.9ppm/ c toc13 4.0955 4.0956 4.0957 4.0958 4.0959 4.0960 4.0961 4.0962 4.0963 4.0964 4.0965 4.75 4.85 4.95 5.05 5.15 5.25 v ref (v) v dd (v) internal reference voltages vs. v dd voltage ref average of 200 devices toc14 -140 -120 -100 -80 -60 -40 -20 0 0 50 100 150 200 250 magnitude (db) frequency (khz) fft plot n sample = 4096 f in = 10101 hz v in = - 0.1dbfs ref mode = 3 snr = 92.7db sinad = 92.4db sfdr = 107.4db thd = - 104.4db toc15 14.0 14.5 15.0 15.5 16.0 86 88 90 92 94 96 98 0.1 1.0 10.0 100.0 enob (bits) sinad (db) frequency (khz) sinad and enob vs. frequency sinad enob v in = - 0.1dbfs average of 128 devices toc17 -140 -120 -100 -80 -60 -40 -20 0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 14.0 magnitude (db) frequency (khz) two tones imd n sample = 16384 f in1 = 9368.9hz v in1 = - 6.1dbfs f in2 = 10651hz v in2 = - 6.1dbfs single device imd = - 119.7dbfs toc16 80 85 90 95 100 105 110 115 120 125 0.1 1.0 10.0 100.0 sfdr and - thd (db) frequency (khz) sfdr and - thd vs. frequency sfdr thd v in = - 0.1dbfs average of 128 devices toc18 downloaded from: http:///
maxim integrated 9 www.maximintegrated.com max11166 16-bit, 500ksps, 5v sar adc with internal reference in tdfn typical operating characteristics (continued) (v dd = 5.0v, v ovdd = 3.3v, f sample = 500ksps; reference mode 3, t a = +25c, unless otherwise noted.) 86 88 90 92 94 96 98 -40 -15 10 35 60 85 snr and sinad (db) temperature ( c) snr sinad snr and sinad vs. temperature f in = 10khz v in = - 0.1dbfs average of 128 devices toc19 85 90 95 100 105 110 115 -40 -15 10 35 60 85 sfdr and - thd (db) temperature ( c) thd sfdr sfdr and thd vs. temperature f in = 10khz v in = - 0.1dbfs average of 128 devices toc20 86 88 90 92 94 96 98 4.75 4.85 4.95 5.05 5.15 5.25 snr and sinad (db) v dd (v) snr sinad snr and sinad vs. v dd supply voltage f in = 10khz v in = - 0.1dbfs average of 128 devices toc21 -90 -80 -70 -60 -50 -40 -30 0.1 1.0 10.0 100.0 1000.0 cmr (db) frequency (khz) cmr vs. input frequency v ain+ = v ain - = 100mv single device toc23 96.0 98.0 100.0 102.0 104.0 106.0 108.0 4.75 4.85 4.95 5.05 5.15 5.25 sfdr and - thd (db) v dd (v) thd sfdr thd and sfdr vs. v dd supply voltage f in = 10khz v in = - 0.1dbfs average of 128 devices toc22 -80 -70 -60 -50 -40 -30 -20 0.1 1.0 10.0 100.0 1000.0 psr (db) frequency (khz) psr vs. v dd supply frequency v vdd = 5.0 250mv v ovdd = 3.3v single device toc24 downloaded from: http:///
maxim integrated 10 www.maximintegrated.com max11166 16-bit, 500ksps, 5v sar adc with internal reference in tdfn typical operating characteristics (continued) (v dd = 5.0v, v ovdd = 3.3v, f sample = 500ksps; reference mode 3, t a = +25c, unless otherwise noted.) 2 3 4 5 6 7 8 -40 -15 10 35 60 85 i vdd (ma) temperature ( c) v dd supply current vs. temperature ref mode 0 & 1 ref mode 2 & 3 average of 128 devices toc25 0 1 2 3 4 5 -40 -15 10 35 60 85 i ovdd (ma) temperature ( c) ovdd supply current vs. temperature 500ksps 10ksps c dout = 65pf average of 128 devices toc26 2 3 4 5 6 7 8 4.75 4.85 4.95 5.05 5.15 5.25 i vdd (ma) v dd (v) v dd supply current vs. v dd supply voltage ref mode 0 & 1 ref mode 2 & 3 average of 128 devices toc27 0 2 4 6 8 10 -40 -15 10 35 60 85 shutdown current (a) temperature ( c ) v dd and ovdd shutdown current vs. temperature ivdd iovdd average of 128 devices toc29 0 1 2 3 4 5 6 2.25 2.75 3.25 3.75 4.25 4.75 5.25 i ovdd (ma) v ovdd (v) ovdd supply current vs. ovdd supply voltage 500ksps 10ksps c dout = 65pf average of 128 devices toc28 0 2 4 6 8 10 2.25 2.75 3.25 3.75 4.25 4.75 5.25 shutdown current (a) v dd or v ovdd (v) v dd and ovdd shutdown current vs. supply voltage ivdd iovdd average of 128 devices toc30 downloaded from: http:///
maxim integrated 11 max11166 16-bit, 500ksps, 5v sar adc with internal reference in tdfn www.maximintegrated.com pin conigurationpin description pin name i/o function 1 refio i/o external reference input/internal reference output. place a 0.1f capacitor from refio to agnds. 2 ref i/o external reference input/reference buffer decoupling. bypass to agnds in close proximity with a x5r or x7r 10f 16v capacitor. see the layout , grounding , and bypassing section. 3 v dd i analog power supply. bypass to gnd with a 0.1f capacitor for each device and one 10f per pcb. 4 ain+ i positive analog input 5 ain- i negative analog input. connect ain- to the analog ground plane or to a remote-sense ground. 6 gnd i power-supply ground 7 cnvst i convert start input. the rising edge of cnvst initiates conversions. the falling edge of cnvst with sclk high enables the serial interface. 8 dout o serial data output. dout will change stated on the falling edge of sclk. 9 sclk i serial clock input. clocks data out of the serial interface when the device is selected. 10 din i serial data input. din data is latched into the serial interface on the rising edge of sclk. 11 ovdd i digital power supply. bypass to gnd with a 0.1f capacitor for each device and one 10f per pcb. 12 agnds i analog ground sense. zero current reference for the on-board dac and reference source. reference for refio and ref. ep exposed pad. connect to pcb gnd. 13 4 1210 98 agnds din sclk dout max11 166 2 11 ovdd 56 + 7 cnvst refio v dd ain+ ain- ref gnd ep tdfn top view downloaded from: http:///
maxim integrated 12 max11166 16-bit, 500ksps, 5v sar adc with internal reference in tdfn www.maximintegrated.com functional diagramdetailed description the max11166 is a 16-bit single-channel, pseudo- differential adc with maximum throughput rates of 500ksps/250ksps. this adc includes a precision internal reference that allows for measuring a bipolar input voltage range of q 5v. input ranges of 3.05v to 5.19v can be obtained by applying an external reference. both inputs (ain+ and ain-) are sampled with a pseudo-differential on-chip track-and-hold. the max11166 measures a true bipolar voltage of q 5v (10v p-p ) and the inputs are protected for up to q 20ma of overrange current. this adc is powered from a 4.75v to 5.25v analog supply (v dd ) and a separate 2.3v to 5.25v digital supply (ovdd). the max11166 requires 500ns to acquire the input sample on an internal track-and-hold and then convert the sampled signal to 16 bits of accuracy using an internally clocked converter. analog inputs the max11166 adc consists of a true sampling pseudo- differential input stage with high-impedance, capacitive inputs. the internal t/h circuitry feature a small-signal bandwidth of about 6mhz to provide 16-bit accurate sampling in 500ns. this allows for accurate sampling of a number of scanned channels through an external mul - tiplexer. the max11166 can thus convert input signals on ain+ in the range of -(k o v ref + ain-) to +(k o v ref + ain-) where k = 5.000/4.096. ain+ should also be limited to (v dd + 0.1v) for accurate conversions. ain- has an input range of -0.1v to +0.1v and should be connected to the ground reference of the input signal source. the max11166 performs a true differential sampling on inputs between ain+ and ain- with good common-mode rejec - tion (see the typical operating circuit ). this allows for improved sampling of remote transducer inputs. many traditional adcs with single supplies that measure bipolar input signals use resistive divider networks directly on the analog inputs. these networks increase the com - plexity of the input signal conditioning. however, the max11166 includes a patented input switch architecture that allows direct sampling of high-impedance sources. this architecture requires a minimum sample rate of 10hz to maintain accurate conversions over the designed tem - perature and supply ranges. 16-b it ad c configuration registe r refbuf internal referenc e ain+ ain- a gnds sw1 10k refio cnvst doutref gnd ovdd v dd sclk din interfac e and contro l max11166 sw2 configuration register reference mode reference switch state b5 00 1 1 b4 01 0 1 sw2 closedclosed openopen sw1 closed open closed open 01 2 3 downloaded from: http:///
maxim integrated 13 max11166 16-bit, 500ksps, 5v sar adc with internal reference in tdfn www.maximintegrated.com overvoltage input clamps the max11166 includes an input clamping circuit that activates when the input voltage at ain+ is above (v dd + 300mv) or below -(v dd + 300mv). the clamp circuit remains high impedance while the input signal is within the range of q (v dd + 100mv) and draws little to no cur - rent. however, when the input signal exceeds this range the clamps begin to turn on. consequently, to obtain the highest accuracy, ensure that the input voltage does not exceed the range of q (v dd + 100mv). to make use of the input clamps, connect a resistor (r s ) between the ain+ input and the voltage source to limit the voltage at the analog input and to ensure the fault current into the devices does not exceed q 20ma. note that the voltage at the ain+ input pin limits to approximately 7v during a fault condition so the following equation can be used to calculate the value of r s : max fault s v 7v r 20ma ? = where v fault max is the maximum voltage that the source produces during a fault condition. figure 1 and figure 2 illustrate the clamp circuit volt - age current characteristics for a source impedance r s = 1280 i . while the input voltage is within the q (v dd + 300mv) range, no current flows in the input clamps. once the input voltage goes beyond this voltage range, the clamps turn on and limit the voltage at the input pin. internal/external reference (refio) coniguration the max11166 includes a standard spi interface that selects internal or external reference modes of opera - tion through an input configuration register (see the input configuration interface section). the max11166 features an internal bandgap reference circuit (v refio = 4.096v) that is buffered with an internal reference buffer that drives the ref pin. the max11166 configure regis - ter allows four combinations of reference configuration. these reference mode are: reference mode 00: adc reference is provided by the internal bandgap feed out the refio pin, noise filtered with an external capacitor on the refio pin, then buff - ered by the internal reference buffer and decoupled with an external capacitor on the ref pin. in this mode the adc requires no external reference source. reference mode 01: adc reference is provided exter - nally and feeds into the refio pin, buffered with the internal reference buffer and decoupled with an external capacitor on the ref pin. this mode is typically used when a common reference source is needed for more than one max11166. reference mode 10: the internal bandgap is used as a reference source output and feed out the refio pin. however, the internal reference buffer is in a shutdown state and the ref pin is high impedance. this state would typically be used to provide a common reference source to a set of external reference buffers for several max11166. figure 1. input clamp characteristics figure 2. input clamp characteristics (zoom in) max11166 input clamp characteristics signal voltage at source and ain+ input (v) i clamp (ma) 30 20 0 10 -20 -10 -30 -20 -15 -10 -5 0 5 10 15 20 25 -25 -40 40 r s = 1280 i v dd = 5.0v ain+ pin input source max11166 input clamp characteristics signal voltage at source and ain+ input (v) i clamp (ma) 5 0 -5 -15 -5 5 15 25 -25 -10 10 r s = 1280 i v dd = 5.0v ain+ pin input source downloaded from: http:///
maxim integrated 14 max11166 16-bit, 500ksps, 5v sar adc with internal reference in tdfn www.maximintegrated.com reference mode 11: the internal bandgap reference source as well as the internal reference buffer are both in a shutdown state. the ref pin is in a high-impedance state. this mode would typically be used when an exter - nal reference source and external reference buffer is used to drive all max11166 parts in a system. regardless of the reference mode used, the max11166 requires a low-impedance reference source on the ref pin to support 16-bit accuracy. when using the internal reference buffer, externally bypass the reference buffer output using at least a 10 f f, low-inductance, low-esr capacitor placed as close as possible to the ref pin, thus minimizing additional pcb inductance. when using the internal bandgap reference source, bypass the refio pin with a 0.1 f f capacitor to ground. if providing an external reference and using the internal reference buffer, drive the refio pin directly with an external reference source in the range of 3.0v to 4.25v. finally, if disabling the max11166 internal bandgap reference source and inter - nal reference buffer, drive the ref pin with a reference voltage in the range of 2.5v to 4.25v and place at least a 10 f f, low-inductance, low-esr capacitor placed as close as possible to the ref pin . when using the max11166 in external reference mode, it is recommended that an external reference buffer be used. for bypass capacitors on the ref pin, x7r or x5r ceramic capacitors in a 1210 case size or smaller have been found to provide adequate bypass performance. y5u or z5u ceramics capacitors are not recommended due to their high voltage and temperature coefficients. maxim integrated offers a wide range of precision refer - ences ideal for 16-bit accuracy. table 1 lists some of the options recommended. input ampliier the conversion results are accurate when the adc acquires the input signal for an interval longer than the input signal's worst-case settling time. the adc input sampling capacitor charges during the acquisition period. during this acquisition period, the settling of the sampled voltage is affected by the source resistance and the input sampling capacitance. sampling error can be estimated by modeling the time constant of the total input capaci - tance and the driving source impedance. although the max11166 is easy to drive, an amplifier buf - fer is recommended if the source impedance is such that when driving a switch capacitor of ~20pf a significant settling error in the desired sampling period will occur. if this is the case, it is recommended that a configuration shown in the typical operating circuit is used where at least a 500pf capacitor is attached to the ain+ pin. this capacitance reduces the size of the transient at the start of the acquisition period, which in some buffers will cause an input signal dependent offsets. regardless of whether an external buffer amp is used or not, the time constant, r source c load , of the input should not exceed t acq /12, where r source is the total signal source impedance, c load is the total capacitance at the adc input (external and internal) and t acq is the acquisition period. thus to obtain accurate sampling in a 500ns acquisition time a source impedance of less than 1042 should be used if driving the adc directly. when driving the adc from a buffer, it is recommended a series resistance (5 to 50 typical) between the amplifier and the external input capacitance as shown in the typical operating circuit . 1) fast settling time: for multichannel multiplexed appli - cations the driving operational amplifier must be able to settle to 16-bit resolution when a full-scale step is applied during the minimum acquisition time. 2) low noise: it is important to ensure that the driver amplifier has a low average noise density appropriate for the desired bandwidth of the application. when the max11166 is used with its full bandwidth of 6mhz, it is preferable to use an amplifier that will produce an output noise spectral density of less than 6nv/ hz , to ensure that the overall snr is not degraded signifi - cantly. it is recommended to insert an external rc filter table 1. max11166 external reference recommendations part v out (v) temperature coefficient (max) initial accuracy (%) noise (0.1hz to 10hz) (v p-p ) package max6126 2.5, 3, 4.096, 5.0 3 (a), 5 (b) 0.06 1.35 max-8 so-8 max6325max6341 max6350 2.5, 4.096, 5.0 1 0.04, 0.02 1.5, 2.4, 3.0 so-8 downloaded from: http:///
maxim integrated 15 max11166 16-bit, 500ksps, 5v sar adc with internal reference in tdfn www.maximintegrated.com at the max11166 ain+ input to attenuate out-of-band input noise and preserve the adcs snr. the effec - tive rms noise at the max11166 ain+ input is 64 f v, thus additional noise from a buffer circuit should be significantly lower in order to achieve the maximum snr performance. 3) thd performance: the input buffer amplifier used should have a comparable thd performance with that of the max11166 to ensure the thd of the digitized signal is not degraded. table 2 summarizes the operational amplifiers that are compatible with the max11166. the max9632 has suf - ficient bandwidth, low enough noise and distortion to sup - port the full performance of the max11166. the max9633 is a dual amp and can support buffering for true pseudo- differential sampling. transfer function the ideal transfer characteristic for the max11166 is shown in figure 3 . the precise location of various points on the transfer function are given in table 3 . table 2. list of recommended adc driver op amps for max11166 figure 3. bipolar transfer function table 3. transfer function example amplifier input-noise density (nv/ hz ) small-signal bandwidth (mhz) slew rate (v/s) thd (db) i cc (ma) comments max9632 0.9 55 30 -128 3.9 low noise, thd at 10khz max9633 3 27 18 -130 3.5/amp low noise, dual amp, thd at 10khz code transition bipolar input (v) digital output code (hex) +fs - 1.5 lsb +4.999771 fffe - ffff midscale + 0.5 lsb +0.000076 8000 - 8001 midscale 0 8000 midscale - 0.5 lsb -0.000076 7fff - 8000 -fs + 0.5 lsb -4.999924 0000 - 0001 -fs ffff 8001 8000 0000 0001 7ffe outputcode (hex) input vol ta ge (lsb) 7fff 0 full-scale transition -fs fffe -fs + 0.5 lsb +fs - 1.5 lsb +fs = 5 x v ref 4.096 lsb = +fs - (-fs) 65536 -fs = -5 x v ref 4.096 downloaded from: http:///
maxim integrated 16 max11166 16-bit, 500ksps, 5v sar adc with internal reference in tdfn www.maximintegrated.com input coniguration interfacean spi interface clocked at up to 50mhz controls the max11166. input configuration data is clocked into the configuration register on the falling edge of sclk through the din pin. the data on din is used to program the adc configuration register. the construct of this register is illustrated in table 4 . the configuration register defines the output interface mode, the reference mode, and the power-down state of the max11166. coniguring in cs mode figure 4 details the timing for loading the input configura - tion register when the max11166 is connected in cs mode (see figure 6 and figure 8 for hardware connections). the load process is enabled on the falling edge of cnvst when sclk is held high. the configuration data is clocked into the configuration register through din on the next 8 sclk falling edges. pull cnvst high to complete the input configuration register load process. din should idle high outside an input configuration register read. table 4. adc configuration register figure 4. input configuration timing in cs mode bit name bit default state logic state function mode 7:6 00 00 cs mode, no-busy indicator 01 cs mode, with busy indicator 10 daisy-chain mode, no-busy indicator 11 daisy-chain mode, with busy indicator ref 5:4 00 00 reference mode 0. internal reference and reference buffer are both powered on. 01 reference mode 1. internal reference is turned off, but internal reference buffer powered on. apply the external reference voltage at refio. 10 reference mode 2. internal reference is powered on, but the internal reference buffer is powered off. this mode allows for internal reference to be used with an external reference buffer. 11 reference mode 3. internal reference and reference buffer are both powered off. apply an external reference voltage at ref. shdn 3 0 0 normal mode. all circuitry is fully powered up at all times. 1 static shutdown. all circuitry is powered down. reserved 2:0 0 0 reserved, set to 0 01234 56 7 t hsckcnf t ssckcnf cnvst sclk din t hdinsck t sdinsck b6 b5 b4 b3 b2 b1 b0 b7 downloaded from: http:///
maxim integrated 17 max11166 16-bit, 500ksps, 5v sar adc with internal reference in tdfn www.maximintegrated.com coniguring in daisy-chain mode figure 5 details the configuration register load process when the max11166 is connected in a daisy-chain con - figuration (see figure 12 and figure 14 for hardware con - nections). the load process is enabled on the falling edge of cnvst when sclk is held high. in daisy-chain mode, the input configuration registers are chained together through dout to din. device as dout will drive device bs din. the input configuration register is an 8-bit, first- in first-out shift register. the configuration data is clocked in n times through 8 o n falling sclk edges. after the max11166 adcs in the chain are loaded with the configu - ration byte, pull cnvst high to complete the configuration register loading process. figure 5 illustrates a configura - tion sequence for loading two devices in a chain. data loaded into the configuration register alters the state of the max11166 on the next conversion cycle after the regis - ter is loaded. however, powering up the internal reference buffer or stabilizing the refio pin voltage will take several milliseconds to settle to 16-bit accuracy. shutdown mode the shdn bit in the configuration register forces the max11166 into and out of shutdown. set shdn to 0 for normal operation. set shdn to 1 to shut down all internal circuitry and reset all registers to their default state. output interface the max11166 can be programmed into one of four out - put modes; cs modes with and without busy indicator and daisy-chain modes with and without busy indicator. when operating without busy indication, the user must exter - nally timeout the maximum adc conversion time before commencing readback. when operating in one of the two busy indication modes, the user can connect the dout output of the max11166 to an interrupt input on the digital host and use this interrupt to trigger the output data read. regardless of the output interface mode used, digital activity should be limited to the first half of the conversion phase. having sclk or din transitions near the sampling instance can also corrupt the input sample accuracy. therefore, keep the digital inputs quiet for approximately 25ns before and 10ns after the rising edge of cnvst. these times are denoted as t sq and t hq in all subse - quent timing diagrams. in all interface modes, the data on dout is valid on both sclk edges. however, the input setup time into the receiving digital host will be maximized when data is clocked into that digital host on the falling sclk edge. doing so will allow for higher data transfer rates between the max11166 and the digital host and consequently higher converter throughput. in all interface modes, it is recommended that the sclk be idled low to avoid triggering an input configuration write figure 5. input configuration timing in daisy-chain mode b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 t hsckcnf t sdinsck t hdinsck da ta loaded to pa rt b shifted through pa rt a da ta loaded to pa rt a t ssckcnf cnvst 01 23456701 234567 sclk din downloaded from: http:///
maxim integrated 18 max11166 16-bit, 500ksps, 5v sar adc with internal reference in tdfn www.maximintegrated.com on the falling edge of cnvst. if at anytime the device detects a high sclk state on a falling edge of cnvst, it will enter the input configuration write mode and will write the state of din on the next 8 falling sclk edges to the input configuration register. in all interface modes, all data bits from a previous con - version must be read before reading bits from a new conversion. when reading out conversion data, if too few sclk falling edges are provided and all data bits are not read out, only the remaining unread data bits will be outputted during the next readout cycle. in such an event, the output data in every other readout cycle will appear to have been truncated as only the leftover bits from the previous readout cycle are outputted. this is an indication to the user that there are insufficient sclk falling edges in a given readout cycle. table 5 provides a guide to aid in the selection of the appropriate output interface mode for a given application. cs no-busy indicator mode the cs no-busy indicator mode is ideally suited for maximum throughput when a single max11166 is con - nected to a spi-compatible digital host. the connection diagram is shown in figure 6 , and the corresponding timing is provided in figure 7 . a rising edge on cnvst completes the acquisition, initi - ates the conversion, and forces dout to high impedance. the conversion continues to completion irrespective of the state of cnvst allowing cnvst to be used as a select line for other devices on the board. if cnvst is brought low during a conversion and held low throughout the maximum conversion time, the msb will be output at the end of the conversion. when the conversion is complete, the max11166 enters the acquisition phase. drive cnvst low to out - put the msb onto dout. the remaining data bits are then clocked by subsequent sclk falling edges. dout returns to high impedance after the 16th sclk falling edge, or when cnvst goes high. table 5. adc output interface mode selector guide figure 6. cs no-busy indicator mode connection diagram mode typical application and benefits cs mode, no-busy indicator single or multiple adcs connected to spi- compatible digital host. ideally suited for maximum throughput. cs mode, with busy indicator single adc connected to spi-compatible digital host with interrupt input. ideally suited for maximum throughput. daisy-chain mode, no-busy indicator multiple adcs connected to a spi- compatible digital host. ideally suited for multichannel simultaneous sampled isolated applications. daisy-chain mode, with busy indicator multiple adcs connected to a spi- compatible digital host with interrupt input. ideally suited for multichannel simultaneous sampled isolated applications. clk da ta in digi ta l host convert config dout sclk cnvst din max1 11 66 downloaded from: http:///
maxim integrated 19 max11166 16-bit, 500ksps, 5v sar adc with internal reference in tdfn www.maximintegrated.com figure 7. cs no busy indicator mode timing figure 8. cs with busy indicator mode connection diagram cs with busy indicator mode the cs with busy indicator mode is shown in figure 8 where a single adc is connected to a spi-compatible digital host with interrupt input. the corresponding timing is given in figure 9 . a rising edge on cnvst completes the acquisition, initi - ates the conversion and forces dout to high impedance. the conversion continues to completion irrespective of the state of cnvst allowing cnvst to be used as a select line for other devices on the board. t conv t acq din acquisition sclk dout conversion acquisition 12 31 41 51 6 t ddo t en t sclkh t sclkl t hsckcn f t ssckcnf d15 d14 d13 d1 d0 cnvst t cnvpw t cyc t sclk t dis clk da ta in irq ovdd 10k digi ta l host convert config dout sclk cnvst din max1 11 66 downloaded from: http:///
maxim integrated 20 max11166 16-bit, 500ksps, 5v sar adc with internal reference in tdfn www.maximintegrated.com figure 9. cs with busy indicator mode timing when the conversion is complete, dout transitions from high impedance to a low logic level, signaling to the digital host through the interrupt input that data readback can commence. the max11166 then enters the acquisition phase. the data bits are then clocked out, msb first, by subsequent sclk falling edges. dout returns to high impedance after the 17th sclk falling edge or when cnvst goes high, and is then pulled to ovdd through the external pullup resistor. t cnvpw d14 d15 busy bit dout sclk acquisition acquisition conversion din cnvst d13 d1 d0 12 34 15 16 17 t conv t acq t cyc t sclkl t sclk t ddo t sclkh t dis t hsckcnf t ssckcnf downloaded from: http:///
maxim integrated 21 max11166 16-bit, 500ksps, 5v sar adc with internal reference in tdfn www.maximintegrated.com multichannel cs coniguration, asynchronous or simultaneous sampling the multichannel cs configuration is generally used when multiple max11166 adcs are connected to an spi- compatible digital host. figure 10 shows the connection diagram example using two max11166 devices. figure 11 shows the corresponding timing. asynchronous or simultaneous sampling is possible by controlling the cs1 and cs2 edges. in figure 10 , the dout bus is shared with the digital host limiting the throughput rate. however, maximum throughput is possible if the host accommodates each adcs dout pin independently. a rising edge on cnvst completes the acquisition, initiates the conversion and forces dout to high impedance. the conversion continues to completion irrespective of the state of cnvst allowing cnvst to be used as a select line for other devices on the board. however, cnvst must be returned high before the minimum conversion time for proper operation so that another conversion is not initiated with insufficient acquisition time and data correctly read out of the device. when the conversion is complete, the max11166 enters the acquisition phase. each adc result can be read by bringing its cnvst input low, which consequently outputs the msb onto dout. the remaining data bits are then clocked by subsequent sclk falling edges. for each device, its dout will return to a high-impedance state after the 16 th sclk falling edge or when cnvst goes high. this control allows multiple devices to share the same dout bus. figure 10. multichannel cs configuration diagram max11166 max11166 clk da ta in digi ta l host cs2cs1 config dout sclk device b cnvst sclk device a cnvst din dout din downloaded from: http:///
maxim integrated 22 max11166 16-bit, 500ksps, 5v sar adc with internal reference in tdfn www.maximintegrated.com figure 11. multichannel cs configuration timing daisy-chain, no-busy indicator mode the daisy-chain mode with no-busy indicator is ideally suited for multichannel isolated applications that require minimal wiring complexity. simultaneous sampling of multiple adc channels is realized on the serial inter - face where data readback is analogous to clocking a shift register. figure 12 shows a connection diagram of two max11166s configured in a daisy chain. the corre - sponding timing is given in figure 13 . a rising edge on cnvst completes the acquisition and initiates the conversion. once a conversion is initiated, it continues to completion irrespective of the state of cnvst. when a conversion is complete, the msb is presented onto dout and the max11166 returns to the acquisition phase. the remaining data bits are stored within an internal shift register. to read these bits out, cnvst is brought low and each bit is shifted out on sub - sequent sclk falling edge. the din input of each adc in the chain is used to transfer conversion data from the previous adc into the internal shift register of the next adc, thus allowing for data to be clocked through the multichip chain on each sclk falling edge. each adc in the chain outputs its msb data first requiring 16 n clocks to read back n adcs. in daisy-chain mode, the maximum conversion rate is reduced due to the increased readback time. for instance, with a 6ns or less digital host setup time and 3v interface, up to four max11166 devices running at a conversion rate of 324ksps can be daisy-chained. daisy-chain with busy indicator mode the daisy-chain mode with busy indicator is ideally suited for multichannel isolated applications that require minimal wiring complexity while providing a conversion complete indication that can be used to interrupt a host processor to read data. simultaneous sampling of multiple adc channels is real - ized on the serial interface where data readback is analo - gous to clocking a shift register. the daisy-chain mode with busy indicator is shown in figure 14 where three max11166s are connected to a spi-compatible digital host with corresponding timing given in figure 15 . a rising edge on cnvst completes the acquisition and initiates the conversion. once a conversion is initiated, it cnvsta(cs1)cnvstb(cs2) 12 31 51 6 t conv conversion acquisition t cyc d15 d14 d13 d1 d0 t sclkl t sclkh t en t dis t ddo t sclk dout acquisition sclk d15 d14 d1 d0 32 17 18 31 t en d13 19 t dis t cnvpw t cnvpw din t acq t hsckcnf t ssckcnf downloaded from: http:///
maxim integrated 23 max11166 16-bit, 500ksps, 5v sar adc with internal reference in tdfn www.maximintegrated.com figure 13. daisy-chain, no-busy indicator mode timing figure 12. daisy-chain, no-busy indicator mode connection diagram continues to completion irrespective of the state of cnvst. when a conversion is complete, the busy indica tor is pre - sented onto each dout and the max11166 returns to the acquisition phase. the busy indicator for the last adc in the chain can be connected to an interrupt input on the digital host. the digital host should insert a 50ns delay from the receipt of this interrupt before reading out data from all adcs to ensure that all devices in the chain have completed conversion. the conversion data is stored within an internal shift reg - ister. to read these bits out, cnvst is brought low and each bit is shifted out on subsequent sclk falling edge. the din input of each adc in the chain is used to transfer conversion data from the previous adc into the internal shift register of the next adc, thus allowing for data to be clocked through the multichip chain on each sclk falling edge. the total of number of falling sclks needed to read back all data from n adcs is 16 n + 1 edges, the one additional sclk falling edge required to clock out the busy mode bit from the host side adc. max11166 max11166 clk da ta in digi ta l host config convert sclk device b cnvst sclk device a cnvst dout d b din din dout d a sclk 12 31 51 6 cnvst t conv conversion acquisition acquisition t acq t sclk t sclkl t sclkh t ddo 30 31 32 17 18 dout b d b 15 d b 14 d b 13 d b 1d b 0d a 15 d a 14 d a 1d a 0 t cnvpw din t cyc 14 t hsckcnf t ssckcn f downloaded from: http:///
maxim integrated 24 max11166 16-bit, 500ksps, 5v sar adc with internal reference in tdfn www.maximintegrated.com figure 15. daisy-chain mode with busy indicator timing figure 14. daisy-chain mode with busy indicator connection diagram max1 11 66 max11166 clk da ta in irq digi ta l host config convert sclk device c cnvst sclk device b cnvst dout d c din din dout d b max11166 sclk device a cnvst din dout d a t conv acquisition conversion dout a = din b dout b = din c dout c cnvst din sclk acquisition t cnvpw t acq t sclk t sclkh 12 34 15 16 17 18 19 31 32 33 34 35 47 48 49 t sclkl t ddo t cyc busy bi t busy bi t busy bi t d a 15 d b 15 d c 15 d c 14 d c 13 d a 14 d a 13 d b 14 d b 13 d a 1 d b 1 d c 1 d a 0 d b 0 d c 0 d a 15 d b 15 d a 14 d b 14 d a 1 d a 15 d a 14 d a 1d a 10 d a 0 d b 1d b 0 t hsckcnf t ssckcnf downloaded from: http:///
maxim integrated 25 max11166 16-bit, 500ksps, 5v sar adc with internal reference in tdfn www.maximintegrated.com in daisy-chain mode, the maximum conversion rate is reduced due to the increased readback time. for instance, with a 6ns or less digital host setup time and 3v interface, up to four max11166 devices running at a conversion rate of 322ksps can be daisy-chained on a 3-wire port. layout, grounding, and bypassing for best performance, use pcbs with ground planes. ensure that digital and analog signal lines are separated from each other. do not run analog and digital lines parallel to one another (especially clock lines), and avoid running digital lines underneath the adc package. a single solid gnd plane configuration with digital signals routed from one direction and analog signals from the other provides the best performance. connect the gnd and agnds pins on the max11166 to this ground plane. keep the ground return to the power-supply low impedance and as short as possible for noise-free operation. a 4.7nf c0g (or npo) ceramic chip capacitor should be placed between ain+ and the ground plane as close as possible to the max11166. this capacitor reduces the inductance seen by the sampling circuitry and reduces the voltage transient seen by the input source circuit. for best performance, connect the ref output to the ground plane with a 16v, 10 f f ceramic chip capacitor with a x5r or x7r dielectric in a 1210 or smaller case size. ensure that all bypass capacitors are connected directly into the ground plane with an independent via. bypass v dd and ovdd to the ground plane with 0.1 f f ceramic chip capacitors on each pin as close as pos - sible to the device to minimize parasitic inductance. add at least one bulk 10 f f decoupling capacitor to v dd and ovdd per pcb. for best performance, bring a v dd power plane in on the analog interface side of the max11166 and a ovdd power plane from the digital interface side of the device. deinitions integral nonlinearity integral nonlinearity (inl) is the deviation of the values on an actual transfer function from a straight line. for these devices, this straight line is a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. differential nonlinearity differential nonlinearity (dnl) is the difference between an actual step width and the ideal value of 1 lsb. for these devices, the dnl of each digital output code is measured and the worst-case value is reported in the electrical characteristics table. a dnl error specification of less than q 1 lsb guarantees no missing codes and a monotonic transfer function.offset error for the max11166, the offset error is defined at code center 0x8000. this code center should occur at 0v input between ain+ and ain-. the offset error is the actual volt - age required to produce code center 0x8000, expressed in lsb. gain error gain error is defined as the difference between the actual change in analog input voltage required to produce a top code transition minus a bottom code transition, and the ideal change in analog input voltage range to produce the same code transitions. it is expressed in lsb. signal-to-noise ratio for a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (snr) is the ratio of the full-scale analog input (rms value) to the rms quantiza - tion error (residual error). the ideal, theoretical minimum analog-to-digital noise is caused by quantization noise error only and results directly from the adcs resolution (n bits): snr = (6.02 x n + 1.76)db where n = 16 bits. in reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. snr is computed by taking the ratio of the rms signal to the rms noise, which includes all spectral components not including the fundamental, the first five harmonics, and the dc offset. signal-to-noise plus distortion signal-to-noise plus distortion (sinad) is the ratio of the fundamental input frequencys rms amplitude to the rms equivalent of all the other adc output signals: rms rms signal sinad(db) 20 log (noise distortion) ???? = + ???? downloaded from: http:///
maxim integrated 26 max11166 16-bit, 500ksps, 5v sar adc with internal reference in tdfn www.maximintegrated.com effective number of bits the effective number of bits (enob) indicates the global accuracy of an adc at a specific input frequency and sampling rate. an ideal adcs error consists of quantiza - tion noise only. with an input range equal to the full-scale range of the adc, calculate the enob as follows: sinad 1.76 enob 6.02 ? = total harmonic distortion total harmonic distortion (thd) is the ratio of the power contained in the first five harmonics of the converted data to the power of the fundamental. this is expressed as: 2345 1 pppp thd 10 log p +++ ???? = ???? where p1 is the fundamental power and p2 through p5 is the power of the 2nd- through 5th-order harmonics.. spurious-free dynamic range spurious-free dynamic range (sfdr) is the ratio of the rms amplitude of the fundamental (maximum signal component) to the rms value of the next-largest fre - quency component. aperture delayaperture delay (t ad ) is the time delay from the sampling clock edge to the instant when an actual sample is taken. aperture jitter aperture jitter (t aj ) is the sample-to-sample variation in aperture delay. small-signal bandwidth a small -20dbfs analog input signal is applied to an adc in a manner that ensures that the signals slew rate does not limit the adcs performance. the input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased 3db. full-power bandwidth a large -0.5dbfs analog input signal is applied to an adc, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by 3db. this point is defined as full-power input bandwidth frequency. downloaded from: http:///
maxim integrated 27 max11166 16-bit, 500ksps, 5v sar adc with internal reference in tdfn www.maximintegrated.com selector guide package information for the latest package outline information and land patterns (foot - prints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. ordering information +denotes a lead(pb)-free/rohs-compliant package. t = tape and reel. *ep = exposed pad. package type package code outline no. land pattern no. 12 tdfn-ep td1233+1 21-0664 90-0397 part bits input range (v) reference package speed (ksps) max11262 14 0 to 5 external 3mm x 5mm max-10 500 max11160 16 0 to 5 internal 3mm x 5mm max-10 500 max11161 16 0 to 5 internal 3mm x 5mm max-10 250 max11162 16 0 to 5 external 3mm x 5mm max-10 500 max11163 16 0 to 5 external 3mm x 5mm max-10 250 max11164 16 0 to 5 internal/external 3mm x 3mm tdfn-12 500 max11165 16 0 to 5 internal/external 3mm x 3mm tdfn-12 250 max11166 16 5 internal/external 3mm x 3mm tdfn-12 500 max11167 16 5 internal/external 3mm x 3mm tdfn-12 250 max11168 16 5 internal 3mm x 5mm max-10 500 max11169 16 5 internal 3mm x 5mm max-10 250 max11150 18 0 to 5 internal 3mm x 5mm max-10 500 max11152 18 0 to 5 external 3mm x 5mm max-10 500 max11154 18 0 to 5 internal/external 3mm x 3mm tdfn-12 500 max11156 18 5 internal/external 3mm x 3mm tdfn-12 500 max11158 18 5 internal 3mm x 5mm max-10 500 part temp range pin-package max11166etc+t -40c to +85c 12 tdfn-ep* downloaded from: http:///
maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and speciications without n otice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. ? 2015 maxim integrated products, inc. 28 max11166 16-bit, 500ksps, 5v sar adc with internal reference in tdfn revision history revision number revision date description pages changed 0 7/15 initial release for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maximintegrated.com. downloaded from: http:///

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