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| an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. lm5165 snvsa47a ? march 2016 ? revised march 2016 lm5165 3-v to 65-v input, 150-ma synchronous buck converter with ultra-low i q 1 1 features 1 ? wide input voltage range of 3 v to 65 v ? fixed (3.3 v, 5 v) or adjustable output voltages ? maximum output current as high as 150 ma ? 10.5- a no load quiescent current ? ? 40 c to 150 c junction temperature range ? selectable pfm or cot mode operation ? switching frequency as high as 600 khz ? diode emulation mode and pulse skipping for ultra-high light-load efficiency performance ? integrated 2- pmos buck switch ? supports 100% duty cycle for low dropout ? integrated 1- nmos synchronous rectifier ? eliminates external rectifier diode ? programmable current limit setpoint (4 levels) ? 1.223-v internal voltage reference ? 900- s internal or programmable soft start ? monotonic startup into pre-biased output ? no loop compensation or bootstrap components ? precision enable/input uvlo with hysteresis ? open-drain power good indicator ? active slew rate control for low emi ? thermal shutdown protection with hysteresis ? 10-lead, 3-mm x 3-mm vson package 2 applications ? 4 ? 20 ma loop-powered sensors ? automotive and battery-powered equipment ? high-voltage ldo replacement ? industrial control systems ? general purpose bias supplies 3 description the lm5165 is a compact, easy-to-use, 3-v to 65-v, ultra-low i q synchronous buck converter with high efficiency over wide input voltage and load current ranges. with integrated high-side and low-side power mosfets, up to 150-ma of output current can be delivered at fixed output voltages of 3.3 v or 5 v, or an adjustable output. the converter is designed to simplify implementation while providing options to optimize the performance the target application. pulse frequency modulation (pfm) mode is selected for optimal light-load efficiency or constant on-time (cot) control for nearly constant operating frequency. both control schemes do not require loop compensation while providing excellent line and load transient response and short pwm on-time for large step-down conversion ratios. the high-side p-channel mosfet can operate at 100% duty cycle for lowest dropout voltage and does not require a bootstrap capacitor for gate drive. also, the current limit setpoint is adjustable to optimize inductor selection for a particular output current requirement. selectable/adjustable startup timing options include minimum delay (no soft start), internally fixed (900 s), and externally programmable soft start via an external capacitor. an open-drain pgood indicator can be used for sequencing and output voltage monitoring. the lm5165 is qualified to automotive aec-q100 grade 1 and is available in a vson-10 package with 0.5-mm pin pitch. device information (1) part number package body size (nom) lm5165 vson (10) 3 mm x 3 mm lm5165x lm5165y (1) for all available packages, see the orderable addendum at the end of the datasheet. typical schematic, fixed output typical efficiency, v out = 5 v output current (ma) efficiency (%) 0.1 1 10 3030 30 40 50 60 70 80 90 100 d101 v in = 8v v in = 12v v in = 24v v in = 36v v in = 65v v out = 5v * sw vout ilim vin en hys gnd rt ss pgood lm5165x c out c in 22 f 1 f l f 68 h v in = 3v...65v * v out tracks v in if v in < 5v productfolder sample &buy technical documents tools & software support &community
2 lm5165 snvsa47a ? march 2016 ? revised march 2016 www.ti.com product folder links: lm5165 submit documentation feedback copyright ? 2016, texas instruments incorporated 4 revision history changes from original (february 2016) to revision a page ? product preview to production data release ....................................................................................................................... 1 3 lm5165 www.ti.com snvsa47a ? march 2016 ? revised march 2016 product folder links: lm5165 submit documentation feedback copyright ? 2016, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 4 6 specifications ......................................................... 5 6.1 absolute maximum ratings ...................................... 5 6.2 esd ratings .............................................................. 5 6.3 recommended operating conditions ....................... 6 6.4 thermal information .................................................. 6 6.5 electrical characteristics ........................................... 6 6.6 switching characteristics .......................................... 7 6.7 typical characteristics .............................................. 8 7 detailed description ............................................ 13 7.1 overview ................................................................. 13 7.2 functional block diagram ....................................... 13 7.3 feature description ................................................. 14 7.4 device functional modes ........................................ 20 8 applications and implementation ...................... 21 8.1 application information ............................................ 21 8.2 typical applications ................................................ 21 9 power supply recommendations ...................... 35 10 pcb layout .......................................................... 35 10.1 layout guidelines ................................................. 35 10.2 layout example .................................................... 36 11 device and documentation support ................. 38 11.1 device support .................................................... 38 11.2 documentation support ........................................ 38 11.3 community resources .......................................... 38 11.4 trademarks ........................................................... 38 11.5 electrostatic discharge caution ............................ 38 11.6 glossary ................................................................ 38 12 mechanical, packaging, and orderable information ........................................................... 38 (1) for the most current package and ordering information, see the package option addendum at the end of this document, or refer to the ti website . (2) package drawings, thermal data and symbolization are available at www.ti.com/packaging . device comparison table (1) (2) part number voltage option package quantity LM5165XDRCR 5.0v 3000 lm5165xdrct 250 lm5165ydrcr 3.3v 3000 lm5165ydrct 250 lm5165drcr adjustable 3000 lm5165drct 250 4 lm5165 snvsa47a ? march 2016 ? revised march 2016 www.ti.com product folder links: lm5165 submit documentation feedback copyright ? 2016, texas instruments incorporated (1) p = power, g = ground, i = input, o = output. 5 pin configuration and functions drc package 10-pin vson with exposed thermal pad top view pin functions pin i/o (1) description name no. sw 1 p switching node that is internally connected to the drain of the high-side pmos buck switch and the drain of the low-side nmos synchronous rectifier. connect to the switching side of the power inductor. vin 2 p regulator supply input pin to high-side power mosfet and internal bias rail ldo. connect to input supply and input capacitor c in . path from vin to the input capacitor must be as short as possible. ilim 3 i programming pin for current limit. connecting the appropriate resistor from ilim to gnd selects one of four pre-set current limit options. short ilim to gnd for the maximum current setting. ss 4 i programming pin for the soft-start time. if a 100-k resistor is connected from ss to gnd, the internal soft- start circuit is disabled and the fb comparator reference steps immediately from zero to full value when the regulator is enabled by the en input. if the ss pin is left open, the internal soft-start circuit ramps the fb reference from zero to full value in 900 s. if an appropriate capacitance is connected to the ss pin, the soft-start time can be programmed as required. rt 5 i mode selection and on-time programming pin for constant on-time (cot) control. short rt to gnd to select pfm (pulse frequency modulation) operation. connect a resistor from rt to gnd to program the on- time, which sets the switching frequency for cot. pgood 6 o power good output flag pin. pgood is connected to the drain of an nfet that holds the pin low when either fb or vout is below the regulation target. use a pull-up resistor of 10 k to 100 k to the system voltage rail or vout (no higher than 12 v). en 7 i input pin of the precision enable / uvlo comparator. the converter is enabled when the en voltage is greater than 1.212v. vout/fb 8 i feedback input to voltage regulation loop. the vout pin connects the internal feedback resistor divider to the regulator output voltage for fixed 3.3v and 5v options. the fb pin connects the internal feedback comparator to an external resistor divider for the adjustable output voltage option. the fb comparator reference voltage is nominally 1.223v. hys 9 o drain of an internal nfet that is turned off when the en input is greater than the en threshold. an external resistor from hys to the en pin uvlo resistor divider programs the input uvlo hysteresis voltage. gnd 10 g regulator ground return. pad - p exposed pad. connect to the gnd pin and system ground on pcb. path to c in must be as short as possible. ss ilim rt pgood sw fb gnd en vin hys 1 2 3 45 10 9 8 76 ss ilim rt pgood sw vout gnd en vin hys 1 2 3 45 10 9 8 76 lm5165x, lm5165y fixed output versions lm5165 adjustable output version 5 lm5165 www.ti.com snvsa47a ? march 2016 ? revised march 2016 product folder links: lm5165 submit documentation feedback copyright ? 2016, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions may affect device reliability. (2) if military/aerospace specified devices are required, please contact the texas instruments sales office/distributors for availability and specifications. (3) fixed output versions. (4) adjustable output version. (5) high junction temperatures degrade operating lifetime. operating lifetime is derated for junction temperatures greater than 125 c. 6 specifications 6.1 absolute maximum ratings (1) (2) over the recommended operating junction temperature range of ? 40 c to 150 c (unless otherwise noted). (1) parameter min max unit vin to gnd ? 0.3 68 v en to gnd ? 0.3 vin + 0.3 sw to gnd ? 0.7 vin + 0.3 20-ns transient ? 3 pgood, vout (3) to gnd survives short to automotive battery voltage ? 0.3 16 hys to gnd ? 0.3 7 ilim, ss, rt, fb (4) to gnd ? 0.3 3.6 t j maximum junction temperature (5) ? 40 150 c t stg storage temperature range ? 55 150 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.2 esd ratings value unit v esd electrostatic discharge human body model (hbm), per ansi/esda/jedec js-001, all pins (1) 2000 v charged device model (cdm), per jedec specification jesd22-c101, all pins (2) 500 6 lm5165 snvsa47a ? march 2016 ? revised march 2016 www.ti.com product folder links: lm5165 submit documentation feedback copyright ? 2016, texas instruments incorporated (1) operating ratings are conditions under which the device is intended to be functional. for specifications and test conditions, see electrical characteristics . (2) high junction temperatures degrade operating lifetimes. operating lifetime is derated for junction temperatures greater than 125 c. 6.3 recommended operating conditions (1) over the recommended operating junction temperature range of ? 40 c to 150 c (unless otherwise noted). parameter min nom max unit input voltages vin 3 65 v en ? 0.3 v vin pgood ? 0.3 12 hys ? 0.3 5 output current i out (cot mode) 0 150 ma i out (pfm mode) 0 100 ma temperature operating junction temperature (2) ? 40 150 c (1) for more information about traditional and new thermal metrics, see the ic package thermal metrics application report, spra953 . 6.4 thermal information thermal metric (1) lm5165 unit vson 10 pins r ja junction-to-ambient thermal resistance 47.7 c/w r jc(top) junction-to-case (top) thermal resistance 59.9 r jb junction-to-board thermal resistance 22.1 jt junction-to-top characterization parameter 1.0 jb junction-to-board characterization parameter 22.2 r jc(bot) junction-to-case (bottom) thermal resistance 4.0 (1) all hot and cold limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control. (2) the junction temperature (t j in c) is calculated from the ambient temperature (t a in c) and power dissipation (p d in watts) as follows: t j = t a + (p d ? ja ) where ja (in c/w) is the package thermal impedance provided in the thermal information section. 6.5 electrical characteristics typical values correspond to t j = 25 c. minimum and maximum limits apply over ? 40 c to +125 c junction temperature range. v in = 12 v (unless otherwise noted). (1) (2) parameter test conditions min typ max unit quiescent currents i q-shd vin dc supply current, shutdown v en = 0 v, t a = 25 c 4.6 6.0 a i q-sleep vin dc supply current, no load v fb = 1.5 v, t a = 25 c 10.5 15.0 i q-sleep-vinmax vin dc supply current, no load, vin = 65v v fb = 1.5 v, v vin = 65 v, t a = 25 c 11.0 15.0 i q-active-pfm vin dc supply current, active pfm mode 205 i q-active-cot vin dc supply current, active cot mode, r rt = 107 k 300 power switches r dson1 high-side mosfet r ds(on) i sw = ? 10 ma 2 r dson2 low-side mosfet r ds(on) i sw = 10 ma 1 current limiting i lim1 high-side peak current current threshold ilim shorted to gnd 220 240 264 ma i lim2 r ilim = 24.9 k 155 180 205 i lim3 r ilim = 56.2 k 100 120 145 i lim4 r ilim = 100 k 48 60 75 regulation comparator v vout50 vout 5v dc setpoint lm5165x 4.9 5.0 5.1 v v vout33 vout 3.3v dc setpoint lm5165y 3.23 3.30 3.37 7 lm5165 www.ti.com snvsa47a ? march 2016 ? revised march 2016 product folder links: lm5165 submit documentation feedback copyright ? 2016, texas instruments incorporated electrical characteristics (continued) typical values correspond to t j = 25 c. minimum and maximum limits apply over ? 40 c to +125 c junction temperature range. v in = 12 v (unless otherwise noted). (1) (2) parameter test conditions min typ max unit i vout vout pin input current v vout = 5 v, lm5165x 6.7 a v vout = 3.3 v, lm5165y 3.9 v ref1 lower fb regulation threshold (pfm, cot) adjustable output version 1.205 1.223 1.241 v v ref2 upper fb regulation threshold (pfm) 1.220 1.233 1.246 fb hys-pfm fb comparator pfm hysteresis pfm mode 10 mv fb hys-cot fb comparator dropout hysteresis cot mode 4 i fb fb pin input bias current v fb = 1 v 100 na fb line-reg fb threshold variation over line v vin = 3 v to 65 v 0.001 %/v vout line-reg vout threshold variation over line lm5165x, v vin = 6 v to 65 v lm5165y, v vin = 4.5 v to 65 v 0.001 power good uvt rising pgood comparator fb voltage rising, relative to v ref1 94% uvt falling fb voltage falling, relative to v ref1 87% r pgood pgood on-resistance v fb = 1 v 80 200 v inmin-pgood minimum vin for valid pgood vin falling, i pgood = 0.1 ma, v pgood < 0.5 v 1.20 1.65 v i pgood pgood off-state leakage current v fb = 1.2 v, v pgood = 5.5 v 10 100 na enable / uvlo v in-on turn-on threshold vin voltage rising 2.60 2.75 2.95 v v in-off turn-off threshold vin voltage falling 2.35 2.45 2.60 v v en-on enable turn-on threshold en voltage rising 1.163 1.212 1.262 v v en-off enable turn-off threshold en voltage falling 1.109 1.144 1.178 v v en-hys enable hysteresis 68 mv v en-sd en shutdown threshold en voltage falling 0.3 0.6 v r hys hys on-resistance v en = 1 v 80 200 i hys hys off-state leakage current v en = 1.5 v, v hys = 5.5 v 10 100 na soft-start i ss soft-start charging current v ss = 1 v 10 a t ss-int soft-start rise time ss floating 900 s thermal shutdown t j-sd thermal shutdown threshold 170 c t j-sd-hys thermal shutdown hysteresis 10 6.6 switching characteristics over operating free-air temperature range (unless otherwise noted) parameter test conditions min typ max unit t on-min minimum controllable pwm on-time 180 ns t on1 pwm on-time 16 k from rt to gnd 250 ns t on2 pwm on-time 75 k from rt to gnd 1000 ns 8 lm5165 snvsa47a ? march 2016 ? revised march 2016 www.ti.com product folder links: lm5165 submit documentation feedback copyright ? 2016, texas instruments incorporated 6.7 typical characteristics unless otherwise specified, v in = 12 v, v out = 5 v. please refer to the typical applications section for circuit designs. 5-v, 25-ma design l f = 470 h c out = 47 f f sw(nom) = 100 khz r ilim 100 k figure 1. converter efficiency: 5 v, 25 ma, pfm see schematic, figure 37 l f = 220 h c out = 22 f f sw(nom) = 230 khz r rt = 133 k figure 2. converter efficiency: 5 v, 150 ma, cot see schematic, figure 50 l f = 47 h c out = 10 f f sw(nom) = 350 khz r ilim = 56.2 k figure 3. converter efficiency: 3.3 v, 50 ma, pfm see schematic, figure 62 l f = 150 h c out = 22 f f sw(nom) = 160 khz r rt = 121 k figure 4. converter efficiency: 3.3 v, 150 ma, cot see schematic, figure 57 l f = 47 h c out = 10 f f sw(nom) = 500 khz r ilim = 24.9 k figure 5. converter efficiency: 12 v, 75 ma, pfm see schematic, figure 65 l f = 150 h c out = 10 f f sw(nom) = 600 khz r rt = 143 k figure 6. converter efficiency: 15 v, 150 ma, cot output current (ma) efficiency (%) 0.1 1 10 50 30 40 50 60 70 80 90 100 d103 v in = 8v v in = 12v v in = 24v v in = 36v v in = 65v output current (ma) efficiency (%) 0.1 1 10 100 150 30 40 50 60 70 80 90 100 d104 v in = 8v v in = 12v v in = 24v v in = 36v v in = 65v output current (ma) efficiency (%) 0.1 1 10 100 150 30 40 50 60 70 80 90 100 d102 v in = 8v v in = 12v v in = 24v v in = 36v v in = 65v output current (ma) efficiency (%) 0.1 1 10 3030 30 40 50 60 70 80 90 100 d101 v in = 8v v in = 12v v in = 24v v in = 36v v in = 65v output current (ma) efficiency (%) 0.1 1 10 75 30 40 50 60 70 80 90 100 d105 v in = 18v v in = 24v v in = 36v v in = 48v v in = 65v output current (ma) efficiency (%) 0.1 1 10 100 150 30 40 50 60 70 80 90 100 d106 v in = 24v v in = 36v v in = 48v v in = 65v 9 lm5165 www.ti.com snvsa47a ? march 2016 ? revised march 2016 product folder links: lm5165 submit documentation feedback copyright ? 2016, texas instruments incorporated typical characteristics (continued) unless otherwise specified, v in = 12 v, v out = 5 v. please refer to the typical applications section for circuit designs. figure 7. high-side mosfet on-state resistance vs input voltage figure 8. low-side mosfet on-state resistance vs input voltage figure 9. enable threshold voltage vs temperature figure 10. feedback comparator voltage vs temperature lm5165x figure 11. vout regulation thresholds vs temperature lm5165y figure 12. vout regulation thresholds vs temperature temperature (c) v out regulation thresholds (v) -50 -25 0 25 50 75 100 125 150 4.9 4.92 4.94 4.96 4.98 5 5.02 5.04 5.06 5.08 d007 rising falling temperature (c) v out regulation thresholds (v) -50 -25 0 25 50 75 100 125 150 3.24 3.26 3.28 3.3 3.32 3.34 3.36 d006 rising falling temperature (c) en thresholds (v) -50 -25 0 25 50 75 100 125 150 1.1 1.12 1.14 1.16 1.18 1.2 1.22 1.24 d004 rising falling temperature (c) fb regulation thresholds (v) -50 -25 0 25 50 75 100 125 150 1.205 1.21 1.215 1.22 1.225 1.23 1.235 1.24 1.245 1.25 d005 rising falling input voltage (v) r dson ( : ) 0 10 20 30 40 50 60 70 0 0.5 1 1.5 2 2.5 3 3.5 4 d001 40c 25c 150c input voltage (v) r dson ( : ) 0 10 20 30 40 50 60 70 0 0.5 1 1.5 2 d002 40c 25c 150c 10 lm5165 snvsa47a ? march 2016 ? revised march 2016 www.ti.com product folder links: lm5165 submit documentation feedback copyright ? 2016, texas instruments incorporated typical characteristics (continued) unless otherwise specified, v in = 12 v, v out = 5 v. please refer to the typical applications section for circuit designs. figure 13. pgood thresholds vs temperature figure 14. peak current limits vs temperature figure 15. peak current limits vs input voltage figure 16. pgood and hys pulldown r ds(on) vs temperature figure 17. cot one-shot timer t on vs input voltage figure 18. internal v in uvlo voltage vs temperature input voltage (v) current limit (ma) 0 10 20 30 40 50 60 70 0 50 100 150 200 250 300 d010 60 ma 120 ma 180 ma 240 ma temperature (c) pull down resistance ( : ) -50 -25 0 25 50 75 100 125 150 25 50 75 100 125 150 d011 temperature (c) pgood thresholds relative to falling fb threshold (%) -50 -25 0 25 50 75 100 125 150 85 86 87 88 89 90 91 92 93 94 95 d008 fb rising fb falling temperature (c) current limit (ma) -50 -25 0 25 50 75 100 125 150 0 50 100 150 200 250 300 d009 60 ma 120 ma 180 ma 240 ma input voltagae (v) one-shot time (s) 0 10 20 30 40 50 60 70 0 0.5 1 1.5 2 2.5 3 3.5 4 d012 rt = 16 k : rt = 75 k : temperature (c) v in uvlo thresholds (v) -50 -25 0 25 50 75 100 125 150 2 2.2 2.4 2.6 2.8 3 d013 rising falling 11 lm5165 www.ti.com snvsa47a ? march 2016 ? revised march 2016 product folder links: lm5165 submit documentation feedback copyright ? 2016, texas instruments incorporated typical characteristics (continued) unless otherwise specified, v in = 12 v, v out = 5 v. please refer to the typical applications section for circuit designs. figure 19. vin sleep and shutdown supply current vs temperature figure 20. vin sleep and shutdown supply current vs input voltage r rt = 75 k figure 21. vin active mode supply current vs temperature r rt = 75 k figure 22. vin active mode supply current vs input voltage 5-v, 150-ma design figure 23. full load switching waveforms, cot 5-v, 150-ma design figure 24. no load switching waveforms, cot v sw 5 v/div v out 100 mv/div i l 200 ma/div 20 ms/div v sw 5 v/div v out 100 mv/div i l 50 ma/div 2 p s/div temperature (c) current ( p a) -50 -25 0 25 50 75 100 125 150 0 50 100 150 200 250 300 350 400 d016 cot pfm input voltage (v) current ( p a) 0 10 20 30 40 50 60 70 0 50 100 150 200 250 300 350 d017 cot pfm temperature (c) current ( p a) -50 -25 0 25 50 75 100 125 150 0 5 10 15 20 d014 sleep shutdown input voltage (v) current ( p a) 0 10 20 30 40 50 60 70 0 2 4 6 8 10 12 d015 sleep shutdown 12 lm5165 snvsa47a ? march 2016 ? revised march 2016 www.ti.com product folder links: lm5165 submit documentation feedback copyright ? 2016, texas instruments incorporated typical characteristics (continued) unless otherwise specified, v in = 12 v, v out = 5 v. please refer to the typical applications section for circuit designs. 5-v, 150-ma design figure 25. full load startup, cot 5-v, 150-ma design figure 26. short circuit, cot 5-v, 25-ma design figure 27. full load switching waveforms, pfm 5-v, 25-ma design figure 28. no load switching waveforms, pfm 5-v, 25-ma design figure 29. full load startup, pfm 5-v, 25-ma design figure 30. short circuit, pfm v sw 10 v/div i l 20 ma/div 100 p s/div v out 100 mv/div v sw 5 v/div i l 20 ma/div 2 ms/div v out 100 mv/div v sw 10 v/div i l 20 ma/div 20 ms/div v in 5 v/div v out 1 v/div i l 100 ma/div 2 ms/div i l 200 ma/div 200 p s/div v sw 10 v/div v out 1 v/div v in 5 v/div i out 50 ma/div 2 ms/div 13 lm5165 www.ti.com snvsa47a ? march 2016 ? revised march 2016 product folder links: lm5165 submit documentation feedback copyright ? 2016, texas instruments incorporated 7 detailed description 7.1 overview the lm5165 converter is an easy-to-use synchronous buck dc/dc regulator that operates from a 3-v to 65-v supply voltage. the device is intended for step-down conversions from 3.3-v, 5-v, 12-v, 24-v, and 48-v unregulated, semi-regulated and fully-regulated supply rails. with integrated high-side and low-side power mosfets, the lm5165 delivers up to 150-ma dc load current with high efficiency and ultra-low input quiescent current in a very small solution size. designed for simple implementation, a choice of operating modes offers flexibility to optimize its usage according to the target application. in constant on-time (cot) mode of operation, ideal for low-noise, high current, fast load transient requirements, the device operates with predictive on-time switching pulse. a quasi-fixed switching frequency over the input voltage range is achieved by using an input voltage feedforward to set the on-time. alternatively, pulse frequency modulation (pfm) mode, complemented by an adjustable peak current limit, achieves exceptional light-load efficiency performance. control loop compensation is not required with either operating mode, reducing design time and external component count. the lm5165 incorporates other features for comprehensive system requirements, including an open-drain power good circuit for power-rail sequencing and fault reporting, internally-fixed or externally-adjustable soft-start, monotonic startup into prebiased loads, precision enable with customizable hysteresis for programmable line undervoltage lockout (uvlo), adjustable cycle-by-cycle current limit for optimal inductor sizing, and thermal shutdown with automatic recovery. these features enable a flexible and easy-to-use platform for a wide range of applications. the pin arrangement is designed for simple pcb layout , requiring only a few external components. 7.2 functional block diagram lm5165 current limit vdd uvlo on-time one shot ldo bias regulator vin feedback enable thermal shutdown vin uvlo zero cross detect vdd zc i-limit adjust control logic vin in out hysteretic mode reference soft-start enable voltage reference 1.223v vin 1.212v 1.144v en hys ilim sw vout/fb rt ss gnd pgood 1.150v 1.064v uv + + + pg r1 (1) r2 (1) note: (1) r1, r2 are implemented in the fixed output voltage ve rsions only. 14 lm5165 snvsa47a ? march 2016 ? revised march 2016 www.ti.com product folder links: lm5165 submit documentation feedback copyright ? 2016, texas instruments incorporated 7.3 feature description 7.3.1 integrated power mosfets the lm5165 is a step-down buck converter with integrated high-side pmos buck switch and low-side nmos synchronous switch. during the high-side mosfet on-time, the sw voltage v sw swings up to approximately v in , and the inductor current increases with slope (v in ? v out )/l f . when the high-side mosfet is turned off by the control logic, the low-side mosfet turns on after an adaptive deadtime. inductor current flows through the low- side mosfet with slope ? v out /l f . duty cycle d is defined as t on /t sw , where t on is the high-side mosfet conduction time and t sw is the switching period. 7.3.2 selectable pfm or cot mode converter operation figure 31 and figure 32 show converter schematics for pfm and cot modes of operation. figure 31. pfm mode converter schematics: (a) fixed output voltage of 5 v or 3.3 v, (b) adjustable output voltage with programmable soft start, current limit and uvlo figure 32. cot mode converter schematics: (a) fixed output voltage of 5 v or 3.3 v, (b) adjustable output voltage with programmable soft start, current limit and uvlo the lm5165 operates in pfm mode when rt is shorted to gnd. configured as such, the lm5165 behaves as a hysteretic voltage regulator operating in boundary conduction mode, controlling the output voltage within upper and lower hysteresis levels according to the pfm feedback comparator hysteresis of 10 mv. figure 33 is a representation of the relevant output voltage and inductor current waveforms. the lm5165 provides the required switching pulses to recharge the output capacitor, followed by a sleep period where most of the internal circuits are shut off. the load current is supported by the output capacitor during this time, and the lm5165 current consumption approaches the sleep quiescent current of 10.5 a. the sleep period duration depends on load current and output capacitance. v in v out sw fb ilim vin en hys gnd rt ss pgood lm5165 l f c out c in c ss r rt r ilim r uv1 r uv2 r hys r fb1 r fb2 v in v out sw vout ilim vin en hys gnd rt ss pgood lm5165x lm5165y l f c in (a) (b) r esr r rt c out r esr v in v out sw fb ilim vin en hys gnd rt ss pgood lm5165 l f c out c in c ss r ilim r uv1 r uv2 r hys r fb1 r fb2 v in v out sw vout ilim vin en hys gnd rt ss pgood lm5165x lm5165y l f c out c in (b) (a) 15 lm5165 www.ti.com snvsa47a ? march 2016 ? revised march 2016 product folder links: lm5165 submit documentation feedback copyright ? 2016, texas instruments incorporated feature description (continued) figure 33. pfm mode sw node voltage, feedback voltage and inductor current waveforms when operating in pfm mode at given input and output voltages, the chosen filter inductance dictates the pfm pulse frequency as (1) where i pk(pfm) corresponds to one of the four programmable levels for peak limit of inductor current. see the adjustable current limit section for more detail. configured in cot mode, the lm5165 based converter turns on the high-side mosfet with on-time inversely proportional to v in to operate with essentially fixed switching frequency when in continuous conduction mode (ccm). diode emulation mode (dem) prevents negative inductor current, and pulse skipping maintains highest efficiency at light load currents by decreasing the effective switching frequency. the cot-controlled lm5165 waveforms in ccm and dem are represented in figure 34 . the pwm on-time is set by resistor r rt connected from rt to gnd as shown in figure 32 . the control loop maintains a constant output voltage by adjusting the pwm off-time. out out sw(pfm) f pk(pfm) in v v f 1 l i v ? ? ? ? 1 t v ref = 1.233v i lim sleep active sleep active i out1 i out2 active 10mv v out v in sleep active inductor current fb voltage (internal) sw voltage 16 lm5165 snvsa47a ? march 2016 ? revised march 2016 www.ti.com product folder links: lm5165 submit documentation feedback copyright ? 2016, texas instruments incorporated feature description (continued) figure 34. cot mode sw node voltage, feedback voltage and inductor current waveforms the required on-time adjust resistance for a particular frequency is given in equation 2 and tabulated in table 1 . the maximum programmable on-time is 15 s. (2) table 1. on-time adjust resistance (e96 eia values) for various switching frequencies and output voltages f sw (khz) r rt (k ) v out = 1.8 v v out = 3.3 v v out = 5 v v out = 12 v 100 113 205 316 750 200 56.2 105 154 374 300 37.3 68.1 105 249 400 28 51.1 78.7 187 500 23.2 41.2 61.9 150 600 20 34 52.3 124 the choice of control mode and switching frequency requires a compromise between conversion efficiency, quiescent current, and passive component size. lower switching frequency implies reduced switching losses (including gate charge losses, transition losses, etc.) and higher overall efficiency. higher switching frequency, on the other hand, implies a smaller lc output filter and hence a more compact design. lower inductance also helps transient response as the large-signal slew rate of inductor current increases. the ideal switching frequency in a given application is a tradeoff and thus is determined on a case-by-case basis. it relates to the input voltage, output voltage, most frequent load current level(s), external component choices, and circuit size requirement. at light loads, the pfm converter has a relatively longer sleep time interval and thus operates with lower input quiescent current and higher efficiency. t v ref i out2 inductor current fb voltage (internal) i out1 ccm operation dcm operation v out sw voltage extended on-time v in sleep active active sleep 4 mv 4 out rt sw v v 10 r k f khz 1.6 a o ? ? : ? a o ? ? a o ? ? 17 lm5165 www.ti.com snvsa47a ? march 2016 ? revised march 2016 product folder links: lm5165 submit documentation feedback copyright ? 2016, texas instruments incorporated 7.3.3 cot mode light-load operation diode emulation mode (dem) operation occurs when the low-side mosfet switches off as inductor valley current reaches zero. here, the load current is less than half of the peak-to-peak inductor current ripple in ccm. turning off the low-side mosfet at zero current reduces switching loss, and preventing negative current conduction reduces conduction loss. power conversion efficiency is thus higher in a dem converter than an equivalent forced-pwm ccm converter. with dem operation, the duration that both power mosfets remain off progressively increases as load current decreases. 7.3.4 low dropout operation and 100% duty cycle mode if r dson1 and r dson2 are the high-side and low-side mosfet on-state resistances, respectively, and r dcr is the inductor dc resistance, the duty cycle in cot (ccm) or pfm mode is given by equation 3 . (3) the lm5165 offers a low input voltage to output voltage dropout by engaging the high-side mosfet at 100% duty cycle. in cot mode, a frequency foldback feature effectively extends maximum duty cycle to 100% during low dropout conditions or load-on transients. based on the 4-mv fb comparator dropout hysteresis, the duty cycle extends as needed at low input voltage conditions, corresponding to lower switching frequency. the pwm on-time extends based on the requirement that the fb voltage exceeds the dropout hysteresis during a given on- time. 100% duty cycle operation is eventually reached as the input voltage decreases towards the output setpoint. the output voltage stays in regulation at a lower supply voltage, thus achieving an extremely low dropout voltage. note that pfm mode operation provides an inherently natural transition to 100% duty cycle if needed for low dropout applications. use equation 4 to calculate the minimum input voltage to maintain output regulation. (4) 7.3.5 adjustable output voltage (fb) three voltage feedback options are available: the fixed 3.3-v and 5-v versions include internal feedback resistors that sense the output directly through the vout pin; the adjustable voltage option senses the output through an external resistor divider connected from the output to the fb pin. the lm5165 voltage regulation loop regulates the output voltage by maintaining the fb voltage equal to the internal reference voltage, v ref1 . a resistor divider programs the ratio from output voltage v out to fb. for a target v out setpoint, calculate r fb2 based on the selected r fb1 using equation 5 . (5) selecting r fb1 in the range of 100 k to 1 m ? is recommended for most applications. a larger r fb1 consumes less dc current, which is mandatory if light-load efficiency is critical. however, r fb1 larger than 1 m is not recommended as the feedback path becomes more susceptible to noise. high feedback resistances generally require more careful feedback path pcb layout. it is important to route the feedback trace away from the noisy area of the pcb. for more layout recommendations, please refer to the pcb layout section. 7.3.6 adjustable current limit the lm5165 manages overcurrent conditions by cycle-by-cycle current limiting of the peak inductor current. the current sensed in the high-side mosfet is compared every switching cycle to the current limit threshold set by the ilim pin. current is sensed after a leading-edge blanking time following the high-side mosfet turn-on transition. the propagation delay of current limit comparator is 100 ns. four programmable peak current levels are available: 60 ma, 120 ma, 180 ma and 240 ma, corresponding to resistors of 100 k , 56.2 k , 24.9 k and 0 connected at the ilim pin, respectively. in turn, 25ma, 50ma, 75ma and 100ma output current levels in boundary conduction mode pfm operation are possible, respectively. fb2 fb1 out 1.223v r r v 1.223v ? in(min) out out dson1 dcr v v i r r ? out dson2 dcr out out in dson1 dson2 out in v r r i v d v r r i v ? | ? 18 lm5165 snvsa47a ? march 2016 ? revised march 2016 www.ti.com product folder links: lm5165 submit documentation feedback copyright ? 2016, texas instruments incorporated note that in pfm mode, the inductor current ramps from zero to the chosen peak threshold every switching cycle. consequently, the maximum output current is equal to half the peak inductor current. meanwhile, the corresponding output current capability in cot mode is higher as the ripple current is determined by the input and output voltage and the chosen inductance. 7.3.7 precision enable (en) and hysteresis (hys) the precision en input supports adjustable input undervoltage lockout (uvlo) with hysteresis programmed independently via the hys pin for application specific power-up and power-down requirements. en connects to a comparator-based input referenced to a 1.212-v bandgap voltage with 68-mv hysteresis. an external logic signal can be used to drive the en input to toggle the output on and off and for system sequencing or protection. the simplest way to enable the lm5165's operation is to connect en directly to vin. this allows self-startup of the lm5165 when v in is within its valid operating range. however, many applications benefit from using a resistor divider r uv1 and r uv2 as shown in figure 35 to establish a precision uvlo level. in tandem with the en setting, use hys to increase the voltage hysteresis as needed. figure 35. programmable input voltage uvlo with (a) fixed hysteresis, (b) adjustable hysteresis use equation 6 and equation 7 to calculate the input uvlo voltages turn-on and turn-off voltages, respectively. (6) (7) there is also a low i q shutdown mode when en is pulled below a base-emitter voltage drop (approximately 0.6 v at room temperature). if en is below this hard shutdown threshold, the internal ldo regulator powers off and the internal bias supply rail collapses, shutting down the bias currents of the lm5165. the lm5165 operates in standby mode when the en voltage is between the hard shutdown and precision enable thresholds. 7.3.8 power good (pgood) the lm5165 provides a pgood flag pin to indicate when the output voltage is within the regulation level. use the pgood signal for startup sequencing of downstream converters, as shown in figure 36 , or for fault protection and output monitoring. pgood is an open-drain output that requires a pull-up resistor to a dc supply not greater than 12 v. typical range of pullup resistance is 10 k ? to 100 k ? . if necessary, use a resistor divider to decrease the voltage from a higher voltage pull-up rail. uv1 in(off) uv2 hys r v 1.144v 1 r r ? ? ? 1 uv1 in(on) uv2 r v 1.212v 1 r ? ? ? 1 v in 1.212v enable comparator r uv1 r uv2 lm5165 1.144v hys r hys 7 en 9 80 ? v in 1.212v enable comparator r uv1 r uv2 lm5165 1.144v 7 en (b) (a) 19 lm5165 www.ti.com snvsa47a ? march 2016 ? revised march 2016 product folder links: lm5165 submit documentation feedback copyright ? 2016, texas instruments incorporated figure 36. master-slave sequencing implementation using pgood and en when the fb voltage exceeds 94% of the internal reference v ref1 , the internal pgood switch turns off and pgood can be pulled high by the external pull-up. if the fb voltage falls below 87% of v ref1 , the internal pgood switch turns on, and pgood is pulled low to indicate that the output voltage is out of regulation. the rising edge of pgood has a built-in deglitch delay of 5 s. 7.3.9 configurable soft start (ss) the lm5165 has a flexible and easy-to-use soft start control pin, ss. the soft-start feature prevents inrush current impacting the lm5165 and the input supply when power is first applied. soft start is achieved by slowly ramping up the target regulation voltage when the device is first enabled or powered up. selectable/adjustable startup timing options include minimum delay (no soft-start), 900- s internally fixed soft start, and an externally programmable soft start. the simplest way to use the lm5165 is to leave the ss pin open. the lm5165 employs the internal soft-start control ramp and starts up to the regulated output voltage in 900 s. in applications with a large amount of output capacitance, higher v out , or other special requirements, extend the soft-start time by connecting an external capacitor c ss from ss to gnd. longer soft-start time further reduces the supply current needed to charge the output capacitors and supply any output loading. an internal current source i ss of 10 a charges c ss and generates a ramp to control the ramp rate of the output voltage. use equation 8 to calculate the c ss capacitance for a desired soft start time t ss . (8) c ss is discharged by an internal fet when v out is shutdown by en, uvlo or thermal shutdown. it is desirable in some applications for the output voltage to reach its nominal setpoint in the shortest possible time. connecting a 100-k resistor from ss to gnd disables the soft-start circuit, and the lm5165 operates in current limit during startup to rapidly charge the output capacitance. as negative inductor current is prevented, the lm5165 is capable of startup into prebiased output conditions. with a prebiased output voltage, the lm5165 waits until the soft-start ramp allows regulation above the prebiased voltage and then follows the soft-start ramp to the regulation setpoint. 7.3.10 thermal shutdown thermal shutdown is an integrated self-protection to limit junction temperature and prevent damage related to over-heating. thermal shutdown turns off the device when the junction temperature exceeds 170 c to prevent further power dissipation and temperature rise. junction temperature decreases after shutdown, and the lm5165 restarts when the junction temperature falls to 160 c. ss ss c nf 8.1 t ms ? a o a o ? ? ? ? 8 fb lm5165 7 en r uv1 r hys 1 m 200 k v out(master) = 2.5 v r fb1 r fb2 105 k 100 k 1.223 v 8 fb lm5165 7 en r pgood 10 k r fb3 r fb4 22.6 k 100 k 1.223 v v out(slave) = 1.5 v v in(on) = 4.50 v v in(off) = 3.15 v regulator #1 startup based on input voltage uvlo regulator #2 sequential startup based on pgood pgood 6 pgood 6 9 hys 9 hys r uv2 365 k 20 lm5165 snvsa47a ? march 2016 ? revised march 2016 www.ti.com product folder links: lm5165 submit documentation feedback copyright ? 2016, texas instruments incorporated 7.4 device functional modes 7.4.1 shutdown mode the en pin provides on and off control for the lm5165. when v en is below approximately 0.6 v, the device is in shutdown mode. both the internal ldo and the switching regulator are off. the quiescent current in shutdown mode drops to 4.6 a at v in = 12 v. the lm5165 also employs internal bias rail undervoltage protection. if the internal bias supply voltage is below its uv threshold, the regulator remains off. 7.4.2 standby mode the internal bias rail ldo has a lower enable threshold than the regulator itself. when v en is above 0.6 v and below the precision enable threshold (1.212 v typically), the internal ldo is on and regulating. the precision enable circuitry is turned on once the internal v cc is above its uv threshold. the switching action and voltage regulation are not enabled until v en rises above the precision enable threshold. 7.4.3 active mode in cot the lm5165 is in active mode when v en is above the precision enable threshold and the internal bias rail is above its uv threshold. in cot active mode, the lm5165 is in one of three modes depending on the load current: 1. ccm with fixed switching frequency when load current is above half of the peak-to-peak inductor current ripple; 2. pulse skipping and diode emulation mode (dem) when the load current is less than half of the peak-to-peak inductor current ripple in ccm operation. refer to the cot mode light-load operation section for more detail; 3. frequency foldback mode to maintain output regulation at low dropout and for improved load-on transient response. refer to the low dropout operation and 100% duty cycle mode section for more detail. 7.4.4 active mode in pfm similarly, the lm5165 is in pfm active mode when v en and the internal bias rail are above the relevant thresholds, fb has fallen below the lower hysteresis level (v ref1 ), and boundary conduction mode is recharging the output capacitor to the upper hysteresis level (v ref2 ). there is a 4- s wake-up delay from sleep to active states. 7.4.5 sleep mode in pfm the lm5165 is in pfm sleep mode when v en and the internal bias rail are above the relevant threshold levels, v fb has exceeded the upper hysteresis level (v ref2 ), and the output capacitor is sourcing the load current. in pfm sleep mode, the lm5165 operates with very low quiescent current. 21 lm5165 www.ti.com snvsa47a ? march 2016 ? revised march 2016 product folder links: lm5165 submit documentation feedback copyright ? 2016, texas instruments incorporated 8 applications and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 8.1 application information the lm5165 only requires a few external components to convert from a wide range of supply voltages to a fixed output voltage. to expedite and streamline the process of designing of a lm5165-based converter, a comprehensive lm5165 quick-start design tool is available for download to assist the designer with component selection for a given application. webench ? online software is also available to generate complete designs, leveraging iterative design procedures and access to comprehensive component databases. the following sections discuss the design procedure for both cot and pfm modes using specific circuit design examples. as mentioned previously, the lm5165 also integrates several optional features to meet system design requirements, including precision enable, uvlo, programmable soft start, programmable switching frequency in cot mode, adjustable current limit, and pgood indicator. each application incorporates these features as needed for a more comprehensive design. the application circuits detailed below show lm5165 configuration options suitable for several application use cases. please see the lm5165evm-hd-c50x and lm5165evm-hd- p50a evm user's guides for more detail. 8.2 typical applications 8.2.1 design 1: wide v in , low i q cot converter rated at 5 v, 150 ma the schematic diagram of a 5-v, 150-ma cot converter is given in figure 37 . figure 37. schematic for design 1 with v in(nom) = 12 v, v out = 5 v, i out(max) = 150 ma, f sw(nom) = 230 khz 8.2.1.1 design requirements the target full-load efficiency is 91% based on a nominal input voltage of 12 v and an output voltage of 5 v. the required input voltage range is 5 v to 65 v. the lm5165x is chosen to deliver a fixed 5-v output voltage. the switching frequency is set by resistor r rt at 230 khz. the output voltage soft-start time is 6 ms. the required components are listed in table 2 . v out = 5 v i out = 150 ma sw vout ilim vin en hys gnd rt ss pgood lm5165x c out c in 22 f 1 f l f 220 h v in = 5 v...65 v r rt 133 k : r esr 1.5 : c ss 47 nf u 1 22 lm5165 snvsa47a ? march 2016 ? revised march 2016 www.ti.com product folder links: lm5165 submit documentation feedback copyright ? 2016, texas instruments incorporated typical applications (continued) (1) see third-party products disclaimer . table 2. list of components for design 1 (1) ref des qty specification vendor part number c in 1 1 f, 100 v, x7r, 1206 ceramic tdk c3216x7r2a105k160aa c out 1 22 f, 10 v, x7r, 1206 ceramic murata grm31cr71a226ke15l l f 1 220 h 20%, 0.29 a, 0.92 typ dcr, 5.8 x 5.8 x 2.8 mm w rth electronik we-tpc 5828 744053221 220 h 30%, 0.3 a, 1.25 max dcr, 5.8 x 5.8 x 3.0 mm bourns srr5028-221y r esr 1 1.5 , 5%, 0402 std std r rt 1 133 k , 1%, 0402 std std c ss 1 47 nf, 10 v, x7r, 0402 ceramic std std u 1 1 lm5165x synchronous buck converter, vson-10, 5v fixed ti LM5165XDRCR 8.2.1.2 detailed design procedure 8.2.1.2.1 switching frequency ? r t as mentioned, the switching frequency of a cot-configured lm5165 is set by the on-time programming resistor at the rt pin. as shown by equation 2 , a standard 1% resistor of 133 k gives a switching frequency of 230 khz. note that at very low duty cycles, the minimum controllable on-time of the high-side mosfet, t on(min) , of 180 ns may affect choice of switching frequency. in ccm, t on(min) limits the voltage conversion step-down ratio for a given switching frequency. the minimum controllable duty cycle is given by (9) given a fixed t on(min) , it follows that higher switching frequency implies a larger minimum controllable duty cycle. ultimately, the choice of switching frequency for a given output voltage affects the available input voltage range, solution size and efficiency. the maximum supply voltage for a given t on(min) before switching frequency reduction occurs is given by equation 10 . (10) 8.2.1.2.2 filter inductor ? l f the inductor ripple current (assuming ccm operation) and peak inductor current are given respectively by equation 11 and equation 12 . (11) (12) for most applications, choose an inductance such that the inductor ripple current, i l , is between 30% and 50% of the rated load current at nominal input voltage. calculate the inductance using equation 13 . (13) choosing a 220- h inductor in this design results in 55 ma peak-to-peak ripple current at nominal input voltage of 12 v, equivalent to 37% of the 150-ma rated load current. the peak inductor current at maximum input voltage of 65 v is 195 ma, sufficiently below the lm5165 peak current limit of 240 ma. l l(peak) out(max) i i i 2 ' out out l sw f in v v i 1 f l v ' ? ? ? ? 1 ? out in(max) on(min) sw v v t f ? min on(min) sw d t f out out f sw l(nom) in(nom) v v l 1 f i v ? ? ? ? ' ? 1 23 lm5165 www.ti.com snvsa47a ? march 2016 ? revised march 2016 product folder links: lm5165 submit documentation feedback copyright ? 2016, texas instruments incorporated check the inductor datasheet to ensure that the inductor's saturation current is well above the current limit setting of a particular design. ferrite designs have low core loss and are preferred at high switching frequencies, so design goals can then concentrate on copper loss and preventing saturation. however, ferrite core materials exhibit a hard saturation characteristic ? the inductance collapses abruptly when the saturation current is exceeded. this results in an abrupt increase in inductor ripple current, higher output voltage ripple, not to mention reduced efficiency and compromised reliability. note that inductor saturation current generally deceases as the core temperature increases. 8.2.1.2.3 output capacitors ? c out select the output capacitor to limit the capacitive voltage ripple at the converter output. this is the sinusoidal ripple voltage that arises from the triangular ripple current flowing in the capacitor. select an output capacitance using equation 14 to limit the voltage ripple component to 0.5% of the output voltage. (14) substituting i l(nom) of 55 ma gives c out greater than 5 f. mindful of the voltage coefficient of ceramic capacitors, select a 22- f, 10-v capacitor with x7r dielectric in 1206 footprint. 8.2.1.2.4 series ripple resistor ? r esr select a series resistor such that sufficient ripple in phase with the sw node voltage appears at the feedback node, fb. use equation 15 to calculate the required ripple resistance, designated r esr . (15) with v out of 5 v, v ref of 1.223 v, and i l(nom) of 55 ma at the nominal input voltage of 12 v, the required r esr is 1.5 . calculate the total output voltage ripple in ccm using equation 16 . (16) 8.2.1.2.5 input capacitor ? c in an input capacitor is necessary to limit the input ripple voltage while providing switching-frequency ac current to the buck power stage. to minimize the parasitic inductance in the switching loop, position the input capacitors as close as possible to the vin and gnd pins of the lm5165. the input capacitors conduct a square-wave current of peak-to-peak amplitude equal to the output current. it follows that the resultant capacitive component of ac ripple voltage is a triangular waveform. together with the esr-related ripple component, the peak-to-peak ripple voltage amplitude is given by equation 17 . (17) the input capacitance required for a particular load current, based on an input voltage ripple specification of v in , is given by equation 18 . (18) the recommended high-frequency capacitance is 1 f or higher and should be a high-quality ceramic type x5r or x7r with sufficient voltage rating. based on the voltage coefficient of ceramic capacitors, choose a voltage rating of twice the maximum input voltage. additionally, some bulk capacitance is required if the lm5165 circuit is not located within approximately 5 cm from the input voltage source. this capacitor provides damping to the resonance associated with parasitic inductance of the supply lines and high-q ceramics. 8.2.1.2.6 soft-start capacitor ? c ss connect an external soft-start capacitor for a specific soft-start time. in this example, select a soft-start capacitance of 47 nf based on equation 8 to achieve a soft-start time of 6 ms. out in sw in out esr i d 1 d c f v d i r ? ? t ? ' ? ? out in out esr sw in i d 1 d v d i r f c ? ? ' ? ? ? 2 2 out l esr sw out 1 v i r 8 f c ' ' ? ? ? ? ? 1 out esr ref l(nom) 20mv v r v i ? t ? ' l(nom) out sw out i 100 c f v ' ? t ? 24 lm5165 snvsa47a ? march 2016 ? revised march 2016 www.ti.com product folder links: lm5165 submit documentation feedback copyright ? 2016, texas instruments incorporated 8.2.1.3 application performance curves unless otherwise stated, application performance curves were taken at t a = 25 c. v out = 5 v figure 38. efficiency figure 39. load regulation v in = 13.5 v i out = 100 ma l in = 22 h c in(ext) = 10 f figure 40. emi plot ? cispr 22 filtered emissions v in = 12 v i out = 0 ma figure 41. sw node and output ripple voltage, no load v in = 12 v i out = 150 ma figure 42. sw node and output ripple voltage, full load v in = 5.7 v i out = 150 ma figure 43. sw node and output ripple voltage showing frequency foldback near dropout v out 100 mv/div 20 ms/div v sw 5 v/div start 150 khz stop 30 mhz 1 mhz 10 mhz 0 10 20 30 40 50 60 -10 70 cispr22 average detector peak detector output current (ma) output voltage (v) 0 25 50 75 100 125 150 4.9 4.95 5 5.05 5.1 v in = 12v v in = 24v output current (ma) efficiency (%) 0.1 1 10 100 150 30 40 50 60 70 80 90 100 d102 v in = 8v v in = 12v v in = 24v v in = 36v v in = 65v v out 100 mv/div 4 p s/div v sw 5 v/div v out 100 mv/div 4 p s/div v sw 2 v/div 25 lm5165 www.ti.com snvsa47a ? march 2016 ? revised march 2016 product folder links: lm5165 submit documentation feedback copyright ? 2016, texas instruments incorporated v in stepped to 24 v 30- load figure 44. startup, full load v in = 24 v 30- load figure 45. enable on and off v in brownout to 3.2 v figure 46. dropout performance, 75-ma resistive load v in brownout to 3.2 v figure 47. dropout performance, 150-ma resistive load v in = 24 v figure 48. load transient, 50 ma to 150 ma, 1 a/ s i out = 150 ma figure 49. input transient ( automotive cold crank profile) v out 2 v/div 200 ms/div v in 2 v/div i out 50 ma/div v out 100 mv/div i l 50 ma/div 10 p s/div v in 1 v/div v out 1 v/div i out 50 ma/div 4 ms/div v in 1 v/div v out 1 v/div i out 50 ma/div 4 ms/div v out 1 v/div v in 5 v/div i out 50 ma/div 2 ms/div v out 1 v/div v en 1 v/div i out 50 ma/div 2 ms/div 26 lm5165 snvsa47a ? march 2016 ? revised march 2016 www.ti.com product folder links: lm5165 submit documentation feedback copyright ? 2016, texas instruments incorporated (1) see third-party products disclaimer . 8.2.2 design 2: small solution size pfm converter rated at 3.3 v, 50 ma the schematic diagram of a 3.3-v, 50-ma pfm converter with minimum component count is given in figure 50 . figure 50. schematic for design 2 with v in(nom) = 12 v, v out = 3.3 v, i out(max) = 50 ma, f sw(nom) = 350 khz 8.2.2.1 design requirements the target full-load efficiency of this design is 88% based on a nominal input voltage of 12 v and an output voltage of 3.3 v. the required total input voltage range is 3.5 v to 65 v. the lm5165 has an internally-set soft- start time of 900 s and an adjustable peak current limit threshold. the bom is listed in table 3 . table 3. list of components for design 2 (1) ref des qty specification vendor part number c in 1 1 f, 100 v, x7s, 0805 ceramic tdk c2012x7s2a474m125ae c out 1 10 f, 6.3 v, x7r, 0805 ceramic taiyo yuden jmk212ab7106kg-t murata grm21br70j106ke76k l f 1 47 h 20%, 0.56 a, 650 m max dcr, 3.9 x 3.9 x 1.7 mm coilcraft lps4018-473mrc 47 h 20%, 0.7 a, 620 m typ dcr, 4.0 x 4.0 x 1.8 mm w rth 74404042470 47 h 20%, 0.57 a, 650 m typ dcr, 4.0 x 4.0 x 1.8 mm taiyo yuden nr4018t470m r ilim 1 56.2 k , 1%, 0402 std std u 1 1 lm5165y synchronous buck converter, vson-10, 3.3 v fixed ti lm5165ydrcr 8.2.2.2 detailed design procedure 8.2.2.2.1 peak current limit setting ? r ilim install a 56.2 k resistor from ilim to gnd to select a 120-ma peak current limit threshold setting to meet the rated output current of 50 ma. 8.2.2.2.2 switching frequency ? l f tie rt to gnd to select pfm mode of operation. the inductor, input voltage, output voltage and peak current determine the pulse switching frequency of a pfm-configured lm5165. for a given input voltage, output voltage and peak current, the inductance of l f sets the switching frequency when the output is in regulation. use equation 19 to select an inductance of 47 h based on the target pfm converter switching frequency of 350 khz at 12-v input. (19) v out = 3.3 v i out = 50 ma sw vout ilim vin en hys gnd rt ss pgood lm5165y c out c in 10 f 1 f l f 47 h v in = 3.5 v...65 v r ilim 56.2 k : u 1 out out f sw(pfm) pk(pfm) in v v l 1 f i v ? ? ? ? 1 27 lm5165 www.ti.com snvsa47a ? march 2016 ? revised march 2016 product folder links: lm5165 submit documentation feedback copyright ? 2016, texas instruments incorporated i pk(pfm) in this example is the peak current limit setting of 120 ma plus an additional 10% margin added to include the effect of the 100-ns peak current comparator delay. an additional constraint on the inductance is the 180-ns minimum on-time of the high-side mosfet. therefore, in order to keep the inductor current well controlled, choose an inductance that is larger than l f(min) using equation 20 where v in(max) is the maximum input supply voltage for the application, t on(min) is 180 ns, and i l(max) is the maximum allowed peak inductor current. (20) choose an inductor with saturation current rating above the peak current limit setting, and allow for derating of the saturation current at the highest expected operating temperature. 8.2.2.2.3 output capacitor ? c out the output capacitor, c out , filters the inductor ? s ripple current and stores energy to meet the load current requirement when the lm5165 is in sleep mode. the output ripple has a base component of amplitude v out /123 related to the 10-mv typical feedback comparator hysteresis in pfm. the wakeup time from sleep to active mode adds a ripple voltage component that is a function of the output current. approximate the total output ripple by equation 21 . (21) also, the output capacitance must be large enough to accept the energy stored in the inductor without a large deviation in output voltage. setting this voltage change equal to 0.5% of the output voltage results in (22) in general, select the capacitance of c out to limit the output voltage ripple at full load current, ensuring that it is rated for worst-case rms ripple current given by i rms = i pk(pfm) /2. in this design example, choose a 10- f, 6.3-v ceramic output capacitor with x7r dielectric and 0805 footprint. 8.2.2.2.4 input capacitor ? c in the input capacitor, c in , filters the high-side mosfet's triangular current waveform, see figure 72 . to prevent large ripple voltage, use a low esr ceramic input capacitor sized for the worst-case rms ripple current given by i rms = i out /2. in this design example, choose a 1- f, 100-v ceramic input capacitor with x7s dielectric and 0805 footprint. 2 pk(pfm) out f out i c 100 l v t ? ? ? ? ? 1 out out out out i 4 v 9 v c 123 ? ' in(max) on(min) f(min) l(max) v t l i ? 28 lm5165 snvsa47a ? march 2016 ? revised march 2016 www.ti.com product folder links: lm5165 submit documentation feedback copyright ? 2016, texas instruments incorporated 8.2.2.3 application performance curves v out = 3.3 v figure 51. efficiency v in = 12 v i out = 50 ma figure 52. sw node and output ripple voltage, full load v in stepped to 12 v 66- load figure 53. startup, full load v in = 12 v 66- load figure 54. enable on and off v in = 12 v figure 55. load transient, 0 ma to 50 ma, 1 a/ s i out = 50 ma figure 56. input voltage transient ( automotive cold crank profile) v out 100 mv/div i out 20 ma/div 10 p s/div v out 1 v/div 200 ms/div v in 2 v/div v out 1 v/div v in 2 v/div i out 20 ma/div 1 ms/div v out 1 v/div v en 1 v/div i out 20 ma/div 1 ms/div v out 100 mv/div 10 p s/div v sw 5 v/div output current (ma) efficiency (%) 0.1 1 10 50 30 40 50 60 70 80 90 100 d103 v in = 8v v in = 12v v in = 24v v in = 36v v in = 65v 29 lm5165 www.ti.com snvsa47a ? march 2016 ? revised march 2016 product folder links: lm5165 submit documentation feedback copyright ? 2016, texas instruments incorporated (1) see third-party products disclaimer . 8.2.3 design 3: high density 12-v, 75-ma pfm converter the schematic diagram of 12-v, 75-ma pfm converter is given in figure 57 . figure 57. schematic for design 3 with v in(nom) = 24 v, v out = 12 v, i out(max) = 75 ma, f sw(nom) = 500 khz 8.2.3.1 design requirements the full-load efficiency specification is 92% based on a nominal input voltage of 24 v and an output voltage of 12 v. the total input voltage range is 18 v to 65 v, with uvlo turn on and turn off at 16 v and 14.5 v, respectively. the output voltage setpoint is established by feedback resistors, r fb1 and r fb2 . the switching frequency is set by inductor l f at 500 khz at nominal input voltage. the required components are listed in table 4 . table 4. list of components for design 3 (1) ref des qty specification vendor part number c in 1 1 f, 100 v, x7s, 0805 ceramic murata grj21bc72a105ke11l 1 f, 100 v, x7s, 0805 ceramic, aec-q200 tdk cga4j3x7s2a105k125ae c out 1 10 f, 16 v, x7r, 0805 ceramic taiyo yuden emk212bb7106mg-t 10 f, 16 v, x7r, 0805 ceramic, aec-q200 tdk cga4j1x7s1c106k125ac l f 1 47 h 20%, 0.56 a, 650 m max dcr, 3.9 x 3.9 x 1.7 mm aec-q200 coilcraft lps4018-473mrc r ilim 1 24.9 k , 1%, 0402 std std r fb1 1 1 m , 1%, 0402 std std r fb2 1 113 k , 1%, 0402 std std r uv1 1 10 m , 1%, 0603 std std r uv2 1 825 k , 1%, 0402 std std r hys 1 37.4 k , 1%, 0402 std std c ss 1 22 nf, 10 v, x7r, 0402 std std u 1 1 lm5165 synchronous buck converter, vson-10, 3mm x 3 mm ti lm5165drcr 8.2.3.2 detailed design procedure the component selection procedure for this pfm design is quite similar to that of design 2, see figure 50 . 8.2.3.2.1 peak current limit setting ? r ilim install a 24.9 k resistor from ilim to gnd to select the 180-ma peak current limit setting for a rated output current of 75 ma. v out = 12 v i out = 75 ma c out 10 f 1 f v in = 18 v...65 v sw fb ilim vin en hys gnd rt ss pgood lm5165 c in c ss r ilim r uv1 r uv2 r hys r fb1 r fb2 24.9 k : l f 47 h 10 m : 825 k : 37.4 k : 22 nf 1 m : 113 k : u 1 30 lm5165 snvsa47a ? march 2016 ? revised march 2016 www.ti.com product folder links: lm5165 submit documentation feedback copyright ? 2016, texas instruments incorporated 8.2.3.2.2 switching frequency ? l f tie rt to gnd to select pfm mode of operation. set the switching frequency by the filter inductance, l f . calculate an inductance of 47 h based on the target pfm converter switching frequency of 500 khz at 24-v input using equation 19 . use a peak current limit setting, i pk(pfm) , of 180 ma plus an additional 50% margin in this high-frequency design to include the effect of the 100-ns current limit comparator delay. choose an inductor with saturation current rating well above the peak current limit setting, and allow for derating of the saturation current at the highest expected operating temperature. 8.2.3.2.3 input and output capacitors ? c in , c out choose a 1- f, 100-v ceramic input capacitor with 0805 footprint. such a capacitor is typically available in x5r or x7s dielectric. based on equation 22 , select a 10- f, 16-v ceramic output capacitor with x7r dielectric and 0805 footprint. 8.2.3.2.4 feedback resistors ? r fb1 , r fb2 the output voltage of the lm5165 is externally adjustable using a resistor divider network. the divider network comprises the upper feedback resistor r fb1 and lower feedback resistor r fb2 . select r fb1 of 1 m to minimize quiescent current and improve light-load efficiency in this application. with the desired output voltage setpoint of 12 v and v fb = 1.223 v, calculate the resistance of r fb2 using equation 5 as 113.5 k . choose the closest available standard value of 113 k for r fb2 . please refer to the adjustable output voltage (fb) section for more detail. 8.2.3.2.5 undervoltage lockout setpoint ? r uv1 , r uv2 , r hys adjust the undervoltage lockout (uvlo) using an externally-connected resistor divider network of r uv1 , r uv2 and r hys . the uvlo has two thresholds, one for power up when the input voltage is rising and one for power down or brownouts when the input voltage is falling. the en rising threshold for the lm5165 is 1.212 v. rearranging equation 6 and equation 7 , the expressions to calculate r uv2 and r hys are as follows. (23) (24) choose r uv1 as 10 m ? to minimize input quiescent current. given the desired input voltage uvlo thresholds of 16 v and 14.5v, calculate the resistance of r uv2 and r hys as 825 k ? and 37.4 k ? , respectively. please refer to the precision enable (en) and hysteresis (hys) section for more detail. 8.2.3.2.6 soft start ? c ss install a 22-nf capacitor from ss to gnd for a soft-start time of 3 ms. en(off) hys uv1 uv2 in(off) en(off) v r r r v v ? en(on) uv2 uv1 in(on) en(on) v r r v v ? 31 lm5165 www.ti.com snvsa47a ? march 2016 ? revised march 2016 product folder links: lm5165 submit documentation feedback copyright ? 2016, texas instruments incorporated 8.2.3.3 application performance curves v out = 12 v figure 58. efficiency v in stepped to 24 v 160- load figure 59. startup, full load v in = 24 v i out = 75 ma figure 60. sw node and output ripple voltage, full load v in = 24 v i out = 0 ma figure 61. sw node and output ripple voltage, no load v out 500 mv/div 10 p s/div v sw 10 v/div v out 500 mv/div 10 ms/div v sw 10 v/div output current (ma) efficiency (%) 0.1 1 10 75 30 40 50 60 70 80 90 100 d105 v in = 18v v in = 24v v in = 36v v in = 48v v in = 65v v out 2 v/div 1 ms/div v in 5 v/div i out 20 ma/div 32 lm5165 snvsa47a ? march 2016 ? revised march 2016 www.ti.com product folder links: lm5165 submit documentation feedback copyright ? 2016, texas instruments incorporated (1) see third-party products disclaimer . 8.2.4 design 4: 3.3-v, 150-ma cot converter with high efficiency the schematic diagram of a 3.3-v, 150-ma cot converter is given in figure 62 . figure 62. schematic for design 4 with v in(nom) = 24 v, v out = 3.3 v, i out(max) = 150 ma, f sw(nom) = 160 khz 8.2.4.1 design requirements the target full-load efficiency is 91% based on a nominal input voltage of 24 v and an output voltage of 3.3 v. the required input voltage range is 3 v to 65 v. the lm5165y is chosen to deliver a fixed 3.3-v output voltage. the switching frequency is set by resistor r rt at approximately 160 khz. the output voltage soft-start time is 4 ms. the required components are listed in table 5 . the component selection procedure for this cot design is quite similar to that of design 1, see figure 37 . table 5. list of components for design 4 (1) ref des qty specification vendor part number c in 1 1 f, 100 v, x7r, 1206 ceramic murata grm31cr72a105ka01l c out 1 22 f, 6.3 v, x7s, 0805 ceramic murata grm21br660j226me39k l f 1 150 h 20%, 0.29 a, 0.86 typ dcr, 4.8 x 4.8 x 2.9 mm coilcraft lps5030-154mlc r esr 1 0.5 , 5%, 0402 std std r rt 1 121 k , 1%, 0402 std std c ss 1 33 nf, 10 v, x7r, 0402 ceramic std std u 1 1 lm5165y synchronous buck converter, vson-10, 3.3v fixed ti lm5165ydrcr 8.2.4.2 application performance curves figure 63. efficiency v in = 24 v i out = 150 ma figure 64. sw node and output ripple voltages, full load output current (ma) efficiency (%) 0.1 1 10 100 150 30 40 50 60 70 80 90 100 d104 v in = 8v v in = 12v v in = 24v v in = 36v v in = 65v v out 0.5 v/div 4 p s/div v sw 5 v/div v out = 3.3 v * i out = 150 ma sw vout ilim vin en hys gnd rt ss pgood lm5165y c out c in 22 f 1 f l f 150 h v in = 3 v...65 v r rt 121 k : r esr 0.5 : c ss 33 nf u 1 * v out tracks v in if v in d 3.3v 33 lm5165 www.ti.com snvsa47a ? march 2016 ? revised march 2016 product folder links: lm5165 submit documentation feedback copyright ? 2016, texas instruments incorporated (1) see third-party products disclaimer . 8.2.5 design 5: 15-v, 150-ma, 600-khz cot converter the schematic diagram of a 15-v, 150-ma cot converter is given in figure 65 . figure 65. schematic for design 5 with v in(nom) = 36 v, v out = 15 v, i out(max) = 150 ma, f sw(nom) = 600 khz 8.2.5.1 design requirements the target full-load efficiency is 92% based on a nominal input voltage of 36 v and an output voltage of 15 v. the input voltage operating range is 24 v to 48 v, but transients as high as 65 v are possible in the application. uvlo turn on and turn off are set at 19 v and 17 v, respectively. the lm5165 switching frequency is set at approximately 600 khz by resistor r rt of 143 k . the output voltage soft-start time is 6 ms. the required components are listed in table 6 . the component selection procedure for this cot design is quite similar to that of design 1, see figure 37 . table 6. list of components for design 5 (1) ref des qty specification vendor part number c in 1 1 f, 100 v, x7r, 1206 ceramic avx 12061c105kat2a c out 1 10 f, 25 v, x7r, 1206 ceramic taiyo yuden tmk316b7106kl-td l f 1 150 h 20%, 0.29 a, 0.86 typ dcr, 4.8 x 4.8 x 2.9 mm coilcraft lps5030-154mlc r esr 1 2.2 , 5%, 0402 std std r rt 1 143 k , 1%, 0402 std std r fb1 1 499 k , 1%, 0402 std std r fb2 1 44.2 k , 1%, 0402 std std r uv1 1 10 m , 1%, 0603 std std r uv2 1 681 k , 1%, 0402 std std r hys 1 40.2 k , 1%, 0402 std std c ff 1 10 pf, 10 v, x7r, 0402 ceramic std std c ss 1 47 nf, 10 v, x7r, 0402 ceramic std std u 1 1 lm5165 synchronous buck converter, vson-10, 3 mm x 3 mm ti lm5165drcr 8.2.5.2 detailed design procedure 8.2.5.2.1 cot output ripple voltage reduction depending on the required ripple resistance when operating in cot mode, the resultant output voltage ripple may be deemed too high for a given application. one option is to place a feed-forward capacitor c ff in parallel with the upper feedback resistor r fb1 . capacitor c ff increases the high-frequency gain from v out to v fb close to unity such that the output voltage ripple couples directly to the fb node. v out = 15 v i out = 150 ma 1 f v in = 24 v...48 v sw fb ilim vin en hys gnd rt ss pgood lm5165 c in c ss r uv1 r uv2 r hys r fb1 r fb2 l f 150 h 10 m : 681 k : 40.2 k : 47 nf 499 k : 44.2 k : u 1 c out 10 f r esr 0.5 : r rt 143 k : c ff 10 pf 34 lm5165 snvsa47a ? march 2016 ? revised march 2016 www.ti.com product folder links: lm5165 submit documentation feedback copyright ? 2016, texas instruments incorporated 8.2.5.3 application performance curves v out = 15 v figure 66. efficiency v in stepped to 36 v i out = 150 ma figure 67. startup, full load v in = 36 v i out = 150 ma figure 68. sw node and output ripple voltage, full load v in = 36 v i out = 0 ma figure 69. sw node and output ripple voltage, no load v in = 36 v figure 70. enable on and off v in = 36 v figure 71. short circuit recovery v out 1 v/div v en 1 v/div i out 100 ma/div 2 ms/div v in 10 v/div v out 5 v/div i out 100 ma/div 400 p s/div v sw 10 v/div v out 100 m/div 10 ms/div v sw 10 v/div v out 100 mv/div 1 p s/div output current (ma) efficiency (%) 0.1 1 10 100 150 30 40 50 60 70 80 90 100 d106 v in = 24v v in = 36v v in = 48v v in = 65v v out 5 v/div v in 10 v/div i out 100 ma/div 2 ms/div 35 lm5165 www.ti.com snvsa47a ? march 2016 ? revised march 2016 product folder links: lm5165 submit documentation feedback copyright ? 2016, texas instruments incorporated 9 power supply recommendations the lm5165 is designed to operate from an input voltage supply range between 3 v and 65 v. this input supply should be able to provide the maximum input current and maintain a voltage above 3 v. ensure that the resistance of the input supply rail is low enough that an input current transient does not cause a high enough drop at the lm5165 supply rail to cause a false uvlo fault triggering and system reset. if the input supply is located more than a few inches from the lm5165 converter, additional bulk capacitance may be required in addition to the ceramic input capacitance. a 4.7- f electrolytic capacitor is a typical choice for this function, whereby the capacitor esr provides a level of damping against input filter resonances. a typical esr of 0.5 provides enough damping for most input circuit configurations. 10 pcb layout the performance of any switching converter depends as much upon pcb layout as it does the component selection. the following guidelines are provided to assist with designing a pcb with the best power conversion performance, thermal performance, and minimized generation of unwanted emi. 10.1 layout guidelines pcb layout is a critical for good power supply design. there are several paths that conduct high slew-rate currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise and emi or degrade the power supply's performance. 1. bypass the vin pin to gnd with a low esr ceramic capacitor of x5r or x7r dielectric. place c in as close as possible to the lm5165 vin and gnd pins. ground return paths for both the input and output capacitors should consist of localized top-side planes that connect to the gnd pin and exposed pad. 2. minimize the loop area formed by the input capacitor connections and the vin and gnd pins. 3. locate the power inductor close to the sw pin. minimize the area of the sw trace/plane to prevent excessive capacitive coupling. 4. tie the gnd pin directly to the power pad under the device and to a heat-sinking pcb ground plane. 5. use a ground plane in one of the middle layers as a noise shielding and heat dissipation path. 6. have a single-point ground connection to the plane. route the ground connections for the feedback, soft- start, and enable components to the ground plane. this prevents any switched or load currents from flowing in analog ground traces. if not properly handled, poor grounding results in degraded load regulation or erratic output voltage ripple behavior. 7. make v in , v out and ground bus connections as wide as possible. this reduces any voltage drops on the input or output paths of the converter and maximizes efficiency. 8. minimize trace length to the fb pin. locate both feedback resistors close to the fb pin. place c ff (if used) directly in parallel with r fb1 . route the v out sense path away from noisy nodes and preferably on a layer at the other side of a shielding layer. 9. locate the components at rt and ss as close as possible to the device. route with minimal trace lengths. 10. provide adequate heat-sinking for the lm5165 to keep the junction temperature below 150 c. for operation at full rated load, the top-side ground plane is an important heat-dissipating area. use an array of heat- sinking vias to connect the exposed pad to the pcb ground plane. if the pcb has multiple copper layers, connect these thermal vias to inner-layer ground planes. 10.1.1 compact pcb layout for emi reduction radiated emi generated by high di/dt components relates to pulsing currents in switching converters. the larger area covered by the path of a pulsing current, the more electromagnetic emission is generated. the key to minimize radiated emi is to identify the pulsing current path and minimize the area of that path. the critical switching loop of the power stage in terms of emi is denoted in figure 72 . the topological architecture of a buck converter means that a particularly high di/dt current effective path exists in the loop comprising the input capacitor and the lm5165's integrated mosfets, and it becomes mandatory to reduce the parasitic inductance of this loop by minimizing the effective loop area. 36 lm5165 snvsa47a ? march 2016 ? revised march 2016 www.ti.com product folder links: lm5165 submit documentation feedback copyright ? 2016, texas instruments incorporated layout guidelines (continued) figure 72. synchronous buck converter with power stage critical switching loop the input capacitor provides the primary path for the high di/dt components of the high-side mosfet's current. placing a ceramic capacitor as close as possible to the vin and gnd pins is the key to emi reduction. keep the trace connecting sw to the inductor as short as possible and just wide enough to carry the load current without excessive heating. use short, thick traces or copper pours (shapes) for current conduction path to minimize parasitic resistance. place the output capacitor close to the v out side of the inductor, and connect the capacitor's return terminal to the lm5165's gnd pin and exposed pad. 10.1.2 feedback resistor layout for the adjustable output voltage version of the lm5165, reduce noise sensitivity of the output voltage feedback path by placing the resistor divider close to the fb pin, rather than close to the load. this reduces the trace length of fb signal and noise coupling. the fb pin is the input to the feedback comparator and, as such, is a high impedance node sensitive to noise. the output node is a low impedance node, so the trace from v out to the resistor divider can be long if a short path is not available. route the voltage sense trace from the load to the feedback resistor divider away from the sw node path, the inductor and v in path to avoid contaminating the feedback signal with switch noise, while also minimizing the trace length. this is most important when high feedback resistances, greater than 100 k , are used to set the output voltage. also, route the voltage sense trace on a different layer from the inductor, sw node and v in path, such that there is a ground plane that separates the feedback trace from the inductor and sw node copper polygon. this provides further shielding for the voltage feedback path from switching noise sources. 10.2 layout example figure 73 shows an example layout for the pcb top layer of a single-sided design. the bottom layer is essentially a full ground plane except for short connecting traces for sw, en and pgood. 1 sw vin v out gnd lm5165 low-side nmos gate driver high-side pmos gate driver 10 c in c out q 1 q 2 l f gnd 2 high di/dt loop v in 37 lm5165 www.ti.com snvsa47a ? march 2016 ? revised march 2016 product folder links: lm5165 submit documentation feedback copyright ? 2016, texas instruments incorporated layout example (continued) figure 73. pcb layout example connect ceramic input cap close to vin and gnd c ss r rt r ilim place ss cap close to pin c in c out r esr thermal vias under lm5165 pad r fb2 r fb1 c ff r hys r uv1 r uv2 place fb resistors very close to fb & gnd pins r pg vout connection vin connection short sw node trace routed underneath pgood connection en connection sw via gnd connection l f 38 lm5165 snvsa47a ? march 2016 ? revised march 2016 www.ti.com product folder links: lm5165 submit documentation feedback copyright ? 2016, texas instruments incorporated 11 device and documentation support 11.1 device support 11.1.1 third-party products disclaimer ti's publication of information regarding third-party products or services does not constitute an endorsement regarding the suitability of such products or services or a warranty, representation or endorsement of such products or services, either alone or in combination with any ti product or service. 11.1.2 development support ? lm5165 quick-start design tool ? tidesigns reference design library ? webench ? designer 11.2 documentation support 11.2.1 related documentation ? lm5165-hd-p50a evm user's guide , snvu474 ? lm5165-hd-c50x evm user's guide , snvu511 ? an-2162: simple success with conducted emi from dc-dc converters , snva489 ? automotive cranking simulator user's guide , slvu984 ? using new thermal metrics application report, sbva025 ? semiconductor and ic package thermal metrics , spra953 11.3 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 11.4 trademarks e2e is a trademark of texas instruments. webench is a registered trademark of texas instruments. 11.5 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 11.6 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 12 mechanical, packaging, and orderable information the following pages include mechanical packaging and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this datasheet, refer to the left-hand navigation. package option addendum www.ti.com 30-mar-2016 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples lm5165drcr active vson drc 10 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 150 5165 lm5165drct active vson drc 10 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 150 5165 LM5165XDRCR active vson drc 10 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 150 5165x lm5165xdrct active vson drc 10 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 150 5165x lm5165ydrcr active vson drc 10 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 150 5165y lm5165ydrct active vson drc 10 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 150 5165y (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. package option addendum www.ti.com 30-mar-2016 addendum-page 2 (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. other qualified versions of lm5165 : ? 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