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| automotive power data sheet rev. 1.0, 2017-03-03 tle9869qxa20 microcontroller with lin and h-bridge mo sfet driver for automotive applications bf-step
tle9869qxa20 table of contents data sheet 2 rev. 1.0, 2017-03-03 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 device pinout and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 device pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 power management unit (pmu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2.2 pmu modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3 power supply generation unit (pgu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.3.1 voltage regulator 5.0v (vddp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.3.2 voltage regulator 1.5v (vddc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.3.3 external voltage regulator 5.0v (vddext) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6 system control unit - digital modules (scu-dm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.3 clock generation unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.3.1 low precision clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.3.2 high precision oscillator circuit (osc_hp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.3.2.1 external input clock mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.3.2.2 external crystal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7 system control unit - power modules (scu-pm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8 arm cortex-m3 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9dma controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.3.1 dma mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10 address space organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 11 memory control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 11.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 11.2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 11.3 nvm module (flash memory) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table of contents tle9869qxa20 table of contents data sheet 3 rev. 1.0, 2017-03-03 12 interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 12.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 12.2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 13 watchdog timer (wdt1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 13.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 14 gpio ports and peripheral i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 14.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 14.2.1 port 0 and port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 14.2.2 port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 14.3 tle9869qxa20 port module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 14.3.1 port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 14.3.1.1 port 0 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 14.3.2 port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 14.3.2.1 port 1 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 14.3.3 port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 14.3.3.1 port 2 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 15 general purpose timer units (gpt12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 15.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 15.1.1 features block gpt1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 15.1.2 features block gpt2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 15.2.1 block diagram gpt1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 15.2.2 block diagram gpt2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 16 timer2 and timer21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 16.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 16.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 16.2.1 timer2 and timer21 modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 17 timer3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 17.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 17.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 17.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 17.3.1 timer3 modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 18 capture/compare unit 6 (ccu6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 18.1 feature set overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 18.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 18.2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 19 uart1/uart2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 19.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 19.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 19.2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 19.3 uart modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 20 lin transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 20.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 20.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 20.2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 tle9869qxa20 table of contents data sheet 4 rev. 1.0, 2017-03-03 21 high-speed synchronous serial interface (ssc1/ssc2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 21.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 21.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 21.2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 22 measurement unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 22.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 22.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 22.2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 23 measurement core module (incl. adc2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 23.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 23.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 23.2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 23.2.2 measurement core module modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 24 10-bit analog digital converter (adc1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 24.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 24.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 24.2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 25 high-voltage monitor input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 25.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 25.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 25.2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 26 bridge driver (incl. charge pump) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 26.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 26.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 26.2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 26.2.2 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 27 current sense amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 27.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 27.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 27.2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 28 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 28.1 h-bridge driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 28.2 esd immunity according to iec61000-4-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 29 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 29.1 general characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 29.1.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 29.1.2 functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 29.1.3 current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 29.1.4 thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 29.1.5 timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 29.2 power management unit (pmu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 29.2.1 pmu i/o supply (vddp) parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 29.2.2 pmu core supply (vddc) parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 29.2.3 vddext voltage regulator (5.0v) parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 29.2.4 vpre voltage regulator (pmu subblock) parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 29.2.4.1 load sharing scenarios of vpre regu lator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 29.2.5 power down voltage regulator (pmu subblock) parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 29.3 system clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 tle9869qxa20 table of contents data sheet 5 rev. 1.0, 2017-03-03 29.3.1 oscillators and pll parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 29.3.2 external clock parameters xtal1, xtal2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 29.4 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 29.4.1 flash parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 29.5 parallel ports (gpio) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 29.5.1 description of keep and force current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 29.5.2 dc parameters of port 0, port 1, tms and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 29.5.3 dc parameters of port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 29.6 lin transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 29.6.1 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 29.7 high-speed synchronous serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 29.7.1 ssc timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 29.8 measurement unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 29.8.1 system voltage measurement parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 29.8.2 central temperature sensor parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 29.8.3 adc2-vbg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 29.8.3.1 adc2 reference voltage vbg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 29.8.3.2 adc2 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 29.9 adc1 reference voltage - varef . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 29.9.1 electrical characteristics varef . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 29.9.2 electrical characteristics adc1 (10-bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 29.10 reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 29.11 high-voltage monitoring input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 29.11.1 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 29.12 mosfet driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 29.12.1 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 29.13 operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 29.13.1 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 30 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 24 31 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 vqfn-48-31 type package marking tle9869qxa20 vqfn-48-31 data sheet 6 rev. 1.0, 2017-03-03 microcontroller with lin an d h-bridge mosfet driver for automotive applications tle9869qxa20 1overview summary of features ? 32 bit arm cortex m3 core ? up to 24 mhz clock frequency ? one clock per machine cycle architecture ? on-chip memory ? 128 kbyte flash including ? 4 kbyte eeprom (emulated in flash) ? 512 byte 100 time programmable memory (100tp) ? 6 kbyte ram ? boot rom for startup firmware and flash routines ? on-chip osc and pll for clock generation ? pll loss-of-lock detection ? mosfet driver including charge pump ? 10 general-purpose i/o ports (gpio) ? 5 analog inputs, 10-bit a/d converter (adc1) ? 16-bit timers - gpt12, timer 2, timer 21 and timer 3 ? capture/compare unit for pwm signal generation (ccu6) ? 2 full duplex serial interfaces (uart) with lin support (for uart1 only) ? 2 synchronous serial channels (ssc) ? on-chip debug support via 2-wire swd ? 1 lin 2.2 transceiver ? 1 high voltage monitoring input ? single power supply from 5.5 v to 27 v ? extended power supply voltage range from 3 v to 28 v ? low-dropout voltage regulators (ldo) ? high speed operational amplifier for motor current sensing via shunt ? 5 v voltage supply for extern al loads (e.g. hall sensor) ? core logic supply at 1.5 v ? programmable window watchdog (wdt1) with independent on-chip clock source ? power saving modes ? mcu slow-down mode ? sleep mode ? stop mode ? cyclic wake-up sleep mode ? power-on and undervoltage/brownout reset generator tle9869qxa20 overview data sheet 7 rev. 1.0, 2017-03-03 ? overtemperature protection ? short circuit protection ? loss of clock detection with fail safe mo de entry for low syste m power consumption ? temperature range t j = -40 c to +150 c ? package vqfn-48 with lti feature ? green package (rohs compliant) ? aec qualified tle9869qxa20 overview data sheet 8 rev. 1.0, 2017-03-03 1.1 abbreviations the following acronyms and terms are used within this document. list see in table 1 . table 1 acronyms acronyms name ahb advanced high-performance bus apb advanced peripheral bus ccu6 capture compare unit 6 cgu clock generation unit cmu cyclic management unit cp charge pump fo r mosfet driver csa current sense amplifier dpp data post processing ecc error correction code eeprom electrically erasable pr ogrammable read only memory eim exceptional interrupt measurement fsm finite state machine gpio general purpose input output h-bridge half bridge icu interrupt control unit ien interrupt enable iir infinite impulse response ldm load instruction ldo low dropout voltage regulator lin local interconnect network lsb least significant bit lti lead tip inspection mcu memory control unit mf measurement functions msb most significant bit mpu memory protection unit mrst master receive slave transmit mtsr master transmit slave receive mu measurement unit nmi non maskable interrupt nvic nested vector interrupt controller nvm non-volatile memory otp one time programmable osc oscillator pba peripheral bridge tle9869qxa20 overview data sheet 9 rev. 1.0, 2017-03-03 pcu power control unit pd pull down pgu power supply generation unit pll phase locked loop ppb private peripheral bus pu pull up pwm pulse width modulation ram random access memory rcu reset control unit rmu reset management unit rom read only memory scu-dm system control unit - digital modules scu-pm system control unit - power modules sfr special function register sow short open window (for wdt) spi serial peripheral interface ssc synchronous serial channel stm store instruction swd arm serial wire debug tccr temperature compensation control register tms test mode select tsd thermal shut down uart universal asynchronous receiver transmitter vbg voltage reference band gap vco voltage controlled oscillator vpre pre regulator wdt watchdog timer in scu-dm wdt1 watchdog timer in scu-pm wmu wake-up management unit 100tp 100 time programmable table 1 acronyms acronyms name tle9869qxa20 block diagram data sheet 10 rev. 1.0, 2017-03-03 2 block diagram figure 1 block diagram cp1l cp2l cp2h cp1h test / debug interface arm cortex-m3 flash sram rom multilayer ahb matrix pba0 mosfet driver pmu ? power control system functions mon pba1 uart1 uart2 ssc1 ssc2 t2 t21 pll gpio p0.1 ? p0.4 p1.0 ? p1.4 gh2 mon mu mf / adc2 lin t3 dma controller vddc vddp vddext reset vs gnd_lin lin sh2 gl2 gh1 gl1 sh1 vdh systembus slave slave slave slave slave dma controller slave p0.0 tms gpt12 ccu6 cp vsd vcp sl dpp2 op amp op2 op1 scu_dm scu_pm wdt1/ clkwdt wdt adc 1 dpp1 p2.0, p2.2, p2.3, p2.4, p2.5 (an0, an2, an3, an4, an5) gnd_ref varef mu-varef op amp vbat_sense op amp scu_dm xtal1 xtal2 tle9869qxa20 device pinout and pin configuration data sheet 11 rev. 1.0, 2017-03-03 3 device pinout and pin configuration 3.1 device pinout figure 2 device pinout vs 45 vdh 44 lin 43 14 m on 17 p1 .2 18 p0. 4 19 gnd 20 tms 22 reset 21 p0 .0 23 p0 .1 24 p0 .3 25 p0.2 26 p1.3 27 p1.4 28 gnd 29 p2.0/xtal1 30 p2.2/xtal2 31 p2.5 32 p2.4 33 gnd_ref 35 p2.3 36 op 2 34 va re f gl2 12 nu 11 sl 10 gh1 9 sh1 8 gh2 7 gnd 39 13 gl 1 vddext 41 gnd_lin 42 nu 5 sh2 6 vddc 38 op1 37 15 p1 .0 16 p1 .1 vddp 40 ep tle 9869 ep vsd 47 cp 1l 1 vcp 2 cp2h 3 cp2l 4 cp 1h 48 vbat _ sense 46 note: = low voltage pins tle9869qxa20 device pinout and pin configuration data sheet 12 rev. 1.0, 2017-03-03 3.2 pin configuration after reset, all pins are configured as input (except supply and lin pins) with one of the following settings: ? pull-up device enabled only (pu) ? pull-down device enabled only (pd) ? input with both pull-up and pull-down devices disabled (i) ? output with output stage deacti vated = high impedance state (hi-z) the functions and default states of the tle9869qxa20 external pins are provided in the following table. type: indicates the pin type. ? i/o: input or output ? i: input only ? o: output only ? p: power supply not all alternate functions listed. table 2 pin definitions and functions symbol pin number type reset state 1) function p0 port 0 port 0 is a 5-bit bidirectional general purpose i/o port. alternate functions can be assigned and are listed in the port description. main function is listed below. p0.0 21 i/o i/pu swd serial wire debug clock p0.1 23 i/o i/pu gpio general purpose io alternate function mapping see table 8 p0.2 25 i/o i/pd gpio general purpose io alternate function mapping see table 8 note: for a functional swd connection this gpio must be tied to zero! p0.3 24 i/o i/pu gpio general purpose io alternate function mapping see table 8 p0.4 18 i/o i/pd gpio general purpose io alternate function mapping see table 8 p1 port 1 port 1 is a 5-bit bidirectional general purpose i/o port. alternate functions can be assigned and are listed in the port description. the principal functions are listed below. p1.0 15 i/o i gpio general purpose io alternate function mapping see table 9 p1.1 16 i/o i gpio general purpose io alternate function mapping see table 9 p1.2 17 i/o i gpio general purpose io alternate function mapping see table 9 p1.3 26 i/o i gpio general purpose io, used for inrush transistor alternate function mapping see table 9 p1.4 27 i/o i gpio general purpose io alternate function mapping see table 9 tle9869qxa20 device pinout and pin configuration data sheet 13 rev. 1.0, 2017-03-03 p2 port 2 port 2 is a 5-bit general purpose input-only port. alternate functions c an be assigned and are listed in the port description. main function is listed below. p2.0/xtal1 29 i/i i an0 adc analog input 0 alternate function mapping see table 10 p2.2/xtal2 30 i/o i an2 adc analog input 2 alternate function mapping see table 10 p2.3 35 i i an3 adc analog input 3 alternate function mapping see table 10 p2.4 32 i i an4 adc analog input 4 alternate function mapping see table 10 p2.5 31 i i an5 adc analog input 5 alternate function mapping see table 10 power supply vs 45 p ? battery supply input vddp 40 p ? 2) i/o port supply (5.0 v). connect external buffer capacitor. vddc 38 p ? 3) core supply (1.5 v during active mode). do not connect external loads, connect external buffer capacitor. vddext 41 p ? external voltage supply output (5.0 v, 20 ma) gnd 19 p ? gnd digital gnd 28 p ? gnd digital gnd 39 p ? gnd analog monitor input mon 14 i ? high voltage monitor input lin interface lin 43 i/o ? lin bus interface input/output gnd_lin 42 p ? lin ground charge pump cp1h 48 p ? charge pump capacity 1 high, connect external c cp1l 1 p ? charge pump capacity 1 low, connect external c cp2h 3 p ? charge pump capacity 2 high, connect external c cp2l 4 p ? charge pump capacity 2 low, connect external c vcp 2 p ? charge pump capacity vsd 47 p ? battery supply input for charge pump mosfet driver vdh 44 p ? voltage drain high side mosfet driver sh2 6 p ? source high side fet 2 gh2 7 p ? gate high side fet 2 table 2 pin definitions and functions (cont?d) symbol pin number type reset state 1) function tle9869qxa20 device pinout and pin configuration data sheet 14 rev. 1.0, 2017-03-03 sh1 8 p ? source high side fet 1 gh1 9 p ? gate high side fet 1 sl 10 p ? source low side fet gl2 12 p ? gate low side fet 2 gl1 13 p ? gate low side fet 1 others gnd_ref 33 p ? gnd for varef varef 34 i/o ? 5v adc1 reference voltage, optional buffer or input op1 37 i ? negative operational amplifier input op2 36 i ? positive operational amplifier input tms 20 i i/o i/pd tms swd test mode select input serial wire debug input/output reset 22 i/o ? reset input, not available during sleep mode vbat_sense 46 i ? battery supply voltage sense input ep ? ? ? exposed pad, connect to gnd 1) only valid for digital ios 2) also named vdd5v. 3) also named vdd1v5. table 2 pin definitions and functions (cont?d) symbol pin number type reset state 1) function tle9869qxa20 modes of operation data sheet 15 rev. 1.0, 2017-03-03 4 modes of operation this highly integrated circuit contains analog and digita l functional blocks. an embe dded 32-bit microcontroller is available for system and interface cont rol. on-chip, low-dropout regulators are provided for internal and external power supply. an internal os cillator provides a cost effective clock that is particularly well suited for lin communications. a lin transceiver is available as a comm unication interface. driver stages for an h-bridge with external mosfet are integr ated, featuring pwm capabilit y, protection featur es and a charge pump for operation at low supply voltage. a 10-bit sar ad c is implemented for high precision sensor measurement. an 8-bit adc is used for diagnostic measurements. the micro controller unit supervision and system protection (including a reset feature) is complemented by a programmable window watchdog. a cyclic wake-up circuit, supply voltage supervision and integrated temperature sensors are available on-chip. all relevant modules offer power saving modes in order to support automotive applications connected to terminal 30. a wake-up from power-save mode is possible via a lin bus message, via the monitoring input or using a programmable time period (cyclic wake-up). featuring lti, the integrated circuit is available in a vqfn-48-31 package with 0.5 mm pitch, and is designed to withstand the severe conditions of automotive applications. the tle9869qxa20 has several operation modes mainly to support low power consumption requirements. reset mode the reset mode is a transition mode used e.g. during powe r-up of the device after a power-on reset, or after wake- up from sleep mode. in this mode, the on-chip power su pplies are enabled and all other modules are initialized. once the core supply vddc is stable, the device enters active mode. if t he watchdog timer wdt1 fails more than four times, the device performs a fail-safe transition to sleep mode. active mode in active mode, all modules are activated and the tle9869qxa20 is fully operational. stop mode stop mode is one of two major low power modes. the tran sition to the low power modes is performed by setting the corresponding bits in the mode co ntrol register. in stop mode the embedded microcontroller is still powered, allowing faster wake-up response time s. wake-up from this mode is possible through lin bus activity, by using the high-voltage monitoring pin or the corresponding 5v gpios. stop mode with cyclic wake-up the cyclic wake-up mode is a specia l operating mode of the stop mode. the transition to the cyclic wake-up mode is done by first setting the corresponding bits in the mode control register followed by the stop mode command. in addition to the cyclic wake-up behavior (wake-up after a programmable time period), asynchronous wake events via the activated sources (lin and/or mon) are available, as in normal stop mode . sleep mode the sleep mode is a low-power mode. the transition to the low-power mode is done by setting the corresponding bits in the mcu mode control register or in case of fa ilure, see below. in sleep mode the embedded microcontroller power supply is deactivated allowing the lowest system power consumption. a wake-up from this mode is possible by lin bus activity, the high voltage monitor input pin or cyclic wake-up. sleep mode in case of failure tle9869qxa20 modes of operation data sheet 16 rev. 1.0, 2017-03-03 sleep mode is activated after 5 consecutive watchdog failures or in case of supply failure (5 times). in this case, mon is enabled as the wake so urce and cyclic wake-up is activated with 1s of wake time. sleep mode with cyclic wake-up the cyclic wake-up mode is a special operating mode of the sleep mode. the transiti on to cyclic wake-up mode is performed by first setting the corresponding bits in the mode control register fo llowed by the sleep and stop mode command. in addition to the cyclic wake-up behavior (wake-up after a programmable time period), asynchronous wake events via the activated sources (lin and/or mon) are available, as in normal sleep mode . when using sleep mode with cyclic wake-up the voltage re gulator is switched off and started again with the wake. a limited number of registers is buffered during sleep, and can be used by sw e.g. for counting sleep/wake cycles. mcu slow down mode in mcu slow down mode the mcu frequency is reduced for saving power during operation. lin communication is still possible. ls mosfet can be activated. wake-up source prioritization all wake-up sources have the same priority. in order to handle the asynchronous nature of the wake-up sources, the first wake-up signal will in itiate the wake-up se quence. nevertheless all wake-up sources are latched in order to provide all wake-up events to the application software . the software can clear the wake-up source flags. this is to ensure that no wake-up event is lost. as default wake-up source, the mon input is activated a fter power-on reset only. additionally, the device is in cyclic wake-up mode with the max. configurable dead time setting. the following table shows the possible power mode configurations including the stop mode. table 3 power mode configurations module/function active mode stop mode sleep mode comment vddext on/off on (no dynamic load)/off off ? bridge driver on/off off off lin trx on/off wake-up only/ off wake-up only/ off ? vs sense on/off brownout detection brownout detection por on vs brownout det. done in pcu vbat_sense on/off off off ? gpio 5v (wake-up) n.a. disabled/static off ? gpio 5v (active) on on off ? wdt1 on off off ? cyclic wake n.a. cyclic wake-up/ cyclic sense/off cyclic wake-up/ off ? measurement on 1) off off ? mcu on/slow- down/stop stop 2) off ? clock gen (mc) on off off ? tle9869qxa20 modes of operation data sheet 17 rev. 1.0, 2017-03-03 wake-up levels and transitions the wake-up can be trigge red by rising, falling or both signal edges for the mo nitor input, by lin or by cyclic wake- up. lp_clk (18 mhz) on off off wdt1 lp_clk2 (100 khz) on/off on/off on/off for cyclic wake-up 1) may not be switched off due to safety reasons 2) mc pll clock disabled, mc supply reduced to 1.1 v table 3 power mode configurations (cont?d) module/function active mode stop mode sleep mode comment tle9869qxa20 power management unit (pmu) data sheet 18 rev. 1.0, 2017-03-03 5 power management unit (pmu) 5.1 features ? system modes control (startup, sleep, stop and active) ? power management (cyclic wake-up) ? control of system voltage re gulators with diagnosis (overload, short, overvoltage) ? fail safe mode detection and operation in case of system errors (watchdog fail) ? wake-up sources configuration and management (lin, mon, gpios) ? system error logging 5.2 introduction the power management unit is responsible for generating all required voltage supplies for the embedded mcu (vddc, vddp) and the external supply (vddext). the power management unit is designed to ensure fail-safe behavior of the system ic by controlling all system modes including the correspon ding transitions. additionally, the pmu provides well defined sequences for the system mode tr ansitions and generates hierarchical reset priorities. the reset priorities control the reset behavior of all syst em functionalities especially the reset behavior of the embedded mcu. all these functions are controlled by a st ate machine. the system master functionality of the pmu make use of an independent logic supply and system clock. for this reason, th e pmu has an "internal logic supply and system clock" module whic h works independently of the mcu clock. tle9869qxa20 power management unit (pmu) data sheet 19 rev. 1.0, 2017-03-03 5.2.1 block diagram the following figure shows the structure of the power management unit. table 4 describes the submodules in more detail. figure 3 power management unit block diagram table 4 description of pmu submodules mod. name modules functions power down supply independent supply voltage generation for pmu this supply is dedicated to the pmu to ensure an independent operation from generated power supplies (vddp, vddc). lp_clk (= 18 mhz) - clock source for all pmu submodules - backup clock source for system - clock source for wdt1 this ultra low power oscillato r generates the clock for the pmu. this clock is also used as backup clock for the system in case of pll clock failure and as an independent clock source for wdt1. lp_clk2 (= 100 khz) clock source for pmu this ultra low power oscillator generates the clock for the pmu in stop mode and in the cyclic modes. peripherals peripheral blocks of pmu these blocks include the analog peripherals to ensure a stable and fail-safe pmu startup and operation (bandgap, bias). power_management_7x.vsd power down supply lp_clk lp_clk2 peripherals power supply generation unit (pgu) ldo for external supply vddext pmu-wmu p1.0...p1.4 p0.0...p0.4 lin mon pmu-pcu pmu-sfr pmu-rmu pmu-cmu e.g. for wdt 1 e.g. for cyclic wake and sense vs vddp vddc vddext power management unit pmu-control i n t e r n a l b u s tle9869qxa20 power management unit (pmu) data sheet 20 rev. 1.0, 2017-03-03 power supply generation unit (pgu) voltage regulators for vddp and vddc this block includes the voltage regulators for the pad supply (vddp) and the core supply (vddc). vddext voltage regula tor for vddext to supply external modules (e.g. sensors) this voltage regulator is a dedicated supply for external modules and can also be used for cyclic sense operations (e.g. with hall sensor). pmu-sfr all extended special function registers that are relevant to the pmu. this module contains all registers needed to control and monitor the pmu. pmu-pcu power control unit of the pmu this block is responsible for cont rolling all power related actions within the pgu module. it also contains all regulator related diagnostics such as undervoltage and overvoltage detection as we ll as overcurrent and short circuit diagnostics. pmu-wmu wake-up management unit of the pmu this block is responsible for controlling all wa ke-up related actions within the pmu module. pmu-cmu cyclic management unit of the pmu this block is responsible fo r controlling all actions in cyclic mode. pmu-rmu reset management unit of the pmu this bloc k generates resets triggered by the pmu such as undervoltage or short circuit reset, and passes all resets to the relevant modules and their register. table 4 description of pmu submodules (cont?d) mod. name modules functions tle9869qxa20 power management unit (pmu) data sheet 21 rev. 1.0, 2017-03-03 5.2.2 pmu modes overview the following state diagram shows the available modes of the device. figure 4 power management unit system modes start-up active stop sleep stop command (from mcu) lin-wake or mon-wake or gpio-wake or cyclic _wake or pmu_pin = 1 or sup_tmout = 1 vddc =stable and error_supp<5 error_supp=5 v s > 4v and v s ramp up or v s < 3v and v s ramp down lin-wake or mon-wake or cyclic -wake vddc / vddp = fail (short circuit) ? error_supp ++ sleep command (from mcu) or wdt1_seq_fail = 1 ( ? error_wdt = 5) or vddc / vddp = overload pmu_pin = 1 or pmu_soft = 1 or (pmu_ext_wdt = 1 and wdt1_seq_fail = 0 ? error_wdt ++) cyclic -sense tle9869qxa20 power management unit (pmu) data sheet 22 rev. 1.0, 2017-03-03 5.3 power supply gene ration unit (pgu) 5.3.1 voltage regulator 5.0v (vddp) this module represents the 5 v voltage regulator, which pr ovides the pad supply for the parallel port pins and other 5 v analog functions (e .g. lin transceiver). features ? 5 v low-drop voltage regulator ? overcurrent monitoring and shutdown with mcu signaling (interrupt) ? overvoltage monitoring with mcu signaling (interrupt) ? undervoltage monitoring with mcu signaling (interrupt) ? undervoltage monitoring with re set (undervoltage reset, v ddpuv ) ? pre-regulator for vddc regulator ? gpio supply ? pull down current source at the output for sleep mode only (typ. 5 ma) the output capacitor c vddp is mandatory to ensure proper regulator functionality. figure 5 module block diagram of vddp voltage regulator 5v ldo ldo supervision vs pmu_5v_overload pmu_5v_overvolt vddp regulator v i a vpre vddp c vddp gnd (pin 39) tle9869qxa20 power management unit (pmu) data sheet 23 rev. 1.0, 2017-03-03 5.3.2 voltage regulator 1.5v (vddc) this module represents the 1.5 v voltage regulator, which provides the supply for the microcontroller core, the digital peripherals and other internal analog 1.5 v function s (e.g. adc2) of the chip. to further reduce the current consumption of the mcu during stop mode th e output voltage can be lowered to 1.1 v. features ? 1.5 v low-drop vo ltage regulator ? overcurrent monitoring and shutdown with mcu signaling (interrupt) ? overvoltage monitoring with mcu signaling (interrupt) ? undervoltage monitoring with mcu signaling (interrupt) ? undervoltage monitoring with reset ? pull down current source at the output for sleep mode only (typ. 100 a) the output capacitor c vddc is mandatory to ensure a pr oper regulator functionality. figure 6 module block diagram of vddc voltage regulator 1.5v ldo vddc (1.5v) ldo supervision vddp (5v) pmu_1v5_overload pmu_1v5_overvolt c vddp c vddc vddc r egulator a i v gnd (pin 39) tle9869qxa20 power management unit (pmu) data sheet 24 rev. 1.0, 2017-03-03 5.3.3 external voltage re gulator 5.0v (vddext) this module represents the 5 v voltage regulator, which serves as a supply for extern al circuits. it can be used e.g. to supply an external sensor, leds or potentiometers. features ? switchable +5 v, low-dr op voltage regulator ? switch-on overcurrent blanking time in order to drive small capacitive loads ? overcurrent monitoring and shutdown with mcu signaling (interrupt) ? overvoltage monitoring with mcu signaling (interrupt) ? undervoltage monitoring with mcu signaling (interrupt) ? pull down current source at the output for sleep mode only (typ. 100 a) ? cyclic sense option together with gpios the output capacitor c vddext is mandatory to ensure a proper regulator functionality. figure 7 module block diagram of external voltage regulator 5v ldo ldo supervision vs vddext_overload vddext_overvolt vddext regulator v i a vpre vddext c vddext gnd (pin 39) vddext_short tle9869qxa20 system control unit - digital modules (scu-dm) data sheet 25 rev. 1.0, 2017-03-03 6 system control unit - digital modules (scu-dm) 6.1 features ? flexible clock conf iguration features ? reset management of all system resets ? system modes control for all power modes (active, power down, sleep) ? interrupt enabling for many system peripherals ? general purpose input output control ? debug mode control of system peripherals 6.2 introduction the system control unit (scu) suppor ts all central control tasks in the tle9869qxa20. the scu is made up of the following sub-modules: ? clock system and control ? reset control ? power management ? interrupt management ? general port control ? flexible peripheral management ? module suspend control ? watchdog timer ? error detection and corr ection in data memory ? miscellaneous control tle9869qxa20 system control unit - digital modules (scu-dm) data sheet 26 rev. 1.0, 2017-03-03 6.2.1 block diagram figure 8 system control unit - digital modules block diagram ahb (advanced high-performance bus) pmcu (power module control unit) wdt (watchdog timer in scu-dm) ? f sys system clock cgu (clock generation unit) ? f sys system clock ? f pclk peripheral clock system control unit -digital modules pmcu ahb on signals to digital peripherals; status signals from digital peripherals cgu f sys lp_clk wdt icu i n t e r n a l b u s nmi intisr <9:0> f sys rcu pmu_1v5didpor port control p0_pocony.pdmx misc control modpiselx pmu_pin pmu_extwdt pmu_intwdt pmu_soft pmu_wake reset_type_3 reset_type_4 p1_pocony.pdmx f mi_clk f tfilt _clk f pclk xtal1 xtal2 pll cg f pll osc_hp f osc tle9869qxa20 system control unit - digital modules (scu-dm) data sheet 27 rev. 1.0, 2017-03-03 ? f mi_clk measurement interface clock ? f tfilt_clk analog module filter clock ? lp_clk clock source for all pmu submodules and wdt1 icu (interrupt control unit) ? nmi (non-maskable interrupt) ? intisr<15,13:4,1,0> external interrupt signals rcu (reset control unit) ? pmu_1v5didpor undervoltage reset of power down supply ? pmu_pin reset generated by reset pin ? pmu_extwdt wdt1 reset ? pmu_intwdt wdt (scu) reset ? pmu_soft software reset ? pmu_wake sleep mode/stop mode exit with reset ? reset_type_3 peripheral re set (contains all resets) ? reset_type_4 peripheral reset (without soft and wdt reset) port control ? p0_pocony.pdmx driver strength control ? p1_pocony.pdmx driver strength control misc control ? modpiselx mode selection registers for uart (source section) and timer (trigger or count selection) 6.3 clock generation unit the clock generation unit (cgu) enables a flexible cloc k generation for tle9869qxa20. during user program execution, the frequency can be modified to optimize the performance/power cons umption ratio, allowing power consumption to be adapted to the actual application state. the cgu in the tle9869qxa20 consists of one oscillator circuit (osc_h p), a phase-locked loop (pll) module with an internal oscillator (o sc_pll), and a clock control unit (ccu). the cgu can convert a low-frequency input/external clock signal to a high-frequency internal clock. the system clock f sys is generated from of the following selectable clocks: ? pll clock output f pll ? direct clock from oscillator osc_hp f osc ? low precision clock f lp_clk (hw-enabled for startup after reset and during power-down wake-up sequence) tle9869qxa20 system control unit - digital modules (scu-dm) data sheet 28 rev. 1.0, 2017-03-03 figure 9 clock generation unit block diagram the following sections describe t he different parts of the cgu. 6.3.1 low precision clock the clock source lp_clk is a low-precision rc oscillato r (lp-osc) with a nominal frequency of 18 mhz that is enabled by hardware as an independent clock source for the tle9869qxa20 startup after reset and during the power-down wake-up sequence. f lp_clk is not user configurable. 6.3.2 high precisi on oscillator ci rcuit (osc_hp) the high precision oscillator circuit, designed to work with both an external crystal os cillator or an external stable clock source, consists of an inverting amplifie r with xtal1 as the input, and xtal2 as the output. figure 10 shows the recommended external circuitry for both operating modes, external crystal mode and external input clock mode. 6.3.2.1 external input clock mode when supplying the clock signal direct ly, not using an external crystal a nd bypassing the oscillator, the input frequency needs to be equal or greater than 4 mhz if the pll vco part is used. when using an external clock signal it must be connected to xtal1. xtal2 is left open (unconnected). 6.3.2.2 external crystal mode when using an external crystal, its fr equency can be withi n the range of 4 mhz to 25 mhz. an external oscillator load circuitry must be used, connected to both pins, xtal1 and xtal2. it normally consists of the two load capacitances c1 and c2. a series damping resistor could be required for some crystals. the exact values and the corresponding operating ranges depend on the crystal and have to be determined and optimized in cooperation with the crystal vendor using the negative resistance method. the following load cap values can be used as starting point for the evaluation: hposccon osc_hp cgu ccu pll cmcon pllcon f pll cgu_block syscon0 osc_con lp_clk f lp_clk f sys f osc pmu lp_clk xtal1 xtal2 tle9869qxa20 system control unit - digital modules (scu-dm) data sheet 29 rev. 1.0, 2017-03-03 figure 10 tle9869qxa20 external circuitry for the osc_hp table 5 external cap capacitors fundamental mode crystal frequency (approx., mhz) load caps c 1 , c 2 (pf) 433 818 12 12 16 10 20 10 25 8 ext_osc .vsd osc_hp 4 - 25 mhz c 2 osc_hp xtal1 xtal2 external clock signal fundamental mode crystal external crystal mode external input clock mode v ss = gnd = pin 39 v ss f osc v ddp f osc xtal1 xtal2 v ss v ddp c 1 tle9869qxa20 system control unit - power modules (scu-pm) data sheet 30 rev. 1.0, 2017-03-03 7 system control unit - power modules (scu-pm) 7.1 features ? clock watchdog unit (cwu): superv ision of all clocks with nmi sign aling relevant to power modules ? interrupt control unit (icu): all interrupt flags and status flags with system relevance ? power control unit (pcu): takes over control wh en device enters and exits sleep and stop mode ? external watchdog (wdt1): independent system watchdog for monitoring system activity 7.2 introduction 7.2.1 block diagram the system control unit of the power modules consis ts of the sub-modules in the figure shown below: figure 11 block diagram of system control unit - power modules ahb (advanced high-performance bus) cwu (clock watchdog unit) ? f sys system frequen cy: pll output ? mi_clk measurement interface clock (analog clock): derived from fsys using division factors 1/2/3/4 ? tfilt_clk clock used for digita l filters: derived from fsys usin g configurable division factors system control unit -power modules pcu ahb on signals to analog peripherals; status signals from analog peripherals cwu fsys mi_clk tfilt_clk wdt1 icu i n t e r n a l b u s prewarn_sup_nmi prewarn_sup_int int tle9869qxa20 system control unit - power modules (scu-pm) data sheet 31 rev. 1.0, 2017-03-03 wdt1 (system watchdog) ? lp_clk clock source for all pmu submodules and wdt1 icu (interrupt control unit) ? prewarn_sup_nmi supply prewarning nmi request ? prewarn_sup_int supply prewarning interrupt ? grouping of peripheral interrupts for external interupt nodes: ? grouping single peripheral interrupts for in terrupt node int<2> (measurement unit (mu)) ? grouping single peripheral interrupts for interrupt node int<3> (adc1-varef) ? grouping single peripheral interrupts for interrupt node int<10> (uart1-lin transceiver) ? grouping single peripheral interrupts for interrupt node int<14> (bridge driver) tle9869qxa20 arm cortex-m3 core data sheet 32 rev. 1.0, 2017-03-03 8 arm cortex-m3 core 8.1 features the key features of the cortex -m3 implemented are listed below. processor core; a low gate count core, with low latency interrupt processing: ? a subset of the thumb ? -2 instruction set ? banked stack pointer (sp) only ? 32-bit hardware divide instructions, sd iv and udiv (thumb-2 instructions) ? handler and thread modes ? thumb and debug states ? interruptible-continued instructions ldm/ stm, push/pop for low interrupt latency ? automatic processor st ate saving and restoration for low latency in terrupt service routine (isr) entry and exit ? arm architecture v7-m style be8/le support ? armv6 unaligned accesses nested vectored interrupt controller (nvic) closely integrated with the processor core to achieve low latency interrupt processing: ? interrupts, configurable from 1 to 16 ? bits of priority (4) ? dynamic reprioritization of interrupts ? priority grouping. this enables selection of preemptive interrupt levels and non-preemptive interrupt levels ? support for tail-chaining and late arrival of interrupts . this enables back-to-back interrupt processing without the overhead of state saving an d restoration between interrupts. ? processor state automatically saved on interrupt entr y, and restored on interrupt exit, with no instruction overhead bus interfaces ? advanced high-performance bus-lite (ahb-lite) inte rfaces: icode, dcode, and system bus interface ? memory access alignment ? write buffer for buffering of write data tle9869qxa20 arm cortex-m3 core data sheet 33 rev. 1.0, 2017-03-03 8.2 introduction the arm cortex-m3 processor is a leading 32-bit proces sor and provides a high-performance and cost-optimized platform for a broad range of applications including microcontrollers, automotive body systems and industrial control systems. like the other cortex family proc essors, the cortex-m3 processor implements the thumb ? -2 instruction set architecture. with the optimized feature set the cortex -m3 delivers 32-bit performance in an application space that is usually associat ed with 8- and 16-bit microcontrollers. 8.2.1 block diagram figure 12 shows the functional blocks of the cortex-m3. figure 12 cortex-m3 block diagram cortex_ m3 _block_diagram .vsd ahb access port (ahb-ap) bus matrix cortex-m3 processor core nested vectored interrupt controller (nvic) serial-wire (sw-dp) cortex-m3 processor serial-wire debug interface interrupt and power control icode ahb-lite instruction interface system bus icode pba0 pba1 dcode ahb-lite data interface tle9869qxa20 dma controller data sheet 34 rev. 1.0, 2017-03-03 9 dma controller figure 13 shows the top level block diagram of the tle9869qxa20. the bus matrix allows the dma to access the pba0, pba1 and ram. 9.1 features the principal features of the dma controller are that: ? it is compatible with ahb- lite for the dma transfers ? it is compatible with apb fo r programming the registers ? it has a single ahb-lite master for transferring data using a 32-bit address bus and 32-bit data bus ? it supports 13 dma channels ? each dma channel has dedicated handshake signals ? each dma channel has a programmable priority level ? each priority level arbitrates using a fixed priority that is determined by the dma channel number. the dma also supports multiple transfer types: - memory-to-memory - memory-to-peripheral - peripheral-to-memory ? it supports multiple dma cycle types ? it supports multiple dma transfer data widths ? each dma channel can access a primary, and alternate, channel control data structure ? all the channel control data is stored in system memory (ram) in little-endian format ? it performs all dma transfers using the single ahb-lite burst type. the destination da ta width is equal to the source data width. ? the number of transfers in a single dma cycle can be programmed from 1 to 1024 ? the transfer address increment can be greater than the data width tle9869qxa20 dma controller data sheet 35 rev. 1.0, 2017-03-03 9.2 introduction please also refer to chapter 9.3 , functional description . 9.2.1 block diagram figure 13 dma controller top level block diagram dma controller arm core apb interface bus matrix ahb lite ssc1 adc1 interrupts scu_dm interrupts ahb lite a h b l i t e ahb lite dma requests dma requests pba1 ahb lite ahb2apb m m m m m s s s s s ahb lite ram pba0 ahb lite m m s s dma requests timer3 tle9869qxa20 dma controller data sheet 36 rev. 1.0, 2017-03-03 9.3 functional description 9.3.1 dma mode overview the dma controller implements the following 13 hardware dma requests: ? adc1 complete sequence 1 done: dma transfer is requ ested on completion of t he adc1 channel conversion sequence. ? adc1 exceptional sequence 2 (esm) done: dma transfer is requested on completion of the adc1 conversion sequence triggered by an exceptional measurement request. ? ssc1/2 transmit byte: dma transfer is requested upon the completion of data transmission via ssc1/2 ? ssc1/2: receive byte: dma transf er is requested upon the completion of data reception via ssc1/2. ? adc1 channel 0 conversion done: dma transfer is re quested on completion of the adc1 channel 0 conversion. ? adc1 channel 1 conversion done: dma transfer is re quested on completion of the adc1 channel 1 conversion. ? adc1 channel 2 conversion done: dma transfer is re quested on completion of the adc1 channel 2 conversion. ? adc1 channel 3 conversion done: dma transfer is re quested on completion of the adc1 channel 3 conversion. ? adc1 channel 4 conversion done: dma transfer is re quested on completion of the adc1 channel 4 conversion. ? adc1 channel 5 conversion done: dma transfer is re quested on completion of the adc1 channel 5 conversion. ? adc1 channel 6 conversion done: dma transfer is re quested on completion of the adc1 channel 6 conversion. ? adc1 channel 7 conversion done: dma transfer is re quested on completion of the adc1 channel 7 conversion. ? timer3 ccu6_int: dma transfer is re quested following a timer trigger. tle9869qxa20 address space organization data sheet 37 rev. 1.0, 2017-03-03 10 address space organization the tle9869qxa20 manipulates operands in the following memory spaces: ? 128 kbyte of flash memory in code space ? 32 kbyte boot rom memory in code spac e (used for boot code and ip storage) ? 6 kbyte ram memory in code space and data space (ram can be read/written as program memory or external data memory) ? special function registers (sfrs) in peripheral space the figure below shows the detailed address alignment of tle9869qxa20: figure 14 tle9869qxa20 memory map / e00fffff h e0000000 h reserved (bootrom) 00000000 h flash , 128k 00008000 h / 10ffffff h 11000000 h / 1101ffff h sram, 6k 18000000 h / 180017ff h reserved 18001800 h / 3fffffff h pba0 40000000 h / 47ffffff h pba1 48000000 h / 5fffffff h reserved 60000000 h / dfffffff h private peripheral bus reserved ffffffff h reserved 11020000 h / 17ffffff h tle9869qxa20 memory control unit data sheet 38 rev. 1.0, 2017-03-03 11 memory control unit 11.1 features ? handles all system memories an d their interaction with the cpu ? memory protection functions for all s ystem memories (d-flash, p-flash, ram) ? address management with access vi olation detection including reporting ? linear address range for all memories (no paging) 11.2 introduction 11.2.1 block diagram the memory control unit (mcu) is divided in the following sub-modules: ? nvm memory module (embedded flash memory) ? ram memory module ? bootrom memory module ? memory protection unit (mpu) module ? peripheral bridge pba0 tle9869qxa20 memory control unit data sheet 39 rev. 1.0, 2017-03-03 figure 15 mcu block view mcu_block_diagram_overview.vsd bus matrix ram brom s0 memory protection unit s1 s2 nvm code/ data m1 m2 ram code/ data rom code/ data m0 pba0 s3 m3 sx: bus slave mx: bus master nvm tle9869qxa20 memory control unit data sheet 40 rev. 1.0, 2017-03-03 11.3 nvm module (flash memory) the flash memory provides an embedded user-programma ble non-volatile memory, allowing fast and reliable storage of user code and data. features ? in-system programming via lin (flash mode) and swd ? error correction code (ecc) for dete ction of single-bit and double-bit erro rs and dynamic correction of single bit errors. ? interrupts and signals double-bit error by nmi ? program width of 128 byte (page) ? minimum erase width of 128 bytes (page) ? integrated hardw are support for eeprom emulation ? 8 byte read access ? physical read access time: 75 ns ? code read access acceleration integrated; read buffer and automatic pre-fetch ? page program time: 3 ms ? page erase (128 bytes) and sector erase (4k bytes) time: 4ms note: the user has to ensure that no flash operations wh ich change the content of the flash get interrupted at any time. the clock for the nvm is supplied with th e system frequency fsys. integrated firmware routines are provided to erase nvm, and other operations includin g eeprom emulation are provided as well. data sheet 41 rev. 1.0, 2017-03-03 tle9869qxa20 interrupt system 12 interrupt system 12.1 features ? up to 16 interrupt nodes for on-chip peripherals ? up to 8 nmi nodes for critical system events ? maximum flexibility fo r all 16 interrupt nodes 12.2 introduction before enabling an interrupt, all correspondi ng interrupt status flags should be cleared. 12.2.1 overview the tle9869qxa20 supports 16 interrupt vectors with 16 pr iority levels. fifteen of these interrupt vectors are assigned to the on-chip peripherals: gpt12, ssc, ccu6, dma, bridge driver and a/d converter are each assigned to one dedicated interrupt vector; while uart1 a nd timer2 or uart2, external interrupt 2 and timer21 share interrupt vectors. two vectors are dedicated for external interrupt 0 and 1. table 6 interrupt vector table service request node id description gpt12 0/1 gpt interrupt (t2-t6, capin) mu- adc8/t3 2 measurement unit, vbg, timer3 adc1 3 adc1 interrupt / vref5v over load / vref5v ov/uv, 10-bit adc ccu0 4 ccu6 node 0 interrupt ccu1 5 ccu6 node 1 interrupt ccu2 6 ccu6 node 2 interrupt ccu3 7 ccu6 node 3 interrupt ssc1 8 ssc1 interrupt (receive, transmit, error) ssc2 9 ssc2 interrupt (receive, transmit, error) uart1 10 uart1 (asc-lin) interrupt (recei ve, transmit), timer2, linsync1, lin uart2 11 uart2 interrupt (receive, transmit), timer21, external interrupt (eint2) exint0 12 external inte rrupt (eint0), mon exint1 13 external in terrupt (eint1) bdrv/cp 14 bridge driver / charge pump dma 15 dma controller table 7 nmi interrupt table service request node description watchdog timer nmi nmi watchdog timer overflow pll nmi nmi pll loss-of-lock nvm operation complete nmi nmi nvm operation complete overtemperature nmi nmi system overtemperature data sheet 42 rev. 1.0, 2017-03-03 tle9869qxa20 interrupt system oscillator watchdog nmi nmi oscillator watchdog / mi_clk watchdog timer overflow nvm map error nmi nmi nvm map error ecc error nmi nmi ram / nvm uncorrectable ecc error supply prewarning nmi nmi supply prewarning table 7 nmi interrupt table service request node description tle9869qxa20 watchdog timer (wdt1) data sheet 43 rev. 1.0, 2017-03-03 13 watchdog timer (wdt1) 13.1 features there are two watchdog timers in the system. the watchdog timer (wdt) within the system control unit - digital modules (see scu_dm) and the watchdog timer (wdt1) located within the system control unit - power modules (see scu_pm). the watchdog time r wdt1 is described in this section. in active mode, the wdt1 acts as a windowed watchdog timer, which provides a high ly reliable and safe way to recover from software or hardware failures. the wdt1 is always enabled in ac tive mode. in sleep mode, low power mode and swd mode the wdt1 is automatically disabled. functional features ? windowed watchdog timer with programmable timing in active mode ? long open window (typ. 80ms) after power-up, reset, wake-up ? short open window (typ. 30ms) to facilitate flash programming ? disabled during debugging ? safety shutdown to sleep mode after 5 missed wdt1 services tle9869qxa20 watchdog timer (wdt1) data sheet 44 rev. 1.0, 2017-03-03 13.2 introduction the behavior of the watchdog timer in active mode is illustrated in figure 16 . figure 16 watchdog timer behavior trigger & count_sow = 0 always timeout reset reset reset trigger sow & count_sow++ trigger sow & count_sow++ trigger & count_sow = 0 timeout or trigger in closed window reset power-up timeout long open window normal ?windowed? operation short open window & sow trigger & count_sow = 0 maximum number of count_sow trigger sow data sheet 45 rev. 1.0, 2017-03-03 tle9869qxa20 gpio ports and peripheral i/o 14 gpio ports and peripheral i/o the tle9869qxa20 has 15 port pins organized into three pa rallel ports: port 0 (p0), port 1 (p1) and port 2 (p2). each port pin has a pair of internal pull-up and pull-down devices that can be individu ally enabled or disabled. p0 and p1 are bidirectional and can be used as general purpose input/output (gpio) or to perform alternate input/output functions for the on-chip peripherals. when configured as an output, the open drain mode can be selected. on port 2 (p2) analog inputs are shared with general purpose input. 14.1 features bidirectional port features (p0, p1) ? configurable pin direction ? configurable pull-up/ pull-down devices ? configurable open drain mode ? configurable drive strength ? transfer of data through digital inputs and outputs (general purpose i/o) ? alternate input/output for on-chip peripherals analog port features (p2) ? configurable pull-up/ pull-down devices ? transfer of data through digital inputs ? alternate inputs for on-chip peripherals 14.2 introduction 14.2.1 port 0 and port 1 figure 17 shows the block diagram of an tle9869qxa20 bidirect ional port pin. each port pin is equipped with a number of control and data bits, thus enabling very flexible usage of the pin. by defini ng the contents of the control register, each individual pin can be c onfigured as an input or an output. th e user can also configure each pin as an open drain pin with or without internal pull-up/pull-down device. each bidirectional port pin can be configured for inpu t or output operation. switching between input and output mode is accomplished through the regist er px_dir (x = 0 or 1), which enables or disables the output and input drivers. a port pin can only be configured as either input or output mode at any one time. in input mode (default after reset), the output driver is switched off (high-impedance). the voltage level present at the port pin is translated into a logic 0 or 1 via a schmi tt trigger device and can be read via the register px_data. in output mode, the output driver is activated and drives the value supplied through the multiplexer to the port pin. in the output driver, each port line can be switched to op en drain mode or normal mode (push-pull mode) via the register px_od. the output multiplexer in front of the output driver ena bles the port output function to be used for different purposes. if the pin is used for general purpose output, the multiplexer is switched by so ftware to the data register px_data. software can set or clear th e bit in px_data and therefore directly influence the state of the port pin. if an on-chip peripheral uses the pin fo r output signals, alternate output lines (altdataout) can be switched via the multiplexer to the output driver circui try. selection of the alternate output function is defined in registers px_altsel0 and px_altsel1. when a port pin is used as an alternate function, its direction must be set accordingly in the register px_dir. data sheet 46 rev. 1.0, 2017-03-03 tle9869qxa20 gpio ports and peripheral i/o each pin can also be programmed to activate an intern al weak pull-up or pull-down device. register px_pudsel selects whether a pull-up or the pull-down device is acti vated while register px_puden enables or disables the pull device. figure 17 general structure of bidirectional port (p0, p1) od open drain control register px_data data register altdataout 3 altdataout 2 altsel0 alternate select register 0 altsel1 alternate select register 1 altdatain puden pull-up / pull-down enable register dir direction register pudsel pull-up / pull-down select register pull-up / pull-down control logic altdataout 1 pad out in pull device output driver input driver schmitt trigger px_pocony port output driver control registers tccr temperature compensation control register i n t e r n a l b u s 11 10 00 01 data sheet 47 rev. 1.0, 2017-03-03 tle9869qxa20 gpio ports and peripheral i/o 14.2.2 port 2 figure 18 shows the structure of an input-on ly port pin. each p2 pin can onl y function in input mode. register p2_dir is provided to enable or disable the input driver. wh en the input driver is enabl ed, the actual voltage level present at the port pin is translated into a logic 0 or 1 via a schmitt trigger device and can be read via register p2_data. each pin can also be programmed to activate an internal weak pull-up or pull-down device. register p2_pudsel selects whether a pull-up or the pull-down de vice is activated while register p2_puden enables or disables the pull device. the analog in put (analogin) bypasses the digital circ uitry and schmitt trigger device for direct feed-through to the adc input channels. figure 18 general structure of input port (p2) data data register altdatain puden pull-up / pull-down enable register pudsel pull-up / pull-down select register pull-up / pull-down control logic analogin pad in pull device input driver schmitt trigger i n t e r n a l b u s data sheet 48 rev. 1.0, 2017-03-03 tle9869qxa20 gpio ports and peripheral i/o 14.3 tle9869qxa20 port module 14.3.1 port 0 14.3.1.1 port 0 functions table 8 port 0 input/output functions port pin input/output select connected signal(s) from/to module p0.0 input gpi p0_data.p0 inp1 swclk / tck_0 sw inp2 t12hr_0 ccu6 inp3 t4ina gpt12t4 inp4 t2_0 timer 2 inp5 ? ? inp6 exint2_3 scu output gpo p0_data.p0 alt1 t3out gpt12t3 alt2 exf21_0 timer 21 alt3 rxdo_2 uart2 p0.1 input gpi p0_data.p1 inp2 t13hr_0 ccu6 inp3 txd1 lin_txd inp4 capina gpt12cap inp5 t21_0 timer 21 inp6 t4inc gpt12t4 inp7 mrst_1_2 ssc1 inp8 exint0_2 scu output gpo p0_data.p1 alt1 txd1 uart1 / lin_txd alt2 ? ? alt3 t6out gpt12t6 data sheet 49 rev. 1.0, 2017-03-03 tle9869qxa20 gpio ports and peripheral i/o p0.2 input gpi p0_data.p2 inp1 ccpos2_1 ccu6 inp2 t2euda gpt12t2 inp3 mtsr_1 ssc1 inp4 t21ex_0 timer 21 inp5 t6ina gpt12t6 output gpo p0_data.p2 ? alt1 cout60_0 ccu6 alt2 mtsr_1 ssc1 alt3 exf2_0 timer 2 p0.3 input gpi p0_data.p3 inp1 sck_1 ssc1 inp2 capinb gpt12 inp3 t5ina gpt12t5 inp4 t4euda gpt12t4 inp5 ccpos0_1 ccu6 output gpo p0_data.p3 alt1 sck_1 ssc1 alt2 exf21_2 timer 21 alt3 t6out gpt12t6 p0.4 input gpi p0_data.p4 inp1 mrst_1_0 ssc1 inp2 cc60_0 ccu6 inp3 t21_2 timer 21 inp4 exint2_2 scu inp5 t3euda gpt12t3 inp6 ccpos1_1 ccu6 output gpo p0_data.p4 alt1 mrst_1_0 ssc1 alt2 cc60_0 ccu6 alt3 clkout_0 scu table 8 port 0 input/output functions (cont?d) port pin input/output select connected signal(s) from/to module data sheet 50 rev. 1.0, 2017-03-03 tle9869qxa20 gpio ports and peripheral i/o 14.3.2 port 1 14.3.2.1 port 1 functions table 9 port 1 input / output functions port pin input/output select connected signal(s) from/to module p1.0 input gpi p1_data.p0 inp1 t3inc gpt12t3 inp2 t4eudb gpt12t4 inp3 cc61_0 ccu6 inp4 sck_2 ssc2 inp5 exint1_2 scu output gpo p1_data.p0 alt1 sck_2 ssc2 alt2 cc61_0 ccu6 alt3 exf21_3 timer 21 p1.1 input gpi p1_data.p1 inp1 ? ? inp2 t6euda gpt12t6 inp3 ? - inp4 mtsr_2 ssc2 inp5 t21_1 timer 21 inp6 exint1_0 scu output gpo p1_data.p1 ? alt1 mtsr_2 ssc2 alt2 cout61_0 ccu6 alt3 txd2_0 uart2 p1.2 input gpi p1_data.p2 inp1 t2ina gpt12t2 inp2 t2ex_1 timer 2 inp3 t21ex_3 timer 21 inp4 mrst_2_0 ssc2 inp5 rxd2_0 uart2 inp6 ccpos2_2 ccu6 inp7 exint0_1 scu output gpo p1_data.p2 alt1 mrst_2_0 ssc2 alt2 cout63_0 ccu6 alt3 t3out gpt12t3 data sheet 51 rev. 1.0, 2017-03-03 tle9869qxa20 gpio ports and peripheral i/o p1.3 input gpi p1_data.p3 inp1 t6inb gpt12t6 inp2 ? inp3 cc62_0 ccu6 inp4 t6eudb gpt12t6 inp5 ? inp6 ccpos0_2 ccu6 inp7 exint1_1 scu output gpo p1_data.p3 alt1 exf21_1 timer 21 alt2 cc62_0 ccu6 alt3 txd2_1 uart2 p1.4 input gpi p1_data.p4 inp1 exint2_1 scu inp2 t21ex_1 timer 21 inp3 t5euda gpt12t5 inp4 rxd1 uart1 inp5 t2inb gpt12t2 inp6 ccpos1_2 ccu6 inp7 mrst_1_3 ssc1 output gpo p1_data.p4 alt1 clkout_1 scu alt2 cout62_0 ccu6 alt3 rxd1 uart1 / lin_rxd table 9 port 1 input / output functions (cont?d) port pin input/output select connected signal(s) from/to module data sheet 52 rev. 1.0, 2017-03-03 tle9869qxa20 gpio ports and peripheral i/o 14.3.3 port 2 14.3.3.1 port 2 functions table 10 port 2 input functions port pin input/output select connected signal(s) from/to module p2.0 input gpi p2_data.p0 inp1 ccpos0_3 ccu6 inp2 - - inp3 t12hr_2 ccu6 inp4 exint0_0 scu inp5 cc61_2 ccu6 analog an0 adc xtal (in) xtal p2.2 input gpi p2_data.p2 inp1 ccpos2_3 ccu6 inp2 t13hr_2 ccu6 inp3 ? inp4 cc62_2 ccu6 analog an2 adc out xtal (out) xtal p2.3 input gpi p2_data.p3 inp1 ccpos1_0 ccu6 inp2 ctrap#_1 ccu6 inp3 t21ex_2 timer 21 inp4 cc60_1 ccu6 inp5 exint0_3 scu analog an3 adc p2.4 input gpi p2_data.p4 inp1 ctrap#_0 ccu6 inp2 t2eudb gpt12t2 inp3 mrst_1_1 ssc1 inp4 exint1_3 scu analog an4 adc p2.5 input gpi p2_data.p5 inp1 rxd2_1 uart2 inp2 t3eudb gpt12t3 inp3 mrst_2_1 ssc2 inp4 t2_1 timer 2 analog an5 adc data sheet 53 rev. 1.0, 2017-03-03 tle9869qxa20 general purpose ti mer units (gpt12) 15 general purpose ti mer units (gpt12) 15.1 features 15.1.1 features block gpt1 the following list summarizes the supported features: ? f gpt /4 maximum resolution ? 3 independent timers/counters ? timers/counters can be concatenated ? 4 operating modes: ?timer mode ? gated timer mode ? counter mode ? incremental interface mode ? reload and capture functionality ? shared interrupt: node 0 15.1.2 features block gpt2 the following list summarizes the supported features: ? f gpt /2 maximum resolution ? 2 independent timers/counters ? timers/counters can be concatenated ? 3 operating modes: ?timer mode ? gated timer mode ? counter mode ? extended capture/reload functions via 16-bit capture/reload register caprel ? shared interrupt: node 1 15.2 introduction the general purpose timer unit blocks gpt1 and gpt2 have very flexible multifunctional timer structures which may be used for timing, event counting, pulse width meas urement, pulse generation, frequency multiplication, and other purposes. they incorporate five 16-bit timers that are grouped into the two timer blocks gpt1 and gpt2. each timer in each block may operate independently in a number of different modes such as gated timer or counter mode, or may be concatenated with another timer of the same block. each block has alternate input/output functions and spec ific interrupts associated with it. input signals can be selected from several sources by register pisel. the gpt module is clocked with clock f gpt . f gpt is a clock derived from f sys . data sheet 54 rev. 1.0, 2017-03-03 tle9869qxa20 general purpose ti mer units (gpt12) 15.2.1 block diagram gpt1 block gpt1 contains three timers/counters: the core timer t3 and the two auxiliary timers t2 and t4. the maximum resolution is f gpt /4. the auxiliary timers of gp t1 may optionally be configur ed as reload or capture registers for the core timer. figure 19 gpt1 block diagram (n = 2 ? 5) t3 mode control 2 n : 1 f gp t t2 mode control t4 mode control aux. timer t4 reload capture core timer t3 t3otl t4in t4eud toggle latch u/d interrupt request (t2irq) interrupt request (t3irq) interrupt request (t4irq) t3out basic clock t3con.bps1 mc _gpt0101_bldiax1.vsd t3in t3eud u/d t2in t2eud aux. timer t2 reload capture u/d data sheet 55 rev. 1.0, 2017-03-03 tle9869qxa20 general purpose ti mer units (gpt12) 15.2.2 block diagram gpt2 block gpt2 contains two timers/co unters: the core ti mer t6 and the auxiliary time r t5. the maximum resolution is f gpt /2. an additional capture/reload register (caprel) supports capture and reload operation with extended functionality. figure 20 gpt2 block diagram (n = 1 ? 4) caprel mode control 2 n : 1 f gp t t2 mode control t6 mode control gpt2 timer t6 reload clear gpt2 caprel t6otl t6in t6eud toggle ff u/d interrupt request (t5irq) t6ouf interrupt request (t6irq) t6out basic clock t6con.bps2 capin t3in/ t3eud t5in t5eud clear capture u/d gpt2 timer t5 interrupt request (crirq ) data sheet 56 rev. 1.0, 2017-03-03 tle9869qxa20 timer2 and timer21 16 timer2 and timer21 16.1 features ? 16-bit auto-reload mode ? selectable up or down counting ? one channel 16-bit capture mode 16.2 introduction the timer modules are general-purpose 16-bit timers. timer 2/21 can function as a timer or counter in each of its modes. as a timer, it counts with an input clock of f pclk /12 (if prescaler is disabled). as a counter, timer 2 counts 1-to-0 transitions on pin t2. in the counter mode, the maximum resolution for the count is f pclk /24 (if prescaler is disabled). 16.2.1 timer2 and time r21 modes overview table 11 timer2 and timer21 modes mode description auto-reload up/down count disabled ? count up only ? start counting from 16-bit reload value, overflow at ffff h ? reload event configurable for trigger by overflow condition only, or by negative/positive edge at input pin t2ex as well ? programmable reload value in register rc2 ? interrupt is generated with reload events. auto-reload up/down count enabled ? count up or down, direction determined by level at input pin t2ex ? no interrupt is generated ? count up ? start counting from 16-bit reload value, overflow at ffff h ? reload event triggered by overflow condition ? programmable reload value in register rc2 ? count down ? start counting from ffff h , underflow at value defined in register rc2 ? reload event triggered by underflow condition ? reload value fixed at ffff h channel capture ? count up only ? start counting from 0000 h , overflow at ffff h ? reload event triggered by overflow condition ? reload value fixed at 0000 h ? capture event triggered by falling/rising edg e at pin t2ex ? captured timer value stored in register rc2 ? interrupt is generated by reload or capture events tle9869qxa20 timer3 data sheet 57 rev. 1.0, 2017-03-03 17 timer3 17.1 features ? 16-bit incremental timer/counter (counting up) ? counting frequency up to f sys ? selectable clock prescaler ? 6 modes of operation ? interrupt up on overflow ? interrupt on compare 17.2 introduction the possible applications for the timer include measuring the time interval between events, counting events and generating a signal at regular intervals. timer3 can function as timer or counter. when functionin g as a timer, timer3 is incremented in periods based on the mi_clk or lp_clk clock. when functioning as a counter, timer3 is incremented in response to a 1-to-0 transition (falling edge) at its respecti ve input. timer3 can be configured in four different operating modes to use in a variety of applications, see table 12 . several operating modes can be used for different tasks such as the following: ? simple time measurement between two events ? triggering of the measuring unit upon pwm/ccu6 unit ? measurement of the 100khz lp_clk2 17.3 functional description six modes of operation are provided to fulfill various tasks using this timer. in every mode the clocking source can be selected between mi_clk and lp_clk . a prescaler provides in addition ca pability to divide the selected clock source by 2, 4 or 8. the timer count s upwards, starting with the value in the timer count registers, until the maximum count value which depends on the selected mo de of operation. timer 3 provides two individual interrupts upon counter overflow, one for the low- byte and one for the high-byte counter register. 17.3.1 timer3 modes overview the following table provides an overview of the timer modes together with the reason able configuration options in table 12 . table 12 timer3 modes mode sub- mode operation 0 no sub- mode 13-bit timer the timer is essentially an 8-bit counter with a divide-by-32 prescaler. 1 a 16-bit timer the timer registers, tl3 and th3, are concatenated to form a 16-bit counter. 1 b 16-bit timer triggered by an event the timer registers, tl3 and th3, are concat enated to form a 16-bit counter, which is triggered by an event to enable a single shot measurement on a preset channel with the measurement unit. tle9869qxa20 timer3 data sheet 58 rev. 1.0, 2017-03-03 2 no sub- mode 8-bit timer with auto-reload the timer register tl3 is reloaded with a us er-defined 8-bit value in th3 upon overflow. 3 a timer3 operates as two 8-bit timers the timer registers tl3 and th3, operate as two separate 8-bit counters. 3 b timer3 operates as two 8-bi t timers for clock measurement the timer registers, tl3 and th3 operate as tw o separate 8-bit counters. in this mode the lp_clk2 low power clock can be measured. tl 3 acts as an edge counter for the clock edges and th3 as a counter which counts the time between the edges. table 12 timer3 modes (cont?d) mode sub- mode operation tle9869qxa20 capture/compare unit 6 (ccu6) data sheet 59 rev. 1.0, 2017-03-03 18 capture/compare unit 6 (ccu6) 18.1 feature set overview this section gives an overview over the different building blocks and their main features. timer 12 block features ? three capture/compare channels, each channel can be used either as capture or as compare channel ? generation of a three-phase pwm supported (six outp uts, individual signals for high-side and low-side switches) ? 16-bit resolution, maximum count frequency = peripheral clock ? dead-time control for each channel to av oid short-circuits in the power stage ? concurrent update of t12 registers ? center-aligned and edge-aligned pwm can be generated ? single-shot mode supported ? start can be controlled by external events ? capability of counti ng external events ? multiple interrupt request sources ? hysteresis-like control mode timer 13 block features ? one independent compare channel with one output ? 16-bit resolution, maximum count frequency = peripheral clock ? concurrent update of t13 registers ? can be synchronized to t12 ? interrupt generation at period-match and compare-match ? single-shot mode supported ? start can be controlled by external events ? capability of counti ng external events additional specific functions ? block commutation for brushless dc-drives implemented ? position detection via hall-sensor pattern ? noise filter supported for position input signals ? automatic rotational speed measurement an d commutation control for block commutation ? integrated error handling ? fast emergency stop without cpu load via external signal (ctrap ) ? control modes for multi-channel ac-drives ? output levels can be selected and adapted to the power stage 18.2 introduction the ccu6 unit is made up of a timer t12 block with three capture/compare channels and a timer t13 block with one compare channel. the t12 channels can independently generate pwm signals or accept capture triggers, or they can jointly generate control signal pa tterns to drive dc-motors or inverters. a rich set of status bits, synchronize d updating of parameter values via shad ow registers, and flexible generation of interrupt request signals provide efficient software-control. tle9869qxa20 capture/compare unit 6 (ccu6) data sheet 60 rev. 1.0, 2017-03-03 note: the capture/compare module itself is referred to as ccu6 (capture/compare unit 6). a capture/compare channel inside this module is referred to as cc6x. the timer t12 can work in capture and/or compare mode for its three channels. the modes can also be combined (e.g. a channel works in compare mode, whereas another channel works in capture mode). the timer t13 can work in compare mode only. the multi-channel control unit generates output patterns which can be modulated by t12 and/or t13. the modulation sources can be sele cted and combined for the signal modulation. 18.2.1 block diagram figure 21 ccu6 block diagram ccu6 module kernel input / output control port control compare compare 22 compare output select 3 hall input output select 1 trap input 3 capture t13 cc63 start 2 1 multi- channel control trap control dead- time control cc60 cc61 compare 1 1 1 t12 cc62 cout60 cout63 t13hr t12hr ccpos0 ccpos1 ccpos2 ctrap clock control interrupt control f cc 6 sr[3:0] cc61 cout61 cc62 cout62 cc60 debug suspend t13susp t12susp p0.x p1.x p2.x compare ccu6_mcb05506.vsd data sheet 61 rev. 1.0, 2017-03-03 tle9869qxa20 uart1/uart2 19 uart1/uart2 19.1 features ? full-duplex asynchronous modes ? 8-bit or 9-bit data frames, lsb first ? fixed or variable baud rate ? receive buffered ? multiprocessor communication ? interrupt generation on the completion of a data transmission or reception ? baud-rate generator with fractional divider for generating a wide range of baud rates ? hardware logic for break and synch byte detection 19.2 introduction the uart provides a full-duplex asynchronous receiv er/transmitter, i.e., it can transmit and receive simultaneously. it is also receive-buffered, i.e., it ca n commence reception of a sec ond byte before a previously received byte has been re ad from the receive register. ho wever, if the first byte still has not been re ad by the time reception of the second byte is complete, one of the bytes will be lost. the serial port receive and transmit registers are both accessed at special function register (sfr ) sbuf. writing to sbuf loads the transmit register, and reading sbuf accesses a physica lly separate receive register. 19.2.1 block diagram figure 22 uart block diagram scu_dm uart disreq from scu _dm uart module ri ti clock control address decoder f uart2 scu_d m interrupt control uart ahb interface rxd txd port control gpios f br baud rate generator urios txd rxd_1 scu_dm rxdo _2 p0 .x p1 .x p2 .x rxd_0 data sheet 62 rev. 1.0, 2017-03-03 tle9869qxa20 uart1/uart2 19.3 uart modes the uart can be used in four different modes. in mode 0, it operates as an 8-bit sh ift register. in mode 1, it operates as an 8-bit serial port. in modes 2 and 3, it operates as a 9-bit serial po rt. the only difference between mode 2 and mode 3 is the baud rate, which is fixed in mode 2 but variable in mode 3. the variable baud rate is set by the underflow rate on the dedicated baud-rate generator. the different modes are selected by setting bits sm0 and sm1 to their corresponding values, as shown in table 13 . the uart1 is connected to the integrated lin transceiver, and to gpio for test purpose. the uart2 is connected to gpio only. table 13 uart modes sm0 sm1 operating mode baud rate 0 0 mode 0: 8-bit shift register f pclk /2 0 1 mode 1: 8-bit shift uart variable 1 0 mode 2: 9-bit shift uart f pclk /64 1 1 mode 3: 9-bit shift uart variable tle9869qxa20 lin transceiver data sheet 63 rev. 1.0, 2017-03-03 20 lin transceiver 20.1 features general functional features ? compliant to lin2.2 standard, backward compatible to lin1.3, lin2.0 and lin 2.1 ? compliant to sae j2602 (sle w rate, receiver hysteresis) special features ? measurement of lin master baudrate via timer 2 ? lin can be used as input/output with sfr bits. ? txd timeout feature (opt ional, on by default) operation mode features ? lin sleep mode (lslm) ? lin receive-only mode (lrom) ? lin normal mode (lnm) ? high voltage input / output mode (lhvio) supported baud rates ? mode for a transmission up to 10.4 kbaud ? mode for a transmission up to 20 kbaud ? mode for a transmission up to 40 kbaud ? mode for a transmission up to 115.2 kbaud slope mode features ? normal slope mode (20 kbit/s) ? low slope mode (10.4 kbit/s) ? flash mode (115.2 kbit/s) wake-up features ? lin bus wake-up tle9869qxa20 lin transceiver data sheet 64 rev. 1.0, 2017-03-03 20.2 introduction the lin module is a transceiver for the local interc onnect network (lin) compliant to the lin2.2 standard, backward compatible to lin1.3, lin2.0 and lin2.1. it oper ates as a bus driver between the protocol controller and the physical network. the lin bus is a si ngle wire, bi-directional bus typically used for in-vehicle networks, using baud rates between 2.4 kbaud and 20 kbaud. additionally baud rates up to 115.2 kbaud are implemented. the lin module offers several different operation mode s, including a lin sleep mode and the lin normal mode. the integrated slope control allows to use several data transmission rates with optimized emc performance. for data transfer at the end of line, a flash mode up to 115.2 kbaud is implemented. this flash mode can be used for data transfer under special conditions for up to 250 kbit/s (in production environment, point-to-point communication with reduced wire length and limited supply voltage). 20.2.1 block diagram figure 23 lin transceiver block diagram driver + curr. limit. + tsd lin transceiver sleep comparator gnd_lin rxd_1 to uart receiver vs txd_1 from uart lin_wake 30 k lin_ctrl _sts lin-fsm lin gnd_lin lin_block_diagram_customer.vsd status ctrl status ctrl filter filter transmitter data sheet 65 rev. 1.0, 2017-03-03 tle9869qxa20 high-speed synchronous serial interface (ssc1/ssc2) 21 high-speed synchronous se rial interface (ssc1/ssc2) 21.1 features ? master and slave mode operation ? full-duplex or half-duplex operation ? transmit and receive buffered ? flexible data format ? programmable number of data bits: 2 to 16 bits ? programmable shift direction: least significant bi t (lsb) or most signific ant bit (msb) shift first ? programmable clock polarity: idle low or high state for the shift clock ? programmable clock/data phase: data shift with leading or trailing edge of the shift clock ? variable baud rate ? compatible with serial peripheral interface (spi) ? interrupt generation ? on a transmitter empty condition ? on a ?receiver full? condition ? on an error condition (receive, ph ase, baud rate, transmission error) data sheet 66 rev. 1.0, 2017-03-03 tle9869qxa20 high-speed synchronous serial interface (ssc1/ssc2) 21.2 introduction the high-speed synchronous serial interface (ssc) suppor ts both full-duplex and half-duplex serial synchronous communication. the serial clock signal can be generated by the ssc internally (master mode), using its own 16- bit baud rate generator, or can be received from an external master (slave mode). data wi dth, shift direction, clock polarity, and phase are programmable. this allows comm unication with spi-compatible devices or devices using other synchronous serial interfaces. data is transmitted or received on txd and rxd lines, which are normally connected to the mtsr (mastertransmit/slave receive) and mr st (master receive/slave transmit) pi ns. the clock signal is output via line ms_clk (master serial shift clock) or input via lin e ss_clk (slave serial shif t clock). both lines are normally connected to the pin sclk. transmission and reception of data are double-buffered. 21.2.1 block diagram figure 24 shows all functional relevant interf aces associated with the ssc kernel. figure 24 ssc interface diagram ssc module eir tir clock control address decoder rir slave f hw_clk sclk sclka sclkb master scu_dm interrupt control module product interface ahb interface p0.x p1.x p2.x port control ssc_interface_overview.vsd master mrsta mrstb mtsr slave mtsra mtsrb mrst tle9869qxa20 measurement unit data sheet 67 rev. 1.0, 2017-03-03 22 measurement unit 22.1 features ? 1 x 8-bit adc with 10 inputs including attenuator allowing measurement of high voltage input signals ? supply voltage attenuators with attenuation of vbat_sense , vs , vddp and vddc . ? vbg monitoring of 8-bit adc to guarantee functional safety requirements. ? bridge driver diagnosis measurement (vdh, vcp). ? temperature sensor for monitoring the chip temperature and pmu regulator temperature. ? supplement block with reference vo ltage generation, bias current generation, voltage buffer for nvm reference voltage, voltage buffer for analog module reference voltage and test interface. 22.2 introduction the measurement unit is a functional unit that comprises the following associated sub-modules: table 14 measurement functions and associated modules module name modules functions central functions unit bandgap reference circuit the bandgap-reference sub-module provides two reference voltages 1. a trimmable reference voltage for the 8-bit adcs. a local dedicated bandgap circuit is implemented to avoid deterioration of the referenc e voltage arising e.g. from crosstalk or ground voltage shift. 2. the reference voltage for the nvm module 8-bit adc (adc2) 8-bit adc module with 10 multiplexed inputs, including hv input attenuator 5 high voltage full supply range capable inputs (2.5v...30,7v(fs)) 2 medium voltage inputs (0..5v/7v fs). 3 low voltage inputs (0..1.2v/1.6v fs) (allocation see follo wing overview figure) 10-bit adc (adc1) 10-bit adc module with 8 multiplexed inputs five (5v) analog inputs from port 2.x vdh input voltage attenuator vdh input voltage attenuator scales down v(vdh) to the input voltage range of adc1.ch6 temperature sensor temperature sensor with two multiplexed sensing elements: ? pmu located sensor ? central chip located sensor generates output voltage which is a linear function of the local chip (junction) temperature. measurement core module digital signal processing and adc2 control unit 1. generates the control sign al for the 8-bit adc2 and the synchronous clock for the switched capacitor circuits, 2. performs digital signal processing functions and provides status outputs for interrupt generation. tle9869qxa20 measurement unit data sheet 68 rev. 1.0, 2017-03-03 22.2.1 block diagram figure 25 measurement unit-overview (with opamp) 8 bit adc + dpp2 10 bit adc + dpp1 mux ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 ch9 a d vs vsd mux ch6 ch5 ch4 ch3 ch2 ch1 ch0 ch7 vref a d channel sequencer / 10 / 8 calibration & filter unit with upper / lower threshold detection / interrupt 1.23 v p2.0 varef x 0.055 x 0.039 x 0.039 sfr sfr 5 v adc 1 adc 2 gnd_sense vagnd temperature sensor pmu-vbg vddp vddc x 0.164 x 0.75 x 0.219 programmable range setting varef op 1 op 2 x 0.226 x 0.166 rfu p2.2 p2.3 p2.4 p2.5 vdh vcp x 0.023 g = 10/20/40/60 x 0.039 op measurement -unit vbat_sense x 0.055 x 0.039 mon tle9869qxa20 measurement core mo dule (incl. adc2) data sheet 69 rev. 1.0, 2017-03-03 23 measurement core module (incl. adc2) 23.1 features ? 8 individually programmable channels split into two gr oups of user configurable and non user configurable ? individually programmable channel prioritization scheme for measurement unit ? two independent filter stages with programmable low- pass and time filter characteristics for each channel ? two channel configurations: ? programmable upper- and lower trigger thresholds comprising a fully programmable hysteresis ? two individually programmable trigger th resholds with limit hysteresis settings ? individually programmable interrupts and statuses for all channel thresholds 23.2 introduction the basic function of this block is the digital postproc essing of several analog digitized measurement signals by means of filtering, level comparison and interrupt genera tion. the measurement postpr ocessing block consists of ten identical channel units attached to the outputs of the 10-channel 8-bit adc (adc2). it processes ten channels, where the channel sequence and prioritization is programmable within a wide range. 23.2.1 block diagram figure 26 module block diagram digital signal processing 1st order iir mux vs vsd varef temperature sensor vddp ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 ch9 vref calibration unit : y= a + (1+b)*x + - + - / channel controller (sequencer) mux_sel<3:0> a d up_x_sts low_x_sts 4 / 8 + / - + / - / 10 / 8 / 1 / 1 8 bit adc adc2 - sfr vddc vcp tsense coeff a co eff_b mux_ctrl en coeff_iir mux_ctrl en fi lt _ou t x. ou t _ch x mux_ctrl filte nup filtenlo w filtenlo w hyslow hysup mmode cntlow cntup en ctrl_sts sq0 ? sq9 ts ens _s el pmu-vbg vbat_sense thy_z_ upper. chx thy_z_ low er. chx measurement core module mon tle9869qxa20 measurement core mo dule (incl. adc2) data sheet 70 rev. 1.0, 2017-03-03 23.2.2 measurement core module modes overview the basic function of this unit, is the digital signal pr ocessing of several analog digitized measurement signals by means of filtering, level comparison and interrupt generation. the measurement core module processes ten channels in a quasi parallel process. as shown in the figure above, the adc2 postprocessing unit cons ists of a channel contro ller (sequencer), an 10- channel demultiplexer and the signal processing block, wh ich filters and compares the sampled adc2 values for each channel individually. the channel control block cont rols the multiplexer sequencing on the analog side before the adc2 and on the digital domain after the adc2. as de scribed in the following section, the channel sequence can be controlled in a flexible way, which allo ws a certain degree of channel prioritization. this capability can be used e.g. to se t a higher priority to supply voltage channels compared to the other channel measurements. the measurement core module offers a dditionally two different post-processing measurement modes for over-/undervoltage detection and for two-level threshold detection. the channel controller (sequencer) runs in one of the following modes: ?normal sequencer mode? ? channels are selected ac cording to the 10 sequence registers which contain individual enablers for each of the 10 channels. ?exceptional interrupt measurement? ? following a hardware event, a high priority channel is inserted into the current sequence. the current actual measurement is not destroyed. ?exceptional sequence measurement? ? following a hardware event, a complete sequence is inserted after the current measurement is finished. the current sequence is interrupted by the exception sequence. tle9869qxa20 10-bit analog digital converter (adc1) data sheet 71 rev. 1.0, 2017-03-03 24 10-bit analog digital converter (adc1) 24.1 features the principal features of the adc1 are: ? up to 8 analog input channels (channel 7 reserved for future use) ? flexible results handling - 8-bit and 10-bit resolution ? flexible source selection due to sequencer - insert one exceptional sequence (esm) - insert one interrupt measurement into the current sequence (eim), single or up to 128 times - software mode ? conversion sample time (separate for each channe l) adjustable to adapt to sensors and reference ? standard external reference (varef) to support ra tiometric measurements and different signal scales ? dma support, transfer adc conver sion results via dma into ram ? support of suspend and power saving modes ? result data protection for slow cpu access (wait-for-read mode) ? programmable clock divider ? integrated sample and hold circuitry 24.2 introduction the tle9869qxa20 includes a high-performance 10-b it analog-to-digital c onverter (adc1) with eight multiplexed analog input channels. the adc1 uses a successive approximation technique to convert the analog voltage levels from up to eight different sources. the analog input channels of the adc1 are available at an0, an2 - an5. tle9869qxa20 10-bit analog digital converter (adc1) data sheet 72 rev. 1.0, 2017-03-03 24.2.1 block diagram figure 27 adc1 top level block diagram as shown in the figure above, the adc1 postprocessing consists of a channel controller (sequencer) and an 8- channel demultiplexer. the channel c ontrol block controls the multiplexer sequencing on the analog side before the adc1 and on the digital domain after the adc1. as de scribed in the following section, the channel sequence can be controlled in a flexible way, which allo ws a certain degree of channel prioritization. this capability can be used e.g. to gi ve a higher priority to some chan nels compared to the other channel measurements. mux ch0 mux_sel <2:0> channel controller (sequencer) settings adc1 s e t t i n g s adc1 - sfr mux / 3 / 3 / 10 p2.0 ch1 ch2 p2.2 p2.3 ch3 ch4 p2.4 p2.5 ch5 ch6 vdh rfu ch7 / 10 d a adc1_out_ch0 eoc - soc / 10 adc1_out_ch1 / 10 adc1_out_ch2 / 10 adc1_out_ch3 / 10 adc1_out_ch4 / 10 adc1_out_ch5 / 10 adc1_out_ch6 / 10 adc1_out_ch7 / 10 adc1_out_ch0 / 10 adc1_out_ch1 / 10 adc1_out_ch2 / 10 adc1_out_ch3 10 adc1_out_ch4 / 10 adc1_out_ch5 / 10 adc1_out_ch6 / 10 adc1_out_ch7 / 10 adc1_res_out_eim opa op1 op2 tle9869qxa20 high-voltage monitor input data sheet 73 rev. 1.0, 2017-03-03 25 high-voltage monitor input 25.1 features ? high-voltage input with v s /2 threshold voltage ? integrated selectable pull-up and pull-down current sources ? wake capability for power saving modes ? level change sensitivity configurable for transitions from low to high , high to low or both directions 25.2 introduction this module is dedicated to monitor external voltage leve ls above or below a specified threshold or it can be used to detect a wake-up event at the high-voltage mon pin in low-power mode. the input is sensitive to a input level monitoring, this is available w hen the module is switched to ac tive mode with the sfr bit en. to use the wake function during low power mode of the ic, the monitoring pin is switched to sleep mode via the sfr bit en. 25.2.1 block diagram figure 28 monitoring i nput block diagram monx_input _circuit_ext .vsd sfr logic filter mon + - to internal circuitry mon vs tle9869qxa20 bridge driver (incl. charge pump) data sheet 74 rev. 1.0, 2017-03-03 26 bridge driver (incl. charge pump) 26.1 features the mosfet driver is intended to drive external normal level nfet transistors in bridge configuration. the driver provides many diagnostic poss ibilities to detect faults. functional features ? external power nfet transis tor driver stage with driver capability for max. 100 nc gate charge @ 25 khz switching frequency. ? implemented adjustable cross conduction protection. ? supply voltage (vsd) monitoring incl. adjustable over- and undervoltage shutdown with configurable interrupt signalling. ? vsd operating range down to 5.4 v ? vds comparators for short circui t detection in on- and off-state ? open-load detection in off-state 26.2 introduction the mosfet driver stage can be us ed for controlling external power nfet transistors (normal level). the module output is cont rolled by sfr or system pwm machine (ccu6). tle9869qxa20 bridge driver (incl. charge pump) data sheet 75 rev. 1.0, 2017-03-03 26.2.1 block diagram figure 29 driver module block diagram (incl. system connections) 26.2.2 general the driver can be controlled in two different ways: ? in normal mode the output stage is fully controllable through the sfr registers ct rlx (x = 1,2,3). protection functions such as overcurrent and open-load detection are available. ? the pwm mode can also be enabled by the corresponding bit in ctrl1 and ctrl2. the pwm must be configured in the system pwm module (ccu6). all prot ection functions are available in pwm mode as well. protection functions ? overcurrent detection and shutdo wn feature for external mosfet by drain source measurement ? programmable minimum cross current protection time ? open-load detection feature in off-state for external mosfet. vcp predriver _customer.vsd vdh ghx shx high side driver + - vds sfr sl + - vds vref vref low side driver pre-driver pwm-unit ccu6 (not part of the module ) spike filter blank filter spike filter blank filter drv.trim_drvx. ls_hs_bt _tfilt_sel drv.trim_drvx. lsdrv_ds_tfilt_sel drv.trim_drvx. ls_hs_bt_tfilt_sel drv.trim_drvx. lsdrv_ds_tfilt_sel drv.ctrl3. dsmonvth drv.ctrl3. dsmonvth glx 1 0 drv.ctrl1.hsx_pwm 1 0 drv.ctrl1.lsx_pwm r ggnd r ggnd tle9869qxa20 current sense amplifier data sheet 76 rev. 1.0, 2017-03-03 27 current sense amplifier 27.1 features main features ? programmable gain settings: g = 10, 20, 40, 60 ? differential input voltage: 1.5v / g ? wide common mode input range 2 v ? low setting time < 1.4 s 27.2 introduction the current sense amplifier in figure 30 can be used to measure near ground differential voltages via the 10-bit adc. its gain is digitally programmable through internal control registers. linear calibration has to be applied to achieve high gain ac curacy, e.g. end-of-line calibration including the shunt resistor. figure 30 shows how the current sense amplifier can be used as a low-side current sense amplifier where the motor current is converted to a volt age by means of a shunt resistor r sh . a differential amplif ier input is used in order to eliminate measurement errors due to voltage drop across the stray resistance r stray and differences between the external and internal ground. if the voltage at one or both inputs is out of the operating range, the input circuit is overloaded and requires a certain specified recovery time . in general, the external low pass filter should provide suppression of emi. 27.2.1 block diagram figure 30 simplified application diagram current_sense_amplifier.vsd m ext. gnd v bat op2 op1 lp filter amplifier configurable gain: 10, 20, 40, 60 10-bit adc v aref 5v motor current vp vn v zero v zero + ( v op2 - v op 1 ) * g csa_ctrl r opafilt r sh c opafilt r stray r opafilt / 10 adc1_out_ch1 tle9869qxa20 application information data sheet 77 rev. 1.0, 2017-03-03 28 application information 28.1 h-bridge driver figure 31 shows the tle9869qxa20 in an electric drive application setup controllin g an h-bridge motor. note: the following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. figure 31 simplified application diagram example note: this is a very simplified example of an applicatio n circuit and bill of materials. the function must be verified in the actual application. tle9869 emc filter vbat_sense lin vdd_ext vddc vs cp1h cp1l vcp cp2l gnd_lin varef gnd_ref cp2h vdh gh1 gl1 vddp vbat gl2 sh1 gh2 sh2 sl gnd vsd op1 op2 r vd h c vb at _se n se r vb at _se n se c vd d _ ex t1 c cps1 c cps2 c vc p c vs d c vd h c ph 1 c ph 2 c em c c em c l pf il t r ga te r ga te c op afi lt r opafilt r opafilt c va r ef c ad c r ad c r vd d pu p0.3 temp sensor p2.2 p1.2 p1.0 p2.5 p1.3 r vs d r ga te r ga te c vddp2 c vddc2 c vddc1 c vddp1 c vs 1 d vs c vs 2 t l2 t h2 t h1 t rp c vdd_ext2 c pf ilt1 c pf ilt1 lin tms p0.0 debug connector r tm s r ga te tle4946-2k hall r ga te t l1 m r sw i tc h c gs g d s r gs c gs g d s r gs c gs g d s r gs c gs g d s r gs gnd h-bridge system switch r sh u n t c lin c mon r mon mon p0.4 p0.1 rev. po larit y prot ection tle9869qxa20 application information data sheet 78 rev. 1.0, 2017-03-03 table 15 external components (bom) symbol function component c vs1 blocking capacitor at vs pin 100 nf ceramic, esr < 1 ? c vs2 blocking capacitor at vs pin > 2.2 f elco 1) c vddp blocking capacitor at vddp pin 470 nf + 100 nf ceramic, esr < 1 ? c vdd_ext blocking capacitor at vddext pin 100nf, ceramic esr < 1 ? c vddc blocking capacitor at vddc pin 470 nf + 100 nf ceramic, esr < 1 ? c varef blocking capacitor at varef pin 100 nf, ceramic esr < 1 ? c lin standard c for lin slave 220 pf c vsd filter c for charge pump end driver 1 f c cps1 charge pump capacitor 220 nf c cp2s charge pump capacitor 220 nf c vcp charge pump capacitor 470 nf c mon1 filter c for iso pulses 10 nf c vdh capacitor 1 nf c ph1 capacitor 220 f c ph2 capacitor 220 f c opafilt capacitor 100 nf c emcp1 capacitor 1 nf c emcp2 capacitor 1 nf c pfilt1 , c pfilt2 capacitor 10 f c vbat_sense capacitor 10 nf r mon resistor at mon pin 1 k ? r vsd limitation of reverse current due to transient (-2v, 8ms) max. ratings of the vsd pin has to be met, alternatively the resistor shall be replaced by a diode 2 ? r vdh resistor 1 k ? r gate resistor 2 ? r opafilt resistor 12 ? r vbat_sense resistor r sh1 resistor optional r sh2 resistor optional l pfilt d vs reverse-polarity protection diode ? 1) the capacitor must be dimensioned so as to ensure that flash operations modifying the content of the flash are never interrupted (e.g. in case of power loss). tle9869qxa20 application information data sheet 79 rev. 1.0, 2017-03-03 28.2 esd immunity according to iec61000-4-2 note: tests for esd immunity according to iec61000-4-2 ?gun test? (150pf, 330 ? ) has been performed. the results and test condition will be available in a test report. table 16 esd ?gun test? performed test r esult unit remarks esd at pin lin, versus gnd 1) 1) esd test ?esd gun? is specified with ex ternal components; see application diagram: c mon = 100 nf, r mon = 1 k ? , c lin = 220 pf, c vs = >20 f elco + 100 nf esr < 1 ? , c vsd = 1 f, r vsd = 2 ? . > 6 kv 2) positive pulse 2) esd susceptibility ?esd gun? according to lin emc test spec ification, section 4.3 (iec 61000-4-2). tested by external test house (ibee zwickau, emc test report nr. 09-07-14) esd at pin lin, versus gnd 1) < -6 kv 2) negative pulse tle9869qxa20 electrical characteristics data sheet 80 rev. 1.0, 2017-03-03 29 electrical characteristics this chapter includes all relevant electrical characteristics of the product tle9869qxa20. 29.1 general characteristics 29.1.1 absolute maximum ratings table 17 absolute maximum ratings 1) t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. voltages ? supply pins supply voltage ? vs v s -0.3 ? 40 v load dump p_1.1.1 supply voltage ? vsd v sd -0.3 ? 48 v ? p_1.1.2 supply voltage ? vsd v sd_max_exten d -2.8 ? 48 v series resistor r vsd = 2.2 ? , t = 8 ms 2) p_1.1.32 voltage range ? vddp v ddp -0.3 ? 5.5 v ? p_1.1.3 voltage range ? vddp v ddp_max_ext end -0.3 ? 7 v in case of voltage transients on v s with d v s /d t 1v/s; duration: t 150s; c vddp 570 nf p_1.1.41 voltage range ? vddext v ddext -0.3 ? 5.5 v ? p_1.1.4 voltage range ? vddext v ddext_max_ extend -0.3 ? 7 v in case of voltage transients on v s with d v s /d t 1v/s; duration: t 150s; c vddext 570 nf p_1.1.42 voltage range ? vddc v ddc -0.3 ? 1.6 v ? p_1.1.5 voltages ? high voltage pins battery voltage vbat_sense v bat_sense -28 ? 40 v 3) p_1.1.6 input voltage at lin v lin -28 ? 40 v ? p_1.1.7 input voltage at mon v mon_maxrate -28 ? 40 v 4) p_1.1.8 input voltage at vdh v vdh_maxrate -2.8 ? 40 v 5) p_1.1.38 voltage range at ghx v gh -8.0 ? 48 v 6) p_1.1.9 voltage range at ghx vs. shx v ghvssh 14 ? ? v ? p_1.1.44 voltage range at shx v sh -8.0 ? 48 v ? p_1.1.11 voltage range at glx v gl -8.0 ? 48 v 7) ? p_1.1.13 voltage range at glx vs. sl v glvssl 14 ? ? v ? p_1.1.45 tle9869qxa20 electrical characteristics data sheet 81 rev. 1.0, 2017-03-03 voltage range at charge pump pins cp1h, cp1l, cp2h, cp2l, vcp v cpx -0.3 ? 48 v 8) p_1.1.15 voltages ? gpios voltage on any port pin 9) v in -0.3 ? v ddp +0.3 v v in < v ddpmax 10) p_1.1.16 current at vcp pin max. current at vcp pin i vcp -15 ? ? ma ? p_1.1.35 injection current at gpios injection current on any port pin i gpionm -5 ? 5 ma 11) p_1.1.34 sum of all injected currents in normal mode i gpioam_sum -50 ? 50 ma 11) p_1.1.30 sum of all injected currents in power down mode (stop mode) i gpiopd_sum -5000 ? 50 a 11) p_1.1.36 sum of all injected currents in sleep mode i gpiosleep_su m -5 ? 5 ma 11) p_1.1.37 other voltages input voltage varef v aref -0.3 ? v ddp +0.3 v ? p_1.1.17 input voltage op1, op2 v oai -7 ? 7 v ? p_1.1.23 temperatures junction temperature t j -40 ? 150 c ? p_1.1.18 storage temperature t stg -55 ? 150 c ? p_1.1.19 esd susceptibility esd susceptibility all pins v esd1 -2 ? 2 kv hbm 12) p_1.1.20 esd susceptibility pins mon, vs, vsd, vbat_sense vs.gnd v esd2 -4 ? 4 kv hbm 13) p_1.1.21 esd susceptibility pins lin vs. gnd_lin v esd3 -6 ? 6 kv hbm 12) p_1.1.22 esd susceptibility cdm all pins vs. gnd v esd_cdm1 -500 ? 500 v 14) p_1.1.28 esd susceptibility cdm pins 1, 12, 13, 24, 25, 36, 37, 48 (corner pins) vs. gnd v esd_cdm2 -750 ? 750 v 14) p_1.1.43 1) not subject to production test, specified by design. 2) conditions and min. value is derived from application condition for reverse polarity event. table 17 absolute maximum ratings 1) (cont?d) t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. tle9869qxa20 electrical characteristics data sheet 82 rev. 1.0, 2017-03-03 notes 1. stresses above the ones listed here may cause perma nent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. integrated protection func tions are designed to prevent ic destructi on under fault conditions described in the data sheet. fault conditions are considered as ?outside? normal operating range. pr otection functi ons are not designed for continuous repetitive operation. 3) min voltage -28v with external 3.9k ? series resistor only. 4) min voltage -28v with external 3.9k ? series resistor only. 5) min voltage -2.8v with external 1k ? series resistor only. 6) to achieve max. ratings on this pin, parameter p_1.1.44 has to be taken into account resulting in the following dependency: v gh < v sh + v ghvssh_min and additionally v sh < v gh + 0.3v. 7) to achieve max. ratings on this pin, parameter p_1.1.45 has to be taken into account resulting in the following dependency: v gl < v sl + v glvssl_min and additionally v sl < v gl + 0.3v. 8) these limits can be kept if max current draw n out of pin does not exceed limit of 200 a. 9) see xtal parameter specification, when gpio s (port pin p2.0 and p2.2) are used as xtal. 10) includes tms and reset. 11) maximum rating for injection current of gpio with v in respected. 12) esd susceptibility hbm according to ansi/esda/jedec js-001 (1.5k ? , 100pf) 13) mon with external circuitry of a series resistor of 3.9k ? and 10nf (at connector); vs with an external ceramic capacitor of 100nf; vsd with an external capacitor of 470nf; vdh with external circuitry of a series resistor of 1k ? and 3.3nf (at pin). 14) esd susceptibility, hbm accordin g to ansi/esda/jedec jesd22-c101f tle9869qxa20 electrical characteristics data sheet 83 rev. 1.0, 2017-03-03 29.1.2 functional range table 18 functional range t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. supply voltage in active mode v s_am 5.5 ? 28 v ? p_1.2.1 extended supply voltage in active mode v s_am_exte nd 28 ? 40 v 1) functional with parameter deviation 1) this operation voltage range is on ly allowed for a short duration: t max 400 ms (continuous operat ion at this voltage is not allowed), f sys = 24 mhz, i vddp = 10 ma, i vddext = 5 ma. in addition, the power dissipation caused by the charge pump + mosfet driver have to be considered. p_1.2.16 supply voltage in active mode for mosfet driver supply v sd_am 5.4 ? 28 v p_1.2.18 extended supply voltage in active mode for mosfet driver supply v sd_am_ext end 28 ? 32 v 1)3) functional with parameter deviation p_1.2.17 specified supply voltage for lin transceiver v s_am_lin 5.5 ? 18 v parameter specification p_1.2.2 extended supply voltage for lin transceiver v s_am_lin 4.8 ? 28 v functional with parameter deviation p_1.2.14 supply voltage in active mode with reduced functionality (microcontroller / flash with full operation) v s_ammin 3.0 ? 5.5 v 2) 2) reduced functionality (e.g. cranking pulse) - parameter deviation possible. p_1.2.3 supply voltage in sleep mode v s_sleep 3.0 ? 28 v ? p_1.2.4 supply voltage transients slew rate d v s /d t -1?1v/s 3) 3) not subject to production test, specified by design. p_1.2.5 output sum current for all gpio pins i gpio,sum -50 ? 50 ma 3) p_1.2.7 operating frequency f sys 5?24mhz 4) 4) function not specified when limits are exceeded. p_1.2.20 junction temperature t j -40 ? 150 c ? p_1.2.9 tle9869qxa20 electrical characteristics data sheet 84 rev. 1.0, 2017-03-03 29.1.3 current consumption table 19 electrical characteristics v s = 5.5 v to 28 v, t j = -40 c to +150 c; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. current consumption @vs pin current consumption in active mode at pin vs i vs ?30 35 ma f sys = 20 mhz no loads on pins, lin in recessive state 1) p_1.3.1 current consumption in active mode at pin vsd i vsd ? ? 40 ma 20 khz pwm on bridge driver p_1.3.8 current consumption in slow down mode i sdm ?? 30 ma f sys = 5 mhz; lin communication running; charge pump on (reverse polarity fet on), external low side fet static on (motor break mode); vddext on; all other module set to power down; v s = 13.5v p_1.3.6 current consumption in sleep mode i sleep ? 30 35 a system in sleep mode, microcontroller not powered, wake capable via lin and mon; mon connected to vs or gnd; gpios open (no loads) or connected to gnd: t j = -40c to 85c; v s = 5.5 v to 18v; 2) p_1.3.3 current consumption in sleep mode extended range i sleep_exten d ? 90 200 a system in sleep mode, microcontroller not powered, wake capable via lin and mon; mon connected to vs or gnd; gpios open (no loads) or connected to gnd: t j = -40c to 150c; v s = 5.5 v to 18v; 2) p_1.3.15 current consumption in sleep mode i sleep ? ? 33 a system in sleep mode, microcontroller not powered, wake capable via lin and mon; mon connected to vs or gnd; gpios open (no loads) or connected to gnd: t j = -40c to 40c; v s = 5.5 v to 18v; 2) p_1.3.9 tle9869qxa20 electrical characteristics data sheet 85 rev. 1.0, 2017-03-03 note: within the functional range, the ic operates as described in the ci rcuit description. the electrical characteristics are specifi ed within the conditions given in the re lated electrical ch aracteristics table. current consumption in sleep mode with cyclic wake i cyclic ? ? 110 a t j = -40c to 85c; v s = 5.5 v to 18v; t cyclic_on = 4ms; t cyclic_off = 2048 ms; 2) p_1.3.4 current consumption in stop mode i stop ? 110 160 a system in stop mode, microcontroller not clocked, wake capable via lin and mon; mon connected to vs or gnd; gpios open (no loads) or connected to gnd; t j = - 40c to 85c; v s = 5.5 v to 18v p_1.3.10 current consumption in stop mode-extended temperature range 1 i stop_extend ? 600 1800 a system in stop mode, microcontroller not clocked, wake capable via lin and mon; mon connected to vs or gnd; gpios open (no loads) or connected to gnd; t j = -40cto150c; v s = 5.5 v to 18 v p_1.3.20 1) current on v s , adc1/2 active, timer runni ng, lin active (recessive). 2) incl. leakage currents form vbat_sense, vdh, vsd and mon table 19 electrical characteristics (cont?d) v s = 5.5 v to 28 v, t j = -40 c to +150 c; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. tle9869qxa20 electrical characteristics data sheet 86 rev. 1.0, 2017-03-03 29.1.4 thermal resistance 29.1.5 timing characteristics the transition times between the system modes are specified here. generally the timings are defined from the time when the corresponding bits in register pmcon0 are set until the sequence is terminated. table 20 thermal resistance parameter symbol values unit note / test condition number min. typ. max. junction to soldering point r thjsp ?6?k/w 1) measured to exposed pad 1) not subject to production test, specified by design. p_1.4.1 junction to ambient r thja ?33?k/w 2) 2) according to jedec jesd51-2,-5,-7 at natural convection on fr4 2s2p board. board: 76. 2x114.3x1.5mm3 with 2 inner copper layers (35m thick), with thermal via array under th e exposed pad contacting the first inner copper layer and 300mm 2 cooling area on the bottom layer (70m). p_1.4.2 table 21 system timing 1) v s = 5.5 v to 28 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) 1) not subject to production test, specified by design. parameter symbol values unit note / test condition number min. typ. max. wake-up over battery t start ? ? 3 ms battery ramp-up time to code execution p_1.5.6 wake-up over battery t startsw ? ? 1.5 ms battery ramp-up time to till mcu reset is released; v s > 3 v and reset = 1 p_1.5.1 sleep-exit t sleep - exit ? ? 1.5 ms rising/falling edge of any wake-up signal (lin, mon) till mcu reset is released; p_1.5.2 sleep-entry t sleep - entry ?? 330s 2) 2) wake events during sleep-entry are stored and lead to wake-up after sleep mode is reached. p_1.5.3 tle9869qxa20 electrical characteristics data sheet 87 rev. 1.0, 2017-03-03 29.2 power management unit (pmu) this chapter includes all electrical characteristics of the power management unit 29.2.1 pmu i/o supply (vddp) parameters this chapter describes all electrical parameters which ar e observable on soc level. for this purpose only the pad- supply vddp and the transition times be tween the system modes are specified here. table 22 electrical characteristics v s = 5.5 v to 28 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. specified output current i vddp 0?50ma 1) p_2.1.1 specified output current i vddp 0?30ma 1)2) p_2.1.22 required decoupling capacitance c vddp1 0.47 ? 2.2 f 3)4) esr < 1 ? ; the specified capacitor value is a typical value. p_2.1.2 required buffer capacitance for stability (load jumps) c vddp2 1?2.2f 3)4) the specified capacitor value is a typical value. p_2.1.20 output voltage including line and load regulation @ active mode v ddpout 4.9 5.0 5.1 v 5) i load < 90ma; v s > 5.5v p_2.1.3 output voltage including line and load regulation @ active mode v ddpout 4.9 5.0 5.1 v 2)5) i load < 70ma; v s > 5.5v p_2.1.23 output voltage including line and load regulation @ stop mode v ddpouts top 4.5 5.0 5.5 v 5) i load is only internal; v s > 5.5v p_2.1.21 output drop @ active mode v svddpout ? 50 400 mv i vddp = 30ma 6) ; 3.5v < v s <5.0v p_2.1.4 load regulation @ active mode v vddplor -50 ? 50 mv 2 ... 90ma; c = 570nf p_2.1.5 line regulation @ active mode v vddplir -50 ? 50 mv v s = 5.5 ... 28v p_2.1.6 overvoltage detection v ddpov 5.14 ? 5.4 v v s > 5.5v; overvoltage leads to supply_nmi p_2.1.7 overvoltage detection filter time t filt_vddp ov ?735?s 3)7) p_2.1.24 voltage ok detection v ddpok ?3?v 3) p_2.1.25 voltage stable detection range 8) ? v ddpstb - 220 ? + 220 mv 3) p_2.1.26 undervoltage reset v ddpuv 2.5 2.6 2.7 v ? p_2.1.8 overcurrent diagnostic i vddpoc 91 ? 220 ma ? p_2.1.9 tle9869qxa20 electrical characteristics data sheet 88 rev. 1.0, 2017-03-03 overcurrent diagnostic filter time t filt_vddp oc ?27?s 3)7) p_2.1.27 overcurrent diagnostic shutdown time t filt_vddp oc_sd ?290?s 3)7)9) p_2.1.28 1) specified output current for port supply and addition al other external loads already excluding vddc current. 2) this use case applies to cases where output current on vddext is max. 40 ma. 3) not subject to production test, specified by design. 4) ceramic capacitor. 5) load current includes internal supply. 6) output drop for ivddp without internal supply current. 7) this filter time and its variation is derived from the time base t lp_clk = 1 / f lp_clk . 8) the absolute voltage value is the sum of parameters v ddp + ? v ddpstb . 9) after t filt_vddcoc_sd is passed and the overcurrent condition is still present, the device will enter sleep mode. table 22 electrical characteristics (cont?d) v s = 5.5 v to 28 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. tle9869qxa20 electrical characteristics data sheet 89 rev. 1.0, 2017-03-03 29.2.2 pmu core supply (vddc) parameters this chapter describes all electrical parameters which are observable on soc level. for this purpose only the core- supply vddc and the transition times between the system modes are specified here. table 23 electrical characteristics v s = 5.5 v to 28 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. required decoupling capacitance c vddc1 0.1 ? 1 f 1)2) esr < 1 ? ; the specified capacitor value is a typical value. 1) not subject to production test, specified by design. 2) ceramic capacitor. p_2.2.1 required buffer capacitance for stability (load jumps) c vddc2 0.33 ? 1 f 2) the specified capacitor value is a typical value. p_2.2.17 output voltage including line regulation @ active mode v ddcout 1.44 1.5 1.56 v i load < 40ma p_2.2.2 reduced output voltage including line regulation @ stop mode v ddcout_ stop_red 0.95 1.1 1.3 v with internal vddc load only: i load_internal < 1.5ma p_2.2.23 load regulation @ active mode v ddclor -50 ? 50 mv 2 ... 40ma; c =430nf p_2.2.3 line regulation @ active mode v ddclir -25 ? 25 mv v ddp = 2.5 ... 5.5v p_2.2.4 overvoltage detection v ddcov 1.59 1.62 1.68 v overvoltage leads to supply_nmi p_2.2.5 overvoltage detection filter time t filt_vddc ov ?735? s 1)3) 3) this filter time and its variation is derived from the time base t lp_clk = 1 / f lp_clk . p_2.2.18 voltage ok detection range 4) 4) the absolute voltage value is the sum of parameters v ddc + ? v ddcstb . ? v ddcok - 280 ? + 280 mv 1) p_2.2.19 voltage stable detection range 5) 5) the absolute voltage value is the sum of parameters v ddc + ? v ddcok . ? v ddcstb - 110 ? + 110 mv 1) p_2.2.20 undervoltage reset v ddvuv 1.136 1.20 1.264 v ? p_2.2.6 overcurrent diagnostic i vddcoc 45 ? 100 ma ? p_2.2.7 overcurrent diagnostic filter time t filt_vddc oc ?27? s 1)3) p_2.2.21 overcurrent diagnostic shutdown time t filt_vddc oc_sd ?290? s 1)3)6) 6) after t filt_vddcoc_sd is passed and the overcurrent condition is still present the device will enter sleep mode. p_2.2.22 tle9869qxa20 electrical characteristics data sheet 90 rev. 1.0, 2017-03-03 29.2.3 vddext voltage regulat or (5.0v) parameters table 24 electrical characteristics v s = 5.5 v to 28 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. specified output current i vddext 0 ? 20 ma ? p_2.3.1 specified output current i vddext 0?40ma 1) 1) this use case requires the reduced utilizatio n of vddp output current by 20 ma, see p_2.1.22. p_2.3.21 required decoupling capacitance c vddext1 0.1 ? 2.2 f 3) 2) esr < 1 ? ; the specified capacitor value is a typical value. 2) ceramic capacitor. p_2.3.22 required buffer capacitance for stability (load jumps) c vddext2 1?2.2f 3)2) the specified capacitor value is a typical value. p_2.3.20 output voltage including line and load regulation v ddext 4.9 5.0 5.1 v 3) i load <20ma; v s > 5.5v p_2.3.3 output voltage including line and load regulation v ddext 4.8 5.0 5.2 v i load <40ma; v s > 5.5v p_2.3.23 output drop @ active mode v s - v ddext 50 +300 mv 3) i load <20ma; 3v < v s <5.0v p_2.3.4 output drop @ active mode v s - v ddext ? +400 mv i load <40ma; 3v < v s <5.0v p_2.3.14 load regulation @ active mode v ddextlor -50 ? 50 mv 2 ... 40ma; c =200nf p_2.3.5 line regulation @ active mode v vddextlir -50 ? 50 mv v s = 5.5 ... 28v p_2.3.6 power supply ripp le rejection @ active mode p ssrvddext 50 ? ? db 3) v s = 13.5v; f =0 ... 1khz; vr=2vpp 3) not subject to production test, specified by design. p_2.3.7 overvoltage detection v vddextov 5.18 ? 5.4 v v s > 5.5v p_2.3.8 overvoltage detection filter time t filt_vddext ov ? 735 ? s 3)4) 4) this filter time and its variation is derived from the time base t lp_clk = 1 / f lp_clk . p_2.3.24 voltage ok detection range v vddextok ?3?v 3) p_2.3.25 voltage stable detection range 5) ? v vddextst b - 220 ? + 220 mv 3) p_2.3.26 undervoltage trigger v vddextuv 2.6 2.8 3.0 v 6) p_2.3.9 overcurrent diagnostic i vddextoc 50 ? 160 ma ? p_2.3.10 overcurrent diagnostic filter time t filt_vddcoc ?27?s 3)4) p_2.3.27 overcurrent diagnostic shutdown time t filt_vddcoc _sd ? 290 ? s 3)4) p_2.3.28 tle9869qxa20 electrical characteristics data sheet 91 rev. 1.0, 2017-03-03 5) the absolute voltage value is the sum of parameters v ddext + ? v ddextstb . 6) when the condition is met, the bi t vddext_ctrl.bit.short will be set. tle9869qxa20 electrical characteristics data sheet 92 rev. 1.0, 2017-03-03 29.2.4 vpre voltage regulator (pmu subblock) parameters the pmu vpre regulator acts as a supply of vddp and vddext voltage regulators. 29.2.4.1 load sharing scen arios of vpre regulator the figure below shows the possible load sharing scenarios of vpre regulator. figure 32 load sharing scenarios of vpre regulator table 25 functional range parameter symbol values unit note / test condition number min. typ. max. specified output current i vpre ??110ma 1) 1) not subject to production test, specified by design. p_2.4.1 load _sharing_vpre.vsd vddp - 5v 1: max. 90 ma 2: max. 70 ma vddc - 1.5v max. 40 ma vpre max. 110 ma vs vddp gnd (pin 39) vddc c vddc gnd (pin 39) load sharing vpre ? scenarios 1 & 2 c vddp vddext - 5v 1: max. 20 ma 2: max. 40 ma c vddext gnd (pin 39) vddext tle9869qxa20 electrical characteristics data sheet 93 rev. 1.0, 2017-03-03 29.2.5 power down voltage regula tor (pmu subblock) parameters the pmu power down voltage regulator consists of two subblocks: ? power down pre regulator: vdd5vpd ? power down core regulator: vdd1v5_pd (supply used for gpudataxy registers) both regulators are used as purely internal supplies. the following table contains all relevant parameters: table 26 functional range parameter symbol values unit note / test condition number min. typ. max. vdd1v5_pd power-on reset threshold v dd1v5_pd_ rstth 1.2 ? 1.5 v 1) 1) not subject to production test, specified by design p_2.5.1 tle9869qxa20 electrical characteristics data sheet 94 rev. 1.0, 2017-03-03 29.3 system clocks 29.3.1 oscillators and pll parameters table 27 electrical characteristics system clocks v s = 5.5 v to 28 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. pmu oscillators (power management unit) frequency of lp_clk f lp_clk 14 18 22 mhz this clock is used at startup and can be used in case the pll fails p_3.1.1 frequency of lp_clk2 f lp_clk2 70 100 130 khz this clock is used for cyclic wake p_3.1.2 cgu oscillator (clock genera tion unit microcontroller) short term frequency deviation 1) f trimst -0.4 ? +0.4 % 2)3) within any 10 ms, e.g. after synchronization to a lin frame (pll settings untouched within 10 ms) p_3.1.3 absolute accuracy f trimabsa -1.5 ? +1.5 % including temperature and lifetime deviation p_3.1.4 cgu-osc start-up time t osc ??10s 3) startup time osc from sleep mode, power supply stable p_3.1.5 pll (clock generation unit microcontroller) 3) vco frequency range mode 0 f vco-0 48 ? 112 mhz vcosel =?0? p_3.1.6 vco frequency range mode 1 f vco-1 96 ? 160 mhz vcosel =?1? p_3.1.7 input frequency range f osc 4 ? 16 mhz ? p_3.1.8 xtal1 input freq. range f osc 4 ? 16 mhz ? p_3.1.9 output freq. range f pll 0.04687 ? 80 mhz ? p_3.1.10 free-running frequency mode 0 f vcofree_0 ? ? 38 mhz vcosel =?0? p_3.1.11 free-running frequency mode 1 f vcofree_1 ? ? 76 mhz vcosel =?1? p_3.1.12 input clock high/low time t high/low 10 ? ? ns ? p_3.1.13 peak period jitter t jp -500 ? 500 ps 4) for k=1 p_3.1.14 accumulated jitter jacc ? ? 5 ns 4) for k=1 p_3.1.15 lock-in time t l ? ? 200 s ? p_3.1.16 tle9869qxa20 electrical characteristics data sheet 95 rev. 1.0, 2017-03-03 29.3.2 external clock para meters xtal1, xtal2 1) the typical oscillator frequency is 5 mhz 2) v ddc = 1.5 v, t j = 25c 3) not subject to production test, specified by design. 4) this parameter is valid for pll operation with an external clock source and thus reflects the real pll performance. table 28 functional range v s = 5.5 v to 28 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) 1) 1) this parameter table is not subject to production test, specified by design. parameter symbol values unit note / test condition number min. typ. max. input voltage range limits for signal on xtal1 v ix1_sr -1.7 + v ddc ?1.7 v 2) 2) overload conditions must not occur on pin xtal1. p_3.2.1 input voltage (amplitude) on xtal1 v ax1_sr 0.3 x v ddc ?? v 3) peak-to-peak voltage 3) the amplitude voltage v ax1 refers to the offset voltage v off . this offset voltage must be stable during the operation and the resulting voltage peaks must remain within the limits defined by v ix1 . p_3.2.2 xtal1 input current i il ??20a0v < v in < v ddi p_3.2.3 oscillator frequency f osc 4 ? 24 mhz clock signal p_3.2.4 oscillator frequency f osc 4 ? 16 mhz crystal or resonator p_3.2.5 high time t 1 6 ? ? ns ? p_3.2.6 low time t 2 6 ? ? ns ? p_3.2.7 rise time t 3 ? 8 8 ns ? p_3.2.8 fall time t 4 ? 8 8 ns ? p_3.2.9 tle9869qxa20 electrical characteristics data sheet 96 rev. 1.0, 2017-03-03 29.4 flash memory this chapter includes the parameters for the 128 kbyte embedded flash module. 29.4.1 flash parameters table 29 flash characteristics 1) v s = 3.0 v to 28 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) 1) not subject for production test, specified by design. parameter symbol values unit note / test condition number min. typ. max. programming time per 128 byte page t pr ?3 2) 2) programming and erase times depend on the internal flash clock source. the control state machine needs a few system clock cycles. the requirement is only rele vant for extremely low system frequencies. 3.5 ms 3v < v s < 28v p_4.1.1 erase time per sector/page t er ?4 2) 4.5 ms 3v < v s < 28v p_4.1.2 data retention time t ret 20 ? ? years 1,000 erase / program cycles p_4.1.3 data retention time t ret 50 ? ? years 1,000 erase / program cycles t j = 30c 3) 3) derived by extrapolation of lifetime tests. p_4.1.9 flash erase endurance for user sectors n er 30 ? ? kcycles data retention time 5 years p_4.1.4 flash erase endurance for security pages n sec 10??cycles 4) data retention time 20 years 4) t j = 25 c. p_4.1.5 drain disturb limit n dd 32 ? ? kcycles 5) 5) this parameter limits the number of subsequent programming operations within a physical sector without a given page in this sector being (re-)programmed. the drain disturb limit is applicable if wordline erase is used repeatedly. for normal sector erase/program cycles this limit will not be violated. for da ta sectors the integrated eeprom emulation firmware routines handle this limit automatically, for wordline er ases in code sectors (withou t eeprom emulation) it is recommended to execute a software based refresh, which ma y make use of the integrat ed random number generator nvmbrng to statistically start a refresh. p_4.1.6 tle9869qxa20 electrical characteristics data sheet 97 rev. 1.0, 2017-03-03 29.5 parallel ports (gpio) 29.5.1 description of keep and force current figure 33 pull-up/down device figure 34 pull-up keep and forced current pull-up-down.vsd pu device pd device p1.x p0.x keeper current keeper current pudsel \pudsel v ss v ddp logical "1" undefined logical "0" current_diag.vsd -i plk -i plf v ih -v ddp v il -v ddp u gpio i 7.5 kohm (equivalent) (1.5v / 200ua) 2.33 kohm (equivalent) (3.5v / 1.5ma) tle9869qxa20 electrical characteristics data sheet 98 rev. 1.0, 2017-03-03 figure 35 pull-down keep and force current 29.5.2 dc parameters of port 0, port 1, tms and reset note: operating conditions apply. keeping signal levels within the limits specified in th is table ensures operation without overload conditions. for signal levels outside these specifications, also refer to the specification of the maximum allowed ocurrent which can be taken out of vddp. table 30 current limits fo r port output drivers 1) 1) not subject to production test, specified by design. port output driver mode maximum output current ( i olmax , - i ohmax) maximum output current ( i olnom , - i ohnom) number v ddp 4.5v 2.6v < v ddp < 4.5v v ddp 4.5v 2.6v < v ddp < 4.5v strong driver 2) 2) not available for port pins p0.4, p1.0, p1.1 and p1.2 5 ma 3 ma 1.6 ma 1.0 ma p_5.1.15 medium driver 3) 3 ma 1.8 ma 1.0 ma 0.8 ma p_5.1.1 weak driver 3) 3) all p0.x and p1.x 0.5 ma 0.3 ma 0.25 ma 0.15 ma p_5.1.2 table 31 dc characteristics port0, port1 v s = 5.5 v to 28 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. input hysteresis hys p0_p1 0.11 x v ddp ?? v 1) series resistance = 0 ? ; 4.5v v ddp 5.5v p_5.1.5 input hysteresis hys p0_p1 _exend ? 0.09 x v ddp ?v 1) series resistance = 0 ? ; 2.6v v ddp 4.5v p_5.1.16 logical "1" undefined logical "0" current_diag-pull _down.vsd i plk i plf i 2.33 kohm (equivalent) (3.5v / 1.5ma) 7.5 kohm (equivalent ) (1.5v / 200ua) u gpio v ih v il tle9869qxa20 electrical characteristics data sheet 99 rev. 1.0, 2017-03-03 input low voltage v il -0.3 ? 0.3 x v ddp v 2) 4.5v v ddp 5.5v p_5.1.3 input low voltage v il_extend -0.3 0.42 x v ddp ?v 1) 2.6v v ddp 4.5v p_5.1.17 input high voltage v ih 0.7 x v ddp ? v ddp + 0.3 v 2) 4.5v v ddp 5.5v p_5.1.4 input high voltage v ih_extend ? 0.52 x v ddp v ddp + 0.3 v 1) 2.6v v ddp 4.5v p_5.1.18 output low voltage v ol ??1.0v 3) 4) i ol i olmax p_5.1.6 output low voltage v ol ??0.4v 3) 5) i ol i olnom p_5.1.7 output high voltage v oh v ddp - 1.0 ? ? v 3) 4) i oh i ohmax p_5.1.8 output high voltage v oh v ddp - 0.4 ? ? v 3) 5) i oh i ohnom p_5.1.9 input leakage current i oz_extend1 -500 ? +500 na -40c t j 25c, 0.45 v < v in < v ddp p_5.1.20 input leakage current i oz1 -5 ? +5 a 6) 25c < t j 85c, 0.45 v < v in < v ddp p_5.1.10 input leakage current i oz_extend2 -15 ? +15 a 85c < t j 150c, 0.45 v < v in < v ddp p_5.1.11 pull level keep current i plk -200 ? +200 a 7) v pin v ih (up) v pin v il (dn) p_5.1.12 pull level force current i plf -1.5 ? +1.5 ma 7) v pin v il (up) v pin v ih (dn) p_5.1.13 pin capacitance c io ??10pf 1) p_5.1.14 reset pin timing reset pin input filter time t filt_reset ?5?s 1) p_5.1.19 1) not subject to production test, specified by design. 2) tested at v ddp = 5v, specified for 4.5v < v ddp < 5.5v. 3) the maximum deliverable output current of a port driver dep ends on the selected output dr iver mode. the limit for pin groups must be respected. 4) tested at 4.9v < v ddp < 5.1v, i ol = 4ma, i oh = -4ma, specified for 4.5v < v ddp < 5.5v. 5) as a rule, with decreasing output current the output levels approac h the respective supply level ( v ol gnd , v oh v ddp ). tested at 4.9v < v ddp < 5.1v, i ol = 1ma, i oh = -1ma. table 31 dc characteristics port0, port1 (cont?d) v s = 5.5 v to 28 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. tle9869qxa20 electrical characteristics data sheet 100 rev. 1.0, 2017-03-03 29.5.3 dc parameters of port 2 these parameters apply to the io voltage range, 4.5 v v ddp 5.5 v. note: operating conditions apply. keeping signal levels within the limits specified in th is table ensures operation without overload conditions. for signal levels outside these specifications, also refer to the specification of the overload current i ov . 6) the given values are worst-case values. in production tests, this leakage current is only te sted at 150c; ot her values are ensured by correlation. for derating, please refer to the following descriptions: leakage derating depending on temperature ( t j = junction temperature [c]): i oz = 0.05 e (1.5 + 0.028tj) [a]. for example, at a temperature of 95 c the resulting leakage current is 3.2 a. leakage derating depending on voltage level (dv = v ddp - v pin [v]): i oz = i oztempmax - (1.6 dv) [a] this voltage derating formula is an approxim ation which applies for maximum temperature. 7) keep current: limit the current through this pin to the indi cated value so that the enabled pull device can keep the default pin level: v pin v ih for a pull-up; v pin v il for a pull-down. force current: drive the indicat ed minimum current through this pin to change the default pin level driven by the enabled pull device: v pin v il for a pull-up; v pin v ih for a pull-down. these values apply to the fixed pull-devices in dedicated pins and to the user-selectable pull-devices in general purpose io pins. table 32 dc characteristics port 2 v s = 5.5 v to 28 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. input low voltage v il -0.3 ? 0.3 x v ddp v 1) 4.5v v ddp 5.5v p_5.2.1 input low voltage v il_extend -0.3 0.42 x v ddp ?v 2) 2.6v v ddp 4.5v p_5.2.10 input high voltage v ih 0.7 x v ddp ? v ddp + 0.3 v 1) 4.5v v ddp 5.5v p_5.2.2 input high voltage v ih_extend ? 0.52 x v ddp v ddp + 0.3 v 2) 2.6v v ddp 4.5v p_5.2.11 input hysteresis hys p2 0.11 x v ddp ?? v 2) series resistance = 0 ? ; 4.5v v ddp 5.5v p_5.2.3 input hysteresis hys p2_ext end ? 0.09 x v ddp ?v 2) series resistance = 0 ? ; 2.6v vddp < 4.5v p_5.2.12 input leakage current i oz2 -400 ? +400 na t j 85c, 0v < v in < v ddp p_5.2.4 pull level keep current i plk -30 ? +30 a 3) v pin v ih (up) v pin v il (dn) p_5.2.5 tle9869qxa20 electrical characteristics data sheet 101 rev. 1.0, 2017-03-03 pull level force current i plf -750 ? +750 a 3) v pin v il (up) v pin v ih (dn) p_5.2.6 pin capacitance (digital inputs/outputs) c io ??10pf 2) p_5.2.7 1) tested at v ddp = 5v, specified for 4.5v < v ddp < 5.5v. 2) not subject to production test, specified by design. 3) keep current: limit the current through this pin to the indi cated value so that the enabled pull device can keep the default pin level: v pin v ih for a pull-up; v pin v il for a pull-down. force current: drive the indicat ed minimum current through this pin to change the default pin level driven by the enabled pull device: v pin v il for a pull-up; v pin v ih for a pull-down. table 32 dc characteristics port 2 (cont?d) v s = 5.5 v to 28 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. tle9869qxa20 electrical characteristics data sheet 102 rev. 1.0, 2017-03-03 29.6 lin transceiver 29.6.1 electrical characteristics table 33 electrical characteristics lin transceiver v s = 5.5v to 18v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. bus receiver interface receiver threshold voltage, recessive to dominant edge v th_dom 0.4 v s 0.45 v s 0.53 x v s v sae j2602 p_6.1.1 receiver dominant state v busdom -27 ? 0.4 v s v lin spec 2.2 (par. 17) p_6.1.2 receiver threshold voltage, dominant to recessive edge v th_rec 0.47 x v s 0.55 v s 0.6 v s v sae j2602 p_6.1.3 receiver recessive state v busrec 0.6 v s ?1.15 v s v 1) lin spec 2.2 (par. 18) p_6.1.4 receiver center voltage v bus_cn t 0.475 v s 0.5 v s 0.525 v s v 2) lin spec 2.2 (par. 19) p_6.1.5 receiver hysteresis v hys 0.07 v s 0.12 v s 0.175 v s v 3) lin spec 2.2 (par. 20) p_6.1.6 wake-up threshold voltage v bus,wk 0.4 v s 0.5 v s 0.6 v s v ? p_6.1.7 dominant time for bus wake- up (internal analog filter delay) t wk,bus 3 ? 15 s the overall dominant time for bus wake-up is a sum of t wk,bus + adjustable digital filter time. the digital filter time can be adjusted by pmu.cnf_wake_fil ter.cnf_lin_ft; p_6.1.8 bus transmitter interface bus recessive output voltage v bus,ro 0.8 v s ? v s v v txd = high level p_6.1.9 bus dominant output voltage v bus,do ? ? 0.22 v s v driver dominant voltage r l = 500 ohm p_6.1.78 tle9869qxa20 electrical characteristics data sheet 103 rev. 1.0, 2017-03-03 bus short circuit current i bus,sc 40 100 150 ma current limitation for driver dominant state driver on v bus = 18 v; lin spec 2.2 (par. 12) p_6.1.10 bus short circuit filter time t bus,sc ?5 ? s 6) the overall bus short circuit filter time is a sum of tbus,sc + digital filter time. the digital filter time is 4 s (typ.) p_6.1.71 leakage current (loss of ground) i bus_no_ gnd -1000 -450 1000 a v s = 12 v; 0 < v bus < 18 v; lin spec 2.2 (par. 15) p_6.1.11 leakage current i bus_no_ bat ?1020 a v s = 0 v; v bus = 18 v; lin spec 2.2 (par. 16) p_6.1.12 leakage current i bus_pas _dom -1 ? ? ma v s = 18 v; v bus = 0 v; lin spec 2.2 (par. 13) p_6.1.13 leakage current i bus_pas _rec ?? 20 a v s = 8 v; v bus = 18 v; lin spec 2.2 (par. 14) p_6.1.14 bus pull-up resistance r bus 20 30 47 k ? normal mode lin spec 2.2 (par. 26) p_6.1.15 ac characteristics - transceiver normal slope mode propagation delay bus dominant to rxd low t d(l),r 0.1 ? 6 s lin spec 2.2 (param. 31) p_6.1.16 propagation delay bus recessive to rxd high t d(h),r 0.1 ? 6 s lin spec 2.2 (param. 31) p_6.1.17 receiver delay symmetry t sym,r -2 ? 2 s t sym,r = t d(l),r - t d(h),r ; lin spec 2.2 (par. 32) p_6.1.18 duty cycle d1 normal slope mode (for worst case at 20 kbit/s) t duty1 0.396 ? ? 4) duty cycle 1 th rec (max) = 0.744 v s ; th dom (max) = 0.581 v s ; v s = 5.5 ? 18 v; t bit = 50 s; d1 = t bus_rec(min) /2 t bit ; lin spec 2.2 (par. 27) p_6.1.19 table 33 electrical characteristics lin transceiver (cont?d) v s = 5.5v to 18v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. tle9869qxa20 electrical characteristics data sheet 104 rev. 1.0, 2017-03-03 duty cycle d2 normal slope mode (for worst case at 20 kbit/s) t duty2 ? ? 0.581 4) duty cycle 2 th rec (min) = 0.422 v s ; th dom (min) = 0.284 v s ; v s = 5.5 ? 18 v; t bit = 50 s; d2 = t bus_rec(max) /2 t bit ; lin spec 2.2 (par. 28) p_6.1.20 ac characteristics - transceiver low slope mode propagation delay bus dominant to rxd low t d(l),r 0.1 ? 6 s lin spec 2.2 (param. 31) p_6.1.21 propagation delay bus recessive to rxd high t d(h),r 0.1 ? 6 s lin spec 2.2 (param. 31) p_6.1.22 receiver delay symmetry t sym,r -2 ? 2 s t sym,r = t d(l),r - t d(h),r ; lin spec 2.2 (par. 32) p_6.1.23 duty cycle d3 (for worst case at 10.4 kbit/s) t duty1 0.417 ? ? 4) duty cycle 3 th rec (max) = 0.778 v s ; th dom (max) = 0.616 v s ; v s = 5.5 ? 18 v; t bit = 96 s; d3 = t bus_rec(min) /2 t bit ; lin spec 2.2 (par. 29) p_6.1.24 duty cycle d4 (for worst case at 10.4 kbit/s) t duty2 ? ? 0.590 4) duty cycle 4 th rec (min) = 0.389 v s ; th dom (min) = 0.251 v s ; v s = 5.5 ? 18 v; t bit = 96 s; d4 = t bus_rec(max) /2 t bit ; lin spec 2.2 (par. 30) p_6.1.25 ac characteristics - transceiver fast slope mode propagation delay bus dominant to rxd low t d(l),r 0.1 ? 6 s ? p_6.1.26 propagation delay bus recessive to rxd high t d(h),r 0.1 ? 6 s ? p_6.1.27 receiver delay symmetry t sym,r -1.5 ? 1.5 s t sym,r = t d(l),r - t d(h),r ;p_6.1.28 ac characteristics - flash mode propagation delay bus dominant to rxd low t d(l),r 0.1 ? 6 s ? p_6.1.31 table 33 electrical characteristics lin transceiver (cont?d) v s = 5.5v to 18v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. tle9869qxa20 electrical characteristics data sheet 105 rev. 1.0, 2017-03-03 propagation delay bus recessive to rxd high t d(h),r 0.1 ? 6 s ? p_6.1.32 receiver delay symmetry t sym,r -1.0 ? 1.5 s t sym,r = t d(l),r - t d(h),r ;p_6.1.33 duty cycle d7 (for worst case at 115 kbit/s) for +1 s receiver delay symmetry t duty1 0.399 ? ? 5) duty cycle d7 threc(max) = 0.744 v s ; th dom (max) = 0.581 v s ; v s = 13.5 v; t bit = 8.7 s; d7 = t bus_rec(min) /2 t bit ; p_6.1.34 duty cycle d8 (for worst case at 115 kbit/s) for +1 s receiver delay symmetry t duty2 ? ? 0.578 5) duty cycle 8 th rec (min) = 0.422 v s ; th dom (min) = 0.284 v s ; v s = 13.5 v; t bit = 8.7 s; d8 = t bus_rec(max) /2 t bit ; p_6.1.35 lin input capacity c lin_in ?1530 pf 6) p_6.1.69 txd dominant time out t timeout 61220 ms v txd = 0 v p_6.1.36 thermal shutdown (junction temperature) thermal shutdown temp. t jsd 190 200 215 c 6) p_6.1.65 thermal shutdown hyst. ? t ?10? k 6) p_6.1.66 1) maximum limit specified by design. 2) v bus_cnt = ( v th_dom + v th rec )/2 3) v hys = v busrec - v busdom 4) bus load concerning lin spec 2.2: load 1 = 1 nf / 1 k ? = c bus / r bus load 2 = 6.8 nf / 660 ? = c bus / r bus load 3 = 10 nf / 500 ? = c bus / r bus 5) bus load load 1 = 1 nf / 500 ? = c bus / r bus 6) not subject to production test, specified by design. table 33 electrical characteristics lin transceiver (cont?d) v s = 5.5v to 18v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. tle9869qxa20 electrical characteristics data sheet 106 rev. 1.0, 2017-03-03 29.7 high-speed synchr onous serial interface 29.7.1 ssc timing parameters the table below provides the ssc timing in the tle9869qxa20. figure 36 ssc master mode timing table 34 ssc master mode timing (o perating conditions apply; cl = 50 pf) v s = 5.5 v to 28 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. sclk clock period t 0 1) 2 * t ssc 1) t sscmin =t cpu =1/ f cpu . if f cpu = 20 mhz, t 0 = 100 ns. t cpu is the cpu clock period. ?? 2) v ddp > 2.7 v 2) not subject to production test, specified by design. p_7.1.1 mtsr delay from sclk t 1 10 ??ns 2) v ddp > 2.7 v p_7.1.2 mrst setup to sclk t 2 10 ??ns 2) v ddp > 2.7 v p_7.1.3 mrst hold from sclk t 3 15 ??ns 2) v ddp > 2.7 v p_7.1.4 ssc_tmg1 sclk 1) mtsr 1) t 1 t 1 mrst 1) t 3 data valid t 2 t 1 1) this timing is based on the following setup: con.ph = con.po = 0. t 0 tle9869qxa20 electrical characteristics data sheet 107 rev. 1.0, 2017-03-03 29.8 measurement unit 29.8.1 system voltage measurement parameters table 35 supply voltage signal conditioning v s = 5.5 v to 28 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. measurement output voltage range @ varef5 v a5 0 ? 5 v ? p_8.1.15 measurement output voltage range @ varef1v2 v a1v2 0 ? 1.23 v ? p_8.1.16 battery / supply voltage measurement v bat_sense / v s input to output voltage attenuation: v s att vs_1 ? 0.055 ? sfr setting 1 p_8.1.41 input to output voltage attenuation: v bat_sense att vbat_sense _1 ? 0.055 ? sfr setting 1 p_8.1.60 nominal operating input voltage range v bat_sense and v s v bat_sense ,range1 , v s,range1 3? 22v 1) sfr setting 1; max. value corresponds to typ. adc full scale input; 3v < v bat_sense / v s < 28v p_8.1.1 accuracy of v bat_sense / v s after calibration v bat_sense ,range1 , v s,range1 -220 ? 220 mv sfr setting 1, v s =5.5 v to 18v p_8.1.70 input to output voltage attenuation: v s att vs_2 ? 0.039 ? sfr setting 2 p_8.1.42 input to output voltage attenuation: v bat_sense att vbat_sense _2 ? 0.039 ? sfr setting 2 p_8.1.61 nominal operating input voltage range v bat_sense and v s v bat_sense ,range2 , v s,range2 3? 31v 1) sfr setting 2; max. value corresponds to typ. adc full scale input 3v < v bat_sense / v s < 28v p_8.1.40 accuracy of v bat_sense / v s after calibration v bat_sense ,range2 , v s,range2 -370 ? 370 mv sfr setting 2, v s = 5.5v to 18v p_8.1.44 tle9869qxa20 electrical characteristics data sheet 108 rev. 1.0, 2017-03-03 measurement input leakage current for v bat_sense i leak_vbat_sense , measure 0 ? 4.0 a pd_n=0 (off-state), v bat_sense = 13.5v p_8.1.72 driver supply voltage measurement v sd input to output voltage attenuation: v sd att vsd ? 0.039 ? ? p_8.1.21 nominal operating input voltage range v sd v sd,range 2.5 ? 31 v 1) p_8.1.2 accuracy of v sd sense after calibration ? v sd -440 ? 440 mv v s = 5.5v to 18v p_8.1.47 charge pump voltage measurement v cp input to output voltage attenuation: v cp att vcp ? 0.023 ? ? p_8.1.56 nominal operating input voltage range v cp v cp,range 2.5 ? 52 v 1) p_8.1.7 accuracy of v cp sense after calibration ? v cp -747 ? 747 mv v s = 5.5v to 18v p_8.1.62 monitoring input voltage measurement v mon input to output voltage attenuation: v mon att vmon ? 0.039 ? ? p_8.1.49 nominal operating input voltage range v mon v mon,range 2.5 ? 31 v 1) p_8.1.8 accuracy of v mon sense after calibration ? v mon -440 ? 440 mv v s = 5.5v to 18v p_8.1.68 pad supply voltage measurement v vddp input-to-output voltage attenuation: v ddp att vddp ? 0.164 ? ? p_8.1.33 nominal operating input voltage range v ddp v ddp,range 0 ? 7.50 v 1) p_8.1.50 accuracy of v ddp sense after calibration ? v ddp_sense -105 ? 105 mv 2) v s = 5.5 to 18v p_8.1.5 10-bit adc reference voltage measurement v aref input to output voltage attenuation: v aref att varef ? 0.219 ? ? p_8.1.22 table 35 supply voltage signal conditioning (cont?d) v s = 5.5 v to 28 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. tle9869qxa20 electrical characteristics data sheet 109 rev. 1.0, 2017-03-03 nominal operating input voltage range v aref v aref,range 0 ? 5.62 v 1) p_8.1.51 accuracy of v aref sense after calibration ? v aref -79 ? 79 mv v s = 5.5v to 18v p_8.1.48 8-bit adc reference vo ltage measurement v bg input-to-output voltage attenuation: v bg att vbg ? 0.75 ? ? p_8.1.57 nominal operating input voltage range v bg v bg,range 0.8 ? 1.64 v 1) p_8.1.52 value of adc2- v bg measurement after calibration v bg_pmu 1.01 1.07 1.18 v p_8.1.73 core supply voltage measurement v ddc input-to-output voltage attenuation: v ddc att vddc ? 0.75 ? ? p_8.1.34 nominal operating input voltage range v ddc v ddc,range 0.8 ? 1.64 v 1) p_8.1.53 accuracy of v ddc sense after calibration ? v ddc_sense -22 ? 22 mv v s = 5.5 to 18v p_8.1.6 vdh input voltage measurement v vdh10bitadc vdh input to output voltage attenuation: att vdh_1 ? 0.166 ? sfr setting 1 p_8.1.64 vdh input to output voltage attenuation: att vdh_2 ? 0.224 ? sfr setting 2 p_8.1.65 vdh input to output voltage attenuation: att vdh_3 -0.226- 1) sfr setting 2 tj = -40..85c p_8.1.75 nominal operating input voltage range v vdh , range 1 v vdh,range1 ? ? 30 sfr setting 1 p_8.1.66 nominal operating input voltage range v vdh , range 2 v vdh,range2 ? ? 20 sfr setting 2 p_8.1.67 v vdh 10-bit adc, range 1 ? v vdhadc10b -300 ? 300 mv v dh = 5.5 to 17.5v, t j = -40..150c p_8.1.39 v vdh 10-bit adc, range 3 ? v vdhadc10b -200 ? 200 mv 1) vdh= 5.5v to 17.5v, tj = -40..85c att vdh_3 p_8.1.71 table 35 supply voltage signal conditioning (cont?d) v s = 5.5 v to 28 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. tle9869qxa20 electrical characteristics data sheet 110 rev. 1.0, 2017-03-03 v vdh 10-bit adc, range 2 ? v vdhadc10b_ex tend_t -400 ? 400 mv v dh = 5.5v to 17.5v, t j = -40..150c p_8.1.74 10-bit adc measurement input resistan ce for vdh r in_vdh,measure 200 390 470 k ? pd_n=1 (on-state) p_8.1.3 measurement input leakage current for v vdh i leak_vdh, measure -0.05 ? 2.0 a pd_n=0 (off-state), v vdh = 13.5v p_8.1.10 1) not subject to production test, specified by design. 2) accuracy is valid fo r a calibrated device. table 35 supply voltage signal conditioning (cont?d) v s = 5.5 v to 28 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. tle9869qxa20 electrical characteristics data sheet 111 rev. 1.0, 2017-03-03 29.8.2 central temperature sensor parameters table 36 electrical characteristics temperature sensor module v s = 3.0 v to 28 v, t j = -40 c to +150 c; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. output voltage v temp at t 0 =273 k (0c) a ? 0.666 ? v 1) t 0 =273 k (0c) 1) not subject to production test, specified by design p_8.2.2 temperature sensitivity b b ? 2.31 ? mv/k 1) p_8.2.4 accuracy_1 acc_1 -10 ? 10 c 2)1) -40c < tj < 85c 2) accuracy with reference to on-chip temperat ure calibration measurement, valid for mode1 p_8.2.5 accuracy_2 acc_2 -10 ? 10 c 2)1) 125c < tj < 150c p_8.2.6 accuracy_3 acc_3 -5 ? 5 c 2)1) 85c < tj < 125c p_8.2.7 tle9869qxa20 electrical characteristics data sheet 112 rev. 1.0, 2017-03-03 29.8.3 adc2-vbg 29.8.3.1 adc2 reference voltage vbg 29.8.3.2 adc2 specifications table 37 dc specifications v s = 3.0 v to 28 v, t j = -40 c to +150 c; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. reference voltage v bg 1.199 1.211 1.223 v 1) 1) not subject to production test, spedesign p_8.3.1 table 38 dc specifications v s = 5.5 v to 28 v, t j = -40 c to +150 c; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. resolution res ? 8 ? bits full p_8.3.18 guaranteed offset error ea off_8 bit -2.0 0.3 2.0 lsb not calibrated p_8.3.19 gain error ea gain_8 bit -2.0 0.5 2.0 %fsr not calibrated p_8.3.20 differential non-linearity (dnl) ea dnl_8 bit -0.8 0 0.8 lsb full p_8.3.21 integral non-linearity (inl) ea inl_8bi t -1.2 0 1.2 lsb ? p_8.3.22 tle9869qxa20 electrical characteristics data sheet 113 rev. 1.0, 2017-03-03 29.9 adc1 reference voltage - varef 29.9.1 electrical ch aracteristics varef table 39 electrical characteristics varef v s = 5.5 v to 28 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. required buffer capacitance c varef 0.1?1fesr < 1 ? p_9.1.1 reference output voltage v aref 4.95 5 5.05 v v s > 5.5v p_9.1.2 dc supply voltage rejection dc psrvaref 30??db 1) ? 1) not subject to production test, specified by design. p_9.1.3 supply voltage ripple rejection ac psrvaref 26??db 1) v s = 13.5v; f = 0 ... 1khz; v r = 2vpp p_9.1.4 turn on time t so ? ? 200 s 1) c ext = 100nf pd_n to 99.9% of final value p_9.1.5 input resistance at varef pin r in,varef ?100?k ? 1) input impedance in case of varef is applied from external p_9.1.20 tle9869qxa20 electrical characteristics data sheet 114 rev. 1.0, 2017-03-03 29.9.2 electrical charact eristics adc1 (10-bit) these parameters describe the conditions for optimum adc performance. note: operating conditions apply. table 40 a/d converter characteristics v s = 5.5 v to 28 v, t j = -40 c to +150 c; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. analog reference supply v aref v agnd + 1.0 ? v ddpa + 0.05 v 1) p_9.2.1 analog reference ground v agnd v ss - 0.05 ? 1.5 v ? p_9.2.2 analog input voltage range v ain v agnd ? v aref v 2) p_9.2.3 analog clock frequency f adci 5?24mhz 3) p_9.2.4 conversion time for 10- bit result t c10 (13 + stc) t adci +2x t sys (13 + stc ) t adci +2x t sys (13 + stc ) t adci +2x t sys ? 1)4) p_9.2.5 conversion time for 8-bit result t c8 (11 + stc) t adci +2 t sys (11 + stc ) t adci +2 t sys (11 + stc ) t adci +2 t sys ? 1) p_9.2.6 wakeup time from analog powerdown, fast mode t waf ? ?4s 1) p_9.2.7 wakeup time from analog powerdown, slow mode t was ??15s 1)5) p_9.2.8 total unadjusted error (8 bit) tue 8b -2 1 +2 counts 6)7) reference is internal v aref p_9.2.9 total unadjusted error (10 bit) tue 10b -12 6 +12 counts 7)8) reference is internal v aref p_9.2.22 dnl error ea dnl -3 0.8 +3 counts ? p_9.2.10 inl error ea inl_int_v aref -5 0.8 +5 counts reference is internal v aref p_9.2.11 gain error ea gain_int_ varef -10 0.4 +10 counts reference is internal v aref p_9.2.12 offset error ea off -2 0.5 +2 counts ? p_9.2.13 total capacitance of an analog input c aint ? ? 10 pf 1)5)9) p_9.2.14 switched capacitance of an analog input c ains ? ?4pf 1)5)9) p_9.2.15 resistance of the analog input path r ain ? ?2k ? 1)5)9) p_9.2.16 tle9869qxa20 electrical characteristics data sheet 115 rev. 1.0, 2017-03-03 29.10 reserved total capacitance of the reference input c areft ? ? 15 pf 1)5)9) p_9.2.17 switched capacitance of the reference input c arefs ? ?7pf 1)5)9) p_9.2.18 resistance of the reference input path r aref ? ?2k ? 1)5)9) p_9.2.19 1) not subject to production test, specified by design. 2) v ain may exceed v agnd or v arefx up to the absolute maximum ratings. however, the conversion result in these cases will be 0000 h or 03ff h , respectively. 3) the limit values for f adci must not be exceeded when selecting the peripheral frequency and the prescaler setting. 4) this parameter includes the sample time (also the additional sample time specif ied by stc), the time to determine the digital result and the time to load the result register with the conversion result. 5) the broken wire detection delay against v agnd is measured in numbers of consecut ive precharge cycles at a conversion rate of not more than 500 s. 6) the total unadjusted error tue is the maximum deviation from the ideal adc transfer curve, not the sum of individual errors. all error specifications are based on meas urement methods standar dized by ieee 1241.2000. 7) the specified tue is valid only if the abso lute sum of input overload currents (see i ov specification) does not exceed 10 ma, and if v aref and v agnd remain stable during the measurement time. 8) the total unadjusted error tue is the maximum deviation from the ideal adc transfer curve, not the sum of individual errors. all error specifications are based on meas urement methods standar dized by ieee 1241.2000. 9) these parameter values cover the complete operating ran ge. under relaxed operating conditions (temperature, supply voltage) typical values can be used for calculation. at room temperature and nominal supply voltage the following typical values can be used: c ainttyp = 12 pf, c ainstyp = 5 pf, r aintyp = 1.0 k ? , c arefttyp = 15 pf, c arefstyp = 10 pf, r areftyp = 1.0 k ? . table 40 a/d converter characteristics (cont?d) v s = 5.5 v to 28 v, t j = -40 c to +150 c; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. tle9869qxa20 electrical characteristics data sheet 116 rev. 1.0, 2017-03-03 29.11 high-voltage monitoring input 29.11.1 electrical characteristics table 41 electrical characteristics monitoring input t j = -40 c to +150 c; v s = 5.5 v to 28 v, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. mon input pin characteristics wake-up/monitoring threshold voltage v month 0.4* v s 0.5* v s 0.6* v s v without external serial resistor r s (with r s :dv = i pd/pu * r s ); v s = 5.5v to 18v p_11.1.1 wake-up/monitoring threshold voltage extended range v month_ext end 0.44* v s 0.53* v s 0.64* v s v without external serial resistor r s (with r s :dv = i pd/pu * r s ) p_11.1.11 threshold hysteresis v month,hys 0.015* v s 0.05* v s 0.1* v s v in all modes; without external serial resistor r s (with r s :dv = i pd/pu * r s ); v s = 5.5v to 18v; p_11.1.12 threshold hysteresis v month,hys 0.02* v s 0.06* v s 0.12* v s v in all modes; without external serial resistor r s (with r s :dv = i pd/pu * r s ); v s = 18v to 28v; p_11.1.2 pull-up current i pu, mon -20 -10 -1 a 0.6* v s p_11.1.3 pull-down current i pd, mon 31020a0.4* v s p_11.1.4 input leakage current i lk,mon -2.5 ? 2.5 a 1) 0v < v mon_in < 28 v 1) input leakage is valid for disabled state. p_11.1.5 timing wake-up filter time (internal analog filter delay) t ft,mon ? 500 ? ns 2) the overall filter time for mon wake-up is a sum of t ft,mon + adjustable digital filter time. the digital filter time can be adjusted by pmu.cnf_wake_filte r.cnf_mon_ft; 2) with pull-up, pull down current disabled. p_11.1.6 tle9869qxa20 electrical characteristics data sheet 117 rev. 1.0, 2017-03-03 29.12 mosfet driver 29.12.1 electrical characteristics table 42 electrical characteristics mosfet driver v s = 5.5 v to 28 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. mosfet driver output maximum total charge driver capability q tot_max ? ? 100 nc 1) due to charge pump currrent capability only 3 x mosfets + additional external capacitors with a total charge of max. 100nc can be driven simultaneous at a pwm frequency of 25 khz. p_12.1.20 source current - charge current - high side driver i soumax_hs 230 345 450 ma v sd 8v, c load = 10 nf, i sou = c load * slew rate ( = 20%-50% of v ghx1 ), i charge = i dischg = 31(max) p_12.1.78 sink current - discharge current-high side driver i sinkmax_hs 230 330 450 ma v sd 8v, c load = 10 nf, i sink = c load * slew rate ( = 50%-20% of v ghx1 ), i charge = i dischg = 31(max) p_12.1.79 source current - charge current - low side driver i soumax_ls 200 295 375 ma v sd 8v, c load = 10 nf, i sou = c load * slew rate ( = 20%-50% of v glx1 ), i charge = i dischg = 31(max) p_12.1.80 sink current - discharge current-low side driver i sinkmax_ls 200 314 375 ma v sd 8v, c load = 10 nf, i sink = c load * slew rate ( = 50%-20% of v ghx1 ), i charge = i dischg = 31(max) p_12.1.81 high level output voltage gxx vs. sxx v gxx1 10 ? 14 v v sd 8v, c load = 10 nf, i cp =2.5 ma 2) . p_12.1.3 high level output voltage ghx vs. shx v gxx2 8??v v sd =6.4v 1) , c load = 10 nf, i cp =2.5 ma 2) p_12.1.4 high level output voltage ghx vs. shx v gxx3 7??v v sd =5.4v, c load = 10 nf, i cp =2.5 ma 2) p_12.1.5 tle9869qxa20 electrical characteristics data sheet 118 rev. 1.0, 2017-03-03 high level output voltage glx vs. gnd v gxx6 8??v v sd =6.4v 1) , c load = 10 nf, i cp =2.5 ma 2) p_12.1.6 high level output voltage glx vs. gnd v gxx7 7??v v sd =5.4 v, c load = 10 nf, i cp =2.5 ma 2) p_12.1.7 rise time t rise3_3nf ?200?ns 1) cload = 3.3 nf, v sd 8v, 25-75% of v gxx1 , i charge = i dischg = 31(max) p_12.1.8 fall time t fall3_3nf ?200?ns 1) c load =3.3nf, v sd 8v, 75-25% of v gxx1 , i charge = i dischg = 31(max) p_12.1.9 rise time t risemax 100 250 450 ns c load =10nf, v sd 8 v, 25-75% of v gxx1 , i charge = i dischg = 31(max) p_12.1.57 fall time t fallmax 100 250 450 ns c load =10nf, v sd 8 v, 75-25% of v gxx1 , i charge = i dischg = 31(max) p_12.1.58 rise time t risemin 1.25 2.5 5 s 1) c load =10nf, v sd 8 v, 25-75% of v gxx1 , i charge = i dischg = 3(min) p_12.1.14 fall time t fallmin 1.25 2.5 5 s 1) c load =10nf, v sd 8 v, 75-25% of v gxx1 , i charge = i dischg = 3(min) p_12.1.15 absolute rise - fall time difference for all lsx t r_f(diff)lsx ? ? 100 ns c load =10nf, v sd 8 v, 25-75% of v gxx1 , i charge = i dischg = 31(max) p_12.1.35 absolute rise - fall time difference for all hsx t r_f(diff)hsx ? ? 100 ns c load =10nf, v sd 8 v, 25-75% of v gxx1 , i charge = i dischg = 31(max) p_12.1.36 resistor between ghx/glx and gnd r ggnd 30 40 50 k ? 1) ? p_12.1.11 table 42 electrical characteristics mosfet driver (cont?d) v s = 5.5 v to 28 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. tle9869qxa20 electrical characteristics data sheet 119 rev. 1.0, 2017-03-03 resistor between shx and gnd r shgn 30 40 50 k ? 1)3) this resistance is the resistance between ghx and gnd connected through a diode to shx. as a consequence, the voltage at shx can rise up to 0,6v typ. before it is discharged through the resistor. p_12.1.10 low rdson mode (boosted discharge mode) r onccp ?912 ? v vsd =13.5v, v vcp = v vsd + 14.0 v; i charge = i dischg = 31(max); 50ma forced into gx, sx grounded p_12.1.50 resistance between vdh and vsd i bsh ?4?k ? 1) p_12.1.24 input propagation time (ls on) t p(iln)min ?1.53s 1) c load = 10 nf, i charge =3(min), 25% of v gxx1 p_12.1.37 input propagation time (ls off) t p(ilf)min ?1.53s 1) c load = 10 nf, i discharge =3(min), 75% of v gxx1 p_12.1.38 input propagation time (hs on) t p(ihn)min ?1.53s 1) c load = 10 nf, i charge =3(min) 25% of v gxx1 p_12.1.39 input propagation time (hs off) t p(ihf)min ?1.53s 1) c load = 10 nf, i disharge =3(min), 75% of v gxx1 p_12.1.40 input propagation time (ls on) t p(iln)max ? 200 350 ns c load = 10 nf, i charge =31(max), 25% of v gxx1 p_12.1.26 input propagation time (ls off) t p(ilf)max ? 200 300 ns c load = 10 nf, i discharge =31(max), 75% of v gxx1 p_12.1.27 input propagation time (hs on) t p(ihn)max ? 200 350 ns c load = 10 nf, i charge =31(max), 25% of v gxx1 p_12.1.28 input propagation time (hs off) t p(ihf)max ? 200 300 ns c load = 10 nf, i discharge =31(max), 75% of v gxx1 p_12.1.29 table 42 electrical characteristics mosfet driver (cont?d) v s = 5.5 v to 28 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. tle9869qxa20 electrical characteristics data sheet 120 rev. 1.0, 2017-03-03 absolute input propagation time difference between propagation times for all lsx (lsx on) t pon(diff)lsx ? ? 100 ns c load = 10 nf, i charge =31(max), 25% of v gxx1 p_12.1.30 absolute input propagation time difference between propagation times for all lsx (lsx off) t poff(diff)lsx ? ? 100 ns c load = 10 nf, i discharge =31(max), 75% of v gxx1 p_12.1.41 absolute input propagation time difference between propagation times for all hsx (hsx on) t pon(diff)hsx ? ? 100 ns c load = 10 nf, i charge =31(max), 25% of v gxx1 p_12.1.42 absolute input propagation time difference between propagation times for all hsx (hsx off) t poff(diff)hsx ? ? 100 ns c load = 10 nf, i discharge =31(max), 75% of v gxx1 p_12.1.43 drain source monitoring drain source monitoring threshold v dsmonvth ? 0.07 0.35 0.55 0.65 0.90 1.00 1.20 1.40 ? 0.25 0.50 0.75 1.00 1.25 1.5 1.75 2.00 ? 0.40 0.650 0.90 1.25 1.45 1.80 2.10 2.40 v drv_ctrl3.dsmonvt h<2:0> xxx 000 001 010 011 100 101 110 111 p_12.1.46 open load diagnosis currents pull-up diagnosis current i pudiag -220 -370 -520 a i dischg = 1; v shx = 5.0 v p_12.1.47 pull-down diagnosis current i pddiag 650 900 1100 a i dischg = 1; v shx = 5.0 v p_12.1.48 charge pump output voltage vcp vs. vsd v cpmin1 8.5 ? ? v v vsd =5.4v, i cp =5 ma, c cp1 , c cp2 = 220 nf, bridge driver enabled p_12.1.53 regulated output voltage vcp vs. vsd v cp 12 14 16 v 8 v v vsd 28, i cp =10ma, c cp1 , c cp2 =220 nf, f cp =250khz p_12.1.49 table 42 electrical characteristics mosfet driver (cont?d) v s = 5.5 v to 28 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. tle9869qxa20 electrical characteristics data sheet 121 rev. 1.0, 2017-03-03 turn on time t on_vcp 10 24 40 us 8 v v vsd 28, i cp =2.5ma, (25%) of v cp 1)4) , c cp1 , c cp2 =220 nf, f cp =250khz p_12.1.59 rise time t rise_vcp 20 60 88 us 8 v v vsd 28, i cp =2.5ma, (25-75%) of v cp 1)5) , c cp1 , c cp2 =220 nf, f cp =250khz p_12.1.60 1) not subject to production test. 2) the condition i cp =2,5 ma emulates anh-bridge driver wit h 4 mosfet switching at 20 khz with a c load =3.3nf. test condition: i gx = - 100 a, icharge = idischarge = 31(max), idischargediv2_n = 1 and ichargediv2_n = 1. 3) this resistance is connected through a diode between shx and ghx to ground. 4) this time applies when bit drv_cp_ctrl_sts.bit.cp_en is set 5) this time applies when bit drv_cp_clk_ctrl.bit.cpclk_en is set table 42 electrical characteristics mosfet driver (cont?d) v s = 5.5 v to 28 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. tle9869qxa20 electrical characteristics data sheet 122 rev. 1.0, 2017-03-03 29.13 operational amplifier 29.13.1 electrical characteristics table 43 electrical characteristics operational amplifier v s = 5.5 v to 28 v, t j = -40 c to +150 c; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. differential gain (uncalibrated) g 9.5 19 38 57 10 20 40 60 10.5 21 42 63 gain settings gain<1:0>: 00 01 10 11 p_13.1.6 differential input operating voltage range op2 - op1 v ix -1.5 / g ? 1.5 / g v g is the gain specified below p_13.1.1 operating. common mode input voltage range (referred to gnd (op2 - gnd) or (op1 - gnd) v cm -2.0 ? 2.0 v input common mode has to be checked in evaluation if it fits the required range p_13.1.2 max. input voltage range (referred to gnd (op_2 - gnd) or (op1 - gnd) v ix_max -7.0 ? 7.0 v max. rating of operational amplifier inputs, where measurement is not done p_13.1.3 single ended output voltage range (linear range) v out v zero - 1.5 ? v zero + 1.5 v 1)2) typ. output offset voltage 2 v 1.5v p_13.1.4 linearity error e pwm -15 ? 15 mv maximum deviation from best fit straight line divided by max. value of differential output voltage range (0.5v - 3.5v); this parameter is determined at g = 10. p_13.1.5 linearity error e pwm_% -1.0 ? 1.0 % maximum deviation from best fit straight line divided by max. value of differential output voltage range (0.5v - 3.5v); this parameter is determined at g = 10. p_13.1.24 gain drift -1 ? 1 % gain dr ift after calibration at g = 10. p_13.1.7 adjusted output offset voltage v oos -40 10 40 mv v aip = v ain = 0 v and g = 40. p_13.1.17 tle9869qxa20 electrical characteristics data sheet 123 rev. 1.0, 2017-03-03 dc input voltage common mode rejection ratio dc- cmrr 58 80 ? db cmrr (in db)=-20*log (differential mode gain/ common mode gain) v cmi = -2v... 2v, v aip - v ain =0v p_13.1.8 settling time to 98% t set ? 800 1400 ns derived from 80 - 20 % rise fall times for 2v overload condition (3 tau value of settling time constant) 2) p_13.1.9 current sense amplifier input resistance @ op1, op2 r in_op1_ op2 1 1.25 1.5 k ? 2) ? p_13.1.25 table 43 electrical characteristics operational amplifier (cont?d) v s = 5.5 v to 28 v, t j = -40 c to +150 c; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. data sheet 124 rev. 1.0, 2017-03-03 tle9869qxa20 package outlines 30 package outlines figure 37 package outline vqfn-48-31 (with lti) notes 1. you can find all of our packages, sorts of packing an d others in our infineon internet page ?products?: http://www.infineon.com/products . 2. dimensions in mm. pg-vqfn-48-29, -31-po v05 7 0.1 a 6.8 7 0.1 b 11 x 0.5 = 5.5 0.5 0.5 0.07 0.1 0.05 0.13 0.05 0.26 0.15 0.05 (6) (5.2) 0.9 max. (0.65) +0.03 1) 2) 48x 0.08 (0.2) 0.05 max. c (5.2) (6) 0.1 0.03 0.05 0.23 m 48x 0.1 a b c 1) vertical burr 0.03 max., all sides 2) these four metal areas have exposed diepad potential index marking seating plane index marking 6.8 12 1 13 24 25 36 (0.35) 37 48 0.4 x 45 tle9869qxa20 revision history data sheet 125 rev. 1.0, 2017-03-03 31 revision history revision history page or item subjects (major changes since previous revision) rev. 1.0, 2017-03-03 all initial release. trademarks of infineon technologies ag hvic?, ipm?, pfc?, au-convertir?, aurix? , c166?, canpak?, cipos?, cipurse?, cooldp ?, coolgan?, coolir?, coolmos?, coolset?, coolsic?, dave?, di-pol?, directfet?, drblade?, easypim?, econobridge?, ec onodual?, econopack?, econopim?, eicedriver?, eupec?, fcos?, ga npowir?, hexfet?, hitfet?, hybridpack?, imotion?, iram?, isoface?, isopack?, ledrivir?, li tix?, mipaq?, modstack?, my-d?, novalithic?, o ptiga?, optimos?, origa?, powiraudio?, powirstage?, primepack?, primestack?, pr ofet?, pro-sil?, rasic?, real 3?, smartlewis?, solid flas h?, spoc?, strongirfet?, supirbuck?, tempfet?, trenchstop?, tricore?, uhvic?, xhp?, xmc?. trademarks updated november 2015 other trademarks all referenced product or service names and trademarks are the proper ty of their respective owners. edition 2017-03-03 published by infineon technologies ag 81726 munich, germany ? 2017 infineon technologies ag. all rights reserved. do you have a question about any aspect of this document? email: erratum@infineon.com important notice the information given in this document shall in no event be regarded as a guarantee of conditions or characteristics ("beschaffenheitsgarantie"). with respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, infineon technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. in addition, any information given in this document is subject to customer's comp liance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer's products and any use of the product of infineon technologies in customer's applications. the data contained in this document is exclusively intended for technically trained staff. it is the responsibility of customer's technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements products may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. except as otherwise explicitly approved by infineon technologies in a written document signed by authorized representatives of infineon technologies, infineon technologies? products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury. please read the important notice and warnings at the end of this document |
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