View CY7C1059DV33-10ZSXIT_9094567.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

cy7c1059dv33 8-mbit (1m 8) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-00061 rev. *h revised september 12, 2011 features high speed ? t aa = 10 ns low active power ? i cc = 110 ma at f = 100 mhz low cmos standby power ? i sb2 = 20 ma 2.0 v data retention automatic power down when deselected ttl-compatible inputs and outputs easy memory expansion with ce and oe features available in pb-free 44-pin tsop-ii package offered in standard and high reliability (q) grades functional description the cy7c1059dv33 is a high per formance cmos static ram organized as 1m words by 8 bits. easy memory expansion is provided by an active low chip enable (ce ), an active low output enable (oe ), and tri-state drivers. to write to the device, take chip enable (ce ) and write enable (we ) inputs low. data on the eight i/o pins (i/o 0 through i/o 7 ) is then written into the location specified on the address pins (a 0 through a 19 ). to read from the device, take chip enable (ce ) and output enable (oe ) low while forcing write enable (we ) high. under these conditions, the contents of the memory location specified by the address pins appear on the i/o pins. the eight input or output pins (i/o 0 through i/o 7 ) are placed in a high impedance state when the device is deselected (ce high), the outputs are disabled (oe high), or a write operation is in progress (ce low and we low). the cy7c1059dv33 is available in 44-pin tsop-ii package with center power and ground (revolutionary) pinout. a 0 io 0 io 7 io 1 io 2 io 3 io 4 io 5 io 6 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 sense amps power down ce we oe a 13 a 14 a 15 a 16 a 17 row decoder column decoder 1m x 8 array input buffer a 10 a 18 a 11 a 12 a 19 logic block diagram
cy7c1059dv33 document #: 001-00061 rev. *h page 2 of 11 pin configuration figure 1. 44-pin tsop ii a 6 1 2 3 4 5 6 7 8 9 10 11 14 31 32 36 35 34 33 37 40 39 38 top view 12 13 41 44 43 42 16 15 29 30 v cc a 7 a 8 a 9 nc nc nc nc a 18 v ss nc a 15 a 0 i/o 0 a 4 ce a 17 a 12 a 1 18 17 20 19 i/o 1 27 28 25 26 22 21 23 24 nc v ss we i/o 2 i/o 3 a 5 nc a 16 v cc oe i/o 7 i/o 6 i/o 5 i/o 4 a 14 a 13 a 11 a 10 a 19 nc nc a 2 a 3 selection guide description ?10 ?12 unit maximum access time 10 12 ns maximum operating current 110 100 ma maximum cmos standby current 20 20 ma
cy7c1059dv33 document #: 001-00061 rev. *h page 3 of 11 maximum ratings exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. storage temperature ..... ............ ............... ?65 c to +150 c ambient temperature with power applied ..... .............. .............. .......... ?55 c to +125 c supply voltage on v cc to relative gnd [1] ....?0.5 v to + 4.6 v dc voltage applied to outputs in high-z state [1] ................................... ?0.3 v to v cc + 0.3 v dc input voltage [1] ............................... ?0.3 v to v cc + 0.3 v current into outputs (low) ......................................... 20 ma static discharge voltage............. ...............................>2001 v (mil-std-883, method 3015) latch-up current ...................................................... >200 ma operating range range ambient temperature v cc industrial ?40 c to +85 c 3.3 v 0.3 v electrical characteristics over the operating range parameter description test conditions ?10 ?12 unit min max min max v oh output high voltage v cc = min, i oh = ?4.0 ma 2.4 ? 2.4 ? v v ol output low voltage v cc = min i ol = 8.0 ma ?0.4?0.4v v ih input high voltage 2.0 v cc + 0.3 2.0 v cc + 0.3 v v il input low voltage [1] ?0.3 0.8 ?0.3 0.8 v i ix input leakage current gnd < v in < v cc ?1 +1 ?1 +1 a i oz output leakage current gnd < v out < v cc , output disabled ?1 +1 ?1 +1 a i cc v cc operating supply current v cc = max., f = f max = 1/t rc ?110?100ma i sb1 automatic ce power-down current ? ttl inputs max. v cc , ce > v ih, v in > v ih or v in < v il , f = f max ?40?35ma i sb2 automatic ce power-down current ? cmos inputs max. v cc , ce > v cc ? 0.3 v, v in > v cc ? 0.3 v, or v in < 0.3 v, f = 0 ?20?20ma capacitance tested initially and after any design or proc ess changes that may affect these parameters . parameter description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3 v 12 pf c out i/o capacitance 12 pf notes 1. v il(min) = ?2.0 v and v ih(max) = v cc + 2 v for pulse durations of less than 20 ns. 2. tested initially and after any design or proce ss changes that may affect these parameters. thermal resistance tested initially and after any design or proces s changes that may affect these parameters. parameter description test conditions tsop ii unit ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, four-layer printed circuit board 51.43 c/w jc thermal resistance (junction to case) 15.8 c/w
cy7c1059dv33 document #: 001-00061 rev. *h page 4 of 11 ac test loads and waveforms ac characteristics (except high-z) are tested using the load conditions shown in figure 2 (a). high-z characteristics are tested for all speeds using the test load shown in figure 2 (c). figure 2. ac test loads and waveforms figure 3. data retention waveform 90% 10% 3.0 v gnd 90% 10% all input pulses * capacitive load consists of all components of the test environment rise time: 1 v/ns fall time: 1 v/ns 30 pf* output z = 50 50 1.5 v (b) (a) 3.3 v output 5 pf (c) r 317 r2 351 high-z characteristics: data retention characteristics over the operating range parameter description conditions [3] min max unit v dr v cc for data retention 2.0 ? v i ccdr data retention current v cc = v dr = 2.0 v, ce > v cc ? 0.3 v, v in > v cc ? 0.3 v or v in < 0.3 v ?20ma t cdr [2] chip deselect to data retention time 0 ? ns t r [4] operation recovery time t rc ?ns 3.0 v 3.0 v t cdr v dr > 2 v data retention mode t r ce v cc notes 3. no inputs may exceed v cc + 0.3 v. 4. full device operation requires linear v cc ramp from v dr to v cc(min) > 50 s or stable at v cc(min) > 50 s.
cy7c1059dv33 document #: 001-00061 rev. *h page 5 of 11 notes 5. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 v, input pulse levels of 0 to 3 .0 v. 6. t power is the minimum amount of time that the power supply must be at stable, typical v cc values until the first memory access can be performed. 7. t hzoe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in part (d) of ?ac test loads and waveforms? on page 4 . transition is measured when the outputs enter a high impedance state. 8. at any temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any device. 9. the internal write time of the memory is defined by the overlap of ce low, and we low. ce and we must be low to initiate a write, and the transition of either of these signals can terminate the write. the input data setup and hold timing must refer to the leading edge of the signal tha t terminates the write. 10. the minimum write cycle time for write cycle no. 3 (we controlled, oe low) is the sum of t hzwe and t sd . ac switching characteristics over the operating range [5] parameter description ?10 ?12 unit min max min max read cycle t power [6] v cc (typical) to the first access 100 ? 100 ? s t rc read cycle time 10 ? 12 ? ns t aa address to data valid ? 10 ? 12 ns t oha data hold from address change 2.5 ? 2.5 ? ns t ace ce low to data valid ? 10 ? 12 ns t doe oe low to data valid ? 5 ? 6 ns t lzoe oe low to low-z 0 ? 0 ? ns t hzoe oe high to high-z [7, 8] ?5?6ns t lzce ce low to low-z [8] 3?3?ns t hzce ce high to high-z [7, 8] ?5?6ns t pu ce low to power-up 0 ? 0 ? ns t pd ce high to power-down ? 10 ? 12 ns write cycle [9, 10] t wc write cycle time 10 ? 12 ? ns t sce ce low to write end 7 ? 8 ? ns t aw address setup to write end 7 ? 8 ? ns t ha address hold from write end 0 ? 0 ? ns t sa address setup to write start 0 ? 0 ? ns t pwe we pulse width 7 ? 8 ? ns t sd data setup to write end 5 ? 6 ? ns t hd data hold from write end 0 ? 0 ? ns t lzwe we high to low-z [8] 3?3?ns t hzwe we low to high-z [7, 8] ?5?6ns
cy7c1059dv33 document #: 001-00061 rev. *h page 6 of 11 switching waveforms figure 4. read cycle no. 1 (address transition controlled) [11, 12] figure 5. read cycle no. 2 (oe controlled) [12, 13] previous data valid data out valid t rc t aa t oha address data i/o 50% 50% data out valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd high oe ce i cc i sb impedance address data i/o v cc supply current notes 11. device is continuously selected. oe , ce = v il . 12. we is high for read cycle. 13. address valid before or coincident with ce transition low.
cy7c1059dv33 document #: 001-00061 rev. *h page 7 of 11 figure 6. write cycle no. 1 (we controlled, oe high during write) [14, 15] figure 7. write cycle no. 2 (we controlled, oe low) [15] switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe data in valid ce address we data i/o oe note 16 data in valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe ce address we data i/o note 16 notes 14. data i/o is high-impedance if oe = v ih . 15. if ce goes high simultaneously with we going high, the output remains in a high-impedance state. 16. during this period the i/os are in the output state and input signals must not be applied.
cy7c1059dv33 document #: 001-00061 rev. *h page 8 of 11 truth table ce oe we i/o 0 ?i/o 7 mode power h x x high-z power-down standby (i sb ) l l h data out read active (i cc ) l x l data in write active (i cc ) l h h high-z selected, outputs disabled active (i cc ) ordering information speed (ns) ordering code package diagram package type operating range grade 10 cy7c1059dv33-10zsxi 51-85087 44-pin tsop ii (pb-free) industrial standard 12 cy7c1059dv33-12zsxq 51-85087 44-pin tsop ii (pb-free) industrial high reliability (< 100 ppm) ordering code definitions contact your local cypress sales repres entative for availability of these parts. temperature range: x = i or q i = industrial; q = high reliability (< 100 ppm) package type: zsx = 44-pin tsop ii (pb-free) speed: xx = 10 ns or 12 ns v33 = voltage range (3 v to 3.6 v) d = c9, 90 nm technology 9 = data width 8-bits 05 = 8-mbit density 1 = fast asynchronous sram family technology code: c = cmos 7 = sram cy = cypress c cy 1 - xx zsx 7 05 d x v33 9
cy7c1059dv33 document #: 001-00061 rev. *h page 9 of 11 acronyms document conventions units of measure package diagram figure 8. 44-pin tsop ii (51-85087) 51-85087 *d table 1. acronyms used in this document acronym description cmos complementary metal?oxide?semiconductor sram static random-access memory tsop thin small-outline package ttl transistor?transistor logic table 2. units of measure symbol unit of measure c degree celsius mhz megahertz ma milliampere ns nanosecond ohm pf picofarad
cy7c1059dv33 document #: 001-00061 rev. *h page 10 of 11 document history page document title: cy7c1059dv33, 8-mbit (1m 8) static ram document number: 001-00061 revision ecn orig. of change submission date description of change ** 342195 pci see ecn new datasheet *a 380574 syt see ecn redefined i cc values for com?l and ind?l temperature ranges i cc (com?l): changed from 110, 90 and 80 ma to 110, 100 and 95 ma for 8, 10 and 12 ns speed bins respectively i cc (ind?l): changed from 110, 90 and 80 ma to 120, 110 and 105 ma for 8, 10 and 12 ns speed bins respectively changed the capacitance values from 8 pf to 10 pf on page # 3 *b 485796 nxr see ecn changed address of cypress semiconductor corporation on page# 1 from ?3901 north first street? to ?198 champion court? removed -8 and -12 speed bins from product offering, removed commercial operating range option, modified maximum ratings for dc input voltage from -0.5 v to -0.3 v and v cc + 0.5 v to v cc + 0.3 v updated footnote #7 on high-z parameter measurement added footnote #11 changed the description of i ix from input load current to input leakage current. updated the ordering information table and replaced package name column with package diagram. *c 1513285 vkn/aesa see ecn converted from preliminary to final added 12 ns speed bin changed c in and c out specs from 16 pf to 12 pf changed t oha spec from 3 ns to 2.5 ns updated ordering information table *d 2594352 nxr/pyrs 10/21/08 added q-grade part *e 2764423 aju 09/16/2009 corrected typo in the ordering information table *f 2902563 aju 03/31/2010 removed inactive part from ordering information table. updated package diagram. *g 3109147 aju 12/13/2010 added ordering code definitions. *h 3369075 tava 09/12/2011 changed features section: ?i cc = 110 ma at 10 ns? to ?110 ma at f = 100 mhz?. removed reference to ?an1064, sram system guidelines? on page 1. removed reference to 36-ball fbga from functional description section. updated figures under switching waveforms section. updated package diagram revision to *d. added acronyms and units of measure.
document #: 001-00061 rev. *h revised september 12, 2011 page 11 of 11 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c1059dv33 ? cypress semiconductor corporation, 2005-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

▲Up To Search▲

Price & Availability of CY7C1059DV33-10ZSXIT

	To Download CY7C1059DV33-10ZSXIT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .