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september 2013 doc id 5198 rev 10 1/29 1 l9935 two-phase stepper motor driver features 2 x 1.1 a full bridge outputs integrated chopping current regulation minimized power dissipation during flyback output stages with controlled output voltage slopes to reduce electromagnetic radiation short-circuit protection of all outputs error-flag for over load, open load and over temperature pre alarm delayed channel switch on to reduce peak currents max. operating supply voltage 24 v standby consumption typically 40 a serial interface (spi) description the l9935 is a two-phase stepper motor driver circuit suited to drive bipolar stepper motors. the device can be controlled by a serial interface (spi). all protections required to design a well protected system (short-circuit, over temperature, cross conduction etc.) are integrated. '!0'03 powerso20 table 1. device summary order code package packing l9935 powerso20 tube l9935013tr powerso20 tape and reel www.st.com
contents l9935 2/29 doc id 5198 rev 10 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1 basic structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2 full bridge function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2.1 no current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2.2 turning on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2.3 chopping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2.4 reversing phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2.5 chopper control by oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.3 protection and diagnosis functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.4 short from an output to the supply voltage v s . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.5 diagnosis of a short to v s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.6 short from an output to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.7 diagnosis of a short to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.8 shorted load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.9 diagnosis of a shorted load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.10 open load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.10.1 over temperature pre alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.11 application hints using a high resistive stepper motor . . . . . . . . . . . . . . . 18 5.11.1 startup behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.12 limitation of the diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.13 serial data interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.13.1 startup of the serial data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
l9935 contents doc id 5198 rev 10 3/29 5.14 test condition for all propagation times . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.15 cascading several devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.16 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.17 electromagnetic emission classification (e me) . . . . . . . . . . . . . . . . . . . . 25 6 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
list of tables l9935 4/29 doc id 5198 rev 10 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 4. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 5. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 6. current setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 7. high and low resistive motor (error bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 8. diagnosis description - bit7 and bit6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 9. test condition for all propagation times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 10. full step mode control sequences and diagnosis response . . . . . . . . . . . . . . . . . . . . . . . . 23 table 11. half step mode control sequences and diagnosis response . . . . . . . . . . . . . . . . . . . . . . . 24 table 12. electromagnetic emission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 13. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
l9935 list of figures doc id 5198 rev 10 5/29 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. general application circuit proposal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 4. typical average load current dependence on r sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 5. displays a full bridge including the current sense circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 6. principal chopper control circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 7. pulse diagram to explain offset chopping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 8. normal pwm current versus short circuit current and detection of short to v s . . . . . . . . . 16 figure 9. spi data/clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 10. cascading several stepper motor drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 11. control sequence for 3 stepper motor drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 12. paralleling several devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 13. state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 14. emc compatibility for l9935 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 15. powerso20 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . 27
block diagram l9935 6/29 doc id 5198 rev 10 1 block diagram figure 1. block diagram '!0'03 #/--/. ,/')# /3#),,!4/2 $)!'./34)# ")!3).' $2)6%2 ,/')# $2)6%2 ,/')# ^ ^ '.$ '.$ 32 ! /54 ! 6 3 .# /3# # $26 /54 " 32 " '.$ /54 ! 3#+ %. #3. 6## 3$/ 3$) /54 " '.$
l9935 pin description doc id 5198 rev 10 7/29 2 pin description figure 2. pin connection (top view) table 2. pin function pin no name description 1,10,11,20 gnd ground. (all ground pins are internal ly connected to the frame of the device). 2out a1 output1 of full bridge 1 3 sck clock for serial interface (spi) 4 sdi serial data input 5 sdo serial data output 6 vcc 5v logic supply voltage 7 csn chip select (low active) 8en enable (low active) 9out b1 output1of full bridge 2 12 sr b current sense resistor of the chopper regulator for outb 13 out b2 output 2 of full bridge 2 14 c drv charge pump buffer capacitor 15 osc oscillator capacitor or external clock 16 v s supply voltage 17 nc not connected 18 out a2 output of full bridge 1 19 sr a current sense resistor of the chopper regulator for out a '!0'03 '.$ /54 ! 3#+ 3$) 3$/ 6## #3. %. /54 " '.$ '.$ 32 ! /54 ! .# 6 3 /3# # $26 /54 " 32 " '.$
electrical specifications l9935 8/29 doc id 5198 rev 10 3 electrical specifications 3.1 absolute maximum ratings note: note: esd for all pins, except pins sdo, sra and srb, are according to mil883c, tested at 2kv, corresponding to a maximum energy dissipation of 0.2mj. sdo, sra and srb pins are tested with 800v. 3.2 thermal data table 3. absolute maximum ratings symbol parameter value unit v s dc supply voltage -0.3 to 35 v v spulsed pulsed supply voltage t < 400 ms -0.3 to 40 v v out (ai/bi) output voltages internally clamped to v s or gnd depending on the current direction i out (ai/bi) dc output currents peak output currents (t/tp ? 10) ? 1.2 ? 2.5 a a v sra/srb sense resistor voltages -0.3 to 6.2 v v cc logic supply voltages -0.3 to 6.2 v v cdrv charge pump buffer voltage versus v s -0.3 to 10 v v sck , v sdi , v csn , v en logic input voltages -2 to 8 v v osc , v sdo oscillator voltage range, logic output -0.3 to v cc +0.3 v table 4. thermal data symbol parameter value unit r thj-case typical thermal resistance junction-to-case 5 c/w r thj-amb typical thermal resistance junction-to-ambient (6 cm 2 ground plane 35 m thickness) 35 c/w r thj-amb, fr4 typical thermal resistance junction to ambient (soldered on a fr 4 board with through holes for heat transfer and external heat sink applied) 8c/w t s storage temperature -40 to 150 c t sd typical thermal shut-down temperature 180 c
l9935 electrical specifications doc id 5198 rev 10 9/29 3.3 electrical characteristics 8 v ? v s ? 24 v; -40 c ? t j ? 150 c; 4.5 v ? v cc ? 5.5 v, unless otherwise specified. parameters are tested at 125 c. values at 140 c are guaranteed by design and correlation. table 5. electrical characteristics symbol parameter test condit ion min. typ. max. unit supply is 85 total supply current i s + i vcc (both bridges off) v s = 14 v; en = high; t j ? 85 c - 40 100 ? a i sop operating supply current i out ai/bi = 0; f osc = 30 khz v s = 14 v -4.5 -ma i cc 5 v supply current en = low - 1.4 10 ma full bridges r out, sink r dson of sink transistors current bit - 0.4 0.7 ? r out, source r dson of source transistors combinations ll, lh, v s ? 12 v - 0.4 0.7 ? r out8 , sink r dson of sink transistors + r dson of source transistors current bit combinations ll, lh, v s = 8v -1.6 3 ? v fwd forward voltage of the dmos body diodes en = high; i fwd = 1 a; v s ? 12 v - 1 1.4 v v rev reverse dmos voltage en = low i rev = 1 a - 0.5 0.9 v t r , t f rise and fall time of outputs out ai/bi 0.1...0.9 v out v s = 14 v chopping 550 ma 0.3 0.6 1.5 ? s switch off threshold of the chopper (r 1 ? r 2 = 0.33 ? ) v srhl voltage drops across r 1 ? r 2 (1) (voltage at pin sr a or sr b vs. gnd) bit 5, 2 = h; bit 4, 1 = l 12 20 35 mv v srlh bit 5, 2 = l; bit 4, 1 = h 160 180 210 mv v srll bit 5, 4, 2, 1 = l 270 300 340 mv enable input en v en high high input voltage - v cc - 1.2v --v v enlow low input voltage - - - 1.2 v v en hyst enable hysteresis - 0.1 - - v i en high high input current v high = v cc -10 0 10 ? a i en low low input current v low = 0v -3 -10 -30 ? a logic inputs sdi. sck, csn v high high input voltage en = low 2.6 8 v v low low input voltage -0.3 1 v v hyst hysteresis 0.8 1.2 1.6 v
electrical specifications l9935 10/29 doc id 5198 rev 10 i high high input current v high = v cc -10 0 10 ? a i low low input current v low = 0 v -3 -10 -30 ? a logic outputs (sdo) v sdo,high high output voltage i sdo = -1 ma v cc -1 v cc - 0.17 v cc v v sdo,low low output voltage i sdo = 1 ma - 0.17 1 v oscillator v osc, h high peak voltage en = low 2.2 2.46 2.6 v v osc, l low peak voltage en = low 1 1.23 1.4 v i osc charging/discharging current - 45 62 80 ? a f osc oscillator frequency c osc = 1 nf 20 25 31 khz t start oscillator startup time en = high ? low 2/f osc 5/f osc 8/f osc thermal protection t j-off thermal shut-down - 160 180 200 c temperature - - - - t j-alm thermal pre alarm - 130 160 - c ? t mgn margin pre alarm/shut-down - 10 20 30 k 1. currents of combinations lh and ll are sensed at the extern al resistors. the current of bit combination hl is sensed internally and cannot be adjusted by changing the sense resistors. table 5. electrical characteristics (continued) symbol parameter test condit ion min. typ. max. unit
l9935 application hints doc id 5198 rev 10 11/29 4 application hints figure 3. general application circuit proposal c1 and c2 should be placed as close to th e device as possible. low esr of c2 is advantageous. peak currents through c1 and c2 may reach 2 a. care should be taken that the resonance of c1, c2 together with supply wire inductances is not the chopping frequency or a multiple of it. '!0'03 #/--/. ,/')# /3#),,!4/2 $)!'./34)# ")!3).' $2)6%2 ,/')# $2)6%2 ,/')# ^ ^ '.$ '.$ 32 ! 2 7 # n& # /3# n& # $river n& 0/7%2 3500,9 6 34%00%2 -/4/2 # m & /54 ! .# 6 3 /3# # $26 /54 " 32 " '.$ /54 ! 3#+ 3$) ).4%2&!#% m # %. #3. 6## 3$/ 3$) /54 " '.$ 2 7 n&
functional description l9935 12/29 doc id 5198 rev 10 5 functional description 5.1 basic structure the l9935 is a dual full bridge driver for inductive loads with a chopper current regulation. outputs a1 and a2 belong to full bridge a outputs b1 and b2 belong to full bridge b. the polarity of the bridges can be controlled by bit0 and bit3 (for full bridge a, bit3, for full bridge b, bit0). bit5, bit4 (for full bridge a) and bit2, bit1 (for full bridge b) control the currents. bit3 high leads to output a1 high. bit0 high leads to output b1 high. current setting ta b l e 6 using a 0.33 ? sense resistor. figure 4. typical average load current dependence on r sense table 6. current setting bit5, bit2 bit4, bit1 i qx (typ.) i rx/max remark h h 0 0 % - h l 60 ma - internally sensed l h 550 ma 61 % - l l 900 ma 100 % - '!0'03 ) ! ) (, ) ,( ) ,, typicalcurrentlimitationofhighsidetransistor limitrecommendedforusualapplication 7 2 suggestedrangeofoperation
l9935 functional description doc id 5198 rev 10 13/29 5.2 full bridge function figure 5. displays a full bridge including the current sense circuit. 5.2.1 no current bit 5, bit 4 (corresponding bit 2 and bit1 for bridge b) both are hi gh, the current logic will inhibit all drivers d 11 , d 12 , d 21 , d 22 turning off m 11 , m 12 , m 21 , m 22 independently from the signal of the current sense comparator comp 1. 5.2.2 turning on changing bit 5 or bit 4 or both to low will turn on either m 11 and m 22 or m 21 and m 12 (depending on the phase signal bit 3). current will start to flow through the load. the current will be sensed by the drop across r 1 . the threshold of the comparator comp 1 depends on the current settings of bit 5 and bit 4. the current will rise until it exceeds the turn off threshold of comp 1. 5.2.3 chopping exceeding the threshold of comp 1 the driv e logic will turn off the sink transistor (m 12 or m 22 ). the sink transistor periodically is turned on again by the oscillator. immediately after turning on m 12 or m 22 the comparator comp 1 will be inhi bited for a certain time to blank switch over spikes caused by capacitive load components up to 5 nf. turning off for example m 12 will yield a flybac k current through d 11 . (so now the free wheeling current flows through m 21 , the load and d 11 ). this leads to a slow current decay during flyback. maximum duty cycles of more than 85% (at f osc = 25 khz) are possible. in this case curr ent flows of both br idges will overlap (not shown in figure 7 ). '!0'03 $2)6% ,/')# #522%.4 ,/')# bitbit bitbit bitbit #522%.4!$*534 ).()")4 /.(( ,/!$ t $ - $ - $ ! ! 6 3 2 2 %84%2.!, 3%.3%2%3)34/2 $ #/-0 $ $ $ - $ -
functional description l9935 14/29 doc id 5198 rev 10 5.2.4 reversing phase suppose the current flowed via m 21 , the load and m 12 before reversing phase. reversing phase m 21 and m 12 will be turned off. so now the current will flow through d 22 , the load and d 11 . this leads to a fast current decay. 5.2.5 chopper contr ol by oscillator both chopping circuits work with offset phas e. one chopper will switch on the bridge at the maximum voltage of the oscilla tor while the other chopper will switch on the bridge at minimum voltage of the oscillator. ms1 and ms2 blank switching spikes that could lead to errors of the current control circuit. figure 6. principal chopper control circuit '!0'03 32 ! 32 " /3# # /3# -3 -3 #omp inhibit inhibit #omp $r /3#),,!4/2 $r 2%3 2%3 2 2 3 3 -/3$2)6%23 2%3%4 $/-).!.4 2%3%4 $/-).!.4 23&& 23&& f /3# i /3# 6q# /3#
l9935 functional description doc id 5198 rev 10 15/29 figure 7. pulse diagram to explain offset chopping using offset chopping the changes of the supply current remain half as large as using non offset chopping. turning off the oscillator for example by shorti ng pin osc to ground will hinder turning on of the bridges anymore after the comparators have generated a turn off signal. external clocking is possible overdrives the ch arge and discharge curr ents of the oscillator for example with a push pull logic gate. so several devices can be synchronized. 5.3 protection and diagnosis functions the l9935 provides several protection functions and error detection functions. current limitation usually is customer defined by the external current sense resistors. the current sensed there is used to regulate the current through the stepper motor windings by pulse width modulation. this pwm regulation protects the sink transistors. the source transistors are protected by an internal overcurrent shut down turning off the source transistors in case of overload. overload detection of the source transistor w ill turn off the bridge and set the corresponding error flag. to turn on the bridge again a new byte must be written into the interface. (rising slope of csn resets the overload error flag). both bridges use the same flags. to locate which bridge is affected by an error the bridges can be tested individually (one bridge just is turned off to check for the error in the other bridge). 5.4 short from an output to the supply voltage v s the current will be limited by the pulse width mo dulator. the sink transistor will turn off again after some microseconds. the transistor will period ically be turned on again by the oscillator 8 times. after having detected sh ort 8 times the low side transi stor will remain off until the '!0'03 turnoffdelay duetoslope velocitycontrol $ ) 6 /3# 6 32" totalcurrentconsumption current threshold current threshold 6 32! ) 63
functional description l9935 16/29 doc id 5198 rev 10 next data transfer took place. after detection of a short to v s we suggest to turn off the corresponding bridge to reduce power dissipation for at least 1ms. 5.5 diagnosis of a short to v s during the short current through the sink transistor will rise more rapidly than under normal load conditions. reaching a peak current of 1.5 times the maximum pwm current between typically 2 s and 5 s after turn on will be detected as a short to v s . detecting a short the low side transistor will try to turn on again the ne xt 7 trigger pulse of the oscillator. simultaneously the error flag will updated on each pulse. figure 8. normal pwm current versus short circuit current and detection of short to v s between t on and t short the over current detection is totally blanked. between t short and t pwm the current threshold is set to 1.5 times the maximum pwm current (1.5 times the current of current setting ll). overcurrent now will set the error flag. after t pwm the current threshold is the nominal pwm current set by the external resistor. exceeding this current will just tu rn off the sink transistor. this is considered as normal operation. the error flag is detached from the comparator after t pwm so no error flag is set during normal pulse width modulation. '!0'03 t t /. ) 1 shortthreshold t on turnonofthesinktransistor t on t t short activationofshortthreshold t on t delay t 07- activationof07-threshold 07-threshold 07-detection signalinternal 3hortdetection signalinternal %rror t short t 07- t /. t /. t /. t short t short t 07- t short t 07- t 07- t t t
l9935 functional description doc id 5198 rev 10 17/29 5.6 short from an output to ground the current through the short will be detected by the protec tion of the source transistor. the source transistor will turn of f exceeding a current of typically 1.8 a. minimum overload detection current is 1.2 a. to obtain proper current regulation (by the sink transistors and not by source transistor shut down) the maximum current of the pwm regulator should be set to a maximum value of 1.1 a. 5.7 diagnosis of a short to ground detecting an overload will set an overcurrent error (error2 = low) (bit6). to reset the error flag a new byte must be written into the interface. (reset of the error flag takes place at the rising slope of csn). 5.8 shorted load with a shorted load both, the sink- and th e source protection or the pwm alone will respond. in either case th ere will be no flyback pulse. 5.9 diagnosis of a shorted load shorting the load two events may take place: ? overload (of the high side transistor) while low side transistor overcurrent is detected will set the following combinations: bit6 = low bit7 = high ? overload is marginal. so the low side driver may turn off before overload is detected. this leads to the combination bit6 = high and bit7 = low. 5.10 open load an open load will not le ad to any flyback pulses. error de tection will take advantage of the flyback pulse. missing the flyback pulse after reversing the polarity of a motor winding bit7 will become low. open load will not be tested in the low curren t mode (current bits hl) to avoid the risk of instable diagnosis at low flyback currents. open load immediately after reset or power down may on random be detected in the low current mode too. this diagnosis however will not persist longer than 8 changes of polarity. we strongly suggest to test open load at a high current mode (combination ll). while circuit clock speed passes the stepper motor resonant points during acceleration/deceleration phase, it can happen that flyback energy is temporarily insufficient for a proper open load detection. under specific circumstances, pending on motor and load characteristics, this could lead to sporadic faulty open load error messages despite proper system operation. the recommended solution is an appropriate software filter approach. a detailed description is available in the application note an2378 on www.st.com.
functional description l9935 18/29 doc id 5198 rev 10 5.10.1 over temperature pre alarm typically 20k before thermal shut down takes place an over temperature pre alarm (bit7 and bit6 low) takes place. typically over temperature pre alarm temperature is between 150 c and 160 c. 5.11 application hints using a high resistive stepper motor the l9935 was originally targeted on stepper chopping stepper motor application with typical resistances of 8..12 ? . using motors with higher resistance will work too but diagnosis behavior will slightly change. this paragraph shows the details that should be taken in account using diagnosis for high resistive motors. 5.11.1 startup behavior the device has simple digital filter to avoid triggering diagnosis at a single event that could be random noise. this digital filter needs 4 ch opping pulses to settle. using a high resistive motor this chopping does not take place. instead the digital filter samples each time a polarity change takes place. so the first three response telegrams after reset may show an ?open load? error. h means check for high at the error bits. x means don?t care because filter is not yet settled. using 75 ma chopping immediately after stand by: the high resistive motor can be forced to chopping operation in the low current range. this leads to the same behavior as using a low resistive motor. short to v s detection using high resistive motors: the short to v s flag is overwritten each time the chopper comparator responds. having detected a short this flag only can be reset by reaching chopping operation or resetting the circuit (enn=1). for a high resistive motor this leads to the following consequence: once a short to vs is detected the erro r flag will persist even if the short is removed again until either a reset (enn=1) or chopping (for example in 75ma mode) has taken place. we suggest to return to operation once a short to vs was detected by using the low current mode to reset the flag. table 7. high and low resistive motor (error bits) input data high resistive motor (error bits) low resistive motor (error bits) standby - - 1 st telegram (550 ma or 900 ma) hh hh reverse phase (550 ma or 900 ma) xh hh reverse phase (550 ma or 900 ma) xh hh any data xh hh any data hh hh
l9935 functional description doc id 5198 rev 10 19/29 5.12 limitation of the diagnosis the diagnosis depends on either detecting an overcurrent of more than typically 1.8 a through the source transistor or on not detecting a flyback pulse, or on detecting severe overcurrents of the sink transistor immediately after turn on. small currents bypassing th e load will not be detected. in the low current range (hold current) the flyback pulse (especially commutating against the supply voltage after changing ph ase) may (depending on the inductivity of the stepper motor windings) be too short to be detected correctly. for this reason diagnosis using the flyback pulse is blanked at phase reversal at hold current. in the low current range (hold current) the current capability of the bridge is reduced on purpose. short to v s may not be detected. in stead the bridge may just chop like normal operation. flyback pulse detection is not blanked du ring pwm regulation at hold current (here commutation voltage is less than 1v thus providing a longer pulse duration.) this however should be taken in account using stepper motors with low inductivity (less than 0.5mh). using motors with such a low inductivity the flyback voltage in hold mode may decay too fast. motors with extremely low ohmic resistance tend to pump up the current because current decay during flyback approaches ze ro while at bridge turn on the current will increase. this may lead to overcurrent detection. we suggest to use stepper motors with an ohmic resistance of approximately 3 ? or more. partial shorts of windings or shorts of stepper motors with coils in series may still yield a flyback pulses that are accepted by the diagnosis as a proper signal. at stepping rates faster than 1ms/data transfer error flags indicating a short should be used to initiate a pause of at least 1ms to allow the power bridges to cool down again. 5.13 serial data interface (spi) the serial data interface itself consists of the pins scl (serial clock), sdi (serial data input) and sdo (serial data output). to especially support bus controlled applications the additional signals en (chip enable not) and csn (chip select not) are available. table 8. diagnosis description - bit7 and bit6 error 1 bit7 error 2 bit6 description h h normal operation l h short to vs (sink overload immediately after turn on) shorted load (no flyback) open load (no flyback) h l short to gnd (source overload, missing flyback is masked) l l over temperature pre alarm
functional description l9935 20/29 doc id 5198 rev 10 5.13.1 startup of t he serial data interface falling slope of en activates the device. after ten.sck the device is ready to work. falling slope of csn indicates st art of frame. data transfer (reading sdi into the register) takes place at the rising slopes of sck. data transfer of the register to sdo takes place at the falling slope of sck. rising slope of csn indicates end of frame. at the end of frame data will only be accepted if modulo 8 bit (modulo 8 falling slop es to sck) have been transfer red. if this is not the case the input will be ignored and the bridges will maintain the same status as before. sdo is a tristate output. sdo is active while csn = low, while csn = high sdo is high resistive. figure 9. spi data/clock timing '!0'03 -3" bit bit bit bit bit bit bit 3#+ %. #3. #3. 3#+ 3$) 3$/ t t t t zch t t cl t su t sh td 3$) t 0d #522%.4" 0/,!2)49" 0/,!2)49! t en?sck -3" bit bit bit bit bit bit bit bit bit bit bit 3$/ ! 8 #522%.4! %22/2")43 t ch
l9935 functional description doc id 5198 rev 10 21/29 5.14 test condition for all propagation times unless otherwise specified) high ? 3 v; low ? 0.8 v; t r , t f = 10 ns; enable: enn low < 0.8 v, enn high > v cc -0.8 v table of bits bit5,bit4: current range of bridge a (outputs a1 and a2) bit3: polarity of bridge a bit2,bit1: current range of bridge b (outputs b1 and b2) bit0: polarity of bridge b bit7,bit6: error1 and error 2 table 9. test condition for all propagation times symbol parameter test conditi ons min. typ. max. unit f sclk sck-frequency - dc - 2mhz - t 1 sck stable before and after csn = 0 -100 --ns t ch width of sck high pulse - 200 - - ns t cl width of sck low pulse - 200 - - ns t su sdi setup time - 80 - - ns t sh sdi hold time - 80 - - ns t d sdo delay time (c l = 50pf) - - 100 - ns t zc sdo high z csn high - - 100 - ns t en_sck setup time enable to sck high > v cc -1.2 v 30 - - ? s t pd propagation delay spi to output qxx --2 (1) - ? s 1. measured at a transition from high impedance (bridge off) to bridge on. (reversing polarity takes about 1ms longer because the bridge first turns off befor e turning on in reverse direction).
functional description l9935 22/29 doc id 5198 rev 10 5.15 cascading several devices cascading several devices can be done using the sdo output to pass data to the next device. the whole frame now consists of n byte. n is the number of devices used. figure 10. cascading several stepper motor drivers figure 11. control sequence for 3 stepper motor drivers figure 12. paralleling several devices here usually only one stepper motor driver is selected at a time while all others are deselected. '!0'03 3$/ 3#+ #3. #3. m 0 3$/ 3$) 3#+ #3. 3#+ #3. 3#+ 3$/ 3$) 3$/ 3$) no no no '!0'03 byteforno byteforno byteforno 3#+ %. #3. 1 88 3$/ of m 0 '!0'03 3$) 3$/ 3#+ #3. #3. m 0 3$) 3$/ 3#+ #3. 3$) 3$/ 3#+ #3. no no
l9935 functional description doc id 5198 rev 10 23/29 5.16 application information for driving a stepper motor we suggest to use the following codes. the columned ?sdo correct? shows the data returned at sdo in correct function. the columns presented under ?error cases? display the diagnosis bits if errors are detected. examples of control sequences. these sequences are intended to give the user a good starting point for his software development. besides these two there are fu rther possibilities how to implement control sequences for this device (other currents, quarters step etc.). double errors: double errors will create com posite codes by an an d operation between columns of the same dominance. open and short to vs are the least dominant error codes. (first 6 error code columns). short to ground is the second dominant error code. detection of short to gnd will overwrite error codes of th e least dominant kind (open, short to vs). temperature pre alarm and thermal shut down are the most dominant error codes. thermal pre alarm returns error code 00 but the device still is working and re turns the appropriate operation code (bits 0..5). thermal shut down returns error code 00 and turns off the device. the opcode returned corresponds the action eventually performed (bit 0..5 become 1). for example open bridge a and simultaneously open bridge b will lead to error code 01 by performing an and operation between the two corresponding columns. table 10. full step mode control sequences and diagnosis response sdi sdo correct error cases and sdobit7, bit6 fault -- a o p e n b o p e n a1 s h o r t vs a2 s h o r t vs b1 s h o r t vs b2 s h o r t vs a1 (1) s h o r t gnd a2 (1) s h o r t gnd b1 (1) s h o r t gnd b2 (1) s h o r t gnd therm. therm. alarm shut down (reset operating codes) bit 76543210 76543210 76 76 76 76 76 76 76 76 76 76 76 76543210 command/response xx111111 sdo present last data or 11111111 in case prev. state was standby xx011011 xx010011 xx010010 xx011010 xx011011 xx010011 xx010010 xx011010 11111111 11011011 11010011 11010010 11011010 11011011 11010011 11010010 11 11 01 11 01 11 01 11 11 11 11 01 11 01 11 01 11 11 01 01 01 11 01 01 11 01 01 11 01 01 01 11 11 11 11 01 01 01 11 01 11 01 01 01 11 01 01 01 11 10 01 11 10 10 01 11 11 11 10 10 01 11 10 10 11 10 10 01 11 10 10 01 11 11 11 10 10 01 11 10 00 00 00 00 00 00 00 00 00111111 00111111 00111111 00111111 00111111 00111111 00111111 00111111 1. motor resistance approximately 10 ? and v s = 12v. so a short to ground only is detected on one branch of the bridge. lower resistivity of the motor may lead to detection of sh ort to ground on both branches of the bridge leading to code 10 on all steps.
functional description l9935 24/29 doc id 5198 rev 10 table 11. half step mode control sequences and diagnosis response sdi sdo error cases and sdobit7, bit6 fault -- a o p e n b o p e n a1 s h o r t vs a2 s h o r t vs b1 s h o r t vs b2 s h o r t vs a1 (1) s h o r t gnd a2 (1) s h o r t gnd b1 (1) s h o r t gnd b2 (1) s h o r t gnd therm. therm. alarm shut down (reset operating codes) bit 76543210 76543210 76 76 76 76 76 76 76 76 76 76 76 76543210 command/response xx111111 xx011111 xx011111 xx011111 xx011011 xx111011 xx010011 xx010111 xx010010 xx110010 xx011010 xx011110 xx011011 xx111011 xx010011 xx010111 xx010010 xx110010 previous code 11111111 11011111 11011111 11011111 11011111 11011011 11111011 11010011 11010111 11110010 11011010 11011110 11011011 11111011 11010011 11010111 11010010 11 11 11 11 11 01 11 11 11 01 11 11 11 01 11 11 11 11 11 11 11 11 11 11 01 11 11 11 01 11 11 11 01 11 11 11 11 11 11 01 01 01 01 01 11 11 01 01 01 01 01 11 01 01 01 01 01 11 11 11 01 01 01 01 01 11 11 11 11 11 11 11 11 11 11 01 01 01 01 01 11 11 11 01 01 11 11 11 11 01 01 01 01 11 11 11 01 01 01 01 01 11 11 10 10 10 10 01 11 11 11 11 10 01 10 01 11 11 11 11 11 11 11 11 11 10 10 10 01 11 11 11 11 10 10 10 11 11 11 11 10 10 10 01 11 11 11 11 10 10 10 01 11 11 11 11 11 11 11 11 11 10 10 10 01 11 11 11 11 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00111111 00111111 00111111 00111111 00111111 00111111 00111111 00111111 00111111 00111111 00111111 00111111 00111111 00111111 00111111 00111111 00111111 1. motor resistance approximately 10 ? and v s = 12v. so a short to ground only is detected on one branch of the bridge. lower resistivity of the motor may lead to detection of sh ort to ground on both branches of the bridge leading to code 10 on all steps.
l9935 functional description doc id 5198 rev 10 25/29 5.17 electromagnetic emission classification (eme) electromagnetic emission classes presented below are typical data found on bench test. for detailed test description please refer to ?electromagnetic emission (eme) measurement of integrated circuits, dc to 1ghz? of vde/zvei work group 767.13 and vde/zvei work group 767.14 or iec project number 47a 1967ed. this data is targeted to board designers to allow an estimation of emission filtering effort required in application. electromagnetic emission is not tested in production. figure 13. state diagram remark: return to standby is possible from every state note: reversing polarity in low current mode no flyback check will be performed. table 12. electromagnetic emission pin eme class remark gnd e 10 0 1 ? test v cc e - e blocked with 100nf close in to the device en. sdi, csn, csk, sdo in tristate k - h - sdo g - f sdo in low-z state, no data transfer power output a 1 , a 2 , b 1 , b 2 e 5 f sourcing output power output a 1 , a 2 , b 1 , b 2 -6 f sinking output in chopping mode f osc = 20 khz '!0'03 34!.$ "9 /&& /&& /. /. $%6)#%/. #(%#+3&/2 %22/23 #(%#+).' &/2%22/23 #(%#+).' &/2%22/23 ,/')# 3%,%#43 "2!.#(% $%0%.$).' /.02%6)/53 3 4!4 % /. #(%#+).' &,9"!#+ turnon newtelegram noerror newtelegram new telegram new telegram newtelegramcurrent new telegram missing flyback differentpolarity short tognd shortto63 noshort noshort samepolarityasbefore shortto63 short tognd short tognd short to63 short to63 shorttognd short to63 shorttognd newtelegram samepolarity flyback/+ orreversepolarity thanbefore
functional description l9935 26/29 doc id 5198 rev 10 figure 14. emc compatibility for l9935 '!0'03 ?( n& n& ?&
n& bipolarsteppermotor 6s /ut /ut /ut /ut '.$ 6batt
l9935 package information doc id 5198 rev 10 27/29 6 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 15. powerso20 mechanical data and package dimensions /54,).%!.$ -%#(!.)#!,$!4! e a ! % a 03/-%# $%4!),! 4 $ % % hx? $%4!),! lead slug a 3 'age0lane , $%4!)," 2 $%4!)," #/0,!.!2)49 '# # 3%!4).'0,!.% e b c . . ( "/44/-6)%7 % $ $)- mm inch -). 490 -!8 -). 490 -!8 ! a a a b c $ $ % e e % % % ' ( h , . ?typ 3 ?max 4 h$and%vdonotincludemoldflashorprotusions -oldflashorprotusionsshallnotexceedmmv #riticaldimensionsh%vh'vandhav &orsubcontractorsthelimitistheonequotedinjedec-/ 0ower3/ ) *%$ %#-/ 7eight gr '!0'03
revision history l9935 28/29 doc id 5198 rev 10 7 revision history table 13. document revision history date revision changes 13-apr-2003 6 initial release. 02-aug-2006 7 updated at the new corporate template. corrected the figure 14 . 11-dec-2008 8 updated figure 2: pin connection (top view) on page 7 . updated section 6: package information on page 27 . 04-apr-2011 9 updated section 5.10: open load on page 17 . 18-sep-2013 10 updated disclaimer.
l9935 doc id 5198 rev 10 29/29 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particul ar purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ? automotive, automotive safe ty or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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