1 ? caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2003. all rights reserved all other trademarks mentioned are the property of their respective owners. HI5675 8-bit, 20msps, flash a/d converter the HI5675 is an 8-bit, analog-t o-digital converter built in an advanced cmos process. the low power, low differential gain and phase, high sampling rate, and single 5v supply make the HI5675 ideal for video and imaging applications. the adoption of a 2-step flash architecture achieves low power consumption (60mw) at a maximum conversion speed of 20msps with only a 2. 5 clock cycle data latency. the HI5675 also features digita l output enable/disable and a built in voltage reference. the HI5675 can be configured to use the internal reference or an external reference if higher precision is required. pinout HI5675 (soic) top view features ? resolution . . . . . . . . . . . . . . . . . . . . 8-bit 0.3 lsb (dnl) ? maximum sampling frequency . . . . . . . . . . . . . . 20msps ? low power consumption . . . . . . . . . . . . . . . . . . . . .60mw (reference current excluded) ? built-in sample and hold circuit ? built-in reference voltage self bias circuit ? three-state ttl compatible output ? single +5v power supply ? low input capacitance. . . . . . . . . . . . . . . . . . . 11pf (typ) ? reference impedance . . . . . . . . . . . . . . . . . . . 300 ? (typ) ?low cost ? direct replacement for tlc5510 and adc1175 applications ? video digitizing ? pc video capture ? image scanners ? tv set top boxes ?multimedia ? personal communication systems (pcs) part number information part number temp. range ( o c) package pkg. no. HI5675jcb -40 to 85 24 ld soic m24.2-s dv ss d0 (lsb) d1 d2 d3 d4 d6 d5 dv dd clk v rb av ss v in av dd v rbs v rt v rts av dd av dd dv dd oe dv ss 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 20 21 22 23 24 15 14 13 d7 (msb) av ss data sheet march 2003 fn4711.1 o b s o l e t e p r o d u c t p o s s i b l e s u b s t i t u t e p r o d u c t i n t e r s i l p a r t n u m b e r h i 1 1 7 5
2 functional block diagram typical application schematic : ceramic chip capacitor 0.1 f : analog gnd : digital gnd note: it is necessary that av dd and dv dd pins be driven from the same supply. the gain of analog input signal can be changed by adjusting the ratio of r2 to r1. lower data latches upper data latches lower encoder (4-bit) lower encoder (4-bit) upper encoder (4-bit) lower comparators with s/h (4-bit) upper comparators with s/h (4-bit) reference voltage clock generator oe dv ss d0 (lsb) d1 d2 d3 d4 d5 d6 d7 (msb) dv dd clk 11 10 9 8 7 6 5 4 3 2 1 12 lower comparators with s/h (4-bit) 24 23 20 21 22 19 14 15 16 17 18 13 dv ss v rb v rbs av ss av ss v in av dd v rt v rts av dd av dd dv dd 0.6v (typ) 2.6v (typ) d0 (lsb) d1 d2 d3 d4 d6 d5 clk 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 20 21 22 23 24 15 14 13 d7 (msb) v in + c9 4.7 f hc04 clock in +5v c10 0.1 f +5v c12 0.1 f c8 ? + c7 4.7 f c11 0.1 f +5v r12 + - ca158a HI5675 r4 + - ca158a r5 icl8069 r11 + - ha2544 r2 r1 r13 r3 ? HI5675
3 pin descriptions pin number symbol description 1 oe when oe = low, data is valid. when oe = high, d0 to d7 pins high impedance. 2, 24 dv ss digital gnd. 3-10 d0 to d7 d0 (lsb) to d7 (msb) output. 11, 13 dv dd digital +5v. (connect to av dd to avoid latchup). 12 clk clock input. 16 v rts shorted with v rt generates, +2.6v. 17 v rt reference voltage (top). 23 v rb reference voltage (bottom). 14, 15, 18 av dd analog +5v. digital +5v. (connect to dv dd to avoid latchup). 19 v in analog input. 20, 21 av ss analog gnd. 22 v rbs shorted with v rb generates +0.6v. HI5675
4 absolute m aximum ratings thermal information supply voltage, v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7v reference voltage, v rt , v rb . . . . . . . . . . . . . . . . . . . . v dd to v ss analog input voltage, v in . . . . . . . . . . . . . . . . . . . . . . . v dd to v ss digital input voltage, clk . . . . . . . . . . . . . . . . . . . . . . . v dd to v ss digital output voltage, v oh , v ol . . . . . . . . . . . . . . . . . v dd to v ss operating conditions (note 1) temperature range, t a . . . . . . . . . . . . . . . . . . . . . . -40 o c to 85 o c supply voltage av dd , av ss , dv dd , dv ss . . . . . . . . . . . . . . . . +4.75v to +5.25v | dgnd-agnd |. . . . . . . . . . . . . . . . . . . . . . . . . . . . 0mv to 100mv reference input voltage v rb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0v and above v rt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8v and below analog input range, v in . . . . . . . v rb to v rt (1.8v p-p to 2.8v p-p ) clock pulse width t pw1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns (min) t pw0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns (min) thermal resistance (typical, note 1) ja ( o c/w) soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . 150 o c maximum storage temperature range, t stg . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . 300 o c (soic - lead tips only) die characteristics die size: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.23 x 2.24mm caution: stresses above those listed in ?abs olute maximum ratings? may cause permanent dam age to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. ja is measured with the component mount ed on an evaluation pc board in free air. electrical specifications f c = 20msps, av dd = dv dd = 5v, v rb = 0.5v, v rt = 2.5v, t a = 25 o c (note 1) parameter test conditions min typ max unit system performance offset voltage e ot -60 -35 -10 mv e ob 0 +15 +45 mv integral non-linearity, inl f c = 20msps, v in = 0.6v to 2.6v - 0.5 1.3 lsb differential non-linearity, dnl f c = 20msps, v in = 0.6v to 2.6v - 0.3 0.5 lsb dynamic characteristics effective number of bits, enob f in = 1mhz - 7.6 - bits spurious free dynamic range f in = 1mhz - 51 - db signal to noise ratio, sinad f c = 20mhz, f in = 1mhz - 46 - db f c = 20mhz, f in = 3.58mhz - 46 - db maximum conversion speed, f c v in = 0.6v to 2.6v, f in = 1khz ramp 20 - - msps minimum conversion speed - - 0.5 msps differential gain error, dg ntsc 40 ire mod ramp, f c = 14.3msps - 1.0 - % differential phase error, dp - 0.5 - degree aperture jitter, t aj - 30 - ps sampling delay, t ds - 4 - ns data latency, t lat - - 2.5 cycles analog inputs analog input bandwidth (-1db), bw - 18 - mhz analog input capacitance, c in v in = 1.5v + 0.07v rms - 11 - pf rms signal rms noise distortion + ----------------------------------------------------------------- - = HI5675
5 reference input reference pin current, i ref 4.5 6.6 8.7 ma reference resistance (v rt to v rb ), r ref 230 300 450 ? internal voltage reference self bias mode 1 v rb short v rb and v rbs , short v rt and v rts 0.60 0.64 0.68 v v rt - v rb 1.96 2.09 2.21 v self bias mode 2, v rt v rb = agnd, short v rt and v rts 2.25 2.39 2.53 v digital inputs digital input voltage v ih 4.0 - - v v il - - 1.0 v digital input current i ih v dd = max v ih = v dd - - 5 a i il v il = 0v - - 5 a digital outputs digital output current i oh oe = v ss , v dd = min v oh = v dd -0.5v -1.1 - - ma i ol v ol = 0.4v 3.7 - - ma digital output current i ozh oe = v dd , v dd = max v oh = v dd - 0.01 16 a i ozl v ol = 0v - 0.01 16 a timing characteristics output data delay, t dl - 18 30 ns power supply characteristic supply current, i dd f c = 20msps, ntsc ramp wave input - 12 17 ma note: 2. electrical specifications guaranteed onl y under the stated operating conditions. electrical specifications f c = 20msps, av dd = dv dd = 5v, v rb = 0.5v, v rt = 2.5v, t a = 25 o c (note 1) (continued) parameter test conditions min typ max unit timing diagrams figure 1. t pw1 t pw0 clock analog input data output n n - 2 n + 3 n + 4 n - 3 n - 2 n - 1 n n + 1 t d = 18ns : point for analog signal sampling n + 1 HI5675
6 figure 2. timing diagrams (continued) analog input external clock upper comparator block upper data lower reference voltage lower comparator block a lower data a lower comparator block b lower data b digital output v i (1) v i (2) v i (3) v i (4) s (1) c (1) s (2) c (2) s (3) s (4) c (3) c (4) md (0) md (1) md (2) md (3) rv (0) rv (1) rv (2) rv (3) s (1) c (1) s (3) c (3) h (3) h (1) ld (-1) ld (1) h (0) c (0) s (2) h (2) c (2) s (4) h (4) ld (-2) ld (0) ld (2) out (-2) out (-1) out (0) out (1) HI5675
7 detailed description the HI5675 is a 2-step a/d converter featuring a 4-bit upper comparator group and two lower comparator groups of 4 bits each. the reference voltage can be obtained from the onboard bias generator or be supplied externally. this ic uses an offset canceling type comparator that operates synchronously with an external clock. the operating modes of the part are input sampling (s), hold (h), and compare (c). the operation of the part is illustrated in figure 2. a reference voltage that is between v rt -v rb is constantly applied to the upper 4-bit co mparator group. vi(1) is sampled with the falling edge of the first clock by the upper comparator block. the lower block a also samples vi(1) on the same edge. the upper comparator block finalizes comparison data md(1) with the rising edge of the first clock. simultaneously the reference su pply generates a reference voltage rv(1) that corresponds to the upper results and applies it to the lower comparator block a. the lower comparator block finalizes co mparison data ld(1) with the rising edge of the second clock. md(1) and ld(1) are combined and output as out(1) with the rising edge of the third clock. there is a 2.5 cycle clock delay from the analog input sampling point to the corresponding digital output data. notice how the lower comparator blocks a and b alternate generating the lower data in order to increase the overall a/d sampling rate. power, grounding, and decoupling to reduce noise effects, separate the analog and digital grounds. in order to avoid latchup at power up, it is necessary that av dd and dv dd be driven from the same supply. bypass both the digital and analog v dd pins to their respective grounds with a ceramic 0.1 f capacitor close to the pin. analog input the input capacitance is small when compared with other flash type a/d converters. however, it is necessary to drive the input with an amplifier with sufficient bandwidth and drive capability. in order to prevent parasitic oscillation, it may be necessary to insert a low value (i.e., 0.24 ? ) resistor between the output of the amplifier and the a/d input. reference input the range of the a/d is se t by the voltage between v rt and v rb . the internal bias generator will set v rts to 2.6v and v rbs to 0.6v. these can be used as the part reference by shorting v rt and v rts and v rb to v rbs . the analog input range of the a/d will now be from 0.6v to 2.6v and is referred to as self bias mode 1. self bias mode 2 is where vrb is connected to agnd and v rt is shorted to v rts . the analog input range will now be from 0v to 2.4v. table 1. a/d output code table input signal voltage step digital output code msb d6 d5 d4 d3 d2 d1 lsb v rt 255 1 1 1 1 1 1 1 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? 128 1 0 0 0 0 0 0 0 127 0 1 1 1 1 1 1 1 ? ? ? ? ? ? v rb 0 0 0 0 0 0 0 0 0 HI5675
8 test circuits figure 3. integral and differential non-linearity error and offset voltage test circuit figure 4. maximum operational speed and differen tial gain and phase error test circuit figure 5. digital output current test circuit - v in HI5675 dut 8 clk (20mhz) + ab comparator a8 a1 a0 b8 b1 b0 ?0? ?1? 8 s1 s2 -v +v s1: on if a < b s2: on if a > b buffer dvm controller 8 to 111 ? ? ? 10 000 ? ? ? 00 to to signal source ntsc sg v in 8 8 scope vector 620 dg error rate sg (cw) amp HI5675 dut ecl ttl d/a 10-bit -5.2v clk 1 2 1 2 hpf counter dp 620 -5.2v ecl ttl f c -40 0 100 ire sync burst 0.6v 2.6v 40 ire modulation 0.6v 2.6v f c -1khz hi20201 v rt v in v rb clk oe gnd v dd 0.6v 2.6v v ol i ol + - v rt v in v rb clk oe gnd v dd 0.6v 2.6v v oh i oh + - HI5675 HI5675 HI5675
9 static performance definitions offset, full scale, and gain all use a measured value of the internal voltage reference to determine the ideal plus and minus full scale values. the results are all displayed in lsbs. offset error (e ob ) the first code transition should occur at a level 1 / 2 lsb above the bottom reference voltag e. offset is defined as the deviation of the actual code transition from this point. note that this is adjustable to zero. full scale error (e ot ) the last code transition should occur for a analog input that is 1 1 / 2 lsbs below full scale. full scale error is defined as the deviation of the actual code transition from this point. differential linearity error (dnl) dnl is the worst case deviation of a code width from the ideal value of 1 lsb. the converter is guaranteed to have no missing codes. integral linearity error (inl) inl is the worst case deviation of a code center from a best fit straight line calculated from the measured data. dynamic performa nce definitions fast fourier transform (fft) techniques are used to evaluate the dynamic perform ance of the HI5675. a low distortion sine wave is applied to the input, it is sampled, and the output is stored in ram. the data is then transformed into the frequency domain with a 1024 point fft and analyzed to evaluate the dynamic performance of the a/d. the sine wave input to the part is -0.5db down from fullscale for all these tests. the distor tion numbers are quoted in dbc (decibels with respect to carrier) and do not include any correction factors for no rmalizing to fullscale. signal-to-noise ratio (snr) snr is the measured rms signal to rms noise at a specified input and sampling frequency. the noise is the rms sum of all of the spectral components except the fundamental and the first five harmonics. signal-to-noise + dist ortion ratio (sinad) sinad is the measured rms signal to rms sum of all other spectral components below the nyquist frequency excluding dc. effective number of bits (enob) the effective number of bits (enob) is derived from the sinad data. enob is calculated from: enob = (sinad - 1.76 + v corr ) / 6.02, where: v corr = 0.5db. total harmonic distortion this is the ratio of the rms sum of the first 5 harmonic components to the rms value of the measured input signal. 2nd and 3rd harmonic distortion this is the ratio of the rms value of the 2nd and 3rd harmonic component respective ly to the rms value of the measured input signal. spurious free dynamic range (sfdr) sfdr is the ratio of the fundamental rms amplitude to the rms amplitude of the next largest spur or spectral component. if the harmonics are bu ried in the noise floor it is the largest peak. full power input bandwidth full power bandwidth is the frequency at which the amplitude of the digitall y reconstructed output has decreased 3db below the amplit ude of the input sine wave. the input sine wave has a peak-to-peak amplitude equal to the reference voltage. the bandwidth given is measured at the specified sampling frequency. timing definitions sampling delay (t sd ) sampling delay is the time delay between the external sample command (the falling edge of the clock) and the time at which the signal is actually sampled. this delay is due to internal clock path propagation delays. aperture jitter (t aj ) this is the rms variation in the sampling delay due to variation of internal clock path delays. data latency (t lat ) after the analog sample is taken, the data on the bus is available after 2.5 cycles of th e clock. this is due to the architecture of the converter where the data has to ripple through the stages. this delay is specified as the data latency. after the data latency time, the data representing each succeeding sample is output at the following clock pulse. the digital data lags th e analog input by 2.5 cycles. output data delay (t d ) output data delay is the delay time from when the data is valid (rising clock edge) to when it shows up at the output bus. this is due to internal delays at the digital output. HI5675
10 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality ce rtifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that da ta sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com small outline plast ic packages (soic) notes: 1. dimension ?d? does not include mold flash, protrusions or gate burrs. 2. dimension ?e? does not inclu de interlead flash or protrusions. 3. ?l? is the length of terminal for soldering to a substrate. 4. ?n? is the number of terminal positions. 5. terminal numbers are shown for reference only. 6. controlling dimension: millime ter. converted inch dimensions are not necessarily exact. index area e d n 123 0.24 m e l b a1 a seating plane 0.15(0.006) c h m24.2-s 24 lead small outline plastic package (200 mil) symbol inches millimeters notes min max min max a 0.067 0.088 1.70 2.25 - a1 0.002 0.011 0.05 0.30 - b 0.014 0.021 0.35 0.55 - c 0.006 0.011 0.15 0.30 - d 0.587 0.606 14.9 15.4 1 e 0.205 0.220 5.2 5.6 2 e 0.050 bsc 1.27 bsc - h 0.296 0.326 7.5 8.3 - l 0.012 0.027 0.30 0.70 3 n24 244 0 o 10 o 0 o 10 o - rev. 1 4/95
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