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ir3505z page 1 of 20 march 17, 2009 data sheet xphase3 tm phase ic description the ir3505z phase ic combined with an ir xphase3 tm control ic provides a full featured and flexible way to implement power solutions for the latest high perfor mance cpus and asics. the control ic provides overall system control and interfaces with any number of phase ics which each drive and monitor a single phase of a multiphase converter. the xphase3 tm architecture results in a power supply that is smaller, less expensive, and easier to design while providing higher efficiency than conventional approaches. features ? 7v/2a gate drivers (4 a gatel sink current) ? support converter output voltage up to 5.1 v (limited to vccl-1.4v) ? support loss-less inductor current sensing ? feed-forward voltage mode control ? integrated boot-strap synchronous pfet ? only four ic related external components per phase ? 3 wire analog bus connects control a nd phase ics (vdac, error amp, ishare) ? 3 wire digital bus for accurate daisy-chain pha se timing control without external components ? debugging function isolates phase ic from the converter ? self-calibration of pwm ramp, current s ense amplifier, and current share amplifier ? single-wire bidirectional average current sharing ? small thermally enhanced 16l 3 x 3mm mlpq package ? rohs compliant application circuit downloaded from: http:///
ir3505z page 2 of 20 march 17, 2009 ordering information part number package order quantity IR3505ZMtrpbf 16 lead mlpq (3 x 3 mm body) 3000 per reel * IR3505ZMpbf 16 lead mlpq (3 x 3 mm body) 100 piece strips * samples only absolute maximum ratings stresses beyond those listed below may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyo nd those indicated in the operational sections of the specific ations are not implied. operating junction temperature.. 0 o c to 150 o c storage temperature range.-65 o c to 150 o c msl rating2 reflow temperature.260 o c note: 1. maximum gateh C sw = 8v 2. maximum boost C gateh = 8v pin # pin name v max v min i source i sink 1 ishare 8v -0.3v 1ma 1ma 2 dacin 3.3v -0.3v 1ma 1ma 3 lgnd n/a n/a n/a n/a 4 phsin 8v -0.3v 1ma 1ma 5 phsout 8v -0.3v 2ma 2ma 6 clkin 8v -0.3v 1ma 1ma 7 pgnd 0.3v -0.3v 5a for 100ns, 200ma dc n/a 8 gatel 8v -0.3v dc, -5v for 100ns 5a for 100ns, 200ma dc 5a for 100ns, 200ma dc 9 vccl 8v -0.3v n/a 5a for 100ns, 200ma dc 10 boost 34v -0.3v 1a for 100ns, 100ma dc 3a for 100ns, 100ma dc 11 gateh 34v -0.3v dc, -5v for 100ns 3a for 100ns, 100ma dc 3a for 100ns, 100ma dc 12 sw 34v -0.3v dc, -5v for 100ns 3a for 100ns, 100ma dc n/a 13 vcc 18v -0.3v n/a 10ma 14 csin+ 8v -0.3v 1ma 1ma 15 csin- 8v -0.3v 1ma 1ma 16 eain 8v -0.3v 1ma 1ma downloaded from: http:///
ir3505z page 3 of 20 march 17, 2009 recommended operating co nditions for reliable o peration with margin 8.0v v cc 16v, 4.75v v ccl 7.5v, 0.5v v(dacin) 1.6v, 250khz clkin 9mhz, 250khz phsin 1.5mhz, 0 o c t j 125 o c electrical characteristics the electrical characteristics involve the spread of val ues guaranteed within the re commended operating conditions. typical values represent the median values, which are related to 25c. c gateh = 3.3nf, c gatel = 6.8nf (unless otherwise specified). parameter test condition min typ max unit gate drivers gateh source resistance boost C sw = 7v. note 1 1.0 2.5 ? gateh sink resistance boost C sw = 7v. note 1 1.0 2.5 ? gatel source resistance vccl C pgnd = 7v. note 1 1.0 2.5 ? gatel sink resistance vccl C pgnd = 7v. note 1 0.4 1.0 ? gateh source current boost=7v, gateh=2.5v, sw=0v. 2.0 a gateh sink current boost=7v, gateh=2.5v, sw=0v. 2.0 a gatel source current vccl=7v, ga tel=2.5v, pgnd=0v. 2.0 a gatel sink current vccl=7v, ga tel=2.5v, pgnd=0v. 4.0 a gateh rise time boost C sw = 7v, measure 1v to 4v transition time 5 10 ns gateh fall time boost - sw = 7v, measure 4v to 1v transition time 5 10 ns gatel rise time vccl C pgnd = 7v, measure 1v to 4v transition time 10 20 ns gatel fall time vccl C pgnd = 7v, measure 4v to 1v transition time 5 10 ns gatel low to gateh high delay boost = vccl = 7v, sw = pgnd = 0v, measure time from gatel falling to 1v to gateh rising to 1v 10 20 40 ns gateh low to gatel high delay boost = vccl = 7v, sw = pgnd = 0v, measure time from gateh falling to 1v to gatel rising to 1v 10 20 40 ns disable pull-down resistance note 1 30 80 130 k ? clock clkin threshold compare to v(vccl) 40 45 57 % clkin bias current clkin = v(vccl) -0.5 0.0 0.5 a clkin phase delay measure time from clkin<1v to gateh>1v 40 75 125 ns phsin threshold compare to v(vccl) 35 50 55 % phsout propagation delay measure time from clkin > (vccl * 50% ) to phsout > (vccl *50%). 10pf @125 o c 4 15 35 ns phsin pull-down resistance 30 100 170 k ? phsout high voltage i(phsout) = -10ma, measure vccl C phsout 1 0.6 v phsout low voltage i(phsout) = 10ma 0.4 1 v downloaded from: http:///
ir3505z page 4 of 20 march 17, 2009 parameter test condition min typ max unit pwm comparator pwm ramp slope vin=12v 42 52.5 57 mv/ %dc input offset voltage note 1 -5 0 5 mv eain bias current 0 eain 3v -5 -0.3 5 a minimum pulse width note 1 65 75 ns minimum gateh turn-off time 20 80 160 ns current sense amplifier csin+/- bias current -200 0 200 na csin+/- bias current mismatch note 1 -50 0 50 na input offset voltage csin+ = csin- = dacin. measure input referred offset from dacin -1 1 mv gain 0.5v v(dacin) < 1.6v 30 32.5 35 v/v unity gain bandwidth c(ishare)=10pf. measure at ishare. note 1 4.8 6.8 8.8 mhz slew rate 6 v/ s differential input range 0.8v v(dacin) 1.6v, note 1 -10 50 mv differential input range 0.5v v(dacin) < 0.8v, note 1 -5 50 mv common mode input range note 1 0 note2 v rout at t j = 25 o c note 1 2.3 3.0 3.7 k ? rout at t j = 125 o c 3.6 4.7 5.4 k ? ishare source current 0.500 1.6 2.9 ma ishare sink current 0.500 1.4 2.9 ma share adjust amplifier input offset voltage note 1 -3 0 3 mv differential input range note 1 -1 1 v gain csin+ = csin- = dacin. note 1 4 5.0 6 v/v unity gain bandwidth note 1 4 8.5 17 khz pwm ramp floor voltage ishare unconnected measured relative to dacin -116 0 +116 mv maximum pwm ramp floor voltage ishare = dacin - 200mv measured relative to floor with ishare unconnected 120 180 240 mv minimum pwm ramp floor voltage ishare = dacin + 200mv measured relative to floor with ishare unconnected -220 -160 -100 mv body brake comparator threshold voltage with eain falling. measured relative to pwm ramp floor voltage -300 -200 -110 mv threshold voltage with eain rising. measured relative to pwm ramp floor voltage -200 -100 -10 mv hysteresis 70 105 130 mv propagation delay vccl = 5v. measure time from eain < v(dacin) (200mv overdrive) to gatel transition to < 4v. 40 65 90 ns downloaded from: http:///
ir3505z page 5 of 20 march 17, 2009 note 1: guaranteed by design, but not tested in production note 2: vccl-0.5v or vcc C 2.5v, whichever is lower parameter test condition min typ max unit ovp comparator ovp threshold step v(ishare) up until gatel drives high. compare to v(vccl) -1.0 -0.8 -0.4 v propagation delay v(vccl)=5v, step v(ishare) up from v(dacin) to v(vccl). measure time to v(gatel)>4v. 15 40 70 ns synchronous rectification disable comparator threshold voltage the ratio of v(csin-) / v(dacin), below which v(gatel) is always low. 66 75 86 % negative current comparator input offset voltage note 1 -16 0 16 mv propagation delay time apply step voltage to v(csin+) C v(csin-). measure time to v(gatel)< 1v. 100 200 400 ns bootstrap diode forward voltage i(boost) = 30ma, vccl=6.5v 180 260 480 mv debug comparator threshold voltage compare to v(vccl) -250 -150 -50 mv general vcc supply current 1.1 3.0 6.1 ma vccl supply current 3.1 6.7 12.1 ma boost supply current 4.75v v ( boost)-v(sw) 8v 1.2 3.5 5.8 ma dacin bias current -1.5 -0.75 1 a sw floating voltage measured in the application 0.3 v downloaded from: http:///
ir3505z page 6 of 20 march 17, 2009 pin description pin# pin symbol pin description 1 ishare output of the current sense amplif ier is connected to this pin through a 3k ? resistor. voltage on this pin is equal to v( dacin) + 32.5 [v(csin+) C v(csin-)]. connecting all ishare pins together cr eates a share bus which provides an indication of the average current being supp lied by all the phases. the signal is used by the control ic for voltage positioning and over-current protection. ovp mode is initiated if the voltage on this pin rises above v(vccl)- 0.8v. 2 dacin reference voltage input from the c ontrol ic. the current sense signal and pwm ramp is referenced to the voltage on this pin. 3 lgnd ground for internal ic circuits. ic substrate is connected to this pin. 4 phsin phase clock input. 5 phsout phase clock output. 6 clkin clock input. 7 pgnd return for low side driver and re ference for gateh non-overlap comparator. 8 gatel low-side driver output and i nput to gateh non-overlap comparator. 9 vccl supply for low-side driver. internal bootstrap synchronous pfet is connected from this pin to the boost pin. 10 boost supply for high-side driver. internal bootstrap synchronous pfet is connected between this pin and the vccl pin. 11 gateh high-side driver output and i nput to gatel non-overlap comparator. 12 sw return for high-side driver and re ference for gatel non-overlap comparator. 13 vcc supply for internal ic circuits. 14 csin+ non-inverting input to the current se nse amplifier, and input to debug comparator. 15 csin- inverting input to the current sense am plifier, and input to synchronous rectification disable comparator. 16 eain pwm comparator input from the error am plifier output of control ic. body braking mode is initiated if the voltage on th is pin is less than v(dacin). downloaded from: http:///
ir3505z page 7 of 20 march 17, 2009 system theory of operation pwm control method the pwm block diagram of the xphase tm architecture is shown in figure 1. feed-forward voltage mode control with trailing edge modulation is used. a high-gain wide-bandwidth voltage type error amplifier in the control ic is used for the voltage control loop. input voltage is sensed in phase ics and fe ed-forward control is realized. the pwm ramp slope will change with the input voltage and automatically compensate for changes in the input voltage. the input voltage can change due to variations in the silver box output voltage or due to the wire and pcb-trace voltage drop related to changes in load current. pwm comparator rdrp1 vsetpt clkin rcs ccs phsin dacin vcc gateh ishare csin+ gatel eain csin- ccomp1 vcch cbst vccl pgnd sw vid6 phsout vid6 clk d q phsin ccomp rfb + - + - + - + - + - clkin rcs cdrp + - ccs +- rdrp + - 3k gnd vout vdac vo dacin vcc phsin vosns- vosns+ lgnd ishare iin vdrp eain gateh csin- csin+ gatel eaout clkout vin fb irosc vid6 remote sense amplifier vcch rcomp cbst clk 2 r 3 d 1 q 4 q 5 vccl gate drive voltage phsout pwm comparator vid6 vid6 vid6 clk d q + - + - + - + - + - 3k vid6 clk 2 r 3 d 1 q 4 q 5 vid6 - + vid6 + + ramp discharge clamp enable body braking comparator rvsetpt pwm latch current sense amplifier share adjust error amplifier reset dominant 1 2 phase ic pgnd - + sw vid6 + + - + ldo amplifier ramp discharge clamp enable bodybraking comparator vdrpamp vdac ivsetpt clock generator current sense amplifier reset dominant pwm latch share adjust error amplifier error amplifier rfb1 cout control ic cfb 1 2 phsout phase ic figure 1 pwm block diagram frequency and phase timing control the oscillator is located in the control ic and the system cl ock frequency is programmable from 250khz to 9mhz by an external resistor. the control ic system clock signal (clkout) is connected to clkin of all the phase ics. the phase timing of the phase ics is controlled by the daisy chain loop, where control ic phase clock output (phsout) is connected to the phase clock input (phs in) of the first phase ic, and phsout of the first phase ic is connected to phsin of the second phase ic, etc. and phsout of the last phase ic is connected back to phsin of the control ic. during power up, the control ic sends out clock signals from both clkout and phsout pins and detects the feedback at phsin pin to determine the phase number and moni tor any fault in the daisy c hain loop. figure 2 shows the phase timing for a four phase converter. the switching frequency is set by the resist or rosc. the clock frequency equals the number of phase times the switching frequency. downloaded from: http:///
ir3505z page 8 of 20 march 17, 2009 phase ic1 pwm latch set control ic clkout (phase ic clkin) control ic phsout (phase ic1 phsin) phase ic 1 phsout (phase ic2 phsin) phase ic 2 phsout (phase ic3 phsin) phase ic 3 phsout (phase ic4 phsin) phase ic4 phsout (control ic phsin) figure 2 four phase oscillator waveforms pwm operation the pwm comparator is located in the phase ic. upon rece iving the falling edge of a clock pulse, the pwm latch is set; the pwm ramp voltage begins to incr ease; the low side driver is turned off, and the high side driver is turned on after the non-overlap time. when the pwm ramp voltage exce eds the error amplifiers output voltage the pwm latch is reset. this turns off the high side driver, turns on the low side driver after the non-overlap time, and activates the ramp discharge clamp. the clamp drives the pwm ramp vo ltage to the level set by the share adjust amplifier until the next clock pulse. the pwm latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nanoseconds in response to a load step decrease. phases can overlap and go up to 100% duty cycle in response to a load step increase with turn-on gated by the clock pulses. an error amplifier output voltage greater than the common mode input range of the pwm comparator results in 100% duty cycle regardless of the voltage of the pwm ramp. this arrangement guarantees the error amplifie r is always in control and can deman d 0 to 100% duty cycle as required. it also favors response to a load step decrease which is appropriate given the low output to input voltage ratio of most systems. the inductor current will increase much more rapidly than decrease in response to load transients. an additional advantage of this pwm modulator is that diffe rences in ground or input voltage at the phases have no effect on operation since the pwm ramps are referenced to vdac. figure 3 depicts pwm operating waveforms under various conditions. downloaded from: http:///
ir3505z page 9 of 20 march 17, 2009 phase ic clock pulse eain vdac pwmrmp gateh gatel steady-state operation duty cycle decrease due to vin increase (feed-forward) duty cycle increase due to load increase steady-state operation duty cycle decrease due to load decrease (body braking) or fault (vccluv, ocp, vid=11111x) figure 3 pwm operating waveforms body braking tm in a conventional synchronous buck conver ter, the minimum time required to redu ce the current in the inductor in response to a load step decrease is; o min max slew v i i l t ) (* ? = the slew rate of the inductor current can be significantly increased by turning off the synchronous rectifier in response to a load step decrease. the switch node voltage is then forced to decr ease until conduction of the synchronous rectifiers body diode occu rs. this increases the voltage across the inductor from vout to vout + v bodydiode . the minimum time required to reduce the current in the inductor in response to a load transient decrease is now; bodydiode o min max slew v v i i l t + ? = ) (* since the voltage drop in the body diode is often comparabl e to the output voltage, the inductor current slew rate can be increased significantly. this patented technique is refe rred to as body braking and is accomplished through the body braking comparator located in the phase ic. if the error amplifiers output voltage drops below the output voltage of the share adjust amplifier in the phase ic, this comparator turns off the low side gate driver. lossless average inductor current sensing inductor current can be sensed by connecting a series resist or and a capacitor network in parallel with the inductor and measuring the voltage across the capacitor, as shown in figure 4. the equation of the sensing network is, cs cs l l cs cs l c c sr sl r si c sr s v s v + + = + = 1 )( 1 1 )( )( usually the resistor rcs and capacitor ccs are chosen so that the time constant of rcs and ccs equals the time constant of the inductor which is the inductance l over the inductor dcr (r l ). if the two time constants match, the voltage across ccs is proportional to the current through l, and the sense circuit can be treated as if only a sense resistor with the value of r l was used. the mismatch of the time constants does not affect the measurement of inductor dc current, but affects the ac component of the inductor current. downloaded from: http:///
ir3505z page 10 of 20 march 17, 2009 figure 4 inductor current sens ing and current sense amplifier the advantage of sensing the inductor current versus high side or low side sensing is that actual output current being delivered to the load is obtained rather than peak or sampl ed information about the switch currents. the output voltage can be positioned to meet a load line based on real time inform ation. except for a sense resistor in series with the inductor, this is the only sense method that can support a single cycle transient response. other methods provide no information during either load increase (low side sensing) or load decrease (high side sensing). an additional problem associated with peak or valley current mode control for voltage positioning is that they suffer from peak-to-average errors. these errors will show in many ways but one example is the effect of frequency variation. if the frequency of a particular unit is 10% low, the peak to peak i nductor current will be 10% larger and the output impedance of the converter will drop by about 10%. variations in inductance, current sense amplifier bandwidth, pwm prop delay, any added slope compensation, input voltage, and output volt age are all additional sources of peak-to-average errors. current sense amplifier a high speed differential current sense amplifier is located in the phase ic, as shown in figure 5. its gain is nominally 32.5 and the 3850 ppm/oc increase in inductor dcr should be compensated in the voltage loop feedback path. the current sense amplifier ca n accept positive differential input up to 50 mv and negative up to -10mv before clipping. the output of the current sense amplifier is summed with the dac voltage an d sent to the control ic and other phases through an on-chip 3k ? resistor connected to the ishare pin. the ishare pins of all the phases are tied together and the voltage on the share bus represents the average current th rough all the inductors and is used by the control ic for voltage positioning and current limit protection. the input offset of this amplifier is calibrated to +/- 1mv in order to reduce the current sense error. the input offset voltage is the primary source of error for t he current share loop. in order to achieve very small input offset error and superior current sharin g performance, the current sense amplifier continuously calibrates itself. this calibration algorithm creates ripple on ishare bus with a frequency of f sw /(32*28) in a multiphase architecture. average current share loop current sharing between phases of the converter is achieved by the average current share loop in each phase ic. the output of the current sense amplifier is compared with the average current at the share bus. if current in a phase is smaller than the average current, the share adjust amplifier of the phase will pull down the starting point of the pwm ramp thereby increasing its duty cycle and output current; if current in a phase is larger than the average current, the share adjust amplifier of the phase will pull up the starting point of the pwm ramp thereby decreasing its duty cycle and output current. the current share amplifier is internally co mpensated so that the crossover frequency of the current share loop is much slower than that of the voltage loop and the two loops do not interact. c o l r l r cs c cs v o current sense amp csout i l v l c downloaded from: http:///
ir3505z page 11 of 20 march 17, 2009 ir3505z theory of operation block diagram the block diagram of the ir3505z is shown in figure 5, and specific features are discussed in the following sections. pwm_clk pwm_clk 100% duty latch (clkin if 1-phase) reset dominant + negative current latch s r q pwmq phsin vccl 3k clk r d q q + - s r q + - + - + - + - clk d q + - + - + - s r q + - + - vcc lgnd ishare eain gatel pgnd boost vccl csin- sw gateh csin+ clkin dacin phsout phsin calibration rmpout pwm reset vcc calibration csaout calibration dacin phsin dacin debug off share_adj irosc irosc dacin-share_adj vccl pwm latch share adjust amplifier body braking comparator pwm comparator 1v x33 current sense amplifier - synchronous rectification disable comparator + gatel non- overlap comparator 1v pwm ramp generator ovp comparator + gatel non- overlap latch gateh non- overlap latch gateh driver gatel driver set dominant set dominant x0.75 debug comparator (low=open) reset dominant gateh non- overlap comparator negative current comparator 0.8v 100mv 0.2v 200mv clk d q pwmq pwm_clk pwm_clk figure 5 block diagram tri-state gate drivers the gate drivers can deliver up to 2a peak current (4a sink current for bottom driv er). an adaptive non-overlap circuit monitors the voltage on the gateh and gatel pins to prevent mosfet shoot-through current while minimizing body diode conduction. the non-overlap latch is added to eliminate the error triggering caused by the switching noise. an enable signal is provided by the contro l ic to the phase ic without the addition of a dedicated signal line. the error amplifier output of the control ic drives low in response to any fault condition such as vccl under voltage or output overload. the ir3505z body braking tm comparator detects this and drives bottom gate output low. this tri-state operation prevents negative inductor current an d negative output voltage during power- down. a synchronous rectification disable co mparator is used to detect converte r csin- pin voltage, which represents local converter output voltage. if the vo ltage is below 75% of vdac and negative current is detected, gatel drives low, which disables synchronous rectif ication and eliminates negative current during power-up. the gate drivers pull low if the supply voltages are below the normal operating range. an 80k ? resistor is connected across the gateh/gatel and pgnd pins to prevent the gateh/gatel voltage from rising due to leakage or other causes under these conditions. downloaded from: http:///
ir3505z page 12 of 20 march 17, 2009 over voltage protection (ovp) the ir3505z includes over-voltage protection that turn s on the low side mosfet to protect the load in the event of a shorted high-side mosfet, converter out of r egulation, or connection of the converter output to an excessive output voltage. as shown in figure 6, if ishare pin voltage is above v(vccl) C 0.8v, which represents over-voltage condition detected by control ic, the over-voltage latch is set. gatel drives high and gateh drives low. the ovp circuit overrides the normal pwm operation an d within approximately 150ns will fully turn-on the low side mosfet, which remains on until ishare drops below v(vccl) C 0.8v when over voltage ends. the over voltage fault is latched in cont rol ic and can only be reset by cycling the power to control ic. the error amplifier output (eain) is pull ed down by control ic and will remain low. the lower mosfets alone can not clamp the output voltage howeve r an scr or n-mosfet could be triggered with the ovp output to prevent processor damage. after ovp output voltage (vo) ovp threshold ishare(iin) vccl-800 mv ovp condition normal operation gateh gatel error amplifier input (eain) vdac fault latch (control ic) figure 6 - over-voltage protection waveforms downloaded from: http:///
ir3505z page 13 of 20 march 17, 2009 pwm ramp every time the phase ic is powered up pwm ramp magnitude is calibrated to generate a 50 mv/% ramp for a vcc=12v. for example, for a 15% duty ratio the ramp amplitude is 750mv for vcc=12v. feed-forward control is achieved because the pwm ramp varies with vcc voltage proportionally after calibration. in response to a load step-up the error amplifier can demand 100 % duty cycle. in order to avoid pulse skipping under this scenario and allow the boost cap to replenish, a minimum off time is allowed in this mode of operation. as shown in figure 6, 100 % dut y is detected by comparing the pwm latch output (pwmq) and its input clock (pwm_clk). if the pwmq is high when the pwm_clk is asserted the topfet turnoff is initiated. the topfet is again turned on once the rmpout drops within 200 mv of the vdac. phsin clkin rmpout eain (2 phase design) normal operation pwmq 100 % duty operation 80ns vdac+200mv vdac figure 7: pwm operation durin g normal and 100 % duty mode. debugging mode if csin+ pin is pulled up to vccl voltage, ir3505z enters into debugging mode. both drivers are pulled low and ishare output is disconnected from the current share bus, which isolates this phase ic from other phases. however, the phase timing from phsin to phsout does not change. emulated bootstrap diode ir3505z integrates a pfet to emulate the bootstrap di ode. an external bootstrap diode connected from vccl pin to boost pin can be added to reduce the drop acro ss the pfet but is not needed in most applications. downloaded from: http:///
ir3505z page 14 of 20 march 17, 2009 applications information ir3505z external components inductor current sensing capacitor c cs and resistor r cs the dc resistance of the inductor is utilized to se nse the inductor current. usually the resistor r cs and capacitor c cs in parallel with the inductor are chosen to match the time constant of the inductor , and therefore the voltage across the capacitor c cs represents the inductor current. if the two time constants are not the same, the ac component of the capacitor voltage is different from that of the real inductor current. the time constant mismatch does not affect the average current sharing among the multip le phases, but does effect the current signal ishare as well as the output voltage during the load current transient if adaptive voltage positioning is adopted. measure the inductance l and the inductor dc resistance r l . pre-select the capacitor c cs and calculate r cs as follows. cs l cs c rl r = (1) bootstrap capacitor c bst depending on the duty cycle and gate drive current of the phase ic, a capacitor in the range of 0.1uf to 1uf is needed for the bootstrap circuit. decoupling capacitors for phase ic a 0.1uf-1uf decoupling capacitor is required at the vccl pin. current share loop compensation the internal compensation of current share loop ensures that crossover frequency of the current share loop is at least one decade lower than that of the voltage loop so th at the interaction between the two loops is eliminated. the crossover frequency of current share loop is approximately 8 khz. output voltage bleed resistor the floating high side driver draws bias current from t he boost pin (3.5ma typical). this current flows out of the ir3505z through the sw pin and will charge up the output capa citor when the control ic is disabled. a bleed resistor connected from the conv erter output voltage to ground is required to prevent the output voltage from exceeding the control ic over-voltage protection th reshold. the bleed resistor can be selected using the following equation. r bleed = v bleed / (5.8ma x n) (2) where v bleed is the maximum desired output voltage pre-bias and n is the number of ir3505z used in the converter. optional phases a converter can be designed to support more or less phases. this can be quite useful in situations where the final load current is unknown or where increased load current may be required at some time in the future. figure 8 provides an application circuit that allows adjustment to the number of phases. by populating zero ohm jumpers, or not; the number of phases can be adjusted by diverting the daisy chain timing from a 3505z to the next one in sequence. the effect of more or less phases on converter perform ance can be tested without actually removing a 3505z or its mosfets from the printed circuit board through use of a pull-up resistor from vccl to the csin+ pin to enable de-bug mode. downloaded from: http:///
ir3505z page 15 of 20 march 17, 2009 three phase two phase figure 8 C optional phase application circuit downloaded from: http:///
ir3505z page 16 of 20 march 17, 2009 layout guidelines the following layout guidelines are recommended to redu ce the parasitic inductance and resistance of the pcb layout, therefore minimizing the noise coupled to the ic. ? dedicate at least one middle layer for a ground plane. ? separate analog bus (eain, daci n, and ishare) from digital bus (clkin, phsin, and phsout) to reduce the noise coupling. ? connect pgnd and lgnd pins to the ground plane through vias. ? place current sense resistors and capacitors (r cs and c cs ) close to phase ic. use kelvin connection for the inductor current sense wires, but separate the two wires by ground polygon or route as a differential pair. the wire from the inductor terminal to csin- shou ld not cross over the fast transition nodes, i.e. switching nodes, gate drive outputs and bootstrap nodes. ? place the decoupling capacitor c vccl as close as possible to the vccl pin. ? place the phase ic as close as possible to the mosfets to reduce the parasitic resista nce and inductance of the gate drive paths. ? place the input ceramic capacitors close to the drain of top mosfet and the source of bottom mosfet. use a combination of different packages of ceramic capacitors. ? there are two switching power loops. one loop in cludes the input capacitors, top mosfet, inductor, output capacitors and the load; another loop consists of bottom mosfet, inductor, output capacitors and the load. route the switching power paths using wide and short traces or polygons; use multiple vias for connections between layers. downloaded from: http:///
ir3505z page 17 of 20 march 17, 2009 pcb metal and component placement ? lead land width should be equal to nominal part lead width. the minimum lead to lead spacing should be 0.2mm to minimize shorting. ? lead land length should be equal to maximum part lead length + 0.3 mm outboard extension + 0.05mm inboard extension. the outboard extension ensure s a large and inspectable toe fillet, and the inboard extension will accommodate any part misalignment and ensure a fillet. ? center pad land length and width should be equal to maximum part pad length and width. however, the minimum metal to metal spacing should be 0.17mm for 2 oz. copper ( 0.1mm for 1 oz. copper and 0.23mm for 3 oz. copper) ? four 0.3mm diameter vias shall be placed in the pad land spaced at 0.85mm, and connected to ground to minimize the noise effect on the ic, and to transfer heat to the pcb ? no pcb traces should be routed nor vias placed under any of the 4 corners of t he ic package. doing so can cause the ic to rise up from the pcb resu lting in poor solder joints to the ic leads. downloaded from: http:///
ir3505z page 18 of 20 march 17, 2009 solder resist ? the solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. the solder resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all non solder mask defined (nsmd). theref ore pulling the s/r 0.06mm will always ensure nsmd pads. ? the minimum solder resist width is 0.13mm. ? at the inside corner of the solder resist where the lead land groups meet, it is recommended to provide a fillet so a solder resist width of 0.17mm remains. ? the land pad should be solder mask defined (smd), wi th a minimum overlap of the solder resist onto the copper of 0.06mm to accommodate solder resist mis-alignm ent. in 0.5mm pitch cases it is allowable to have the solder resist opening for the land pad to be smaller than the part pad. ? ensure that the solder resist in-b etween the lead lands and the pad land is 0.15mm due to the high aspect ratio of the solder resist strip separa ting the lead lands from the pad land. ? the four vias in the land pad should be tented or plugged from bottom board side with solder resist. downloaded from: http:///
ir3505z page 19 of 20 march 17, 2009 stencil design ? the stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. reducing the amount of solder deposited will minimize the occurrence of lead shorts. since for 0.5mm pitch devices the leads are only 0.25mm wide, t he stencil apertures should not be made narrower; openings in stencils < 0.25mm wide are difficult to maintain repeatable solder release. ? the stencil lead land apertures should therefore be shortened in length by 80% and centered on the lead land. ? the land pad aperture should be approximately 70% area of solder on the center pad. if too much solder is deposited on the center pad the part will float and the lead lands will be open. ? the maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease t he incidence of shorting the center land to the lead lands when the part is pushed into the solder paste. downloaded from: http:///
ir3505z page 20 of 20 march 17, 2009 package information 16l mlpq (3 x 3 mm body) C ja = 38 o c/w, jc = 3 o c/w data and specifications subject to change without notice. this product will be designed and qualified for the consumer market. qualification standards can be found on irs web site. ir world headquarters: 233 kansas st., el segundo, californi a 90245, usa te l: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact information . www.irf.com downloaded from: http:///

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