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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD1839 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?analog devices, inc., 2002 2 adc, 6 dac, 96 khz, 24-bit - codec features 5 v stereo audio system with 3.3 v tolerant digital interface supports up to 96 khz sample rates 192 khz sample rate available on one dac supports 16-/20-/24-bit word lengths multibit sigma-delta modulators with ?erfect differential linearity restoration?for reduced idle tones and noise floor data directed scrambling dacs?east sensitive to jitter single-ended output adcs: ?5 db thd + n, 105 db snr, and dynamic range dacs: ?2 db thd + n, 108 db snr, and dynamic range on-chip volume controls per channel with 1024 step linear scale dac and adc software controllable clickless mutes digital de-emphasis processing supports 256 f s , 512 f s, and 768 f s master mode clocks power-down mode plus soft power-down mode flexible serial data port with right-justified, left- justified, i 2 s compatible, and dsp serial port modes tdm interface mode supports 8 in/8 out using a single sharc sport 52-lead mqfp plastic package applications dvd video and audio players home theatre systems automotive audio systems audio/visual receivers digital audio effects processors functional block diagram outl1 control port clock filtd filtr adclp adcln adcrp adcrn dlrclk dbclk dsdata1 dsdata2 dsdata3 dauxdata mclk asdata abclk alrclk odvdd dvdd av d d av d d dvdd a gnd dgnd cin clatch cclk cout digital filter pd / rst m /s - adc volu me serial data i/o port digital filter - dac v ref outr1 volu me outl2 volu me digital filter - dac outr2 volu me outl3 volu me digital filter - dac outr3 volu me digital filter - adc aauxda ta 3 AD1839 a gnd a gnd a gnd dgnd product overview the AD1839 is a high performance single-chip codec featuring three stereo dacs and one stereo adc. each dac comprises a high performance digital interpolation filter, a multibit sigma-d elta modulator featuring analog devices?patented technology, ( continued on page 11 ) sharc is a registered trademark of analog devices, inc.
rev. a e2e AD1839especifications test conditions supply voltages (av dd , dv dd ) . . . . . . . . . . . . . . . . . . . . . . . 5.0 v ambient temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 ? ? ?
rev. a e3e AD1839 parameter min typ max unit adc decimation filter, 96 khz * pass band 43.54 khz pass-band ripple
rev. a e4e AD1839 timing specifications parameter min m ax unit comments master clock and reset t mh mclk high 15 ns t ml mclk low 15 ns t pdr pd rst spprt p p ds dts tr d dt r s ts tr t r t t d td ts tts tr dsrprt ms d d d d d d
rev. a e5e AD1839 parameter min max unit comments tdm256 mode (master) t tbd bclk delay 20 ns from mclk rising t fsd fstdm delay 5 ns from bclk rising t tabd asdata delay 10 ns from bclk rising t tdds dsdata1 setup 15 ns to bclk falling t tddh dsdata1 hold 15 ns from bclk falling tdm256 mode (slave) f ab bclk frequency 256 pd rst t
rev. a AD1839 e6e absolute maximum ratings * (t a = 25
rev. a AD1839 e7e pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 agnd avdd outr2 nc outl2 nc outr1 nc outl1 nc pd / rst cin clatch dvdd nc outl3 dgnd 52 51 50 49 48 47 46 45 44 43 42 41 40 filtd filtr agnd dauxdata agnd avdd adcln adclp adcrn adcrp agnd dgnd cclk cout asdata odvdd mclk alrclk abclk aauxdata3 dsdata3 dsdata2 dsdata1 AD1839 top view (not to scale ) nc outr3 nc nc nc agnd agnd dlrclk dbclk 27 28 29 30 31 32 33 34 35 36 37 38 39 m /s dvdd avdd 14 15 16 17 18 19 20 21 22 23 24 25 26 pin function descriptions input/ pin no. mnemonic output description 1, 39 dvdd digital power supply. connect to digital 5 v supply. 2c latch i latch input for control data 3 cin i serial control input 4 pd rst pdr d t d tr dr dd ps td r m s dmss ddt dd dr dr d d dd d dsdt ddr dt dd d r dr m m ddd ddps sdt dsd t d d
rev. a AD1839etypical performance characteristics e8e frequency e normalized to f s 05 magnitude e db 10 e150 15 e100 e50 0 tpc 1. adc composite filter response frequency e hz e30 020 5 magnitude e db 10 15 e25 e20 e15 e10 e5 0 5 tpc 2. adc high-pass filter response, f s = 48 khz frequency e normalized to f s e150 0 2.0 0.5 magnitude e db 1.0 1.5 0 e100 e50 tpc 3. adc composite filter response (pass-band section) frequency e hz e30 020 5 magnitude e db 10 15 e25 e20 e15 e10 e5 0 5 tpc 4. adc high-pass filter response, f s = 96 khz khz 0 e50 e150 db e100 0 200 50 100 150 tpc 5. dac composite filter response, f s = 48 khz khz 0 e50 e150 db e100 0 200 50 100 150 tpc 6. dac composite filter response, f s = 96 khz
rev. a e9e AD1839 khz 0 e50 0 200 50 db 100 150 e100 e150 tpc 7. dac composite filter response, f s = 192 khz khz 0.1 0.05 e0.1 020 5 db 10 15 0 e0.05 tpc 8. dac composite filter response, f s = 48 khz (pass-band section) khz 0.2 0.1 e0.2 050 10 db 20 30 40 0 e0.1 tpc 9. dac composite filter response, f s = 96 khz (pass-band section) khz 0.1 0.05 e0.1 0 100 20 db 40 60 80 0 e0.05 tpc 10. dac composite filter response, f s = 192 khz (pass-band section)
rev. a AD1839 e10e definitions dynamic range the ratio of a full-scale input signal to the integrated input noise in the pass band (20 hz to 20 khz), expressed in decibels. dy namic range is measured with a e60 db input signal and is equal to (s/[thd + n]) +60 db. note that spurious harmonics are below the noise with a e60 db input, so the noise level es tablishes the dynamic range. the dynamic range is specified with and without an a-weight filter applied. signal to (total harmonic distortion + noise) [s/(thd + n)] the ratio of the root-mean-square (rms) value of the fundamental input signal to the rms sum of all other spectral components in the pass band, expressed in decibels. pass band the region of the frequency spectrum unaffected by the attenu- ation of the digital decimator?s filter. pass-band ripple the peak-to-peak variation in amplitude response from equal- amplitude input signal frequencies within the pass band, expressed in decibels. stop band the region of the frequency spectrum attenuated by the digital decimator?s filter to the degree specified by stop-band attenuation. gain error with identical near full-scale inputs, the ratio of actual output to expected output, expressed as a percentage. interchannel gain mismatch with identical near full-scale inputs, the ratio of outputs of the two stereo channels, expressed in decibels. gain drift change in response to a near full-scale input with a change in temperature, expressed as parts-per-million (ppm) per
rev. a AD1839 e11e ( continued from page 1 ) and a continuous-time voltage out analog section. each dac has independent volume control and clickless mute functions. the adc comprises two 24-bit conversion channels with m ultibit sigma-delta modulators and decimation filters. the AD1839 also contains an on-chip reference with a nominal value of 2.25 v. the AD1839 contains a flexible serial interface that allows for glueless connection to a variety of dsp chips, aes/ebu receiv ers, and sample rate converters. the AD1839 can be configured in left-justified, right-justified, i 2 s, or dsp compatible serial modes. control of the AD1839 is achieved by means of an spi compatible serial port. while the AD1839 can be operated from a single 5 v supply, it also features a separate supply pin for its digital interface that allows the device to be interfaced to other devices using 3.3 v power supplies. the AD1839 is available in a 52-lead mqfp package and is specified for the industrial temperature range of e40?c to + 85?c. functional overview adcs there are two adc channels in the AD1839, configured as a stereo pair. each adc has fully differential inputs. the adc section can operate at a sample rate of up to 96 khz. the adcs include on-board digital decimation filters with 120 db stop- band attenuation and linear phase response, operating at an oversam pling ratio of 128 (for 48 khz operation) or 64 (for 96 khz operation). adc peak level information for each adc may be read from the adc peak 0 and adc peak 1 registers. the data is sup plied as a 6-bit word with a maximum range of 0 db to e63 db and a resolution of 1 db. the registers will hold peak information until read; after reading, the registers are reset so that new peak information can be acquired. refer to the register description for details of the format. the two adc channels have a common serial bit clock and a left-right framing clock. the clock sig nals are all synchronous with the sample rate. the adc digital pins, abclk and alrclk, can be set to operate as inputs or outputs by connecting the m s dddddw dw d tdd d drd tdm dd dtdd d t d r
rev. a AD1839 e12e reset and power-down pd rst pd rst d t rd sp psr tds t ? ? ? ? ?
rev. a AD1839 e13e the dac serial data input mode defaults to i 2 s. by changing bits 5, 6, and 7 in dac control register 1, the mode can be changed to rj, dsp, lj, or packed mode 256. the word width defaults to 24 bits but can be changed by repro gramming bits 3 and 4 in dac control register 1. packed modes the AD1839 has a packed mode that allows a dsp or other controller to write to all dacs and read all adcs using one input data pin and one output data pin. packed mode 256 re fers to the number of bclks in each frame. the lrclk is low while data from a left channel dac or adc is on the data pin, and high while data from a right channel dac or adc is on the data pin. dac data is applied on the dsdata1 pin, and adc data is available on the asdata pin. figures 7e10 show the timing for the packed mode. packed mode is only available for 48 khz (based on mclk = 12.288 mhz), and when the m s tdmm dd d srdsp srdsp t ttdm w mdr rd wr d ttdm m sddddd stdm d stdm sr s mmm r sdt r sdt r sdt r sdt t rt t rt t rt ms ms ms ms ms ms ms ms s s s s s s s s tstdmdtsttspr smdtsttspr rtstdmdstmrtspr dspmdtsttspr s ts dspmddstdt rrmprtst s ptrdspmdws s rsrm rtmprtdrstmd ssm
rev. a AD1839 e14e t als abclk alrclk asdata lef t-justified mode asdata right-ju stified mode lsb asdata i 2 s-justified mode t abh t abp t abl t ads msb msb-1 t adh t ads msb t adh t ads t ads t adh t adh msb t alh figure 5. adc serial mode timing t dls dbclk dlrclk dsdata lef t-justified mode dsdata right-ju stified mode lsb dsdata i 2 s-justified mode t dbh t dbp t dbl t dds msb msb-1 t ddh t dds msb t ddh t dds t dds t ddh t ddh msb t dlh figure 6. dac serial mode timing
rev. a AD1839 e15e lrclk bclk adc data slot 1 left slot 2 slot 5 right slot 6 msb msbe1 msbe2 32 bclks 256 bclks slot 3 slot 4 slot 7 slot 8 figure 7. adc packed mode 256 lrclk bclk dac data slot 1 left 1 slot 5 right 1 msb msbe1 msbe2 32 bclks 256 bclks slot 2 left 2 slot 3 left 3 slot 4 slot 6 right 2 slot 7 right 3 slot 8 figure 8. dac packed mode 256 t als abclk alrclk asdata t abh t abp t abl t ads msb msb-1 t adh t alh t abdd figure 9. adc packed mode timing t dls dbclk dlrclk dsdata t dbh t dbp t dbl t dds msb msb-1 t ddh t dlh figure 10. dac packed mode timing
rev. a AD1839 e16e table ii. pin function changes in auxiliary mode pin name i 2 s mode aux mode asdata (o) i 2 s data out, internal adc tdm data out to sharc dsdata1 (i) i 2 s data in, internal dac1 tdm data in from sharc dsdata2 (i)/aauxdata1 (i) i 2 s data in, internal dac2 aux-i 2 s data in 1 (from ext. adc) dsdata3 (i)/aauxdata2 (i) i 2 s data in, internal dac3 aux-i 2 s data in 2 (from ext. adc) aauxdata3 (i) not connected aux-i 2 s data in 3 (from ext. adc) alrclk (o) lrclk for adc tdm frame sync out to sharc (fstdm) abclk (o) bclk for adc tdm bclk out to sharc dlrclk (i)/auxlrclk(i/o) lrclk in/out internal dacs aux lrclk in/out. driven by ext. lrclk from adc in slave mode. in master mode, driven by mclk/512. dbclk (i)/auxbclk(i/o) bclk in/out internal dacs aux bclk in/out. driven by ext. bclk from adc in slave mode. in master mode, driven by mclk/8. dauxdata(o) not connected aux-i 2 s data out (to ext. dac) fstdm internal adc l1 aux_adc l2 aux_adc l3 aux_adc l4 internal adc r1 aux_adc r2 aux_adc r3 aux_adc r4 internal dac l1 internal dac l2 internal dac l3 internal dac r1 internal dac r2 internal dac r3 msb tdm 1st ch left right i 2 s e msb right i 2 s e msb left bclk tdm asdata1 tdm (out) asdata dsdata1 tdm (in) dsdata1 aux lrclk i 2 s (from aux adc #1) aux bclk i 2 s (from aux adc #1) aauxdata1 (in) (from aux adc #1) aauxdata2 (in) (from aux adc #2) aauxdata3 (in) (from aux adc #3) aux bclk frequency is 64 frame rate; tdm bclk frequency is 256 frame rate. tdm interface aux e i 2 s in terface msb tdm 8th ch 32 32 msb tdm 1st ch msb tdm 8th ch i 2 s e msb right i 2 s e msb left i 2 s e msb right i 2 s e msb left aux dac l4 aux dac r4 figure 11. aux mode timing
rev. a AD1839 e17e 30mhz 12.288mhz sharc is always running in slave mode (interrupt-driven). fsync-tdm (rfs) rxclk rxdata tfs (nc) txclk txdata asdata fstdm bclk dsdata1 lrclk bclk data mclk adc #1 slave sharc AD1839 master mclk dsdata3/aauxdata2 dsdata2/aauxdata1 dlrclk/auxlrclk lrclk bclk data mclk adc #2 slave lrclk bclk data mclk adc #1 slave aauxdata3 dbclk/auxbclk lrclk bclk data mclk dac #1 slave dauxdata figure 12. aux mode connection to sharc (master mode) 30mhz 12.288mhz sharc is always running in slave mode (interrupt-driven). fsync-tdm (rfs) rxclk rxdata tfs (nc) txclk txdata asdata fstdm bclk dsdata1 lrclk bclk data mclk adc #1 slave sharc AD1839 slave mclk dsdata3/aauxdata2 dsdata2/aauxdata1 dlrclk/auxlrclk lrclk bclk data mclk adc #2 slave lrclk bclk data mclk adc #1 master aauxdata3 dbclk/auxbclk lrclk bclk data mclk dac #1 slave dauxdata figure 13. aux mode connection to sharc (slave mode)
rev. a AD1839 e18e control/status registers the AD1839 has 13 control registers, 11 of which are used to set the operating mode of the part. the other two registers, adc peak 0 and adc peak 1, are read-only and should not be pro grammed. each of the registers is 10 bits wide with the exception of the adc peak reading registers that are six bits wide. writing to a control register requires a 16-bit data frame to be transmitted. bits 15 to 12 are the address bits of the re quired register. bit 11 is a read/write bit. bit 10 is reserved and should always be programmed to 0. bits 9 to 0 contain the 10-bit value that is to be written to the register or, in the case of a read opera tion, the 10-bit register contents. figure 3 shows the format of the spi read and write opera tion. dac control registers the AD1839 register map has eight registers that are used to con trol the functionality of the dac section of the part. the function of the bits in these registers is discussed below. sample rate these bits control the sample rate of the dacs. based on a 24.576 mhz imclk, sample rates of 48 khz, 96 khz, and 192 khz are available. the mclk scaling bits in adc con trol iii should be programmed appropriately, based on the master clock frequency. power-down/reset this bit controls the power-down status of the dac section. by default, normal mode is selected, but by setting this bit, the digital section of the dac stage can be put into a low power mode, thus reducing the digital current. the analog output section of the dac stage is not powered down. dac data-word width these two bits set the word width of the dac data. compact disc (cd) compatibility may require 16 bits, but many modern digital audio formats require 24-bit sample resolution. dac data format the AD1839 serial data interface can be configured to be com patible with a choice of popular interface formats, including i 2 s, lj, rj, or dsp modes. details of these interface modes are given in the serial data port section of this data sheet. de-emphasis the AD1839 provides built-in de-emphasis filtering for the three standard sample rates of 32.0 khz, 44.1 khz, and 48 khz. mute dac each of the six dacs in the AD1839 has its own independent mute control. setting the appropriate bit will mute the dac out put. the AD1839 uses a clickless mute function that at tenu ates the output to approximately e100 db over a number of cycles. stereo replicate setting this bit copies the digital data sent to the stereo pair dac1 to the three other stereo dacs in the system. this allows all three stereo dacs to be driven by one digital data stream. note that in this mode, dac data sent to the other dacs is ignored. dac volume control each dac in the AD1839 has its own independent volume control. the volume of each dac can be adjusted in 1024 linear steps by programming the appropriate register. the de fault value for this register is 1023, which provides no attenua tion, i.e., full volume. adc control registers the AD1839 register map has five registers that are used to control the functionality and read the status of the adcs. the function of the bits in each of these registers is discussed below. adc peak level these two registers store the peak adc result from each channel when the adc peak readback function is enabled. the peak result is stored as a 6-bit number from 0 db to e63 db in 1 db steps. the value contained in the register is reset once it has been read, allowing for continuous level adjustment as required. note that the adc peak level registers use the six most sign ificant bits in the register to store the results. sample rate this bit controls the sample rate of the adcs. based on a 24.576 mhz imclk, sample rates of 48 khz and 96 khz are available. the mclk scaling bits in adc control iii should be programmed appropriately based on the master clock fre quency. adc power-down this bit controls the power-down status of the adc section and operates in a similar manner to the dac power-down. high-pass filter the adc signal path has a digital high-pass filter. enabling this filter will remove the effect of any dc offset in the analog input signal from the digital output codes. dither enabling the dither function will add a small amount of random charge to the sampling capacitors on the adc inputs. this will eliminate the effect of any idle tones that could occur if there were no input signal present. adc data-word width these two bits set the word width of the adc data. adc data format the AD1839 serial data interface can be configured to be co mpatible with a choice of popular interface formats, including i 2 s, lj, rj, or dsp modes. master/slave auxiliary mode when the AD1839 is operating in the auxiliary mode, the auxil iary adc control pins, auxbclk and auxlrclk, that connect to the external adcs can be set to operate as a master or slave. if the pins are set in slave mode, one of the external adcs should provide the lrclk and bclk signals. adc peak readback setting this bit enables adc peak reading. see the adc section for more information.
rev. a AD1839 e19e table iii. control register map register register reset address name description type width setting (hex) 0000 dacctrl1 dac control 1 r/ w dtr d r w d d r w d dr r w d d r w d dr r w d d r w d dr r w rs r r w r rs r r w r dp dp r dp drp r dtr d r w dtr d r w dtr d r w r r r w r t d t dd dd pd r w w w w w ww w w w w w
rev. a AD1839 e20e table viii. adc control i function adc sample address r/ w w w w w w w w w w ww w w w w w w w w w w w w w w w
rev. a AD1839 e21e 5.76k 100pf npo a udio input 600z + 47 f 5.76k 120pf npo vref 5.76k 5.76k vref 750k 237 1nf npo 237 1nf npo 100pf npo adcxp adcxn op275 op275 figure 14. typical adc input filter circuit 3.01k 11k 270pf npo 560pf npo 68pf npo 11k 150pf npo 15k 5.62k 5.62k 604 2n2f npo v bias (2.25v) out x a udio output op275 figure 15. typical dac output filter circuit
rev. a AD1839 e22e outline dimensions 52-lead plastic quad flatpack [mqfp] (s-52) dimensions shown in millimeters seating plane view a 0.23 0.11 2.45 max 1.03 0.88 0.73 top view (pins down) 1 39 40 13 14 27 26 52 pin 1 0.65 bsc 14.15 13.90 sq 13.65 7.80 ref 10.20 10.00 sq 9.80 0.38 0.22 view a rotated 90 ccw 7 0 2.10 2.00 1.95 0.10 min coplanarity compliant to jedec standards mo-112-ac-1 revision history location page 10/02?data sheet changed from rev. 0 to rev. a. changes to functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 changes to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 changes to functional overview section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 change to figure 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 changes to outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
e23e
e24e c02955e0e10/02(a) printed in u.s.a.

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