View AOZ5516QI_9125848.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. 1.0 june 2019 www.aosmd.com page 1 of 16 AOZ5516QI high-current, high-performance drmos power module general description the AOZ5516QI is a high ef ficiency synchronous buck power stage module consisting of two asymmetrical mosfets and an integrated driver. the mosfets are individually optimized for operation in the synchronous buck configuration. the high-side mosfet is optimized to achieve low capacitance and gate charge for fast switching with low duty cycle operation. the low-side mosfet has ultra low on resistance to minimize conduction loss. the compact 5mm x 5mm qfn package is optimally chosen and designed to minimize parasitic inductance for minimal emi signature. the AOZ5516QI uses pwm and/or fccm input for accurate control of the power mosfets switching activities, is compatible with 5v (cmos) logic and supports tri-state pwm. a number of features are provided making the AOZ5516QI a highly versatile power module . the bootstrap diode is integrated in the driver. the low-side mosfet can be driven into diode emulation mode to provide asynchronous operation and improve light-load performance . the pin-out is also optimized for low parasitics, keeping thei r effects to a minimum . features ? 4.5v to 25v power supply range ? 4.5v to 5.5v driver supply range ? 55a continuous output current - up to 80a with 10ms on pulse - up to 120a with 10us on pulse ? up to 2mhz switching operation ? 5v pwm / tri-state input compatible ? under-voltage lockout protection ? fccm pin control for shutdown / diode emulation / ccm operation ? standard 5mm x5mm qfn - 31l package applications ? notebook computers ? memory and graphic cards ? vrms for motherboards ? point of load dc/dc converters ? video gaming console typical application circuit hs driver vin boot c boot c in vswh l1 vout pwm c out gl vcc pgnd pgnd 5v pwm controller driver logic and delay ls driver c pvcc 4.5v ~ 25v fccm pvcc c vcc phase downloaded from: http:///
AOZ5516QI rev. 1.0 june 2019 www.aosmd.com page 2 of 16 ordering information aos green products use reduced levels of halogens, and are also rohs compliant. please visit www.aosmd.com/medi a/aosgreenpolicy.pdf for additional information. pin configuration qfn5x5-31l (top view) part number junction temperature range package environmental AOZ5516QI -40c to +150c qfn5x5-31l rohs 31 30 29 28 27 25 24 1 2 23 3 pwm 22 4 pgnd 21 5 10 11 12 13 14 15 fccm vcc nc phase vin vin vin pgnd pgnd pgnd pgnd vswh vswh vswh vswh vswh gl pgnd pvcc nc nc vin gl 67 8 boot vin nc 20 19 1817 16 vswh vswh vswh vswh 9 26 pgnd vswh vswh downloaded from: http:///
AOZ5516QI rev. 1.0 june 2019 www.aosmd.com page 3 of 16 pin description pin number pin name pin function 1p w m pwm input signal from the controller ic. this input is compatible with 5v and tri-state logic level. 2 fccm continuous conduction mode of opera tion is allowed when fccm = high. discontinuous mode is allowed and diode emul ation mode is active when fccm = low. high impedance on the input of fccm will sh utdown both high-side and low-side mosfets. 3v c c 5v bias for internal logic blocks. ensure to position a 1f mlcc di rectly between vcc and pgnd (pin 28). 4 nc internally connected to pgnd paddle. it can be left floating (no connect) or tied to pgnd. 5b o o t high-side mosfet gate driver supply rail. connect a 100nf ceramic capacitor between boot and the phase (pin 7). 6 nc internally connected to vin paddle. it can be left floating (no connect) or tied to vin. 7 phase this pin is dedicated for bootstrap capacitor ac return path connection from boot (pin 5). 8, 9, 10, 11 vin power stage high voltage i nput (drain connection of high-side mosfet). 12, 13, 14, 15 pgnd power ground pin for power stage (source connection of low-side mosfet). 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26 vswh switching node connected to the source of high-side mosfet and the drain of low-side mosfet. these pins are used for zero cross dete ction and anti-overlap control as well as main inductor terminal. 27 gl low-side mosfet gate connection. this is for test purposes only. 28 pgnd power ground pin for high-side and low-side mosfet gate drivers. ensure to connect 1f directly between pgnd and pvcc (pin 29). 29 pvcc 5v power rail for high-side and low-side mosfet drivers. ensure to position a 1f mlcc directly between pvcc and pgnd (pin 28). 30, 31 nc no connect downloaded from: http:///
AOZ5516QI rev. 1.0 june 2019 www.aosmd.com page 4 of 16 functional block diagram vswh vcc zcd pvcc gl pgnd dcm/ccm detect and tri-state ref/bias uvlo level shifter hs gate driver sequencing and propagation delay control b oot hs control logic driver logic hs gate phase check ls min on zcd detect ls pwm tri-state logic pwm tri-state ls gate ls gate driver fccm pwm vin boot vcc phase pvcc vcc downloaded from: http:///
AOZ5516QI rev. 1.0 june 2019 www.aosmd.com page 5 of 16 absolute maximum ratings exceeding the absolute maximum ratings may damage the device. notes: 1. peak voltages can be applied for 10ns per switching cycle. 2. peak voltages can be appli ed for 20ns per switching cycle. 3. devices are inherently esd sens itive, handling precautions are required. human body model rating: 1.5 ? in series with 100pf. recommended oper ating conditions the device is not guaranteed to operate beyond the maximum recommended op erating conditions. parameter rating low voltage supply (vcc, pvcc) -0.3v to 7v high voltage supply (vin) -0.3v to 30v control inputs (pwm, fccm) -0.3v to (vcc+0.3v) bootstrap voltage dc (boot-pgnd) -0.3v to 35v bootstrap voltage transient (1) (boot-pgnd) -8v to 40v bootstrap voltage dc (boot-phase/vswh) -0.3v to 7v boot voltage transient (1) (boot-phase/vswh) -0.3v to 9v switch node voltage dc (phase/vswh) -0.3v to 30v switch node voltage transient (1) (phase/vswh) -8v to 38v low-side gate voltage dc (gl) (pgnd-0.3v) to (pvcc+0.3v) low-side gate voltage tran- sient (2) (gl) (pgnd-2.5v) to (pvcc+0.3v) vswh current dc 55a vswh current 10ms pulse 80a vswh current 10us pulse 120a storage temperature (t s ) -65c to +150c max junction temperature (t j ) 150c esd rating (3) 2kv parameter rating high voltage supply (vin) 4.5v to 25v low voltage / mosfet driver supply (vcc, pvcc) 4.5v to 5.5v control inputs (pwm, fccm) 0v to vcc operating frequency 200khz to 2mhz downloaded from: http:///
AOZ5516QI rev. 1.0 june 2019 www.aosmd.com page 6 of 16 electrical characteristics (4) tj = 0c to 150c, vin = 12v, vout = 1v, pvcc = vcc = 5v, unless otherwise specified. min/max values are guaranteed by test, design or statistical correlation. notes: 4. all voltages are specified with re spect to the corresponding agnd pin. 5. characterization value . not tested in production. 6. gh is an internal pin. symbol parameter conditions min. typ. max. units general v in power stage power supply 4.5 25 v v cc low voltage bias supply pvcc = vcc 4.5 5.5 v r ? jc (4) thermal resistance reference to high-side mosfet tem- perature rise 2.5 c / w r ? ja (4) freq = 300khz. aos demo board. 12.5 c / w input supply and uvlo v cc_uvlo undervoltage lockout vcc rising 3.5 3.9 v v cc_hyst vcc hysteresis 400 mv i vcc control circuit bias current fccm = floating pwm = floating 3 a fccm = 5v pwm = floating 170 a fccm = 0v pwm = floating 180 a pwm input v pwmh logic high input voltage 4.2 v v pwml logic low input voltage 0.72 v i pwm_src pwm pin input current pwm = 0v -200 a i pwm_snk pwm = 5v 200 a v pwm_tri pwm tri-state window 1.6 3.4 v fccm input v fccm_h logic high input voltage 3.9 v v fccm_l logic low input voltage 1.1 v i fccm_src fccm pin input current fccm = 0v -50 a i fccm_snk fccm = 5v 50 a v fccm_tri fccm tri-state window 2.0 3.0 v t ps4_exit ps4 exit latency 51 5 s gate driver timings t pdlu pwm to hs gate pwm: h ? l, vswh: h ? l3 0 n s t pdll pwm to ls gate pwm: l ? h, gl: h ? l2 5 n s t pdhu ls to hs gate deadtime gl: h ? l, gh (6) : l ? h1 5 n s t pdhl hs to ls gate deadtime vswh: h ? 1v , gl: l ? h1 3 n s t tsshd tri-state shutdown delay pwm: l ? v tri , gl: h ? l and pwm: h ? v tri , vswh: h ? l 150 ns t tsexit tri-state propagation delay pwm: v tri ? h, vswh: l ? h pwm: v tri ? l , gl: l ? h 45 ns t lgmin ls minimum on time fccm = 0v 350 ns downloaded from: http:///
rev. 1.0 june 2019 www.aosmd.com page 7 of 16 AOZ5516QI timing diagrams figure 1. pwm logic input timing diagram figure 2. pwm tri-state hold off and exit timing diagram v pwmh t pdll 90% 1v 1v 90% 1v t pdhu t pdlu t pdhl pwm gl vswh 1v v pwml t tsshd t pts t tsshd t pts t tsshd t pts t tsshd t pts pwm gl gh downloaded from: http:///
rev. 1.0 june 2019 www.aosmd.com page 8 of 16 AOZ5516QI typical performance characteristics t a = 25c, vin = 12v, vout = 1v, pvcc = vcc = 5v, unless otherwise specified. figure 3. efficiency vs. load current figure 4. power loss vs. load current figure 5. pwm threshold vs. temperature figur e 6. fccm input threshold vs. temperature figure 7. uvlo (vcc) threshold vs. temperature figure 8. pwm threshold vs. vcc voltage vin=12v vout=1v f=300khz vin=12v vout=1v f=500khz vin=19v vout=1v f=300khz vin=19v vout=1v f=500khz load current (a) 5 10 15 20 25 30 35 40 efficiency (%) 9492 90 88 86 84 82 80 vin=12v vout=1v f=300khz vin=12v vout=1v f=500khz vin=19v vout=1v f=300khz vin=19v vout=1v f=500khz load current (a) 5 10 15 20 25 30 35 power loss (w) 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 40 pwm voltage (v) temperature (c) -40 -20 0 20 40 60 80 100 120 140 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 pwm high to tri-state logic high threshold pwm low to tri-state logic low threshold shutdown to ccm dcm to shutdown ccm to shutdown shutdown to dcm fccm voltage (v) temperature (c) -40 -20 0 20 40 60 80 100 120 140 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 vcc voltage (v) temperature (c) -40 -20 0 20 40 60 80 100 120 140 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 rising threshold falling threshold 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4 4.25 4.5 4.75 5 5.25 5.5 pwm voltage (v) vvc voltage (v) logic high threshold logic low threshold downloaded from: http:///
rev. 1.0 june 2019 www.aosmd.com page 9 of 16 AOZ5516QI typical performance characteristics t a = 25c, vin = 12v, vout = 1v, pvcc = vcc = 5v, unless otherwise specified. figure 9. high-side mosfet soa figure 10. low-side mosfet soa downloaded from: http:///
AOZ5516QI rev. 1.0 june 2019 www.aosmd.com page 10 of 16 application information AOZ5516QI is a fully integrated power module designed to work over an input voltage range of 4.5v to 25v with a separate 5v supply for gate drive and internal control circuitry. the mosfets are individually optimized for efficient operation on both high-side and low-side for a low duty cycle synchronous buck converter. high current mosfet gate drivers are integrated in the package to minimize parasitic loop inductance for optimum switching efficiency . powering the module and the gate drives an external supply pvcc = 5v is required for driving the mosfets. the mosfets are designed with optimally customized gate thresholds voltages to achieve the most advantageous compromise between high switching speed and minimal power loss. the integrated gate driver is capable of supplying large peak current into the low-side mosfet to achieve fast switching. a ceramic bypass capacitor of 1 ? f or higher is recommended from pvcc (pin 29) to pgnd (pin 28). the control logic supply vcc (pin 3) can be derived from the gate drive supply pvcc (pin 29) through an rc filter to bypass the switching noise (see typi cal application circuit). the boost supply for driving the high-side mosfet is generated by connecting a small capacitor ( 100nf) between the boot (pin 5) and the switching node phase (pin 7). it is recommended that this capacitor c boot should be c onnected to the device across pin 5 and pin 7 as closely as possible. a bootstrap switch is integrated into the device to reduce external component count. an optional resistor r boot in series with c boot between 1 ? to 5 ? can be used to slow down the turn on speed of the high-side mosfet to achieve both short switching time and low vswh switching node spikes at the same time. under-voltage lockout AOZ5516QI starts up to normal operation when vcc rises above the under-voltage lockout (uvlo) threshold voltage. the uvlo release is set at 3.5v typically. since the pwm control signal is provided from an external controller or a digital processor, extra caution must be taken during start up. AOZ5516QI must be powered up before pwm input is applied. normal system operation begins with a soft start sequence by the controller to minimize in-rush current during start up. powering the module with a full duty cycle pwm signal may lead to many undesirable consequences due to excessive power. AOZ5516QI provides some protections such as uvlo and thermal monitor. for system level protection, the pwm controller should monitor the current output and protect the load under all possible operating and transient conditions. input voltage vin AOZ5516QI is rated to operate over a wide input range from 4.5v to 25v. for high current synchronous buck converter applications, large pulse current at high frequency and high current slew rates (di/dt) will be drawn by the module during normal operation. it is strongly recommended to place a bypass capacitor very close to the package leads at the input supply (vin). both x7r or x5r quality surface mount ceramic capacitors are suitable. the high-side mosfet is optimized for fast switching by using a low gate charge (q g ) device. when the module is operated at high duty cycle ratio, conduction loss from the high-side mosfet will be higher. the total power loss for the module is still relatively low but the high-side mosfet higher conduction loss may have higher temperature. the two mosfets have their own exposed pads and pcb copper areas for heat dissipation. it is recommended that worst case junction temperature be measured for both high-side mosfet and low-side mosfet to ensure that they are operating within safe operating area (soa). pwm input AOZ5516QI is compatible with 5v (cmos) pwm logic. refer to figure 1 for pwm logic timing and propagation delays diagram between pwm input and the mosfet gate drives. the pwm is also compatible with tri-state input. when the pwm output from the external pwm controller is in high impedance or not connected, both high-side and low-side mosfets are turned off and vswh is in high impedance state. table 1 show s the thresholds level for high-to-low and low-to-high transitions as well as tri- state window. there is a holdoff delay between the corresponding pwm tri-state signal and the mosfet gate drivers to prevent spurious triggering of tri-state mode which may be caused by noise or pwm signal glitches. the holdoff delay is typically 150ns. table 1. pwm input and tri-state thresholds note: see figure 2 for propagation delays and tri-state window. thresholds ? v pwmh v pwml v trih v tril AOZ5516QI 4.1v 0.7v 1.5v 3.5v downloaded from: http:///
AOZ5516QI rev. 1.0 june 2019 www.aosmd.com page 11 of 16 diode mode emulation of low-side mosfet (fccm) AOZ5516QI can be operated in the diode emulation or pulse skipping mode using fccm (pin 2). this enables the converter to operate in asynchronous mode during start up, light load or under pre-bias conditions. when fccm is high, the module will operate in continuous conduction mode (ccm). the driver logic will use the pwm signal and g enerate both the high-side and low-side complementary gate drive outputs with minimal anti-overlap delays to avoid cross conduction. when fccm is low, the module can operate in discontinuous conduction mode (dcm). the high-side mosfet gate drive output is not affected but low-side mosfet will enter diode emulation mode. see table 2 for the truth table for pwm and fccm inputs. table 2. control logic truth table gate drives AOZ5516QI has an internal high current high speed driver that generates the floating gate driver for the high- side mosfet and a complementary driver for the low- side mosfet. an internal shoot through protection scheme is implemented to ensure that both mosfets cannot be turned on at the same time. the operation of pwm signal transition is illustrated as below. 1) pwm from logic low to logic high when the falling edge of low-side gate driver output gl goes below 1v, the blanking period is activated. after a pre-determined value (t pdhu ), the complementary high- side gate driver output gh is turned on. 2) pwm from logic high to logic low when the falling edge of switching node vswh goes below 1v, the blanking period is activated. after a pre- determined value (t pdhl ), the complementary low-side gate driver output gl is turned on. this mechanism prevents cross conduction across the input bus line vin and pgnd. the anti-overlap circuit monitors the switching node vswh to ensure a smooth transition between the two mosfets under any load transient conditions. fccm pwm gh gl ll l h if i l > 0a l if i l < 0a lhh l hl l h hh h l l tri-state l l h tri-state l l tri-state x l l downloaded from: http:///
rev. 1.0 june 2019 www.aosmd.com page 12 of 16 AOZ5516QI pcb layout guidelines AOZ5516QI is a high current module rated for operation up to 2mhz. this requires high switching speed to keep the switching losses and device temperatures within limits. an integrated gate driver within the package eliminates driver-to-mosfet gate pad parasitic of the package or on pcb. to achieve high switching speeds, high levels of slew rate (dv/dt and di/dt ) will be present throughout the power train which requires careful attention to pcb layout to minimize voltage spikes and other transients. as with any synchronous buck converter layout, the critical requirement is to mini mize the path of the primary switching current loop formed by the high-side mosfet, low-side mosfet, and the input bypass capacitor c in . the pcb design is greatly simplified by the optimization of the AOZ5516QI pin out. the power inputs of vin and pgnd are located adjacent to each other and the input bypass capacitors c in should be placed as close as possible to these pins. the area of the secondary switching loop is formed by low-side mosfet, output inductor l1, and output capacitor c out is the next critical requirement. this requires second layer or inner 1 to be the pgnd plane. vias should then be placed near pgnd pads. while AOZ5516QI is a highly efficient module, it still dissipates a significant amount of heat under high power conditions. special attention is required for thermal design. mosfets in the package are directly attached to individual exposed pads (vin and pgnd) to simplify thermal management. both vin and vswh pads should be attached to large areas of pcb copper. thermal relief pads should be placed to ensure proper heat dissipation to the board. an inner power plane layer dedicated to vin, typically the high voltage system input, is desirable and vias should be provided near the device to connect the vin pads to the power plane. significant amount of heat can also be dissipated through multiple pgnd pins. a large copper area connected to the pgnd pins in addition to the system gr ound plane through vias will further improve thermal dissipation. as shown on figure. 11, the top most layer of the pcb should comprise of wide and exposed copper area for the primary ac current loop which runs along vin pad originating from the input c apacitors c10, c11, and c12 that are mounted to a large pgnd pad. they serve as thermal relief as heat flows down to the vin exposed pad that fans out to a wider ar ea. adding vias will only help transfer heat to cooler regions of the pcb board through the other layers beneath but serve no purpose to ac activity as all the ac curren t sees the lowest impedance on the top layer only. figure 11. top layer of demo board, vin, vswh and pgnd copper pads as the primary and secondary (complimentary) ac current loops move through vin to vswh and through pgnd to vswh, large positive and negative voltage spikes appear at the vswh terminal which are caused by the large internal di/dt produced by the package parasitic. to minimize the ef fects of this interference at the vswh terminal, at whic h the main inductor l1 is mounted, size just enough for the inductor to physically fit. the goal is to employ the least amount of copper area for this vswh terminal, only enough so the inductor can be securely mounted. to minimize the effects of s witching noise coupling to the rest of the sensitive areas of the pcb, the area directly underneath the designated vswh pad or inductor terminal is voided and the shape of this void is replicated descending down through the rest of the layers. refer to figure 12. figure 12. bottom layer of pcb positioning vias through the landing pattern of the vin and pgnd thermal pads will he lp quickly facilitate the thermal build up and spread the heat much more quickly downloaded from: http:///
rev. 1.0 june 2019 www.aosmd.com page 13 of 16 AOZ5516QI towards the surrounding copper layers descending from the top layer. (see recommended landing pattern and via placement section). the exposed pads dimensional footprint of the 5x5 qfn package is shown on the package dimensions page. for optimal thermal relief, it is recommended to fill the pgnd and vin exposed landing pattern with 10mil diameter vias. 10mil diameter is a commonly used via diameter as it is optimally cost effe ctive based on the tooling bit used in manufacturing. each via is associated with a 20mil diameter keep out. maintain a 5mil clearance (127um) around the inside edge of each exposed pad in case of solder overflow, which could potentially short with the adjacent exposed thermal pad. downloaded from: http:///
AOZ5516QI rev. 1.0 june 2019 www.aosmd.com page 14 of 16 package dimensions, qfn5x5a-31l, ep3_s recommended land pattern unit: mm note controlling dimension is millimeter.converted inch dimensions are not necessarily exact. downloaded from: http:///
rev. 1.0 june 2019 www.aosmd.com page 15 of 16 AOZ5516QI tape and reel drawing, qfn5x5a-31l, ep3_s downloaded from: http:///
rev. 1.0 june 2019 www.aosmd.com page 16 of 16 AOZ5516QI as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provi ded in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system wh ose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. legal disclaimer alpha and omega semiconductor makes no representati ons or warranties with respect to the accuracy or completeness of the information prov ided herein and take s no liabilities for the cons equences of use of such information or any product described herein. alpha and om ega semiconductor reserves the right to make changes to such information at any time without further notice. this document does not constitute the grant of any intellectual property rights or representation of non-infringeme nt of any third partys intellectual property rights. life support policy alpha and omega semiconduct or products are not auth orized for use as critical components in life su pport devices or systems. part marking part number code assembly lot code year code & week code AOZ5516QI (5mm x 5mm qfn) br00 ywlt downloaded from: http:///

▲Up To Search▲

Price & Availability of AOZ5516QI

	To Download AOZ5516QI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .