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ST Microelectronics
STMICROELECTRONICS[STMicroelectronics]
SGS Thomson Microelectronics
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| Part No. |
MK5027 4284 MK5027PLCC52 MK5027DIP
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| OCR Text |
.... This pin can be programmed to behave as output RTS or as programmable IO pin DTR. If configured as RTS, the MK5027 will assert this pin if it has data to send and throughout the transmission of a signal unit. RECEIVE CLOCK. A 1x clock inp... |
| Description |
SS7 SIGNALLING LINK CONTROLLER
From old datasheet system
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| File Size |
181.74K /
19 Page |
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Cypress
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| Part No. |
CY3120J CY3120 3120
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| OCR Text |
...-architecture body ARCHITECTURE behave OF half_adder IS BEGIN sum <= x XOR y; carry <= x AND y; END behave; Structural VHDL (RTL) While all of the design methodologies described thus far are high-level entry methods, structural VHDL provide... |
| Description |
Warp2VHDL Compiler for CPLDs
From old datasheet system
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| File Size |
121.82K /
6 Page |
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Cypress Semiconductor Corp.
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| Part No. |
CY7C1347B 7C1347B
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| OCR Text |
.../O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. Advance Input signal,... |
| Description |
128K x 36 Synchronous-Pipelined Cache RAM(128K x 36同步流水线式高速缓冲存储器 RAM)
From old datasheet system
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| File Size |
347.39K /
17 Page |
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it Online |
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Cypress Semiconductor Corp.
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| Part No. |
CY7C1347 7C1347
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| OCR Text |
.../O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. Advance Input signal,... |
| Description |
128K x 36 Synchronous-Pipelined Cache RAM(128K x 36同步流水线式高速缓冲存储器 RAM)
From old datasheet system
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| File Size |
348.83K /
18 Page |
View
it Online |
Download Datasheet |
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Cypress Semiconductor, Corp.
Cypress Semiconductor Corp.
CYPRESS[Cypress Semiconductor]
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| Part No. |
CY7C1350F CY7C1350F-100AC CY7C1350F-100AI CY7C1350F-100BGI CY7C1350F-100BGC CY7C1350F-225AI CY7C1350F-225BGI CY7C1350F-250BGI CY7C1350F-133AC CY7C1350F-133AI CY7C1350F-133BGC CY7C1350F-133BGI CY7C1350F-166AC CY7C1350F-166AI CY7C1350F-166BGC CY7C1350F-166BGI CY7C1350F-200AC CY7C1350F-200AI CY7C1350F-200BGC CY7C1350F-200BGI CY7C1350F-225AC CY7C1350F-225BGC CY7C1350F-250AC CY7C1350F-250AI CY7C1350F-250BGC
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| OCR Text |
...OW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected... |
| Description |
4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture 128K X 36 ZBT SRAM, 2.8 ns, PBGA119
4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture 128K X 36 ZBT SRAM, 4.5 ns, PQFP100
4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture 128K X 36 ZBT SRAM, 2.6 ns, PBGA119
4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture 128K X 36 ZBT SRAM, 2.6 ns, PQFP100
CABLE ASSEMBLY; LEAD-FREE SOLDER; SMA MALE TO SMA MALE; 50 OHM, PE-SR047FL (.047" RE-SHAPABLE) 128K X 36 ZBT SRAM, 3.5 ns, PQFP100
4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture 128K X 36 ZBT SRAM, 2.8 ns, PQFP100
4-Mb (128K x 36) Pipelined SRAM with Nobl(TM) Architecture
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| File Size |
391.04K /
16 Page |
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Cypress Semiconductor Corp.
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| Part No. |
CY7C1350 7C1350
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| OCR Text |
...OW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected... |
| Description |
128Kx36 Pipelined SRAM with NoBL Architecture(带NoBL结构28Kx36流水线式 SRAM) 128K × 36至流水线与总线延迟静态存储器体系结构（带总线延迟结构28K × 36至流水线式的SRAM
128Kx36 Pipelined SRAM with NoBL Architecture(B>NoBL结构28Kx36流水线式 SRAM)
From old datasheet system
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| File Size |
185.89K /
13 Page |
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it Online |
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