| |
|
 |
Cypress
|
| Part No. |
CY7C1325 7C1325
|
| OCR Text |
.../O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. Snooze Input. Active HIGH asynchronous. When HIGH, the device enters a low-power standby mode in which all other... |
| Description |
256K x 18 Synchronous3.3V Cache RAM
From old datasheet system
|
| File Size |
264.13K /
15 Page |
 View
it Online |
Download Datasheet
|
| |
|
|
Cypress
|
| Part No. |
CY7C1365V25 CY7C1363V25 CY7C1361V25 7C1361V
|
| OCR Text |
.../O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. Advance Input signal,... |
| Description |
256K x 36/256K x 32/512K x 18 Flowthrough SRAM
From old datasheet system
|
| File Size |
408.99K /
30 Page |
View
it Online |
Download Datasheet |
| |
|
|
Cypress Semiconductor Corp.
|
| Part No. |
CY7C1365V25
|
| OCR Text |
...o pins. when low, the i/o pins behave as outputs. when deasserted high, i/o pins are three-stated, and act as input data pins. oe is masked during the first clock of a read cycle when emerging from a deselected state. 83 83 adv input-... |
| Description |
512K x 18 Flowthrough SRAM(512K x 18 流通式 SRAM) 直通为512k × 18的SRAM（为512k × 18流通式的SRAM
|
| File Size |
414.91K /
30 Page |
View
it Online |
Download Datasheet |
|
Price and Availability
|
