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Sharp, Corp.
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| Part No. |
LH540225
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| OCR Text |
...ables 1 and 2.) also, the flags behave differently for a short time after a retransmit operation. otherwise, the re- transmit facility is available during standalone opera- tion, in either idt-compatible operating mode or enhanced operating... |
| Description |
512 x 18 / 1024 x 18 Synchronous FIFO 512 ×一千?二十四分之一十八× 18同步FIFO
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| File Size |
430.56K /
48 Page |
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it Online |
Download Datasheet
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Cypress Semiconductor Corp.
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| Part No. |
CY7C1365V25
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| OCR Text |
...o pins. when low, the i/o pins behave as outputs. when deasserted high, i/o pins are three-stated, and act as input data pins. oe is masked during the first clock of a read cycle when emerging from a deselected state. 83 83 adv input-... |
| Description |
512K x 18 Flowthrough SRAM(512K x 18 流通式 SRAM) 直通为512k × 18的SRAM（为512k × 18流通式的SRAM
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| File Size |
414.91K /
30 Page |
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it Online |
Download Datasheet |
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ST Microelectronics
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| Part No. |
MK50H27DIP
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| OCR Text |
.... this pin can be programmed to behave as output rts or as programmable io pin dtr. if configured as rts, the mk50h27 will assert this pin if it has data to send and throughout the transmission of a signal unit. rclk 27 [30] i receive clock... |
| Description |
Signalling System 7 Link Controller
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| File Size |
418.71K /
56 Page |
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it Online |
Download Datasheet |
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Cypress Semiconductor, Corp.
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| Part No. |
CY7C1352-133AI
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| OCR Text |
...w, the i/o pins are allowed to behave as outputs. when deasserted high, i/o pins are three-stated, and act as input data pins. oe is masked during the data portion of a write sequence, during the first clock when emerging from a deselec... |
| Description |
x18 Fast Synchronous SRAM x18快速同步SRAM
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| File Size |
194.23K /
13 Page |
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it Online |
Download Datasheet |
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Cypress Semiconductor Corp.
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| Part No. |
CY7C1353G-117AXC
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| OCR Text |
...w, the i/o pins are allowed to behave as outputs. when deasserted high, i/o pins are tri-stated, and act as input data pins. oe is masked during the data portion of a write seq uence, during the first clock when emerging from a deselec... |
| Description |
4-Mbit (256K x 18) Flow-through SRAM with NoBLArchitecture 4兆位56 × 18）流通过总线延迟⑩建筑的SRAM
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| File Size |
217.30K /
13 Page |
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it Online |
Download Datasheet |
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Cypress
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| Part No. |
CY7C1368B-166AC CY7C1368B-166AJC
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| OCR Text |
.../o pins. when low, the i/o pins behave as outputs. when deasserted high, i/o pins are tri-stated, and act as input data pins. oe is masked during the first clock of a read cycle when emerging from a deselected state. adv 83 input- synch... |
| Description |
9-Mb (256K x 32) Pipelined DCD Sync SRAM
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| File Size |
264.62K /
17 Page |
View
it Online |
Download Datasheet |
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Price and Availability
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