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IDT[Integrated Device Technology]
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| Part No. |
IDT5T9070PAI IDT5T9070 IDT5T9070PAI8
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| OCR Text |
...gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize the possibility of runt pulses or be able to tolerate them in down stream circuitry.
DC ELECTRI... |
| Description |
2.5V Single Data Rate 1:10 Clock Buffer TeraBuffer Jr.
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| File Size |
54.57K /
7 Page |
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it Online |
Download Datasheet
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MOTOROLA[Motorola, Inc]
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| Part No. |
MC100ES6226FA MC100ES6226 MC100ES6226D
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| OCR Text |
...utput enable eliminating output runt pulse generation and metastability * Standard 32 lead LQFP package
* Industrial temperature range
Functional Description MC100ES6226 is designed for very skew critical differential clock distribution... |
| Description |
2.5/3.3V Differential LVPECL 1:9 Clock Distribution Buffer and Clock Divider
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| File Size |
274.46K /
12 Page |
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it Online |
Download Datasheet |
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MOTOROLA[Motorola, Inc]
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| Part No. |
MC100ES6254
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| OCR Text |
...utput enable eliminating output runt pulse generation and metastability * Standard 32 lead LQFP package * Industrial temperature range
FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A
Functional Description MC100ES6254 is designed for very sk... |
| Description |
2.5/3.3V Differential LVPECL 2x2 Clock Switch and Fanout Buffer
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| File Size |
382.29K /
12 Page |
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it Online |
Download Datasheet |
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Motorola, Inc.
MOTOROLA[Motorola, Inc]
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| Part No. |
MC100ES7111FA MC100ES7111
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| OCR Text |
...ed internally preventing output runt pulse generation. Outputs are only disabled or enabled when the outputs are already in logic low state (true outputs logic low, inverted outputs logic high). The internal synchronizer eliminates the setu... |
| Description |
LOW VOLTAGE 1:10 DIFFERENTIAL LVDS CLOCK FANOUT BUFFER
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| File Size |
127.05K /
8 Page |
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it Online |
Download Datasheet |
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MOTOROLA[Motorola, Inc]
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| Part No. |
MC100ES8111
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| OCR Text |
...ed internally preventing output runt pulse generation. Outputs are only disabled or enabled when the outputs are already in logic low state (true outputs logic low, inverted outputs logic high). The internal synchronizer eliminates the setu... |
| Description |
Low Voltage 1:10 Differential HSTL Clock Fanout Buffer
Low Voltage 1:10 Differential HSTL Clock Fanout Buffer
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| File Size |
170.53K /
12 Page |
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it Online |
Download Datasheet |
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Price and Availability
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