| |
|
 |
IDT
|
| Part No. |
IDT72T20108 IDT72T2098 IDT72T20128
|
| OCR Text |
...put and output port bus sizing -x20 in to x20 out -x20 in to x10 out -x10 in to x20 out -x10 in to x10 out Auto power down minimizes standby power consumption Master Reset clears entire FIFO Partial Reset clears data, but retains programmab... |
| Description |
2.5 VOLT HIGH-SPEED TeraSync? DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION
|
| File Size |
459.34K /
51 Page |
 View
it Online |
Download Datasheet
|
| |
|
|
Yageo, Corp.
|
| Part No. |
SJ035M1500AZS-1335
|
| OCR Text |
...0 x11 0 x1 00 x20 120 10x12 30 330 x11 10 x11 0 x11 0 10x12 1030 10x1 130 0 x 11 2 x11 0 x1 1000 x20 120 10x1 120 10x12 1030... |
| Description |
CAPACITOR, ALUMINUM ELECTROLYTIC, NON SOLID, POLARIZED, 35 V, 1500 uF, THROUGH HOLE MOUNT RADIAL LEADED
|
| File Size |
192.69K /
3 Page |
View
it Online |
Download Datasheet |
| |
|
|
http://
|
| Part No. |
VSC7216-01
|
| OCR Text |
... 256-pin, 27mm bga package x20/x10 clock gen tx clock endec resetn wsi dual channel align wso tbcd tbcc tbcb tbca 4 10 encode 8b/10b dq td(7:0) c/dd 88 ptxd- ptxd+ rtxd- rtxd+ wsend kchar rtxend ptxend prxd- prxd+ rrxd- rrxd+ rxp/rd l... |
| Description |
Multi-Gigabit Interconnect Chip
|
| File Size |
552.44K /
38 Page |
View
it Online |
Download Datasheet |
| |
|
|
Vitesse Semiconductor Corporation.
|
| Part No. |
VSC7216UC-01
|
| OCR Text |
... 256-pin, 27mm bga package x20/x10 clock gen tx clock endec resetn wsi dual channel align wso tbcd tbcc tbcb tbca 4 10 encode 8b/10b dq td(7:0) c/dd 88 ptxd- ptxd+ rtxd- rtxd+ wsend kchar rtxend ptxend prxd- prxd+ rrxd- rrxd+ rxp/rd l... |
| Description |
Multi-Gigabit Interconnect Chip
|
| File Size |
557.46K /
38 Page |
View
it Online |
Download Datasheet |
| |
|
|
IDT
|
| Part No. |
IDT72T40108 IDT72T4088IDT72T4098 IDT72T4098
|
| OCR Text |
...g -x40 in to x40 out -x40 in to x20 out -x40 in to x10 out -x20 in to x40 out -x10 in to x40 out Auto power down minimizes standby power consumption Master Reset clears entire FIFO Partial Reset clears data, but retains programmable setting... |
| Description |
2.5 VOLT HIGH-SPEED TeraSync? DDR/SDR FIFO 40-BIT CONFIGURATION
2.5 VOLT HIGH-SPEED TeraSync™ DDR FIFO 40-BIT CONFIGURATION
|
| File Size |
456.68K /
52 Page |
View
it Online |
Download Datasheet |
| |
|
|
IDT
|
| Part No. |
IDT72T54242
|
| OCR Text |
x20 DUAL FIFO CONFIGURATIONS 32,768 x 10 x 4/32,768 x 10 x 2 65,536 x 10 x 4/65,536 x 10 x 2 131,072 x 10 x 4/131,072 x 10 x 2
PRELIMINARY IDT72T54242 IDT72T54252 IDT72T54262
FEATURES
*
* * * * * * * * * * * * * * * * *
* *
... |
| Description |
2.5V QUAD/DUAL TeraSync? DDR/SDR FIFO
|
| File Size |
485.94K /
54 Page |
View
it Online |
Download Datasheet |
| |
|
|
IDT
|
| Part No. |
IDT72T51258 IDT72T51268 IDT72T51248
|
| OCR Text |
...OS[1:0]
D[39:0] Data In
x10,x20,x40
Q[39:0] Data Out
x10,x20,x40
FF0/IR0 PAF0 FF1/IR1 PAF1 FF2/IR2 PAF2 FF3/IR3 PAF3 CFF/CIR
EF0/OR0 PAE0 EF1/OR1 PAE1 EF2/OR2 PAE2 EF3/OR3 PAE3 CEF/COR
Read Port Flag Outputs
6159 drw01
... |
| Description |
2.5V MULTI-QUEUE DDR FLOW-CONTROL DEVICES
|
| File Size |
471.07K /
55 Page |
View
it Online |
Download Datasheet |
|
Price and Availability
|
