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Cypress Semiconductor, Corp.
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| Part No. |
CY7C1298H-166AXC CY7C1298H-166AXI
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| OCR Text |
...o pins. when low, the i/o pins behave as outputs. when dea sserted high, i/o pins are tri-stated, and act as input data pins. oe is masked during the first clock of a read cycle when emerging from a deselected state. adv input- synchro... |
| Description |
64K X 18 CACHE SRAM, 3.5 ns, PQFP100 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP-100
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| File Size |
681.02K /
16 Page |
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it Online |
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Cypress Semiconductor, Corp.
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| Part No. |
CY7C1218H-166AXI CY7C1218H-166AXC
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| OCR Text |
...o pins. when low, the i/o pins behave as outputs. when deassert ed high, i/o pins are tri-stated, and act as input data pins. oe is masked during the first clock of a read cycle when emerging from a deselected state. adv input- synchr... |
| Description |
32K X 36 CACHE SRAM, 3.5 ns, PQFP100 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP-100
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| File Size |
683.95K /
16 Page |
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it Online |
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Cypress Semiconductor, Corp.
Cypress Semiconductor Corp.
CYPRESS[Cypress Semiconductor]
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| Part No. |
CY7C1351F CY7C1351F-100AC CY7C1351F-100AI CY7C1351F-100BGC CY7C1351F-100BGI CY7C1351F-117AC CY7C1351F-117AI CY7C1351F-117BGC CY7C1351F-117BGI CY7C1351F-133AC CY7C1351F-133AI CY7C1351F-133BGC CY7C1351F-133BGI CY7C1351F-66AC CY7C1351F-66AI CY7C1351F-66BGC CY7C1351F-66BGI CY7C1351
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| OCR Text |
...OW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected... |
| Description |
4-Mb (128K x 36) Flow-through SRAM with NoBLArchitecture 128K X 36 ZBT SRAM, 7.5 ns, PQFP100
4-Mb (128K x 36) Flow-through SRAM with NoBLArchitecture 128K X 36 ZBT SRAM, 11 ns, PBGA119
4-Mb (128K x 36) Flow-through SRAM with NoBLArchitecture 128K X 36 ZBT SRAM, 8 ns, PQFP100
4-Mb (128K x 36) Flow-through SRAM with NoBLArchitecture 128K X 36 ZBT SRAM, 8 ns, PBGA119
4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture
4-Mb (128K x 36) Flow-through SRAM with NoBL Architecture
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| File Size |
423.97K /
15 Page |
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it Online |
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Atmel
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| Part No. |
AT49SN12804
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| OCR Text |
...chronous reads, the device will behave like a standard asynchronous flash memory. in the page mode, the avd signal can be tied to gnd or can be pulsed low to latch the page address. in both cases the clk can be tied to gnd. the at49sn/sv1... |
| Description |
128M bit, 1.8-Volt Page Mode Flash Memory.
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| File Size |
383.76K /
41 Page |
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it Online |
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IDT
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| Part No. |
ICS9UMS9633BI
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| OCR Text |
...tated for test 0 = all outputs behave normall y . 7 sclk in clock pin of smbus circuitry, 5v tolerant. 8 sdata i/o data pin for smbus circuitry, 3.3v tolerant. 9 vddcore_3.3 pwr 3.3v power for the pll core 10 vddio_1.5 pwr power suppl y ... |
| Description |
ULTRA MOBILE PC CLOCK
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| File Size |
291.99K /
22 Page |
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it Online |
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http://
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| Part No. |
MK50H28DIP MK50H28PLCC52
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| OCR Text |
.... this pin can be programmed to behave as output rts or as programmable io pin dtr. if configured as rts, the mk50h28 will assert this pin if it has data to send and throughout the transmission of a signal unit. rclk 27 [30] i receive clock... |
| Description |
MULTI LOGICAL LINK FRAME RELAY CONTROLLER
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| File Size |
438.63K /
64 Page |
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it Online |
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Atmel Corp.
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| Part No. |
AT49SN6416T
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| OCR Text |
...chronous reads, the device will behave like a standard asynchronous flash memory. in the page mode, the avd signal can be tied to gnd or can be pulsed low to latch the page address. in both cases the clk can be tied to gnd. the at49sn641... |
| Description |
64-megabit (4M x 16) Burst/Page Mode 1.8-volt Flash Memory
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| File Size |
385.09K /
42 Page |
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it Online |
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Cypress Semiconductor Corp.
Cypress Semiconductor, Corp.
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| Part No. |
CY7C1347G-200AXC CY7C1347G-200AXI CY7C1347G-166AXC CY7C1347G-166AXI CY7C1347G-250AXC CY7C1347G-250AXI CY7C1347G-250BZXI CY7C1347G-250BGXI CY7C1347G-250BZI CY7C1347G-250BGC CY7C1347G-250BGI CY7C1347G-250BZC CY7C1347G-250BGXC CY7C1347G-133BZI CY7C1347G-200BZXI CY7C1347G-166BZXI CY7C1347G-166BZXC
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| OCR Text |
...io pins. when low, the io pins behave as outputs. wh en deasserted high, io pins are tri-stated, and act as input data pins. oe is masked during the first clock of a read cycle when emerging from a deselected state. adv input- synchron... |
| Description |
4-Mbit (128K x 36) Pipelined Sync SRAM 128K X 36 CACHE SRAM, 4 ns, PBGA165
4-Mbit (128K x 36) Pipelined Sync SRAM 128K X 36 CACHE SRAM, 2.8 ns, PBGA165
4-Mbit (128K x 36) Pipelined Sync SRAM 128K X 36 CACHE SRAM, 3.5 ns, PBGA165
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| File Size |
833.02K /
21 Page |
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it Online |
Download Datasheet |
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Cypress Semiconductor Corp.
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| Part No. |
CY7C1346H-166AXI CY7C1346H-166AXC
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| OCR Text |
...o pins. when low, the i/o pins behave as outputs. when deassert ed high, i/o pins are tri-stated, and act as input data pins. oe is masked during the first clock of a read cycle when emerging from a deselected state. adv input- synchr... |
| Description |
2-Mbit (64K x 36) Pipelined Sync SRAM
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| File Size |
684.87K /
16 Page |
View
it Online |
Download Datasheet |
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