| |
|
 |
Motorola
|
| Part No. |
MC12430
|
| OCR Text |
...ous to eliminate possibility of runt pulse generation on the FOUT output. Function
M[8:0] N[1:0] OE Outputs FOUT, FOUT TEST Power VCC PLL_VCC GND Other
(Int. Pullup) (Int. Pullup) (Int. Pullup)
These differential positive-reference... |
| Description |
High Frequency Clock Synthesizer
|
| File Size |
136.76K /
12 Page |
 View
it Online |
Download Datasheet
|
| |
|
|
Motorola
|
| Part No. |
MPC930
|
| OCR Text |
...e the possibility of generating runt pulses. The MPC930/931 devices offer a great deal of flexibility in what is used as the PLL reference. The MPC930 offers an integrated crystal oscillator that allows for an inexpensive crystal to be used... |
| Description |
Low Voltage PLL Clock Drlver
|
| File Size |
158.51K /
14 Page |
View
it Online |
Download Datasheet |
| |
|
|
MICREL
|
| Part No. |
SY100EP15V
|
| OCR Text |
...oids any chance of generating a runt pulse. Positive Power Supply: Bypass with 0.1F//0.01F low ESR capacitors.
9 10
VEE SEL
11, 12
CLK0, /CLK0
13
VBB
14 15
CLK1 /EN
16
VCC
TRUTH TABLE(1)
CLK0 L H X X CLK1 X... |
| Description |
3.3V / 5V 2.5GHz PECL/ECL 1:4 FANOUT BUFFER WITH 2:1 INPUT MUX
|
| File Size |
97.57K /
9 Page |
View
it Online |
Download Datasheet |
| |
|
|
ICST[Integrated Circuit Systems]
|
| Part No. |
ICS8305I 8305AGI 8305AGIL ICS8305AGI ICS8305AGILF ICS8305AGILFT ICS8305AGIT
|
| OCR Text |
...nally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Outputs are forced LOW when the clock is disabled. A separate output enable pin controls whether the outputs are i... |
| Description |
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
Low Skew, 1-to-4, Fanout Buffer. Industrial Temperature.
|
| File Size |
196.85K /
15 Page |
View
it Online |
Download Datasheet |
| |
|
|
ICS
|
| Part No. |
ICS8305
|
| OCR Text |
...nally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Outputs are forced LOW when the clock is disabled. A separate output enable pin controls whether the outputs are i... |
| Description |
Low Skew, 1-to-4, Fanout Buffer
|
| File Size |
218.95K /
16 Page |
View
it Online |
Download Datasheet |
| |
|
|
ICS
|
| Part No. |
ICS84330-02
|
| OCR Text |
...P_LOAD is designed to eliminate runt pulses when changing M and N bits. 84330AV-02
www.icst.com/products/hiperclocks.html
2
REV. A MAY 31, 2005
Integrated Circuit Systems, Inc.
ICS84330-02
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V D... |
| Description |
700MHz, Low Jitter, LVPECL Frequency Synthesizer
|
| File Size |
216.54K /
17 Page |
View
it Online |
Download Datasheet |
| |
|
|
IDT[Integrated Device Technology]
|
| Part No. |
IDT5T93GL0 IDT5T93GL06NLI IDT5T93GL06 IDT5T93GL06NLI8
|
| OCR Text |
...gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize the possibility of runt pulses or be able to tolerate them in down stream circuitry. 3. It is reco... |
| Description |
2.5V LVDS 1:6 Glitchless Clock Buffer TeraBuffer II
2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER-TM II
|
| File Size |
105.00K /
15 Page |
View
it Online |
Download Datasheet |
| |
|
|
AGERE[Agere Systems]
|
| Part No. |
LCK4973
|
| OCR Text |
...re in the low state, preventing runt pulse generation.
1. If fselFB2 is set to 1, it may be necessary to apply a reset pulse after powerup in order to ensure synchronization between the QFB and other inputs.
Table 4. Function Table fo... |
| Description |
Low-Voltage PLL Clock Driver
|
| File Size |
203.19K /
16 Page |
View
it Online |
Download Datasheet |
|
Price and Availability
|
