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Electronic Theatre Controls, Inc.
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| Part No. |
L12-TCPA-PALLADIUM
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| OCR Text |
...can i trust a target machine to behave in an expected manner (maybe based on past performance)? can i have condence in interacting with the platform? can i trust you (the user) to be what you say you are? a trusted computing platform shoul... |
| Description |
TCPA and Palladium 城乡规划和钯
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| File Size |
133.83K /
12 Page |
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it Online |
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Cypress Semiconductor Corp.
Cypress Semiconductor, Corp.
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| Part No. |
CY7C1223H-166AXC CY7C1223H-166AXI CY7C1223H-133AXI CY7C1223H-133AXC
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| OCR Text |
...o pins. when low, the i/o pins behave as outputs. when deasse rted high, i/o pins are tri-stated, and act as input data pins. oe is masked during the first clock of a read cycle when emerging from a deselected state. adv input- synchro... |
| Description |
2-Mbit (128K x 18) Pipelined DCD Sync SRAM 128K X 18 CACHE SRAM, 4 ns, PQFP100
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| File Size |
680.26K /
16 Page |
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it Online |
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TDK Corporation
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| Part No. |
78Q2132
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| OCR Text |
...s a logic zero, the device will behave as a homepna v1.0 compliant phy. this will result in the link status bit mr1.2 always being logic one. if mr19.11 is set to logic one, the device will behave as a homepna 1.1 compliant phy. to enable... |
| Description |
1/10BASE-T HomePNA/Ethernet Transceiver
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| File Size |
179.54K /
36 Page |
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it Online |
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SGS Thomson Microelectronics
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| Part No. |
AN1001
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| OCR Text |
...used to make the selected block behave like rom. it is possible to overlap the effects of the internal and external defences. for example, de-assertion of the wc pin, during a write cycle on some devices, causes the internal write cycle to ... |
| Description |
CHOICE OF SERIAL EEPROMS REQUIRES UNDERSTANDING OF BUS DIFFERENCES
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| File Size |
65.16K /
9 Page |
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it Online |
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Cypress Semiconductor Corp.
Cypress Semiconductor, Corp.
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| Part No. |
7C1351-66 7C1351-40 7C1351-50 CY7C1351-66AC
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| OCR Text |
...w, the i/o pins are allowed to behave as outputs. when deasserted high, i/o pins are three-stated, and act as input data pins. oe is masked during the data portion of a write sequence, during the first clock when emerging from a deselec... |
| Description |
128Kx36 Flow-Through SRAM with NoBL TM Architecture 128K × 36至流通过与总线延迟TM架构的SRAM
128Kx36 Flow-Through SRAM with NoBL TM Architecture 128K X 36 ZBT SRAM, 11 ns, PQFP100
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| File Size |
185.48K /
13 Page |
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it Online |
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