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Samsung Semiconductor Co., Ltd.
SAMSUNG SEMICONDUCTOR CO. LTD.
SAMSUNG[Samsung semiconductor]
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| Part No. |
K7P401822B-HC16 K7P401822B-HC20 K7P401822B-HC25 K7P403622B-HC20 K7P403622B K7P403622B-HC16 K7P403622B-HC25 K7P401822B-HC160 K7P403622B-HC200 K7P401822B-HC20T
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| OCR Text |
... devices. They are organized as 131,072 words by 36 bits for K7P403622B and 262,144 words by 18 bits for K7P401822B, fabricated using Samsung's advanced CMOS technology. Single differential PECL level K clocks or Single ended or differentia... |
| Description |
SENSOR DIFF VACUUM GAGE 10 H2O 128K × 36
128Kx36 & 256Kx18 Synchronous Pipelined SRAM 128K × 36
256K X 18 STANDARD SRAM, 2.7 ns, PBGA119 14 X 22 MM, BGA-119
128K X 36 STANDARD SRAM, 2.7 ns, PBGA119 14 X 22 MM, BGA-119
256K X 18 STANDARD SRAM, 3 ns, PBGA119 14 X 22 MM, BGA-119
SENSOR DIFF VACUUM GAGE 1PSI
SENSOR ABSOLUTE 0-15PSIA
128Kx36 & 256Kx18 Synchronous Pipelined SRAM
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| File Size |
278.02K /
13 Page |
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it Online |
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IDT
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| Part No. |
IDT72T20108 IDT72T2098 IDT72T20128
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| OCR Text |
131,072 x 10 131,072 x 20/262,144 x 10, 262,144 x 20/524,288 x 10
IDT72T2098, IDT72T20108 IDT72T20118, IDT72T20128
FEATURES:
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* *...250MHz Operation of Clocks - 4ns read/write cycle time, 3.2ns access time Users selectable input por... |
| Description |
2.5 VOLT HIGH-SPEED TeraSync? DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION
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| File Size |
459.34K /
51 Page |
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it Online |
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Galvantech
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| Part No. |
GVT71256DA18 GVT71128DA36 DA3618
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| OCR Text |
...nd GVT71256DA18 SRAMs integrate 131,072x36 and 262,144x18 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for ...250MHz) 4.4ns (225MHz) 5.0ns (200MHz) 6.0ns (166MHz) Configurations 128K x 36 256K x 18 Packages 119... |
| Description |
128K X 36/256K X 18 SYNCHRONOUS SRAM
From old datasheet system
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| File Size |
246.90K /
24 Page |
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it Online |
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IDT
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| Part No. |
IDT72T40108 IDT72T4088IDT72T4098 IDT72T4098
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| OCR Text |
131,072 x 40
IDT72T4088, IDT72T4098 IDT72T40108, IDT72T40118
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FEATURES:
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* * * * * * * *
Choose among the following...250MHz Operation of Clocks - 4ns read/write cycle time, 3.2ns access time Users selectable input por... |
| Description |
2.5 VOLT HIGH-SPEED TeraSync? DDR/SDR FIFO 40-BIT CONFIGURATION
2.5 VOLT HIGH-SPEED TeraSync™ DDR FIFO 40-BIT CONFIGURATION
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| File Size |
456.68K /
52 Page |
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it Online |
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