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YAGEO Corporation
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Part No. |
RL1206
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OCR Text |
... ordering information - global part number & 12nc both part number s are identified by the series, size, tolerance, packing typ e , temperature coefficient, t aping reel and resistance value. ... |
Description |
LOW OHMIC CHIP RESISTORS
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File Size |
447.78K /
9 Page |
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ISSI
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Part No. |
IS61SPS25632D IS61SPS25632T IS61SPS25636T IS61LPS51218T
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OCR Text |
...dividual byte write control and global write clock controlled, registered address, data and control linear burst sequence control using mode input three chip enable option for simple depth expansion and address pipelining common dat... |
Description |
256Kx32 Synchronous Pipelined Static RAM
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File Size |
177.88K /
20 Page |
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it Online |
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CYPRESS SEMICONDUCTOR CORP
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Part No. |
MT58L128L32D1F-5
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OCR Text |
...dividual byte write control and global write ? three chip enables for simple depth expansion and address pipelining ? clock-controlled and registered addresses, data i/os and control signals ? internally self-timed write cycle ? burst contr... |
Description |
128K X 32 STANDARD SRAM, 2.8 ns, PBGA165
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File Size |
429.23K /
25 Page |
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ATMEL
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Part No. |
25DF161
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OCR Text |
...ividual sector protection with global protect/unprotect feature ? 32 sectors of 64-kbytes each ? hardware controlled locking of protected sectors via wp pin ? sector lockdown ? make any combination of 64-kbyte sectors permanently read-onl... |
Description |
AT25DF161
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File Size |
815.92K /
60 Page |
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it Online |
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Micron Technology, Inc.
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Part No. |
MT58L128L32D1
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OCR Text |
...dividual byte write control and global write ? three chip enables for simple depth expansion and address pipelining ? clock-controlled and registered addresses, data i/os and control signals ? internally self-timed write cycle ? burst contr... |
Description |
128K x 32锛?.3V I/O Pipelined, DCD SyncBurst SRAM(4Mb锛?.3V杈??/杈??锛??姘寸嚎寮????惊???娑???╋??????????瀛???ī
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File Size |
418.97K /
24 Page |
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INTEGRATED SILICON SOLUTION INC
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Part No. |
IS61LPS25632T-200TQI
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OCR Text |
...dividual byte write control and global write clock controlled, registered address, data and control linear burst sequence control using mode input three chip enable option for simple depth expansion and address pipelining common da... |
Description |
256K X 32 CACHE SRAM, 3.1 ns, PQFP100
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File Size |
176.18K /
29 Page |
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it Online |
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Price and Availability
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