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For signals Found Datasheets File :: 82318    Search Time::3.343ms    
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    Integrated Device Techn...
Part No. 8S89831I-17
OCR Text ...ml, sstl and other differential signals. both signals must meet the v in and v ih input requirements. figures 2a to 2d show interface examples for the in/nin input with built-in 50 ? terminations driven by the most common driver ty...
Description Differential LVPECL-To-LVPECL/ECL Fanout Buffer

File Size 354.82K  /  19 Page

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    Integrated Device Techn...
Part No. 8S89831AKILF 8S89831AKILFT 8S89831I
OCR Text ...l, sstl and other different ial signals. both signals must meet the v in and v ih input requirements. figures 2a to 2d show interface examples for the in/nin input with built-in 50 ? terminations driven by the most common driver typ...
Description Differential LVPECL-To-LVPECL/ECL Fanout Buffer

File Size 348.43K  /  21 Page

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    MAXIM - Dallas Semiconductor
Part No. MAX3864E/DC8R
OCR Text ...amplifier converts single-ended signals todifferential signals and introduces a voltage gain. output buffer the output buffer provides a back-terminated voltageoutput. the buffer is designed to drive a 100 differen- tial load between out+ ...
Description 2.5Gbps, 3V to 5.5V, Wide Dynamic Range Transimpedance Preamplifier

File Size 245.31K  /  10 Page

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    Micross Components
Part No. AS4SD8M16DG-75/IT
OCR Text ...anks) ? fully synchronous; all signals registered on positive edge of system clock ? internal pipelined operation; column address can be changed every clock cycle ? internal banks for hiding row access/precharge ? programmable...
Description Self Refresh Mode

File Size 6,667.99K  /  52 Page

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    ST Microelectronics
Part No. STMT-BOX01
OCR Text ..., digital output, swim and swd signals ? touch application voltage supported from 2.7 to 3.6 v touch keypad board (stm8tl53box/p01) ? core: stm8tl53c4u6 touch sensing microcontroller ? three 5 v power supply options: usb, 5 v supplied ...
Description Demonstration platform for MCU Touch sensing solutions

File Size 74.24K  /  4 Page

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    LTC6820HMSPBF LTC6820HUDPBF LTC6820IMSPBF LTC6820IMSTRPBF LTC6820IUDPBF LTC6820IUDTRPBF

Linear Technology
Part No. LTC6820HMSPBF LTC6820HUDPBF LTC6820IMSPBF LTC6820IMSTRPBF LTC6820IUDPBF LTC6820IUDTRPBF
OCR Text ...6820 encodes logic states into signals that are transmitted across an isolation barrier to another ltc6820. the receiving ltc6820 decodes the transmission and drives the slave bus to the appropriate logic states. the isolation ...
Description isoSPI Isolated Communications Interface

File Size 522.19K  /  30 Page

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    AT7912F-14

ATMEL Corporation
Part No. AT7912F-14
OCR Text ...lines and the required control signals ? fifo interface ? ram interface ? 16-bit data bus and 16-bit address bus ? four chip selects to address 4 different memory pa rtitions ? two independent uart interfaces ? 24 bidirectional general pu...
Description Derived from the T7906 Single Point to Point IEEE 1355 High Speed Controller

File Size 265.65K  /  21 Page

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    2688093

PHOENIX CONTACT
Part No. 2688093
OCR Text ...isition: acquisition of digital signals from symmetrical and asymmetrical incremental encoders ?incremental encoder acquisition: evaluation of linear or rotary axes ?device rating plate stored ?diagnostic and status indicators ? key commer...
Description Axioline special function module, 2 counter inputs, 2 incremental encoder inputs (including bus base module and connectors)

File Size 134.63K  /  7 Page

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    ADS4616A4A ADS4616A4A-5 ADS4616A4A-6 ADS4616A4A-7

ADATA Technology Co., Ltd.
A-DATA[A-Data Technology]
Part No. ADS4616A4A ADS4616A4A-5 ADS4616A4A-6 ADS4616A4A-7
OCR Text ...in), /CSVIH(min), tCK=min input signals are Precharge standby current in Non power down mode IDD2NS Input signals are stable. Active standby current in power down mode CKEVIH(min), /CSVIH(min), Active standby current in Non power IDD3N down...
Description Synchronous DRAM(512K X 16 Bit X 2 Banks) 同步DRAM(为512k × 16位2组)

File Size 205.18K  /  8 Page

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    Freescale (Motorola)
Part No. MPC99J93
OCR Text ...s two differential lvpecl clock signals from which it generates 5 new differential lvpecl clock outputs. two of the output pairs r egenerate the input signals frequency and phase while the other three pairs generate 2x, phase aligned clock ...
Description Intelligent Dynamic Clock Switch

File Size 265.38K  /  8 Page

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